[PATCH v2 0/3] BXT Pooled EU kernel support and WA patches

[PATCH v2 0/3] BXT Pooled EU kernel support and WA patches

[Arun Siluvery]

These patches enable Pooled EU support for BXT.
These patches were sent to the list before and as suggested in [1], code that exposes this feature to userspace is removed as support in userspace is currently being implemented by beignet. Other users of this feature are mesa, libva.

Some of the related WA patches are also included in this series.

[1] https://lists.freedesktop.org/archives/intel-gfx/2016-May/095890.html

Arun Siluvery (3):
  drm/i915:bxt: Enable Pooled EU support
  drm/i915/bxt: Add WaEnablePooledEuFor2x6
  drm/i915/bxt: Add WaDisablePooledEuLoadBalancingFix

 drivers/gpu/drm/i915/i915_debugfs.c          |  4 ++++
 drivers/gpu/drm/i915/i915_dma.c              | 29 ++++++++++++++++++++++++++++
 drivers/gpu/drm/i915/i915_drv.c              |  1 +
 drivers/gpu/drm/i915/i915_drv.h              |  6 +++++-
 drivers/gpu/drm/i915/i915_gem_render_state.c | 28 +++++++++++++++++++++++++++
 drivers/gpu/drm/i915/i915_reg.h              |  3 +++
 drivers/gpu/drm/i915/intel_ringbuffer.c      |  6 ++++++
 7 files changed, 76 insertions(+), 1 deletion(-)

-- 
1.9.1

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

[PATCH v2 1/3] drm/i915:bxt: Enable Pooled EU support

[Arun Siluvery]

This mode allows to assign EUs to pools which can process work collectively.
The command to enable this mode should be issued as part of context initialization.

The pooled mode is global, once enabled it has to stay the same across all
contexts until HW reset hence this is sent in auxiliary golden context batch.
Thanks to Mika for the preliminary review and comments.

v2: explain why this is enabled in golden context, use feature flag while
enabling the support (Chris)

v3: Include only kernel support as userspace support is not available yet.

User space clients need to know when the pooled EU feature is present
and enabled on the hardware so that they can adapt work submissions.
Create a new device info flag for this purpose.

Set has_pooled_eu to true in the Broxton static device info - Broxton
supports the feature in hardware and the driver will enable it by
default.

We need to add getparam ioctls to enable userspace to query availability of
this feature and to retrieve min. no of eus in a pool but we will expose
them once userspace support is available. Opensource users for this feature
are mesa, libva and beignet.

Beignet team is currently working on adding userspace support.

Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk> (v2)
Cc: Winiarski, Michal <michal.winiarski@intel.com>
Cc: Zou, Nanhai <nanhai.zou@intel.com>
Cc: Yang, Rong R <rong.r.yang@intel.com>
Cc: Mika Kuoppala <mika.kuoppala@intel.com>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Armin Reese <armin.c.reese@intel.com>
Cc: Tim Gore <tim.gore@intel.com>
Signed-off-by: Jeff McGee <jeff.mcgee@intel.com>
Signed-off-by: Arun Siluvery <arun.siluvery@linux.intel.com>
---
 drivers/gpu/drm/i915/i915_debugfs.c          |  4 ++++
 drivers/gpu/drm/i915/i915_dma.c              | 19 +++++++++++++++++++
 drivers/gpu/drm/i915/i915_drv.c              |  1 +
 drivers/gpu/drm/i915/i915_drv.h              |  6 +++++-
 drivers/gpu/drm/i915/i915_gem_render_state.c | 28 ++++++++++++++++++++++++++++
 drivers/gpu/drm/i915/i915_reg.h              |  2 ++
 6 files changed, 59 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
index e606c6a..1577fad 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -5284,6 +5284,10 @@ static int i915_sseu_status(struct seq_file *m, void *unused)
 		   INTEL_INFO(dev)->eu_total);
 	seq_printf(m, "  Available EU Per Subslice: %u\n",
 		   INTEL_INFO(dev)->eu_per_subslice);
+	seq_printf(m, "  Has Pooled EU: %s\n", yesno(HAS_POOLED_EU(dev)));
+	if (HAS_POOLED_EU(dev))
+		seq_printf(m, "  Min EU in pool: %u\n",
+			   INTEL_INFO(dev)->min_eu_in_pool);
 	seq_printf(m, "  Has Slice Power Gating: %s\n",
 		   yesno(INTEL_INFO(dev)->has_slice_pg));
 	seq_printf(m, "  Has Subslice Power Gating: %s\n",
diff --git a/drivers/gpu/drm/i915/i915_dma.c b/drivers/gpu/drm/i915/i915_dma.c
index 07edaed..a6c5d87 100644
--- a/drivers/gpu/drm/i915/i915_dma.c
+++ b/drivers/gpu/drm/i915/i915_dma.c
@@ -764,6 +764,22 @@ static void gen9_sseu_info_init(struct drm_device *dev)
 			       (info->slice_total > 1));
 	info->has_subslice_pg = (IS_BROXTON(dev) && (info->subslice_total > 1));
 	info->has_eu_pg = (info->eu_per_subslice > 2);
+
+	if (IS_BROXTON(dev)) {
+#define IS_SS_DISABLED(_ss_disable, ss)    (_ss_disable & (0x1 << ss))
+
+		info->min_eu_in_pool = 0;
+		if (info->has_pooled_eu) {
+			if (IS_SS_DISABLED(ss_disable, 0) ||
+			    IS_SS_DISABLED(ss_disable, 2))
+				info->min_eu_in_pool = 3;
+			else if (IS_SS_DISABLED(ss_disable, 1))
+				info->min_eu_in_pool = 6;
+			else
+				info->min_eu_in_pool = 9;
+		}
+#undef IS_SS_DISABLED
+	}
 }
 
 static void broadwell_sseu_info_init(struct drm_device *dev)
@@ -962,6 +978,9 @@ static void intel_device_info_runtime_init(struct drm_device *dev)
 	DRM_DEBUG_DRIVER("subslice per slice: %u\n", info->subslice_per_slice);
 	DRM_DEBUG_DRIVER("EU total: %u\n", info->eu_total);
 	DRM_DEBUG_DRIVER("EU per subslice: %u\n", info->eu_per_subslice);
+	DRM_DEBUG_DRIVER("Has Pooled EU: %s\n", HAS_POOLED_EU(dev) ? "y" : "n");
+	if (HAS_POOLED_EU(dev))
+		DRM_DEBUG_DRIVER("Min EU in pool: %u\n", info->min_eu_in_pool);
 	DRM_DEBUG_DRIVER("has slice power gating: %s\n",
 			 info->has_slice_pg ? "y" : "n");
 	DRM_DEBUG_DRIVER("has subslice power gating: %s\n",
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 943d7b2..de78a30 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -357,6 +357,7 @@ static const struct intel_device_info intel_broxton_info = {
 	.has_ddi = 1,
 	.has_fpga_dbg = 1,
 	.has_fbc = 1,
+	.has_pooled_eu = 1,
 	GEN_DEFAULT_PIPEOFFSETS,
 	IVB_CURSOR_OFFSETS,
 	BDW_COLORS,
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 78d38c2..cba8062 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -756,7 +756,8 @@ struct intel_csr {
 	func(has_llc) sep \
 	func(has_snoop) sep \
 	func(has_ddi) sep \
-	func(has_fpga_dbg)
+	func(has_fpga_dbg) sep \
+	func(has_pooled_eu)
 
 #define DEFINE_FLAG(name) u8 name:1
 #define SEP_SEMICOLON ;
@@ -782,6 +783,7 @@ struct intel_device_info {
 	u8 subslice_per_slice;
 	u8 eu_total;
 	u8 eu_per_subslice;
+	u8 min_eu_in_pool;
 	/* For each slice, which subslice(s) has(have) 7 EUs (bitfield)? */
 	u8 subslice_7eu[3];
 	u8 has_slice_pg:1;
@@ -2822,6 +2824,8 @@ struct drm_i915_cmd_table {
 				 !IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev) && \
 				 !IS_BROXTON(dev))
 
+#define HAS_POOLED_EU(dev)	(INTEL_INFO(dev)->has_pooled_eu)
+
 #define INTEL_PCH_DEVICE_ID_MASK		0xff00
 #define INTEL_PCH_IBX_DEVICE_ID_TYPE		0x3b00
 #define INTEL_PCH_CPT_DEVICE_ID_TYPE		0x1c00
diff --git a/drivers/gpu/drm/i915/i915_gem_render_state.c b/drivers/gpu/drm/i915/i915_gem_render_state.c
index 7c93327..b7c1b5f 100644
--- a/drivers/gpu/drm/i915/i915_gem_render_state.c
+++ b/drivers/gpu/drm/i915/i915_gem_render_state.c
@@ -94,6 +94,7 @@ free_gem:
 
 static int render_state_setup(struct render_state *so)
 {
+	struct drm_device *dev = so->obj->base.dev;
 	const struct intel_renderstate_rodata *rodata = so->rodata;
 	unsigned int i = 0, reloc_index = 0;
 	struct page *page;
@@ -135,6 +136,33 @@ static int render_state_setup(struct render_state *so)
 
 	so->aux_batch_offset = i * sizeof(u32);
 
+	if (HAS_POOLED_EU(dev)) {
+		/*
+		 * We always program 3x6 pool config but depending upon which
+		 * subslice is disabled HW drops down to appropriate config
+		 * shown below.
+		 *
+		 * In the below table 2x6 config always refers to
+		 * fused-down version, native 2x6 is not available and can
+		 * be ignored
+		 *
+		 * SNo  subslices config                eu pool configuration
+		 * -----------------------------------------------------------
+		 * 1    3 subslices enabled (3x6)  -    0x00777000  (9+9)
+		 * 2    ss0 disabled (2x6)         -    0x00777000  (3+9)
+		 * 3    ss1 disabled (2x6)         -    0x00770000  (6+6)
+		 * 4    ss2 disabled (2x6)         -    0x00007000  (9+3)
+		 */
+		u32 eu_pool_config = 0x00777000;
+
+		OUT_BATCH(d, i, GEN9_MEDIA_POOL_STATE);
+		OUT_BATCH(d, i, GEN9_MEDIA_POOL_ENABLE);
+		OUT_BATCH(d, i, eu_pool_config);
+		OUT_BATCH(d, i, 0);
+		OUT_BATCH(d, i, 0);
+		OUT_BATCH(d, i, 0);
+	}
+
 	OUT_BATCH(d, i, MI_BATCH_BUFFER_END);
 	so->aux_batch_size = (i * sizeof(u32)) - so->aux_batch_offset;
 
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index e307725..1d97321e 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -442,6 +442,8 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
  */
 #define GFX_INSTR(opcode, flags) ((0x3 << 29) | ((opcode) << 24) | (flags))
 
+#define GEN9_MEDIA_POOL_STATE     ((0x3 << 29) | (0x2 << 27) | (0x5 << 16) | 4)
+#define   GEN9_MEDIA_POOL_ENABLE  (1 << 31)
 #define GFX_OP_RASTER_RULES    ((0x3<<29)|(0x7<<24))
 #define GFX_OP_SCISSOR         ((0x3<<29)|(0x1c<<24)|(0x10<<19))
 #define   SC_UPDATE_SCISSOR       (0x1<<1)
-- 
1.9.1

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

[PATCH v2 2/3] drm/i915/bxt: Add WaEnablePooledEuFor2x6

[Arun Siluvery]

Pooled EU is enabled by default for BXT but for fused down 2x6 parts it is
advised to turn it off. But there is another HW issue in these parts (fused
down 2x6 parts) before C0 that requires Pooled EU to be enabled as a
workaround. In this case the pool configuration changes depending upon
which subslice is disabled. This doesn't affect if the device has all 3
subslices enabled.

Userspace need to know min no. of eus in a pool as it varies based on which
subslice is disabled, this is not yet exported because userspace support is
not available yet. Once the support is available this needs to be exported
using getparam ioctls.

Cc: Winiarski, Michal <michal.winiarski@intel.com>
Cc: Zou, Nanhai <nanhai.zou@intel.com>
Cc: Yang, Rong R <rong.r.yang@intel.com>
Cc: Tim Gore <tim.gore@intel.com>
Cc: Jeff McGee <jeff.mcgee@intel.com>
Signed-off-by: Arun Siluvery <arun.siluvery@linux.intel.com>
---
 drivers/gpu/drm/i915/i915_dma.c | 10 ++++++++++
 drivers/gpu/drm/i915/i915_drv.c |  2 +-
 2 files changed, 11 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/i915_dma.c b/drivers/gpu/drm/i915/i915_dma.c
index a6c5d87..50aedfd 100644
--- a/drivers/gpu/drm/i915/i915_dma.c
+++ b/drivers/gpu/drm/i915/i915_dma.c
@@ -767,6 +767,16 @@ static void gen9_sseu_info_init(struct drm_device *dev)
 
 	if (IS_BROXTON(dev)) {
 #define IS_SS_DISABLED(_ss_disable, ss)    (_ss_disable & (0x1 << ss))
+		/*
+		 * There is a HW issue in 2x6 fused down parts that requires
+		 * Pooled EU to be enabled as a WA. The pool configuration
+		 * changes depending upon which subslice is fused down. This
+		 * doesn't affect if the device has all 3 subslices enabled.
+		 */
+		/* WaEnablePooledEuFor2x6:bxt */
+		info->has_pooled_eu = ((info->subslice_total == 3) ||
+				       (info->subslice_total == 2 &&
+					INTEL_REVID(dev) < BXT_REVID_C0));
 
 		info->min_eu_in_pool = 0;
 		if (info->has_pooled_eu) {
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index de78a30..84593c1 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -357,7 +357,7 @@ static const struct intel_device_info intel_broxton_info = {
 	.has_ddi = 1,
 	.has_fpga_dbg = 1,
 	.has_fbc = 1,
-	.has_pooled_eu = 1,
+	.has_pooled_eu = 0,
 	GEN_DEFAULT_PIPEOFFSETS,
 	IVB_CURSOR_OFFSETS,
 	BDW_COLORS,
-- 
1.9.1

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

[PATCH v2 3/3] drm/i915/bxt: Add WaDisablePooledEuLoadBalancingFix

[Arun Siluvery]

This is a WA affecting pooled eu which is a bxt specific feature.

Cc: Winiarski, Michal <michal.winiarski@intel.com>
Cc: Zou, Nanhai <nanhai.zou@intel.com>
Cc: Yang, Rong R <rong.r.yang@intel.com>
Cc: Jeff McGee <jeff.mcgee@intel.com>
Signed-off-by: Arun Siluvery <arun.siluvery@linux.intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h         | 1 +
 drivers/gpu/drm/i915/intel_ringbuffer.c | 6 ++++++
 2 files changed, 7 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 1d97321e..5268aed 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -6072,6 +6072,7 @@ enum skl_disp_power_wells {
 
 #define FF_SLICE_CS_CHICKEN2			_MMIO(0x20e4)
 #define  GEN9_TSG_BARRIER_ACK_DISABLE		(1<<8)
+#define  GEN9_POOLED_EU_LOAD_BALANCING_FIX_DISABLE  (1<<10)
 
 #define GEN9_CS_DEBUG_MODE1		_MMIO(0x20ec)
 #define GEN8_CS_CHICKEN1		_MMIO(0x2580)
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
index 8d35a39..a21eced 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.c
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
@@ -1145,6 +1145,12 @@ static int bxt_init_workarounds(struct intel_engine_cs *engine)
 	WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN,
 			  STALL_DOP_GATING_DISABLE);
 
+	/* WaDisablePooledEuLoadBalancingFix:bxt */
+	if (IS_BXT_REVID(dev_priv, BXT_REVID_B0, REVID_FOREVER)) {
+		WA_SET_BIT_MASKED(FF_SLICE_CS_CHICKEN2,
+				  GEN9_POOLED_EU_LOAD_BALANCING_FIX_DISABLE);
+	}
+
 	/* WaDisableSbeCacheDispatchPortSharing:bxt */
 	if (IS_BXT_REVID(dev_priv, 0, BXT_REVID_B0)) {
 		WA_SET_BIT_MASKED(
-- 
1.9.1

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [PATCH v2 3/3] drm/i915/bxt: Add WaDisablePooledEuLoadBalancingFix

[Mika Kuoppala]

Arun Siluvery <arun.siluvery@linux.intel.com> writes:

> [ text/plain ]
> This is a WA affecting pooled eu which is a bxt specific feature.
>
> Cc: Winiarski, Michal <michal.winiarski@intel.com>
> Cc: Zou, Nanhai <nanhai.zou@intel.com>
> Cc: Yang, Rong R <rong.r.yang@intel.com>
> Cc: Jeff McGee <jeff.mcgee@intel.com>
> Signed-off-by: Arun Siluvery <arun.siluvery@linux.intel.com>

Reviewed-by: Mika Kuoppala <mika.kuoppala@intel.com>

> ---
>  drivers/gpu/drm/i915/i915_reg.h         | 1 +
>  drivers/gpu/drm/i915/intel_ringbuffer.c | 6 ++++++
>  2 files changed, 7 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 1d97321e..5268aed 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -6072,6 +6072,7 @@ enum skl_disp_power_wells {
>  
>  #define FF_SLICE_CS_CHICKEN2			_MMIO(0x20e4)
>  #define  GEN9_TSG_BARRIER_ACK_DISABLE		(1<<8)
> +#define  GEN9_POOLED_EU_LOAD_BALANCING_FIX_DISABLE  (1<<10)
>  
>  #define GEN9_CS_DEBUG_MODE1		_MMIO(0x20ec)
>  #define GEN8_CS_CHICKEN1		_MMIO(0x2580)
> diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
> index 8d35a39..a21eced 100644
> --- a/drivers/gpu/drm/i915/intel_ringbuffer.c
> +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
> @@ -1145,6 +1145,12 @@ static int bxt_init_workarounds(struct intel_engine_cs *engine)
>  	WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN,
>  			  STALL_DOP_GATING_DISABLE);
>  
> +	/* WaDisablePooledEuLoadBalancingFix:bxt */
> +	if (IS_BXT_REVID(dev_priv, BXT_REVID_B0, REVID_FOREVER)) {
> +		WA_SET_BIT_MASKED(FF_SLICE_CS_CHICKEN2,
> +				  GEN9_POOLED_EU_LOAD_BALANCING_FIX_DISABLE);
> +	}
> +
>  	/* WaDisableSbeCacheDispatchPortSharing:bxt */
>  	if (IS_BXT_REVID(dev_priv, 0, BXT_REVID_B0)) {
>  		WA_SET_BIT_MASKED(
> -- 
> 1.9.1
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

✗ Ro.CI.BAT: warning for BXT Pooled EU kernel support and WA patches

[Patchwork]

== Series Details ==

Series: BXT Pooled EU kernel support and WA patches
URL   : https://patchwork.freedesktop.org/series/8200/
State : warning

== Summary ==

Series 8200v1 BXT Pooled EU kernel support and WA patches
http://patchwork.freedesktop.org/api/1.0/series/8200/revisions/1/mbox

Test gem_exec_flush:
        Subgroup basic-batch-kernel-default-uc:
                dmesg-warn -> PASS       (ro-skl-i7-6700hq)
        Subgroup basic-wb-pro-default:
                dmesg-warn -> PASS       (ro-skl-i7-6700hq)
        Subgroup basic-wb-ro-default:
                dmesg-warn -> PASS       (ro-skl-i7-6700hq)
Test gem_mmap_gtt:
        Subgroup basic-small-copy:
                pass       -> DMESG-WARN (ro-skl-i7-6700hq)
        Subgroup basic-write-cpu-read-gtt:
                dmesg-warn -> PASS       (ro-skl-i7-6700hq)
        Subgroup basic-write-gtt:
                dmesg-warn -> PASS       (ro-skl-i7-6700hq)
Test gem_storedw_loop:
        Subgroup basic-render:
                dmesg-warn -> PASS       (ro-skl-i7-6700hq)
        Subgroup basic-vebox:
                dmesg-warn -> PASS       (ro-skl-i7-6700hq)
Test kms_addfb_basic:
        Subgroup bad-pitch-0:
                dmesg-warn -> PASS       (ro-skl-i7-6700hq)
        Subgroup bad-pitch-128:
                pass       -> DMESG-WARN (ro-skl-i7-6700hq)
        Subgroup bad-pitch-32:
                pass       -> DMESG-WARN (ro-skl-i7-6700hq)
        Subgroup bo-too-small:
                dmesg-warn -> PASS       (ro-skl-i7-6700hq)
        Subgroup tile-pitch-mismatch:
                dmesg-warn -> PASS       (ro-skl-i7-6700hq)
        Subgroup unused-pitches:
                pass       -> DMESG-WARN (ro-skl-i7-6700hq)
Test kms_flip:
        Subgroup basic-flip-vs-wf_vblank:
                pass       -> DMESG-WARN (ro-skl-i7-6700hq)

fi-hsw-i7-4770k  total:209  pass:187  dwarn:0   dfail:0   fail:3   skip:19 
fi-snb-i7-2600   total:209  pass:167  dwarn:0   dfail:0   fail:3   skip:39 
ro-bdw-i5-5250u  total:102  pass:93   dwarn:0   dfail:0   fail:0   skip:8  
ro-bdw-i7-5600u  total:102  pass:75   dwarn:0   dfail:0   fail:0   skip:26 
ro-hsw-i3-4010u  total:209  pass:186  dwarn:0   dfail:0   fail:0   skip:23 
ro-hsw-i7-4770r  total:102  pass:82   dwarn:0   dfail:0   fail:0   skip:19 
ro-ilk1-i5-650   total:204  pass:146  dwarn:0   dfail:0   fail:1   skip:57 
ro-ivb-i7-3770   total:102  pass:75   dwarn:0   dfail:0   fail:0   skip:26 
ro-ivb2-i7-3770  total:102  pass:79   dwarn:0   dfail:0   fail:0   skip:22 
ro-skl-i7-6700hq total:204  pass:177  dwarn:6   dfail:0   fail:0   skip:21 
ro-snb-i7-2620M  total:102  pass:72   dwarn:0   dfail:0   fail:0   skip:29 
ro-bdw-i7-5557U failed to connect after reboot
ro-byt-n2820 failed to connect after reboot
ro-ilk-i7-620lm failed to connect after reboot

Results at /archive/results/CI_IGT_test/RO_Patchwork_1088/

cbc3c4a drm-intel-nightly: 2016y-06m-02d-22h-03m-59s UTC integration manifest
821ad9a drm/i915/bxt: Add WaDisablePooledEuLoadBalancingFix
4ccf875 drm/i915/bxt: Add WaEnablePooledEuFor2x6
a656766 drm/i915:bxt: Enable Pooled EU support

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [PATCH v2 2/3] drm/i915/bxt: Add WaEnablePooledEuFor2x6

[Mika Kuoppala]

Arun Siluvery <arun.siluvery@linux.intel.com> writes:

> [ text/plain ]
> Pooled EU is enabled by default for BXT but for fused down 2x6 parts it is
> advised to turn it off. But there is another HW issue in these parts (fused
> down 2x6 parts) before C0 that requires Pooled EU to be enabled as a
> workaround. In this case the pool configuration changes depending upon
> which subslice is disabled. This doesn't affect if the device has all 3
> subslices enabled.
>
> Userspace need to know min no. of eus in a pool as it varies based on which
> subslice is disabled, this is not yet exported because userspace support is
> not available yet. Once the support is available this needs to be exported
> using getparam ioctls.
>
> Cc: Winiarski, Michal <michal.winiarski@intel.com>
> Cc: Zou, Nanhai <nanhai.zou@intel.com>
> Cc: Yang, Rong R <rong.r.yang@intel.com>
> Cc: Tim Gore <tim.gore@intel.com>
> Cc: Jeff McGee <jeff.mcgee@intel.com>
> Signed-off-by: Arun Siluvery <arun.siluvery@linux.intel.com>
> ---
>  drivers/gpu/drm/i915/i915_dma.c | 10 ++++++++++
>  drivers/gpu/drm/i915/i915_drv.c |  2 +-
>  2 files changed, 11 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_dma.c b/drivers/gpu/drm/i915/i915_dma.c
> index a6c5d87..50aedfd 100644
> --- a/drivers/gpu/drm/i915/i915_dma.c
> +++ b/drivers/gpu/drm/i915/i915_dma.c
> @@ -767,6 +767,16 @@ static void gen9_sseu_info_init(struct drm_device *dev)
>  
>  	if (IS_BROXTON(dev)) {
>  #define IS_SS_DISABLED(_ss_disable, ss)    (_ss_disable & (0x1 << ss))
> +		/*
> +		 * There is a HW issue in 2x6 fused down parts that requires
> +		 * Pooled EU to be enabled as a WA. The pool configuration
> +		 * changes depending upon which subslice is fused down. This
> +		 * doesn't affect if the device has all 3 subslices enabled.
> +		 */
> +		/* WaEnablePooledEuFor2x6:bxt */
> +		info->has_pooled_eu = ((info->subslice_total == 3) ||
> +				       (info->subslice_total == 2 &&
> +					INTEL_REVID(dev) < BXT_REVID_C0));
>  

It was agreed on irc that BXT has only one slice in all configurations.
However I still think that for correctness sake, we should
use info->subslice_per_slice here when we check the configuration.

With that changed,

Reviewed-by: Mika Kuoppala <mika.kuoppala@ıntel.com>


>  		info->min_eu_in_pool = 0;
>  		if (info->has_pooled_eu) {
> diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
> index de78a30..84593c1 100644
> --- a/drivers/gpu/drm/i915/i915_drv.c
> +++ b/drivers/gpu/drm/i915/i915_drv.c
> @@ -357,7 +357,7 @@ static const struct intel_device_info intel_broxton_info = {
>  	.has_ddi = 1,
>  	.has_fpga_dbg = 1,
>  	.has_fbc = 1,
> -	.has_pooled_eu = 1,
> +	.has_pooled_eu = 0,
>  	GEN_DEFAULT_PIPEOFFSETS,
>  	IVB_CURSOR_OFFSETS,
>  	BDW_COLORS,
> -- 
> 1.9.1
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

[PATCH v3 2/3] drm/i915/bxt: Add WaEnablePooledEuFor2x6

[Arun Siluvery]

Pooled EU is enabled by default for BXT but for fused down 2x6 parts it is
advised to turn it off. But there is another HW issue in these parts (fused
down 2x6 parts) before C0 that requires Pooled EU to be enabled as a
workaround. In this case the pool configuration changes depending upon
which subslice is disabled. This doesn't affect if the device has all 3
subslices enabled.

Userspace need to know min no. of eus in a pool as it varies based on which
subslice is disabled, this is not yet exported because userspace support is
not available yet. Once the support is available this needs to be exported
using getparam ioctls.

v2: s/subslice_total/subslice_per_slice as it is a more logical field (Mika)

Reviewed-by: Mika Kuoppala <mika.kuoppala@intel.com>
Cc: Winiarski, Michal <michal.winiarski@intel.com>
Cc: Zou, Nanhai <nanhai.zou@intel.com>
Cc: Yang, Rong R <rong.r.yang@intel.com>
Cc: Tim Gore <tim.gore@intel.com>
Cc: Jeff McGee <jeff.mcgee@intel.com>
Cc: Mika Kuoppala <mika.kuoppala@intel.com>
Signed-off-by: Arun Siluvery <arun.siluvery@linux.intel.com>
---
 drivers/gpu/drm/i915/i915_dma.c | 10 ++++++++++
 drivers/gpu/drm/i915/i915_drv.c |  2 +-
 2 files changed, 11 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/i915_dma.c b/drivers/gpu/drm/i915/i915_dma.c
index a6c5d87..24b670f 100644
--- a/drivers/gpu/drm/i915/i915_dma.c
+++ b/drivers/gpu/drm/i915/i915_dma.c
@@ -767,6 +767,16 @@ static void gen9_sseu_info_init(struct drm_device *dev)
 
 	if (IS_BROXTON(dev)) {
 #define IS_SS_DISABLED(_ss_disable, ss)    (_ss_disable & (0x1 << ss))
+		/*
+		 * There is a HW issue in 2x6 fused down parts that requires
+		 * Pooled EU to be enabled as a WA. The pool configuration
+		 * changes depending upon which subslice is fused down. This
+		 * doesn't affect if the device has all 3 subslices enabled.
+		 */
+		/* WaEnablePooledEuFor2x6:bxt */
+		info->has_pooled_eu = ((info->subslice_per_slice == 3) ||
+				       (info->subslice_per_slice == 2 &&
+					INTEL_REVID(dev) < BXT_REVID_C0));
 
 		info->min_eu_in_pool = 0;
 		if (info->has_pooled_eu) {
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index de78a30..84593c1 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -357,7 +357,7 @@ static const struct intel_device_info intel_broxton_info = {
 	.has_ddi = 1,
 	.has_fpga_dbg = 1,
 	.has_fbc = 1,
-	.has_pooled_eu = 1,
+	.has_pooled_eu = 0,
 	GEN_DEFAULT_PIPEOFFSETS,
 	IVB_CURSOR_OFFSETS,
 	BDW_COLORS,
-- 
1.9.1

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

[PATCH v3 3/3] drm/i915/bxt: Add WaDisablePooledEuLoadBalancingFix

[Arun Siluvery]

This is a WA affecting pooled eu which is a bxt specific feature.

Reviewed-by: Mika Kuoppala <mika.kuoppala@intel.com>
Cc: Winiarski, Michal <michal.winiarski@intel.com>
Cc: Zou, Nanhai <nanhai.zou@intel.com>
Cc: Yang, Rong R <rong.r.yang@intel.com>
Cc: Jeff McGee <jeff.mcgee@intel.com>
Signed-off-by: Arun Siluvery <arun.siluvery@linux.intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h         | 1 +
 drivers/gpu/drm/i915/intel_ringbuffer.c | 6 ++++++
 2 files changed, 7 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 1d97321e..5268aed 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -6072,6 +6072,7 @@ enum skl_disp_power_wells {
 
 #define FF_SLICE_CS_CHICKEN2			_MMIO(0x20e4)
 #define  GEN9_TSG_BARRIER_ACK_DISABLE		(1<<8)
+#define  GEN9_POOLED_EU_LOAD_BALANCING_FIX_DISABLE  (1<<10)
 
 #define GEN9_CS_DEBUG_MODE1		_MMIO(0x20ec)
 #define GEN8_CS_CHICKEN1		_MMIO(0x2580)
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
index 8d35a39..a21eced 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.c
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
@@ -1145,6 +1145,12 @@ static int bxt_init_workarounds(struct intel_engine_cs *engine)
 	WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN,
 			  STALL_DOP_GATING_DISABLE);
 
+	/* WaDisablePooledEuLoadBalancingFix:bxt */
+	if (IS_BXT_REVID(dev_priv, BXT_REVID_B0, REVID_FOREVER)) {
+		WA_SET_BIT_MASKED(FF_SLICE_CS_CHICKEN2,
+				  GEN9_POOLED_EU_LOAD_BALANCING_FIX_DISABLE);
+	}
+
 	/* WaDisableSbeCacheDispatchPortSharing:bxt */
 	if (IS_BXT_REVID(dev_priv, 0, BXT_REVID_B0)) {
 		WA_SET_BIT_MASKED(
-- 
1.9.1

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

✗ Ro.CI.BAT: warning for BXT Pooled EU kernel support and WA patches (rev3)

[Patchwork]

== Series Details ==

Series: BXT Pooled EU kernel support and WA patches (rev3)
URL   : https://patchwork.freedesktop.org/series/8200/
State : warning

== Summary ==

Series 8200v3 BXT Pooled EU kernel support and WA patches
http://patchwork.freedesktop.org/api/1.0/series/8200/revisions/3/mbox

Test gem_busy:
        Subgroup basic-parallel-render:
                pass       -> DMESG-WARN (ro-skl-i7-6700hq)
Test gem_close_race:
        Subgroup basic-process:
                pass       -> DMESG-WARN (ro-skl-i7-6700hq)
Test gem_ctx_param:
        Subgroup basic-default:
                dmesg-warn -> PASS       (ro-skl-i7-6700hq)
Test gem_exec_flush:
        Subgroup basic-uc-rw-default:
                pass       -> DMESG-WARN (ro-skl-i7-6700hq)
        Subgroup basic-wb-prw-default:
                dmesg-warn -> PASS       (ro-skl-i7-6700hq)
Test gem_mmap_gtt:
        Subgroup basic-small-copy-xy:
                pass       -> DMESG-WARN (ro-skl-i7-6700hq)
        Subgroup basic-write:
                pass       -> DMESG-WARN (ro-skl-i7-6700hq)
        Subgroup basic-write-gtt-no-prefault:
                dmesg-warn -> PASS       (ro-skl-i7-6700hq)
Test gem_storedw_loop:
        Subgroup basic-render:
                dmesg-warn -> PASS       (ro-skl-i7-6700hq)
Test gem_tiled_pread_basic:
                dmesg-warn -> PASS       (ro-skl-i7-6700hq)
Test kms_addfb_basic:
        Subgroup addfb25-bad-modifier:
                dmesg-warn -> PASS       (ro-skl-i7-6700hq)
        Subgroup bad-pitch-256:
                pass       -> DMESG-WARN (ro-skl-i7-6700hq)
        Subgroup bad-pitch-63:
                pass       -> DMESG-WARN (ro-skl-i7-6700hq)
        Subgroup framebuffer-vs-set-tiling:
                pass       -> DMESG-WARN (ro-skl-i7-6700hq)
        Subgroup no-handle:
                pass       -> DMESG-WARN (ro-skl-i7-6700hq)
        Subgroup size-max:
                pass       -> DMESG-WARN (ro-skl-i7-6700hq)
        Subgroup too-wide:
                dmesg-warn -> PASS       (ro-skl-i7-6700hq)
Test kms_sink_crc_basic:
                pass       -> DMESG-WARN (ro-skl-i7-6700hq)

fi-bdw-i7-5557u  total:102  pass:93   dwarn:0   dfail:0   fail:0   skip:8  
fi-hsw-i7-4770k  total:209  pass:187  dwarn:0   dfail:0   fail:3   skip:19 
fi-skl-i5-6260u  total:209  pass:198  dwarn:0   dfail:0   fail:0   skip:11 
fi-skl-i7-6700k  total:209  pass:184  dwarn:0   dfail:0   fail:0   skip:25 
fi-snb-i7-2600   total:209  pass:167  dwarn:0   dfail:0   fail:3   skip:39 
ro-bdw-i5-5250u  total:102  pass:93   dwarn:0   dfail:0   fail:0   skip:8  
ro-bdw-i7-5600u  total:102  pass:75   dwarn:0   dfail:0   fail:0   skip:26 
ro-byt-n2820     total:209  pass:169  dwarn:0   dfail:0   fail:3   skip:37 
ro-hsw-i3-4010u  total:209  pass:186  dwarn:0   dfail:0   fail:0   skip:23 
ro-hsw-i7-4770r  total:102  pass:82   dwarn:0   dfail:0   fail:0   skip:19 
ro-ilk-i7-620lm  total:1    pass:0    dwarn:0   dfail:0   fail:0   skip:0  
ro-ilk1-i5-650   total:204  pass:146  dwarn:0   dfail:0   fail:1   skip:57 
ro-ivb2-i7-3770  total:102  pass:79   dwarn:0   dfail:0   fail:0   skip:22 
ro-skl-i7-6700hq total:204  pass:170  dwarn:13  dfail:0   fail:0   skip:21 
ro-snb-i7-2620M  total:102  pass:72   dwarn:0   dfail:0   fail:0   skip:29 
ro-bdw-i7-5557U failed to connect after reboot
ro-ivb-i7-3770 failed to connect after reboot

Results at /archive/results/CI_IGT_test/RO_Patchwork_1093/

357b87b drm-intel-nightly: 2016y-06m-03d-08h-46m-18s UTC integration manifest
866e10d drm/i915/bxt: Add WaDisablePooledEuLoadBalancingFix
66ccd7e drm/i915/bxt: Add WaEnablePooledEuFor2x6
723702b drm/i915:bxt: Enable Pooled EU support

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: ✗ Ro.CI.BAT: warning for BXT Pooled EU kernel support and WA patches (rev3)

[Arun Siluvery]

On 03/06/2016 16:28, Patchwork wrote:
> == Series Details ==
>
> Series: BXT Pooled EU kernel support and WA patches (rev3)
> URL   : https://patchwork.freedesktop.org/series/8200/
> State : warning
>
> == Summary ==
>
> Series 8200v3 BXT Pooled EU kernel support and WA patches
> http://patchwork.freedesktop.org/api/1.0/series/8200/revisions/3/mbox
>
> Test gem_busy:
>          Subgroup basic-parallel-render:
>                  pass       -> DMESG-WARN (ro-skl-i7-6700hq)
> Test gem_close_race:
>          Subgroup basic-process:
>                  pass       -> DMESG-WARN (ro-skl-i7-6700hq)
> Test gem_ctx_param:
>          Subgroup basic-default:
>                  dmesg-warn -> PASS       (ro-skl-i7-6700hq)
> Test gem_exec_flush:
>          Subgroup basic-uc-rw-default:
>                  pass       -> DMESG-WARN (ro-skl-i7-6700hq)
>          Subgroup basic-wb-prw-default:
>                  dmesg-warn -> PASS       (ro-skl-i7-6700hq)
> Test gem_mmap_gtt:
>          Subgroup basic-small-copy-xy:
>                  pass       -> DMESG-WARN (ro-skl-i7-6700hq)
>          Subgroup basic-write:
>                  pass       -> DMESG-WARN (ro-skl-i7-6700hq)
>          Subgroup basic-write-gtt-no-prefault:
>                  dmesg-warn -> PASS       (ro-skl-i7-6700hq)
> Test gem_storedw_loop:
>          Subgroup basic-render:
>                  dmesg-warn -> PASS       (ro-skl-i7-6700hq)
> Test gem_tiled_pread_basic:
>                  dmesg-warn -> PASS       (ro-skl-i7-6700hq)
> Test kms_addfb_basic:
>          Subgroup addfb25-bad-modifier:
>                  dmesg-warn -> PASS       (ro-skl-i7-6700hq)
>          Subgroup bad-pitch-256:
>                  pass       -> DMESG-WARN (ro-skl-i7-6700hq)
>          Subgroup bad-pitch-63:
>                  pass       -> DMESG-WARN (ro-skl-i7-6700hq)
>          Subgroup framebuffer-vs-set-tiling:
>                  pass       -> DMESG-WARN (ro-skl-i7-6700hq)
>          Subgroup no-handle:
>                  pass       -> DMESG-WARN (ro-skl-i7-6700hq)
>          Subgroup size-max:
>                  pass       -> DMESG-WARN (ro-skl-i7-6700hq)
>          Subgroup too-wide:
>                  dmesg-warn -> PASS       (ro-skl-i7-6700hq)
> Test kms_sink_crc_basic:
>                  pass       -> DMESG-WARN (ro-skl-i7-6700hq)
>

All dmesg-warn are because of a single known issue,

[BAT SKL] *ERROR* Potential atomic update failure on pipe A
https://bugs.freedesktop.org/show_bug.cgi?id=95632

These patches only affect BXT.

regards
Arun

> fi-bdw-i7-5557u  total:102  pass:93   dwarn:0   dfail:0   fail:0   skip:8
> fi-hsw-i7-4770k  total:209  pass:187  dwarn:0   dfail:0   fail:3   skip:19
> fi-skl-i5-6260u  total:209  pass:198  dwarn:0   dfail:0   fail:0   skip:11
> fi-skl-i7-6700k  total:209  pass:184  dwarn:0   dfail:0   fail:0   skip:25
> fi-snb-i7-2600   total:209  pass:167  dwarn:0   dfail:0   fail:3   skip:39
> ro-bdw-i5-5250u  total:102  pass:93   dwarn:0   dfail:0   fail:0   skip:8
> ro-bdw-i7-5600u  total:102  pass:75   dwarn:0   dfail:0   fail:0   skip:26
> ro-byt-n2820     total:209  pass:169  dwarn:0   dfail:0   fail:3   skip:37
> ro-hsw-i3-4010u  total:209  pass:186  dwarn:0   dfail:0   fail:0   skip:23
> ro-hsw-i7-4770r  total:102  pass:82   dwarn:0   dfail:0   fail:0   skip:19
> ro-ilk-i7-620lm  total:1    pass:0    dwarn:0   dfail:0   fail:0   skip:0
> ro-ilk1-i5-650   total:204  pass:146  dwarn:0   dfail:0   fail:1   skip:57
> ro-ivb2-i7-3770  total:102  pass:79   dwarn:0   dfail:0   fail:0   skip:22
> ro-skl-i7-6700hq total:204  pass:170  dwarn:13  dfail:0   fail:0   skip:21
> ro-snb-i7-2620M  total:102  pass:72   dwarn:0   dfail:0   fail:0   skip:29
> ro-bdw-i7-5557U failed to connect after reboot
> ro-ivb-i7-3770 failed to connect after reboot
>
> Results at /archive/results/CI_IGT_test/RO_Patchwork_1093/
>
> 357b87b drm-intel-nightly: 2016y-06m-03d-08h-46m-18s UTC integration manifest
> 866e10d drm/i915/bxt: Add WaDisablePooledEuLoadBalancingFix
> 66ccd7e drm/i915/bxt: Add WaEnablePooledEuFor2x6
> 723702b drm/i915:bxt: Enable Pooled EU support
>
>

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [PATCH v2 1/3] drm/i915:bxt: Enable Pooled EU support

[Michał Winiarski]

On Fri, Jun 03, 2016 at 06:34:33AM +0100, Arun Siluvery wrote:
> This mode allows to assign EUs to pools which can process work collectively.
> The command to enable this mode should be issued as part of context initialization.
> 
> The pooled mode is global, once enabled it has to stay the same across all
> contexts until HW reset hence this is sent in auxiliary golden context batch.
> Thanks to Mika for the preliminary review and comments.
> 
> v2: explain why this is enabled in golden context, use feature flag while
> enabling the support (Chris)
> 
> v3: Include only kernel support as userspace support is not available yet.
> 
> User space clients need to know when the pooled EU feature is present
> and enabled on the hardware so that they can adapt work submissions.
> Create a new device info flag for this purpose.
> 
> Set has_pooled_eu to true in the Broxton static device info - Broxton
> supports the feature in hardware and the driver will enable it by
> default.
> 
> We need to add getparam ioctls to enable userspace to query availability of
> this feature and to retrieve min. no of eus in a pool but we will expose
> them once userspace support is available. Opensource users for this feature
> are mesa, libva and beignet.
> 
> Beignet team is currently working on adding userspace support.
> 
> Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk> (v2)

Reviewed-by: Michał Winiarski <michal.winiarski@intel.com>

-Michał

> Cc: Winiarski, Michal <michal.winiarski@intel.com>
> Cc: Zou, Nanhai <nanhai.zou@intel.com>
> Cc: Yang, Rong R <rong.r.yang@intel.com>
> Cc: Mika Kuoppala <mika.kuoppala@intel.com>
> Cc: Chris Wilson <chris@chris-wilson.co.uk>
> Cc: Armin Reese <armin.c.reese@intel.com>
> Cc: Tim Gore <tim.gore@intel.com>
> Signed-off-by: Jeff McGee <jeff.mcgee@intel.com>
> Signed-off-by: Arun Siluvery <arun.siluvery@linux.intel.com>
> ---
>  drivers/gpu/drm/i915/i915_debugfs.c          |  4 ++++
>  drivers/gpu/drm/i915/i915_dma.c              | 19 +++++++++++++++++++
>  drivers/gpu/drm/i915/i915_drv.c              |  1 +
>  drivers/gpu/drm/i915/i915_drv.h              |  6 +++++-
>  drivers/gpu/drm/i915/i915_gem_render_state.c | 28 ++++++++++++++++++++++++++++
>  drivers/gpu/drm/i915/i915_reg.h              |  2 ++
>  6 files changed, 59 insertions(+), 1 deletion(-)
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: ✗ Ro.CI.BAT: warning for BXT Pooled EU kernel support and WA patches (rev3)

[Tvrtko Ursulin]

On 06/06/16 07:26, Arun Siluvery wrote:
> On 03/06/2016 16:28, Patchwork wrote:
>> == Series Details ==
>>
>> Series: BXT Pooled EU kernel support and WA patches (rev3)
>> URL   : https://patchwork.freedesktop.org/series/8200/
>> State : warning
>>
>> == Summary ==
>>
>> Series 8200v3 BXT Pooled EU kernel support and WA patches
>> http://patchwork.freedesktop.org/api/1.0/series/8200/revisions/3/mbox
>>
>> Test gem_busy:
>>          Subgroup basic-parallel-render:
>>                  pass       -> DMESG-WARN (ro-skl-i7-6700hq)
>> Test gem_close_race:
>>          Subgroup basic-process:
>>                  pass       -> DMESG-WARN (ro-skl-i7-6700hq)
>> Test gem_ctx_param:
>>          Subgroup basic-default:
>>                  dmesg-warn -> PASS       (ro-skl-i7-6700hq)
>> Test gem_exec_flush:
>>          Subgroup basic-uc-rw-default:
>>                  pass       -> DMESG-WARN (ro-skl-i7-6700hq)
>>          Subgroup basic-wb-prw-default:
>>                  dmesg-warn -> PASS       (ro-skl-i7-6700hq)
>> Test gem_mmap_gtt:
>>          Subgroup basic-small-copy-xy:
>>                  pass       -> DMESG-WARN (ro-skl-i7-6700hq)
>>          Subgroup basic-write:
>>                  pass       -> DMESG-WARN (ro-skl-i7-6700hq)
>>          Subgroup basic-write-gtt-no-prefault:
>>                  dmesg-warn -> PASS       (ro-skl-i7-6700hq)
>> Test gem_storedw_loop:
>>          Subgroup basic-render:
>>                  dmesg-warn -> PASS       (ro-skl-i7-6700hq)
>> Test gem_tiled_pread_basic:
>>                  dmesg-warn -> PASS       (ro-skl-i7-6700hq)
>> Test kms_addfb_basic:
>>          Subgroup addfb25-bad-modifier:
>>                  dmesg-warn -> PASS       (ro-skl-i7-6700hq)
>>          Subgroup bad-pitch-256:
>>                  pass       -> DMESG-WARN (ro-skl-i7-6700hq)
>>          Subgroup bad-pitch-63:
>>                  pass       -> DMESG-WARN (ro-skl-i7-6700hq)
>>          Subgroup framebuffer-vs-set-tiling:
>>                  pass       -> DMESG-WARN (ro-skl-i7-6700hq)
>>          Subgroup no-handle:
>>                  pass       -> DMESG-WARN (ro-skl-i7-6700hq)
>>          Subgroup size-max:
>>                  pass       -> DMESG-WARN (ro-skl-i7-6700hq)
>>          Subgroup too-wide:
>>                  dmesg-warn -> PASS       (ro-skl-i7-6700hq)
>> Test kms_sink_crc_basic:
>>                  pass       -> DMESG-WARN (ro-skl-i7-6700hq)
>>
>
> All dmesg-warn are because of a single known issue,
>
> [BAT SKL] *ERROR* Potential atomic update failure on pipe A
> https://bugs.freedesktop.org/show_bug.cgi?id=95632
>
> These patches only affect BXT.
>
> regards
> Arun
>
>> fi-bdw-i7-5557u  total:102  pass:93   dwarn:0   dfail:0   fail:0   skip:8
>> fi-hsw-i7-4770k  total:209  pass:187  dwarn:0   dfail:0   fail:3
>> skip:19
>> fi-skl-i5-6260u  total:209  pass:198  dwarn:0   dfail:0   fail:0
>> skip:11
>> fi-skl-i7-6700k  total:209  pass:184  dwarn:0   dfail:0   fail:0
>> skip:25
>> fi-snb-i7-2600   total:209  pass:167  dwarn:0   dfail:0   fail:3
>> skip:39
>> ro-bdw-i5-5250u  total:102  pass:93   dwarn:0   dfail:0   fail:0   skip:8
>> ro-bdw-i7-5600u  total:102  pass:75   dwarn:0   dfail:0   fail:0
>> skip:26
>> ro-byt-n2820     total:209  pass:169  dwarn:0   dfail:0   fail:3
>> skip:37
>> ro-hsw-i3-4010u  total:209  pass:186  dwarn:0   dfail:0   fail:0
>> skip:23
>> ro-hsw-i7-4770r  total:102  pass:82   dwarn:0   dfail:0   fail:0
>> skip:19
>> ro-ilk-i7-620lm  total:1    pass:0    dwarn:0   dfail:0   fail:0   skip:0
>> ro-ilk1-i5-650   total:204  pass:146  dwarn:0   dfail:0   fail:1
>> skip:57
>> ro-ivb2-i7-3770  total:102  pass:79   dwarn:0   dfail:0   fail:0
>> skip:22
>> ro-skl-i7-6700hq total:204  pass:170  dwarn:13  dfail:0   fail:0
>> skip:21
>> ro-snb-i7-2620M  total:102  pass:72   dwarn:0   dfail:0   fail:0
>> skip:29
>> ro-bdw-i7-5557U failed to connect after reboot
>> ro-ivb-i7-3770 failed to connect after reboot
>>
>> Results at /archive/results/CI_IGT_test/RO_Patchwork_1093/
>>
>> 357b87b drm-intel-nightly: 2016y-06m-03d-08h-46m-18s UTC integration
>> manifest
>> 866e10d drm/i915/bxt: Add WaDisablePooledEuLoadBalancingFix
>> 66ccd7e drm/i915/bxt: Add WaEnablePooledEuFor2x6
>> 723702b drm/i915:bxt: Enable Pooled EU support

Merged to dinq, thanks for the patches and review.

Regards,

Tvrtko
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx