From mboxrd@z Thu Jan 1 00:00:00 1970 From: Lyude Subject: [PATCH RESEND 2/3] drm/i915/vlv: Reset the ADPA in vlv_display_power_well_init() Date: Fri, 17 Jun 2016 17:58:23 -0400 Message-ID: <1466200705-9405-3-git-send-email-cpaul@redhat.com> References: <1466200705-9405-1-git-send-email-cpaul@redhat.com> Mime-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: QUOTED-PRINTABLE Return-path: In-Reply-To: <1466200705-9405-1-git-send-email-cpaul@redhat.com> Sender: stable-owner@vger.kernel.org To: intel-gfx@lists.freedesktop.org Cc: Lyude , stable@vger.kernel.org, =?UTF-8?q?Ville=20Syrj=C3=A4l=C3=A4?= , Daniel Vetter , Jani Nikula , David Airlie , "open list:INTEL DRM DRIVERS excluding Poulsbo, Moorestow..., linux-kernel@vger.kernel.org open list" List-Id: intel-gfx@lists.freedesktop.org While VGA hotplugging worked(ish) before, it looks like that was mainly because we'd unintentionally enable it in valleyview_crt_detect_hotplug() when we did a force trigger. This doesn't work reliably enough because whenever the display powerwell on vlv gets disabled, the values set in VLV_ADPA get cleared and consequently VGA hotplugging gets disabled. This causes bugs such as on= e we found on an Intel NUC, where doing the following sequence of hotplugs: - Disconnect all monitors - Connect VGA - Disconnect VGA - Connect HDMI Would result in VGA hotplugging becoming disabled, due to the powerwell= s getting toggled in the process of connecting HDMI. Changes since v3: - Expose intel_crt_reset() through intel_drv.h and call that in vlv_display_power_well_init() instead of encoder->base.funcs->reset(&encoder->base); Changes since v2: - Use intel_encoder structs instead of drm_encoder structs Changes since v1: - Instead of handling the register writes ourself, we just reuse intel_crt_detect() - Instead of resetting the ADPA during display IRQ installation, we no= w reset them in vlv_display_power_well_init() Cc: stable@vger.kernel.org Cc: Ville Syrj=C3=A4l=C3=A4 Cc: Daniel Vetter Signed-off-by: Lyude Reviewed-by: Ville Syrj=C3=A4l=C3=A4 --- drivers/gpu/drm/i915/intel_crt.c | 2 +- drivers/gpu/drm/i915/intel_drv.h | 2 +- drivers/gpu/drm/i915/intel_runtime_pm.c | 7 +++++++ 3 files changed, 9 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_crt.c b/drivers/gpu/drm/i915/in= tel_crt.c index e4dc33e..d0fb961 100644 --- a/drivers/gpu/drm/i915/intel_crt.c +++ b/drivers/gpu/drm/i915/intel_crt.c @@ -713,7 +713,7 @@ static int intel_crt_set_property(struct drm_connec= tor *connector, return 0; } =20 -static void intel_crt_reset(struct drm_encoder *encoder) +void intel_crt_reset(struct drm_encoder *encoder) { struct drm_device *dev =3D encoder->dev; struct drm_i915_private *dev_priv =3D dev->dev_private; diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/in= tel_drv.h index 4a24b00..fdec45d 100644 --- a/drivers/gpu/drm/i915/intel_drv.h +++ b/drivers/gpu/drm/i915/intel_drv.h @@ -1054,7 +1054,7 @@ void gen8_irq_power_well_pre_disable(struct drm_i= 915_private *dev_priv, =20 /* intel_crt.c */ void intel_crt_init(struct drm_device *dev); - +void intel_crt_reset(struct drm_encoder *encoder); =20 /* intel_ddi.c */ void intel_ddi_clk_select(struct intel_encoder *encoder, diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c b/drivers/gpu/drm/= i915/intel_runtime_pm.c index 7fb1da4..4a3fd3a 100644 --- a/drivers/gpu/drm/i915/intel_runtime_pm.c +++ b/drivers/gpu/drm/i915/intel_runtime_pm.c @@ -952,6 +952,7 @@ static void vlv_init_display_clock_gating(struct dr= m_i915_private *dev_priv) =20 static void vlv_display_power_well_init(struct drm_i915_private *dev_p= riv) { + struct intel_encoder *encoder; enum pipe pipe; =20 /* @@ -987,6 +988,12 @@ static void vlv_display_power_well_init(struct drm= _i915_private *dev_priv) =20 intel_hpd_init(dev_priv); =20 + /* Re-enable the ADPA, if we have one */ + for_each_intel_encoder(dev_priv->dev, encoder) { + if (encoder->type =3D=3D INTEL_OUTPUT_ANALOG) + intel_crt_reset(&encoder->base); + } + i915_redisable_vga_power_on(dev_priv->dev); } =20 --=20 2.5.5