From: Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com>
To: Intel-gfx@lists.freedesktop.org
Subject: [PATCH 04/13] drm/i915: Consolidate get and put irq vfuncs
Date: Mon, 27 Jun 2016 15:04:11 +0100 [thread overview]
Message-ID: <1467036260-9252-5-git-send-email-tvrtko.ursulin@linux.intel.com> (raw)
In-Reply-To: <1467036260-9252-1-git-send-email-tvrtko.ursulin@linux.intel.com>
From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
---
drivers/gpu/drm/i915/intel_ringbuffer.c | 46 ++++++++++++---------------------
1 file changed, 17 insertions(+), 29 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
index a4391cbbb2b6..5dddcdd2570d 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.c
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
@@ -2884,6 +2884,23 @@ static void intel_ring_default_vfuncs(struct drm_i915_private *dev_priv,
} else {
engine->add_request = i9xx_add_request;
}
+
+ if (INTEL_GEN(dev_priv) >= 8) {
+ engine->irq_get = gen8_ring_get_irq;
+ engine->irq_put = gen8_ring_put_irq;
+ } else if (INTEL_GEN(dev_priv) >= 6) {
+ engine->irq_get = gen6_ring_get_irq;
+ engine->irq_put = gen6_ring_put_irq;
+ } else if (IS_GEN5(dev_priv)) {
+ engine->irq_get = gen5_ring_get_irq;
+ engine->irq_put = gen5_ring_put_irq;
+ } else if (INTEL_GEN(dev_priv) >= 3) {
+ engine->irq_get = i9xx_ring_get_irq;
+ engine->irq_put = i9xx_ring_put_irq;
+ } else if (IS_GEN2(dev_priv)) {
+ engine->irq_get = i8xx_ring_get_irq;
+ engine->irq_put = i8xx_ring_put_irq;
+ }
}
int intel_init_render_ring_buffer(struct drm_device *dev)
@@ -2922,8 +2939,6 @@ int intel_init_render_ring_buffer(struct drm_device *dev)
engine->init_context = intel_rcs_ctx_init;
engine->add_request = gen8_render_add_request;
engine->flush = gen8_render_ring_flush;
- engine->irq_get = gen8_ring_get_irq;
- engine->irq_put = gen8_ring_put_irq;
engine->irq_enable_mask = GT_RENDER_USER_INTERRUPT;
engine->get_seqno = ring_get_seqno;
engine->set_seqno = ring_set_seqno;
@@ -2938,8 +2953,6 @@ int intel_init_render_ring_buffer(struct drm_device *dev)
engine->flush = gen7_render_ring_flush;
if (IS_GEN6(dev_priv))
engine->flush = gen6_render_ring_flush;
- engine->irq_get = gen6_ring_get_irq;
- engine->irq_put = gen6_ring_put_irq;
engine->irq_enable_mask = GT_RENDER_USER_INTERRUPT;
engine->get_seqno = ring_get_seqno;
engine->set_seqno = ring_set_seqno;
@@ -2969,8 +2982,6 @@ int intel_init_render_ring_buffer(struct drm_device *dev)
engine->flush = gen4_render_ring_flush;
engine->get_seqno = pc_render_get_seqno;
engine->set_seqno = pc_render_set_seqno;
- engine->irq_get = gen5_ring_get_irq;
- engine->irq_put = gen5_ring_put_irq;
engine->irq_enable_mask = GT_RENDER_USER_INTERRUPT |
GT_RENDER_PIPECTL_NOTIFY_INTERRUPT;
} else {
@@ -2980,13 +2991,6 @@ int intel_init_render_ring_buffer(struct drm_device *dev)
engine->flush = gen4_render_ring_flush;
engine->get_seqno = ring_get_seqno;
engine->set_seqno = ring_set_seqno;
- if (IS_GEN2(dev_priv)) {
- engine->irq_get = i8xx_ring_get_irq;
- engine->irq_put = i8xx_ring_put_irq;
- } else {
- engine->irq_get = i9xx_ring_get_irq;
- engine->irq_put = i9xx_ring_put_irq;
- }
engine->irq_enable_mask = I915_USER_INTERRUPT;
}
@@ -3060,8 +3064,6 @@ int intel_init_bsd_ring_buffer(struct drm_device *dev)
if (INTEL_GEN(dev_priv) >= 8) {
engine->irq_enable_mask =
GT_RENDER_USER_INTERRUPT << GEN8_VCS1_IRQ_SHIFT;
- engine->irq_get = gen8_ring_get_irq;
- engine->irq_put = gen8_ring_put_irq;
engine->dispatch_execbuffer =
gen8_ring_dispatch_execbuffer;
if (i915_semaphore_is_enabled(dev_priv)) {
@@ -3071,8 +3073,6 @@ int intel_init_bsd_ring_buffer(struct drm_device *dev)
}
} else {
engine->irq_enable_mask = GT_BSD_USER_INTERRUPT;
- engine->irq_get = gen6_ring_get_irq;
- engine->irq_put = gen6_ring_put_irq;
engine->dispatch_execbuffer =
gen6_ring_dispatch_execbuffer;
if (i915_semaphore_is_enabled(dev_priv)) {
@@ -3097,12 +3097,8 @@ int intel_init_bsd_ring_buffer(struct drm_device *dev)
engine->set_seqno = ring_set_seqno;
if (IS_GEN5(dev_priv)) {
engine->irq_enable_mask = ILK_BSD_USER_INTERRUPT;
- engine->irq_get = gen5_ring_get_irq;
- engine->irq_put = gen5_ring_put_irq;
} else {
engine->irq_enable_mask = I915_BSD_USER_INTERRUPT;
- engine->irq_get = i9xx_ring_get_irq;
- engine->irq_put = i9xx_ring_put_irq;
}
engine->dispatch_execbuffer = i965_dispatch_execbuffer;
}
@@ -3132,8 +3128,6 @@ int intel_init_bsd2_ring_buffer(struct drm_device *dev)
engine->set_seqno = ring_set_seqno;
engine->irq_enable_mask =
GT_RENDER_USER_INTERRUPT << GEN8_VCS2_IRQ_SHIFT;
- engine->irq_get = gen8_ring_get_irq;
- engine->irq_put = gen8_ring_put_irq;
engine->dispatch_execbuffer =
gen8_ring_dispatch_execbuffer;
if (i915_semaphore_is_enabled(dev_priv)) {
@@ -3165,8 +3159,6 @@ int intel_init_blt_ring_buffer(struct drm_device *dev)
if (INTEL_GEN(dev_priv) >= 8) {
engine->irq_enable_mask =
GT_RENDER_USER_INTERRUPT << GEN8_BCS_IRQ_SHIFT;
- engine->irq_get = gen8_ring_get_irq;
- engine->irq_put = gen8_ring_put_irq;
engine->dispatch_execbuffer = gen8_ring_dispatch_execbuffer;
if (i915_semaphore_is_enabled(dev_priv)) {
engine->semaphore.sync_to = gen8_ring_sync;
@@ -3175,8 +3167,6 @@ int intel_init_blt_ring_buffer(struct drm_device *dev)
}
} else {
engine->irq_enable_mask = GT_BLT_USER_INTERRUPT;
- engine->irq_get = gen6_ring_get_irq;
- engine->irq_put = gen6_ring_put_irq;
engine->dispatch_execbuffer = gen6_ring_dispatch_execbuffer;
if (i915_semaphore_is_enabled(dev_priv)) {
engine->semaphore.signal = gen6_signal;
@@ -3225,8 +3215,6 @@ int intel_init_vebox_ring_buffer(struct drm_device *dev)
if (INTEL_GEN(dev_priv) >= 8) {
engine->irq_enable_mask =
GT_RENDER_USER_INTERRUPT << GEN8_VECS_IRQ_SHIFT;
- engine->irq_get = gen8_ring_get_irq;
- engine->irq_put = gen8_ring_put_irq;
engine->dispatch_execbuffer = gen8_ring_dispatch_execbuffer;
if (i915_semaphore_is_enabled(dev_priv)) {
engine->semaphore.sync_to = gen8_ring_sync;
--
1.9.1
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next prev parent reply other threads:[~2016-06-27 14:04 UTC|newest]
Thread overview: 20+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-06-27 14:04 [PATCH 00/13] Legacy engine initialization refactoring Tvrtko Ursulin
2016-06-27 14:04 ` [PATCH 01/13] drm/i915: Consolidate write_tail vfunc initializer Tvrtko Ursulin
2016-06-27 14:04 ` [PATCH 02/13] drm/i915: Consolidate add_request vfunc Tvrtko Ursulin
2016-06-27 14:04 ` [PATCH 03/13] drm/i915: Consolidate seqno_barrier vfunc Tvrtko Ursulin
2016-06-27 14:04 ` Tvrtko Ursulin [this message]
2016-06-28 11:58 ` [PATCH 04/13] drm/i915: Consolidate get and put irq vfuncs Chris Wilson
2016-06-27 14:04 ` [PATCH 05/13] drm/i915: Consolidate get/set_seqno Tvrtko Ursulin
2016-06-27 14:04 ` [PATCH 06/13] drm/i915: Consolidate init_hw vfunc Tvrtko Ursulin
2016-06-27 14:04 ` [PATCH 07/13] drm/i915: Consolidate dispatch_execbuffer vfunc Tvrtko Ursulin
2016-06-28 11:59 ` Chris Wilson
2016-06-27 14:04 ` [PATCH 08/13] drm/i915: Consolidate semaphore vfuncs init Tvrtko Ursulin
2016-06-27 14:04 ` [PATCH 09/13] drm/i915: Compact Gen8 semaphore initialization Tvrtko Ursulin
2016-06-28 12:05 ` Chris Wilson
2016-06-27 14:04 ` [PATCH 10/13] drm/i915: Compact gen8_ring_sync Tvrtko Ursulin
2016-06-27 14:04 ` [PATCH 11/13] drm/i915: Consolidate legacy semaphore initialization Tvrtko Ursulin
2016-06-27 14:04 ` [PATCH 12/13] drm/i915: Remove redundant warning and consolidate gen8 render semaphore vfunc Tvrtko Ursulin
2016-06-27 14:04 ` [PATCH 13/13] drm/i915: Trim some if-else braces Tvrtko Ursulin
2016-06-27 14:31 ` ✗ Ro.CI.BAT: failure for Legacy engine initialization refactoring Patchwork
2016-06-28 12:10 ` [PATCH 00/13] " Chris Wilson
-- strict thread matches above, loose matches on Subject: below --
2016-06-29 15:09 [PATCH 01/13] drm/i915: Consolidate write_tail vfunc initializer Tvrtko Ursulin
2016-06-29 15:09 ` [PATCH 04/13] drm/i915: Consolidate get and put irq vfuncs Tvrtko Ursulin
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