public inbox for intel-gfx@lists.freedesktop.org
 help / color / mirror / Atom feed
From: Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com>
To: Intel-gfx@lists.freedesktop.org
Subject: [PATCH 05/13] drm/i915: Consolidate get/set_seqno
Date: Wed, 29 Jun 2016 16:09:24 +0100	[thread overview]
Message-ID: <1467212972-861-5-git-send-email-tvrtko.ursulin@linux.intel.com> (raw)
In-Reply-To: <1467212972-861-1-git-send-email-tvrtko.ursulin@linux.intel.com>

From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>

Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
---
 drivers/gpu/drm/i915/intel_ringbuffer.c | 18 ++----------------
 1 file changed, 2 insertions(+), 16 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
index 8d9e2e24f67d..e0e90b99bbca 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.c
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
@@ -2877,6 +2877,8 @@ static void intel_ring_default_vfuncs(struct drm_i915_private *dev_priv,
 				      struct intel_engine_cs *engine)
 {
 	engine->write_tail = ring_write_tail;
+	engine->get_seqno = ring_get_seqno;
+	engine->set_seqno = ring_set_seqno;
 
 	if (INTEL_GEN(dev_priv) >= 6) {
 		engine->add_request = gen6_add_request;
@@ -2940,8 +2942,6 @@ int intel_init_render_ring_buffer(struct drm_device *dev)
 		engine->add_request = gen8_render_add_request;
 		engine->flush = gen8_render_ring_flush;
 		engine->irq_enable_mask = GT_RENDER_USER_INTERRUPT;
-		engine->get_seqno = ring_get_seqno;
-		engine->set_seqno = ring_set_seqno;
 		if (i915_semaphore_is_enabled(dev_priv)) {
 			WARN_ON(!dev_priv->semaphore_obj);
 			engine->semaphore.sync_to = gen8_ring_sync;
@@ -2954,8 +2954,6 @@ int intel_init_render_ring_buffer(struct drm_device *dev)
 		if (IS_GEN6(dev_priv))
 			engine->flush = gen6_render_ring_flush;
 		engine->irq_enable_mask = GT_RENDER_USER_INTERRUPT;
-		engine->get_seqno = ring_get_seqno;
-		engine->set_seqno = ring_set_seqno;
 		if (i915_semaphore_is_enabled(dev_priv)) {
 			engine->semaphore.sync_to = gen6_ring_sync;
 			engine->semaphore.signal = gen6_signal;
@@ -2989,8 +2987,6 @@ int intel_init_render_ring_buffer(struct drm_device *dev)
 			engine->flush = gen2_render_ring_flush;
 		else
 			engine->flush = gen4_render_ring_flush;
-		engine->get_seqno = ring_get_seqno;
-		engine->set_seqno = ring_set_seqno;
 		engine->irq_enable_mask = I915_USER_INTERRUPT;
 	}
 
@@ -3059,8 +3055,6 @@ int intel_init_bsd_ring_buffer(struct drm_device *dev)
 		if (IS_GEN6(dev_priv))
 			engine->write_tail = gen6_bsd_ring_write_tail;
 		engine->flush = gen6_bsd_ring_flush;
-		engine->get_seqno = ring_get_seqno;
-		engine->set_seqno = ring_set_seqno;
 		if (INTEL_GEN(dev_priv) >= 8) {
 			engine->irq_enable_mask =
 				GT_RENDER_USER_INTERRUPT << GEN8_VCS1_IRQ_SHIFT;
@@ -3093,8 +3087,6 @@ int intel_init_bsd_ring_buffer(struct drm_device *dev)
 	} else {
 		engine->mmio_base = BSD_RING_BASE;
 		engine->flush = bsd_ring_flush;
-		engine->get_seqno = ring_get_seqno;
-		engine->set_seqno = ring_set_seqno;
 		if (IS_GEN5(dev_priv)) {
 			engine->irq_enable_mask = ILK_BSD_USER_INTERRUPT;
 		} else {
@@ -3124,8 +3116,6 @@ int intel_init_bsd2_ring_buffer(struct drm_device *dev)
 	intel_ring_default_vfuncs(dev_priv, engine);
 
 	engine->flush = gen6_bsd_ring_flush;
-	engine->get_seqno = ring_get_seqno;
-	engine->set_seqno = ring_set_seqno;
 	engine->irq_enable_mask =
 			GT_RENDER_USER_INTERRUPT << GEN8_VCS2_IRQ_SHIFT;
 	engine->dispatch_execbuffer =
@@ -3154,8 +3144,6 @@ int intel_init_blt_ring_buffer(struct drm_device *dev)
 	intel_ring_default_vfuncs(dev_priv, engine);
 
 	engine->flush = gen6_ring_flush;
-	engine->get_seqno = ring_get_seqno;
-	engine->set_seqno = ring_set_seqno;
 	if (INTEL_GEN(dev_priv) >= 8) {
 		engine->irq_enable_mask =
 			GT_RENDER_USER_INTERRUPT << GEN8_BCS_IRQ_SHIFT;
@@ -3209,8 +3197,6 @@ int intel_init_vebox_ring_buffer(struct drm_device *dev)
 	intel_ring_default_vfuncs(dev_priv, engine);
 
 	engine->flush = gen6_ring_flush;
-	engine->get_seqno = ring_get_seqno;
-	engine->set_seqno = ring_set_seqno;
 
 	if (INTEL_GEN(dev_priv) >= 8) {
 		engine->irq_enable_mask =
-- 
1.9.1

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

  parent reply	other threads:[~2016-06-29 15:09 UTC|newest]

Thread overview: 36+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2016-06-29 15:09 [PATCH 01/13] drm/i915: Consolidate write_tail vfunc initializer Tvrtko Ursulin
2016-06-29 15:09 ` [PATCH 02/13] drm/i915: Consolidate add_request vfunc Tvrtko Ursulin
2016-06-29 15:09 ` [PATCH 03/13] drm/i915: Consolidate seqno_barrier vfunc Tvrtko Ursulin
2016-06-29 15:09 ` [PATCH 04/13] drm/i915: Consolidate get and put irq vfuncs Tvrtko Ursulin
2016-06-29 15:09 ` Tvrtko Ursulin [this message]
2016-06-29 15:09 ` [PATCH 06/13] drm/i915: Consolidate init_hw vfunc Tvrtko Ursulin
2016-06-29 15:09 ` [PATCH 07/13] drm/i915: Consolidate dispatch_execbuffer vfunc Tvrtko Ursulin
2016-06-29 16:40   ` [PATCH v3] " Tvrtko Ursulin
2016-06-30 15:12     ` Chris Wilson
2016-06-29 15:09 ` [PATCH 08/13] drm/i915: Consolidate semaphore vfuncs init Tvrtko Ursulin
2016-06-29 15:09 ` [PATCH 09/13] drm/i915: Move semaphore object creation into intel_ring_init_semaphores Tvrtko Ursulin
2016-06-29 15:30   ` Chris Wilson
2016-06-29 15:09 ` [PATCH 10/13] drm/i915: Compact Gen8 semaphore initialization Tvrtko Ursulin
2016-06-29 15:31   ` Chris Wilson
2016-06-29 15:09 ` [PATCH 11/13] drm/i915: Compact gen8_ring_sync Tvrtko Ursulin
2016-06-29 15:33   ` Chris Wilson
2016-06-29 15:09 ` [PATCH 12/13] drm/i915: Consolidate legacy semaphore initialization Tvrtko Ursulin
2016-06-29 15:34   ` Chris Wilson
2016-06-29 15:41     ` Tvrtko Ursulin
2016-06-29 16:00       ` Chris Wilson
2016-06-29 16:14         ` Tvrtko Ursulin
2016-06-29 16:24           ` Chris Wilson
2016-06-29 16:34             ` Tvrtko Ursulin
2016-06-29 16:43               ` Chris Wilson
2016-07-15 13:13         ` Tvrtko Ursulin
2016-07-19 18:38           ` Dave Gordon
2016-07-20  9:54             ` Tvrtko Ursulin
2016-07-20 12:50               ` Dave Gordon
2016-07-20 16:07                 ` Tvrtko Ursulin
2016-07-20 17:08                   ` Dave Gordon
2016-06-29 15:09 ` [PATCH 13/13] drm/i915: Trim some if-else braces Tvrtko Ursulin
2016-06-29 15:35   ` Chris Wilson
2016-06-29 16:06 ` ✗ Ro.CI.BAT: failure for series starting with [01/13] drm/i915: Consolidate write_tail vfunc initializer Patchwork
2016-06-30  5:20 ` ✗ Ro.CI.BAT: warning for series starting with [01/13] drm/i915: Consolidate write_tail vfunc initializer (rev2) Patchwork
2016-06-30  8:44   ` Tvrtko Ursulin
  -- strict thread matches above, loose matches on Subject: below --
2016-06-27 14:04 [PATCH 00/13] Legacy engine initialization refactoring Tvrtko Ursulin
2016-06-27 14:04 ` [PATCH 05/13] drm/i915: Consolidate get/set_seqno Tvrtko Ursulin

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=1467212972-861-5-git-send-email-tvrtko.ursulin@linux.intel.com \
    --to=tvrtko.ursulin@linux.intel.com \
    --cc=Intel-gfx@lists.freedesktop.org \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body. 
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox