From: "Bish, Jim" <jim.bish@intel.com>
To: "intel-gfx@lists.freedesktop.org"
<intel-gfx@lists.freedesktop.org>,
"Deak, Imre" <imre.deak@intel.com>
Cc: "Tamminen, Eero T" <eero.t.tamminen@intel.com>
Subject: Re: [PATCH v3 1/3] drm/i915/gen9: Clean up MOCS table definitions
Date: Fri, 1 Jul 2016 21:23:09 +0000 [thread overview]
Message-ID: <1467408191.2502.3.camel@intel.com> (raw)
In-Reply-To: <1467380406-11954-2-git-send-email-imre.deak@intel.com>
like the cleanup. Perhaps someday we will add more entries and have
the user space consume them :)
Jim
On Fri, 2016-07-01 at 16:40 +0300, Imre Deak wrote:
> Use named struct initializers for clarity. Also fix the target cache
> definition to reflect its role in GEN9 onwards. On GEN8 a TC value of
> 0
> meant ELLC but on GEN9+ it means the TC and LRU controls are taken
> from
> the PTE.
>
> No functional change, igt/gem_mocs_settings still passing after this
> change.
>
> v2: (Chris)
> - Add back the hexa literals for the entries.
> Add note that igt/gem_mocs_settings still passes.
>
> CC: Rong R Yang <rong.r.yang@intel.com>
> CC: Yakui Zhao <yakui.zhao@intel.com>
> CC: Chris Wilson <chris@chris-wilson.co.uk>
> Signed-off-by: Imre Deak <imre.deak@intel.com>
> ---
> drivers/gpu/drm/i915/intel_mocs.c | 88 +++++++++++++++++++++++++++
> ------------
> 1 file changed, 61 insertions(+), 27 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_mocs.c
> b/drivers/gpu/drm/i915/intel_mocs.c
> index 3c1482b..d36e609 100644
> --- a/drivers/gpu/drm/i915/intel_mocs.c
> +++ b/drivers/gpu/drm/i915/intel_mocs.c
> @@ -66,9 +66,10 @@ struct drm_i915_mocs_table {
> #define L3_WB 3
>
> /* Target cache */
> -#define ELLC 0
> -#define LLC 1
> -#define LLC_ELLC 2
> +#define LE_TC_PAGETABLE 0
> +#define LE_TC_LLC 1
> +#define LE_TC_LLC_ELLC 2
> +#define LE_TC_LLC_ELLC_ALT 3
>
> /*
> * MOCS tables
> @@ -96,34 +97,67 @@ struct drm_i915_mocs_table {
> * end.
> */
> static const struct drm_i915_mocs_entry skylake_mocs_table[] = {
> - /* { 0x00000009, 0x0010 } */
> - { (LE_CACHEABILITY(LE_UC) | LE_TGT_CACHE(LLC_ELLC) |
> LE_LRUM(0) |
> - LE_AOM(0) | LE_RSC(0) | LE_SCC(0) | LE_PFM(0) |
> LE_SCF(0)),
> - (L3_ESC(0) | L3_SCC(0) | L3_CACHEABILITY(L3_UC)) },
> - /* { 0x00000038, 0x0030 } */
> - { (LE_CACHEABILITY(LE_PAGETABLE) | LE_TGT_CACHE(LLC_ELLC) |
> LE_LRUM(3) |
> - LE_AOM(0) | LE_RSC(0) | LE_SCC(0) | LE_PFM(0) |
> LE_SCF(0)),
> - (L3_ESC(0) | L3_SCC(0) | L3_CACHEABILITY(L3_WB)) },
> - /* { 0x0000003b, 0x0030 } */
> - { (LE_CACHEABILITY(LE_WB) | LE_TGT_CACHE(LLC_ELLC) |
> LE_LRUM(3) |
> - LE_AOM(0) | LE_RSC(0) | LE_SCC(0) | LE_PFM(0) |
> LE_SCF(0)),
> - (L3_ESC(0) | L3_SCC(0) | L3_CACHEABILITY(L3_WB)) }
> + { /* 0x00000009 */
> + .control_value = LE_CACHEABILITY(LE_UC) |
> + LE_TGT_CACHE(LE_TC_LLC_ELLC) |
> + LE_LRUM(0) | LE_AOM(0) | LE_RSC(0) |
> LE_SCC(0) |
> + LE_PFM(0) | LE_SCF(0),
> +
> + /* 0x0010 */
> + .l3cc_value = L3_ESC(0) | L3_SCC(0) |
> L3_CACHEABILITY(L3_UC),
> + },
> + {
> + /* 0x00000038 */
> + .control_value = LE_CACHEABILITY(LE_PAGETABLE) |
> + LE_TGT_CACHE(LE_TC_LLC_ELLC) |
> + LE_LRUM(3) | LE_AOM(0) | LE_RSC(0) |
> LE_SCC(0) |
> + LE_PFM(0) | LE_SCF(0),
> + /* 0x0030 */
> + .l3cc_value = L3_ESC(0) | L3_SCC(0) |
> L3_CACHEABILITY(L3_WB),
> + },
> + {
> + /* 0x0000003b */
> + .control_value = LE_CACHEABILITY(LE_WB) |
> + LE_TGT_CACHE(LE_TC_LLC_ELLC) |
> + LE_LRUM(3) | LE_AOM(0) | LE_RSC(0) |
> LE_SCC(0) |
> + LE_PFM(0) | LE_SCF(0),
> + /* 0x0030 */
> + .l3cc_value = L3_ESC(0) | L3_SCC(0) |
> L3_CACHEABILITY(L3_WB),
> + },
> };
>
> /* NOTE: the LE_TGT_CACHE is not used on Broxton */
> static const struct drm_i915_mocs_entry broxton_mocs_table[] = {
> - /* { 0x00000009, 0x0010 } */
> - { (LE_CACHEABILITY(LE_UC) | LE_TGT_CACHE(LLC_ELLC) |
> LE_LRUM(0) |
> - LE_AOM(0) | LE_RSC(0) | LE_SCC(0) | LE_PFM(0) |
> LE_SCF(0)),
> - (L3_ESC(0) | L3_SCC(0) | L3_CACHEABILITY(L3_UC)) },
> - /* { 0x00000038, 0x0030 } */
> - { (LE_CACHEABILITY(LE_PAGETABLE) | LE_TGT_CACHE(LLC_ELLC) |
> LE_LRUM(3) |
> - LE_AOM(0) | LE_RSC(0) | LE_SCC(0) | LE_PFM(0) |
> LE_SCF(0)),
> - (L3_ESC(0) | L3_SCC(0) | L3_CACHEABILITY(L3_WB)) },
> - /* { 0x0000003b, 0x0030 } */
> - { (LE_CACHEABILITY(LE_WB) | LE_TGT_CACHE(LLC_ELLC) |
> LE_LRUM(3) |
> - LE_AOM(0) | LE_RSC(0) | LE_SCC(0) | LE_PFM(0) |
> LE_SCF(0)),
> - (L3_ESC(0) | L3_SCC(0) | L3_CACHEABILITY(L3_WB)) }
> + {
> + /* 0x00000009 */
> + .control_value = LE_CACHEABILITY(LE_UC) |
> + LE_TGT_CACHE(LE_TC_LLC_ELLC) |
> + LE_LRUM(0) | LE_AOM(0) | LE_RSC(0) |
> LE_SCC(0) |
> + LE_PFM(0) | LE_SCF(0),
> +
> + /* 0x0010 */
> + .l3cc_value = L3_ESC(0) | L3_SCC(0) |
> L3_CACHEABILITY(L3_UC),
> + },
> + {
> + /* 0x00000038 */
> + .control_value = LE_CACHEABILITY(LE_PAGETABLE) |
> + LE_TGT_CACHE(LE_TC_LLC_ELLC) |
> + LE_LRUM(3) | LE_AOM(0) | LE_RSC(0) |
> LE_SCC(0) |
> + LE_PFM(0) | LE_SCF(0),
> +
> + /* 0x0030 */
> + .l3cc_value = L3_ESC(0) | L3_SCC(0) |
> L3_CACHEABILITY(L3_WB),
> + },
> + {
> + /* 0x0000003b */
> + .control_value = LE_CACHEABILITY(LE_WB) |
> + LE_TGT_CACHE(LE_TC_LLC_ELLC) |
> + LE_LRUM(3) | LE_AOM(0) | LE_RSC(0) |
> LE_SCC(0) |
> + LE_PFM(0) | LE_SCF(0),
> +
> + /* 0x0030 */
> + .l3cc_value = L3_ESC(0) | L3_SCC(0) |
> L3_CACHEABILITY(L3_WB),
> + },
> };
>
> /**
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next prev parent reply other threads:[~2016-07-01 21:23 UTC|newest]
Thread overview: 20+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-07-01 13:40 [PATCH v3 0/3] drm/i915/bxt: Fix performance due to bogus MOCS entry Imre Deak
2016-07-01 13:40 ` [PATCH v3 1/3] drm/i915/gen9: Clean up MOCS table definitions Imre Deak
2016-07-01 21:23 ` Bish, Jim [this message]
2016-07-01 21:47 ` Francisco Jerez
2016-07-12 11:08 ` Imre Deak
2016-07-13 2:10 ` Zhao Yakui
2016-07-01 13:40 ` [PATCH v3 2/3] drm/i915/bxt: Fix inadvertent CPU snooping due to incorrect MOCS config Imre Deak
2016-07-13 2:32 ` Zhao Yakui
2016-07-14 8:33 ` Yang, Rong R
2016-07-01 13:40 ` [PATCH v3 3/3] drm/i915: Give proper names to MOCS entries Imre Deak
2016-07-01 13:49 ` Chris Wilson
2016-07-01 13:56 ` Imre Deak
2016-07-01 14:32 ` [PATCH v4 " Imre Deak
2016-07-13 2:22 ` [PATCH v3 " Zhao Yakui
2016-07-13 10:04 ` Imre Deak
2016-07-14 1:38 ` Zhao Yakui
2016-07-01 14:54 ` ✗ Ro.CI.BAT: warning for drm/i915/bxt: Fix performance due to bogus MOCS entry Patchwork
2016-07-19 18:15 ` Imre Deak
2016-07-01 15:15 ` ✗ Ro.CI.BAT: warning for drm/i915/bxt: Fix performance due to bogus MOCS entry (rev2) Patchwork
2016-07-18 14:28 ` [PATCH v3 0/3] drm/i915/bxt: Fix performance due to bogus MOCS entry Ville Syrjälä
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