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From: "Zanoni, Paulo R" <paulo.r.zanoni@intel.com>
To: "intel-gfx@lists.freedesktop.org"
	<intel-gfx@lists.freedesktop.org>,
	"Kumar, Mahesh1" <mahesh1.kumar@intel.com>
Cc: "Kumar@freedesktop.org" <Kumar@freedesktop.org>
Subject: Re: [PATCH 1/7] drm/i915/hsw+: set intel_crtc active once pipe is active
Date: Tue, 30 Aug 2016 19:18:02 +0000	[thread overview]
Message-ID: <1472584677.2387.12.camel@intel.com> (raw)
In-Reply-To: <20160829123522.9532-2-mahesh1.kumar@intel.com>

Em Seg, 2016-08-29 às 18:05 +0530, Kumar, Mahesh escreveu:
> Set the intel_crtc->active flag after pipe/crtc is actually active in
> haswell_crtc_enable function.

Why?

Can you please elaborate more on why this change is needed, what are
the benefits it brings, what are the problems it solves and why is the
current code bad or wrong? Please explain all this in the commit
message, not just as an email reply.

In other words: if I'm bisecting a theoretical bug and then suddenly
conclude that this patch is the problem, how will I know what's going
to break once I revert this patch?

Thanks,
Paulo

> 
> Signed-off-by: Kumar, Mahesh <mahesh1.kumar@intel.com>
> ---
>  drivers/gpu/drm/i915/intel_display.c | 4 ++--
>  1 file changed, 2 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_display.c
> b/drivers/gpu/drm/i915/intel_display.c
> index e4e6141..7258883 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -5427,8 +5427,6 @@ static void haswell_crtc_enable(struct
> intel_crtc_state *pipe_config,
>  
>  	intel_color_set_csc(&pipe_config->base);
>  
> -	intel_crtc->active = true;
> -
>  	if (intel_crtc->config->has_pch_encoder)
>  		intel_set_cpu_fifo_underrun_reporting(dev_priv,
> pipe, false);
>  	else
> @@ -5475,6 +5473,8 @@ static void haswell_crtc_enable(struct
> intel_crtc_state *pipe_config,
>  	assert_vblank_disabled(crtc);
>  	drm_crtc_vblank_on(crtc);
>  
> +	intel_crtc->active = true;
> +
>  	intel_encoders_enable(crtc, pipe_config, old_state);
>  
>  	if (intel_crtc->config->has_pch_encoder) {
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  reply	other threads:[~2016-08-30 19:18 UTC|newest]

Thread overview: 28+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2016-08-29 12:35 [PATCH 0/7] Implement New DDB allocation algorithm Kumar, Mahesh
2016-08-29 12:35 ` [PATCH 1/7] drm/i915/hsw+: set intel_crtc active once pipe is active Kumar, Mahesh
2016-08-30 19:18   ` Zanoni, Paulo R [this message]
2016-08-31 10:51   ` Maarten Lankhorst
2016-08-31 14:04     ` Mahesh Kumar
2016-08-29 12:35 ` [PATCH 2/7] drm/i915/skl+: use linetime latency instead of ddb size Kumar, Mahesh
2016-08-29 12:35 ` [PATCH 3/7] drm/i915/skl: pass pipe_wm in skl_compute_(wm_level/plane_wm) functions Kumar, Mahesh
2016-08-29 12:35 ` [PATCH 4/7] drm/i915/skl: New ddb allocation algorithm Kumar, Mahesh
2016-08-31 13:38   ` Maarten Lankhorst
2016-08-31 14:18     ` Mahesh Kumar
2016-08-29 12:35 ` [PATCH 5/7] drm/i915: Decode system memory bandwidth Kumar, Mahesh
2016-08-29 12:35 ` [PATCH] FOR_UPSTREAM [VPG]: drm/i915/skl+: Implement Transition WM Kumar, Mahesh
2016-08-30 19:32   ` Zanoni, Paulo R
2016-08-31 13:47     ` Zanoni, Paulo R
2016-09-02 11:46       ` Mahesh Kumar
2016-09-02 12:21         ` Zanoni, Paulo R
2016-08-29 12:35 ` [PATCH] drm/i915/gen9: WM memory bandwidth related workaround Kumar, Mahesh
2016-09-08 11:26 ` [PATCH v2 0/9] New DDB Algo and WM fixes Kumar, Mahesh
2016-09-08 11:26   ` [PATCH v2 1/9] drm/i915/skl: pass pipe_wm in skl_compute_(wm_level/plane_wm) functions Kumar, Mahesh
2016-09-08 11:26   ` [PATCH v2 2/9] drm/i915/skl+: use linetime latency instead of ddb size Kumar, Mahesh
2016-09-08 11:26   ` [PATCH v2 3/9] drm/i915/skl: New ddb allocation algorithm Kumar, Mahesh
2016-09-08 11:26   ` [PATCH v2 4/9] drm/i915: Decode system memory bandwidth Kumar, Mahesh
2016-09-08 11:26   ` [PATCH v2 5/9] drm/i915/gen9: WM memory bandwidth related workaround Kumar, Mahesh
2016-09-08 11:26   ` [PATCH v2 6/9] drm/i915/skl+: change WM calc to fixed point 16.16 Kumar, Mahesh
2016-09-08 11:26   ` [PATCH v2 7/9] drm/i915/bxt: Enable IPC support Kumar, Mahesh
2016-09-08 11:26   ` [PATCH v2 8/9] drm/i915/bxt: set chicken bit as IPC y-tile WA Kumar, Mahesh
2016-09-08 11:26   ` [PATCH v2 9/9] drm/i915/bxt: Implement Transition WM Kumar, Mahesh
2016-09-08 11:55 ` ✗ Fi.CI.BAT: failure for Implement New DDB allocation algorithm Patchwork

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