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From: Mika Kahola <mika.kahola@intel.com>
To: "Pandiyan, Dhinakaran" <dhinakaran.pandiyan@intel.com>
Cc: "intel-gfx@lists.freedesktop.org" <intel-gfx@lists.freedesktop.org>
Subject: Re: [PATCH 10/14] drm/i915: Make DP link training channel equalization DP 1.2 Spec compliant
Date: Wed, 07 Sep 2016 10:50:19 +0300	[thread overview]
Message-ID: <1473234619.28727.9.camel@intel.com> (raw)
In-Reply-To: <1472844047.1219.8.camel@dk-H97M-D3H>

Reviewed-by: Mika Kahola <mika.kahola@intel.com>

On Fri, 2016-09-02 at 22:05 +0300, Pandiyan, Dhinakaran wrote:
> On Fri, 2016-09-02 at 14:20 +0300, Mika Kahola wrote:
> > 
> > On Thu, 2016-09-01 at 15:08 -0700, Manasi Navare wrote:
> > > 
> > > Fix the number of tries in channel euqalization link training
> > > sequence
> > > according to DP 1.2 Spec. It returns a boolean depending on
> > > channel
> > > equalization pass or failure.
> > > 
> > > Signed-off-by: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com
> > > >
> > > Signed-off-by: Manasi Navare <manasi.d.navare@intel.com>
> > > ---
> > >  drivers/gpu/drm/i915/intel_dp_link_training.c | 57 ++++++++++---
> > > ----
> > > ----------
> > >  drivers/gpu/drm/i915/intel_drv.h              |  1 +
> > >  2 files changed, 22 insertions(+), 36 deletions(-)
> > > 
> > > diff --git a/drivers/gpu/drm/i915/intel_dp_link_training.c
> > > b/drivers/gpu/drm/i915/intel_dp_link_training.c
> > > index 13a0341..07f0159 100644
> > > --- a/drivers/gpu/drm/i915/intel_dp_link_training.c
> > > +++ b/drivers/gpu/drm/i915/intel_dp_link_training.c
> > > @@ -240,12 +240,12 @@ static u32 intel_dp_training_pattern(struct
> > > intel_dp *intel_dp)
> > >  	return training_pattern;
> > >  }
> > >  
> > > -static void
> > > +static bool
> > >  intel_dp_link_training_channel_equalization(struct intel_dp
> > > *intel_dp)
> > >  {
> > > -	bool channel_eq = false;
> > > -	int tries, cr_tries;
> > > +	int tries;
> > >  	u32 training_pattern;
> > > +	uint8_t link_status[DP_LINK_STATUS_SIZE];
> > >  
> > >  	training_pattern = intel_dp_training_pattern(intel_dp);
> > >  
> > > @@ -254,20 +254,11 @@
> > > intel_dp_link_training_channel_equalization(struct intel_dp
> > > *intel_dp)
> > >  				     training_pattern |
> > >  				     DP_LINK_SCRAMBLING_DISABLE)
> > > ) {
> > >  		DRM_ERROR("failed to start channel
> > > equalization\n");
> > > -		return;
> > > +		return false;
> > >  	}
> > >  
> > > -	tries = 0;
> > > -	cr_tries = 0;
> > > -	channel_eq = false;
> > > -	for (;;) {
> > > -		uint8_t link_status[DP_LINK_STATUS_SIZE];
> > > -
> > > -		if (cr_tries > 5) {
> > > -			DRM_ERROR("failed to train DP,
> > > aborting\n");
> > > -			intel_dp_dump_link_status(link_status);
> > > -			break;
> > > -		}
> > > +	intel_dp->channel_eq_status = false;
> > > +	for (tries = 0; tries < 5; tries++) {
> > >  
> > >  		drm_dp_link_train_channel_eq_delay(intel_dp-
> > > >dpcd);
> > >  		if (!intel_dp_get_link_status(intel_dp,
> > > link_status)) {
> > > @@ -278,44 +269,38 @@
> > > intel_dp_link_training_channel_equalization(struct intel_dp
> > > *intel_dp)
> > >  		/* Make sure clock is still ok */
> > >  		if (!drm_dp_clock_recovery_ok(link_status,
> > >  					      intel_dp-
> > > >lane_count)) 
> > > {
> > > -			intel_dp_link_training_clock_recovery(in
> > > tel_
> > > dp);
> > > -			intel_dp_set_link_train(intel_dp,
> > > -						training_pattern
> > > |
> > > -						DP_LINK_SCRAMBLI
> > > NG_D
> > > ISABLE);
> > > -			cr_tries++;
> > > -			continue;
> > > +			intel_dp_dump_link_status(link_status);
> > > +			DRM_DEBUG_KMS("Clock recovery check
> > > failed,
> > > cannot "
> > > +				      "continue channel
> > > equalization\n");
> > > +			break;
> > >  		}
> > This clock recovery check got me thinking. Do we really need to
> > check
> > if clock recovery is still ok within a loop? Could we move this
> > outside
> > the loop and return early if we have failed in clock recovery? One
> > idea
> > that I have in mind is that we wouldn't need to enter in channel
> > equalization if we have failed with clock recovery earlier.
> > 
> Looks like we do. This check helps us to break out of the loop for
> link
> rate reduction after adjusting drive setting. 
You're right we do that.
> 
> 
> > 
> > > 
> > >  
> > >  		if (drm_dp_channel_eq_ok(link_status,
> > >  					 intel_dp->lane_count))
> > > {
> > > -			channel_eq = true;
> > > +			intel_dp->channel_eq_status = true;
> > > +			DRM_DEBUG_KMS("Channel EQ done. DP
> > > Training
> > > "
> > > +				      "successful\n");
> > >  			break;
> > >  		}
> > >  
> > > -		/* Try 5 times, then try clock recovery if that
> > > fails */
> > > -		if (tries > 5) {
> > > -			intel_dp_link_training_clock_recovery(in
> > > tel_
> > > dp);
> > > -			intel_dp_set_link_train(intel_dp,
> > > -						training_pattern
> > > |
> > > -						DP_LINK_SCRAMBLI
> > > NG_D
> > > ISABLE);
> > > -			tries = 0;
> > > -			cr_tries++;
> > > -			continue;
> > > -		}
> > > -
> > >  		/* Update training set as requested by target */
> > >  		intel_get_adjust_train(intel_dp, link_status);
> > >  		if (!intel_dp_update_link_train(intel_dp)) {
> > >  			DRM_ERROR("failed to update link
> > > training\n");
> > >  			break;
> > >  		}
> > > -		++tries;
> > > +	}
> > > +
> > > +	/* Try 5 times, else fail and try at lower BW */
> > > +	if (tries == 5) {
> > > +		intel_dp_dump_link_status(link_status);
> > > +		DRM_DEBUG_KMS("Channel equalization failed 5
> > > times\n");
> > >  	}
> > >  
> > >  	intel_dp_set_idle_link_train(intel_dp);
> > >  
> > > -	if (channel_eq)
> > > -		DRM_DEBUG_KMS("Channel EQ done. DP Training
> > > successful\n");
> > > +	return intel_dp->channel_eq_status;
> > > +
> > >  }
> > >  
> > >  void intel_dp_stop_link_train(struct intel_dp *intel_dp)
> > > diff --git a/drivers/gpu/drm/i915/intel_drv.h
> > > b/drivers/gpu/drm/i915/intel_drv.h
> > > index efcd80b..e5bc976 100644
> > > --- a/drivers/gpu/drm/i915/intel_drv.h
> > > +++ b/drivers/gpu/drm/i915/intel_drv.h
> > > @@ -878,6 +878,7 @@ struct intel_dp {
> > >  	bool link_mst;
> > >  	bool has_audio;
> > >  	bool detect_done;
> > > +	bool channel_eq_status;
> > >  	enum hdmi_force_audio force_audio;
> > >  	bool limited_color_range;
> > >  	bool color_range_auto;
-- 
Mika Kahola - Intel OTC

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  reply	other threads:[~2016-09-07  7:50 UTC|newest]

Thread overview: 81+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2016-09-01 22:08 [PATCH 00/14] Enable Upfront Link Training on DDI platforms Manasi Navare
2016-09-01 22:08 ` [PATCH v2 01/14] drm/i915: Don't pass crtc_state to intel_dp_set_link_params() Manasi Navare
2016-09-01 22:08 ` [PATCH v2 02/14] drm/i915: Remove ddi_pll_sel from intel_crtc_state Manasi Navare
2016-09-01 22:08 ` [PATCH v3 03/14] drm/i915: Split intel_ddi_pre_enable() into DP and HDMI versions Manasi Navare
2016-09-01 22:08 ` [PATCH v2 04/14] drm/i915: Split bxt_ddi_pll_select() Manasi Navare
2016-09-01 22:08 ` [PATCH 05/14] drm/i915: Split skl_get_dpll() Manasi Navare
2016-09-01 22:08 ` [PATCH 06/14] drm/i915: Split hsw_get_dpll() Manasi Navare
2016-09-01 22:08 ` [PATCH v3 07/14] drm/i915/dp: Add a standalone function to obtain shared dpll for HSW/BDW/SKL/BXT Manasi Navare
2016-09-02 20:06   ` Pandiyan, Dhinakaran
2016-09-07 22:08     ` Manasi Navare
2016-09-07 22:47   ` [PATCH v4 7/14] " Manasi Navare
2016-09-01 22:08 ` [PATCH 08/14] drm/i915/dp: Move max. vswing check to it's own function Manasi Navare
2016-09-02  8:05   ` Mika Kahola
2016-09-06  9:58     ` Mika Kahola
2016-09-06 21:25       ` Manasi Navare
2016-09-07  0:13   ` [PATCH v2 8/14] " Manasi Navare
2016-09-07  7:00     ` Mika Kahola
2016-09-07 18:28     ` [PATCH v3 " Manasi Navare
2016-09-08  7:38       ` Mika Kahola
2016-09-13 11:44         ` Jani Nikula
2016-09-01 22:08 ` [PATCH 09/14] drm/dp/i915: Make clock recovery in the link training compliant with DP Spec 1.2 Manasi Navare
2016-09-02  9:16   ` Mika Kahola
2016-09-02 17:55     ` Pandiyan, Dhinakaran
2016-09-07  0:13   ` [PATCH v2 9/14] " Manasi Navare
2016-09-07  7:33     ` Mika Kahola
2016-09-07 18:28     ` [PATCH v3 " Manasi Navare
2016-09-08  8:20       ` Mika Kahola
2016-09-01 22:08 ` [PATCH 10/14] drm/i915: Make DP link training channel equalization DP 1.2 Spec compliant Manasi Navare
2016-09-02 11:20   ` Mika Kahola
2016-09-02 19:05     ` Pandiyan, Dhinakaran
2016-09-07  7:50       ` Mika Kahola [this message]
2016-09-13 16:09         ` Rodrigo Vivi
2016-09-01 22:08 ` [PATCH 11/14] drm/i915: Fallback to lower link rate and lane count during link training Manasi Navare
2016-09-02 12:03   ` David Weinehall
2016-09-06 17:34     ` Manasi Navare
2016-09-02 12:49   ` David Weinehall
2016-09-06 17:54     ` Manasi Navare
2016-09-02 13:00   ` Mika Kahola
2016-09-06 18:01     ` Manasi Navare
2016-09-02 19:52   ` Pandiyan, Dhinakaran
2016-09-02 20:01     ` Jim Bride
2016-09-07  0:13   ` [PATCH v2 " Manasi Navare
2016-09-07  9:47     ` Mika Kahola
2016-09-07 16:47       ` Jim Bride
2016-09-07 16:48       ` Manasi Navare
2016-09-07 18:28     ` [PATCH v3 " Manasi Navare
2016-09-08  0:30       ` [PATCH v4 " Manasi Navare
2016-09-08  9:32         ` Mika Kahola
2016-09-09  1:05         ` Rodrigo Vivi
2016-09-09  7:11           ` Jani Nikula
2016-09-09  7:11         ` Jani Nikula
2016-09-09 17:13           ` Manasi Navare
2016-09-09 23:29         ` [PATCH v5 " Manasi Navare
2016-09-01 22:08 ` [PATCH 12/14] drm/i915: Reverse the loop in intel_dp_compute_config Manasi Navare
2016-09-02 13:08   ` Mika Kahola
2016-09-08 14:47     ` Manasi Navare
2016-09-02 20:24   ` Pandiyan, Dhinakaran
2016-09-08 20:02   ` [PATCH v2 12/14] drm/i915: Remove the link rate and lane count loop in compute config Manasi Navare
2016-09-13  1:14     ` Pandiyan, Dhinakaran
2016-09-14  1:05       ` Manasi Navare
2016-09-01 22:08 ` [PATCH v11 13/14] drm/i915/dp: Enable Upfront link training for typeC DP support on HSW/BDW/SKL/BXT (DDI platforms) Manasi Navare
2016-09-07  0:13   ` [PATCH v12 " Manasi Navare
2016-09-07 18:28     ` [PATCH v13 " Manasi Navare
2016-09-08 12:10       ` Mika Kahola
2016-09-08 15:06         ` Manasi Navare
2016-09-08 17:22       ` [PATCH v14 " Manasi Navare
2016-09-08 20:02         ` [PATCH v15 " Manasi Navare
2016-09-09  7:34           ` Jani Nikula
2016-09-09 23:29           ` [PATCH 13-1/14] drm/i915: Change the placement of some static functions in intel_dp.c Manasi Navare
2016-09-12 23:21             ` Rodrigo Vivi
2016-09-09 23:29           ` [PATCH v16 13-2/14] drm/i915/dp: Enable Upfront link training on HSW/BDW/SKL/BXT Manasi Navare
2016-09-13  0:22             ` Rodrigo Vivi
2016-09-09  7:31         ` [PATCH v14 13/14] drm/i915/dp: Enable Upfront link training for typeC DP support on HSW/BDW/SKL/BXT (DDI platforms) Jani Nikula
2016-09-01 22:08 ` [PATCH 14/14] drm/i915/dp/mst: Add support for upfront link training for DP MST Manasi Navare
2016-09-07  0:13   ` [PATCH v2 " Manasi Navare
2016-09-07 10:53     ` Mika Kahola
2016-09-07 16:40       ` Jim Bride
2016-09-08 10:21         ` Mika Kahola
2016-09-08 11:50       ` Mika Kahola
2016-09-01 22:48 ` ✗ Fi.CI.BAT: failure for Enable upfront link training on DDI platforms (rev3) Patchwork
2016-09-07  0:54 ` ✗ Fi.CI.BAT: warning for Enable upfront link training on DDI platforms (rev8) Patchwork

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