From: Mika Kahola <mika.kahola@intel.com>
To: Manasi Navare <manasi.d.navare@intel.com>,
intel-gfx@lists.freedesktop.org
Cc: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
Subject: Re: [PATCH v3 9/14] drm/dp/i915: Make clock recovery in the link training compliant with DP Spec 1.2
Date: Thu, 08 Sep 2016 11:20:40 +0300 [thread overview]
Message-ID: <1473322840.28727.29.camel@intel.com> (raw)
In-Reply-To: <1473272883-28520-2-git-send-email-manasi.d.navare@intel.com>
Reviewed-by: Mika Kahola <mika.kahola@intel.com>
On Wed, 2016-09-07 at 11:28 -0700, Manasi Navare wrote:
> From: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
>
> This function cleans up clock recovery loop in link training
> compliant
> tp Dp Spec 1.2. It tries the clock recovery 5 times for the same
> voltage
> or until max voltage swing is reached and removes the additional non
> compliant retries. This function now returns a boolean values based
> on
> if clock recovery passed or failed.
>
> v3:
> * Better Debug prints in case of failures (Mika Kahola)
> v2:
> * Rebased on top of new revision of vswing patch (Manasi Navare)
>
> Signed-off-by: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
> Signed-off-by: Manasi Navare <manasi.d.navare@intel.com>
> ---
> drivers/gpu/drm/i915/intel_dp_link_training.c | 60 +++++++++++++--
> ------------
> 1 file changed, 28 insertions(+), 32 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_dp_link_training.c
> b/drivers/gpu/drm/i915/intel_dp_link_training.c
> index b9880cf..80b9326 100644
> --- a/drivers/gpu/drm/i915/intel_dp_link_training.c
> +++ b/drivers/gpu/drm/i915/intel_dp_link_training.c
> @@ -125,12 +125,11 @@ static bool
> intel_dp_link_max_vswing_reached(struct intel_dp *intel_dp)
> }
>
> /* Enable corresponding port and start training pattern 1 */
> -static void
> +static bool
> intel_dp_link_training_clock_recovery(struct intel_dp *intel_dp)
> {
> - int i;
> uint8_t voltage;
> - int voltage_tries, loop_tries;
> + int voltage_tries, max_vswing_tries;
> uint8_t link_config[2];
> uint8_t link_bw, rate_select;
>
> @@ -146,6 +145,7 @@ intel_dp_link_training_clock_recovery(struct
> intel_dp *intel_dp)
> if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
> link_config[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
> drm_dp_dpcd_write(&intel_dp->aux, DP_LINK_BW_SET,
> link_config, 2);
> +
> if (intel_dp->num_sink_rates)
> drm_dp_dpcd_write(&intel_dp->aux, DP_LINK_RATE_SET,
> &rate_select, 1);
> @@ -161,58 +161,54 @@ intel_dp_link_training_clock_recovery(struct
> intel_dp *intel_dp)
> DP_TRAINING_PATTERN_1 |
> DP_LINK_SCRAMBLING_DISABLE))
> {
> DRM_ERROR("failed to enable link training\n");
> - return;
> + return false;
> }
>
> - voltage = 0xff;
> - voltage_tries = 0;
> - loop_tries = 0;
> + voltage_tries = 1;
> + max_vswing_tries = 0;
> for (;;) {
> uint8_t link_status[DP_LINK_STATUS_SIZE];
>
> drm_dp_link_train_clock_recovery_delay(intel_dp-
> >dpcd);
> +
> if (!intel_dp_get_link_status(intel_dp,
> link_status)) {
> DRM_ERROR("failed to get link status\n");
> - break;
> + return false;
> }
>
> if (drm_dp_clock_recovery_ok(link_status, intel_dp-
> >lane_count)) {
> DRM_DEBUG_KMS("clock recovery OK\n");
> - break;
> + return true;
> }
>
> - /* Check to see if we've tried the max voltage */
> - if (intel_dp_link_max_vswing_reached(intel_dp)) {
> - ++loop_tries;
> - if (loop_tries == 5) {
> - DRM_ERROR("too many full retries,
> give up\n");
> - intel_dp_dump_link_status(link_statu
> s);
> - break;
> - }
> - intel_dp_reset_link_train(intel_dp,
> - DP_TRAINING_PATTER
> N_1 |
> - DP_LINK_SCRAMBLING
> _DISABLE);
> - voltage_tries = 0;
> - continue;
> + if (voltage_tries == 5) {
> + DRM_DEBUG_KMS("Same voltage tried 5
> times\n");
> + return false;
> + }
> +
> + if (max_vswing_tries == 1) {
> + DRM_DEBUG_KMS("Max Voltage Swing
> reached\n");
> + return false;
> }
>
> - /* Check to see if we've tried the same voltage 5
> times */
> - if ((intel_dp->train_set[0] &
> DP_TRAIN_VOLTAGE_SWING_MASK) == voltage) {
> - ++voltage_tries;
> - if (voltage_tries == 5) {
> - DRM_ERROR("too many voltage retries,
> give up\n");
> - break;
> - }
> - } else
> - voltage_tries = 0;
> voltage = intel_dp->train_set[0] &
> DP_TRAIN_VOLTAGE_SWING_MASK;
>
> /* Update training set as requested by target */
> intel_get_adjust_train(intel_dp, link_status);
> if (!intel_dp_update_link_train(intel_dp)) {
> DRM_ERROR("failed to update link
> training\n");
> - break;
> + return false;
> }
> +
> + if ((intel_dp->train_set[0] &
> DP_TRAIN_VOLTAGE_SWING_MASK) ==
> + voltage)
> + ++voltage_tries;
> + else
> + voltage_tries = 1;
> +
> + if (intel_dp_link_max_vswing_reached(intel_dp))
> + ++max_vswing_tries;
> +
> }
> }
>
--
Mika Kahola - Intel OTC
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
next prev parent reply other threads:[~2016-09-08 8:20 UTC|newest]
Thread overview: 81+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-09-01 22:08 [PATCH 00/14] Enable Upfront Link Training on DDI platforms Manasi Navare
2016-09-01 22:08 ` [PATCH v2 01/14] drm/i915: Don't pass crtc_state to intel_dp_set_link_params() Manasi Navare
2016-09-01 22:08 ` [PATCH v2 02/14] drm/i915: Remove ddi_pll_sel from intel_crtc_state Manasi Navare
2016-09-01 22:08 ` [PATCH v3 03/14] drm/i915: Split intel_ddi_pre_enable() into DP and HDMI versions Manasi Navare
2016-09-01 22:08 ` [PATCH v2 04/14] drm/i915: Split bxt_ddi_pll_select() Manasi Navare
2016-09-01 22:08 ` [PATCH 05/14] drm/i915: Split skl_get_dpll() Manasi Navare
2016-09-01 22:08 ` [PATCH 06/14] drm/i915: Split hsw_get_dpll() Manasi Navare
2016-09-01 22:08 ` [PATCH v3 07/14] drm/i915/dp: Add a standalone function to obtain shared dpll for HSW/BDW/SKL/BXT Manasi Navare
2016-09-02 20:06 ` Pandiyan, Dhinakaran
2016-09-07 22:08 ` Manasi Navare
2016-09-07 22:47 ` [PATCH v4 7/14] " Manasi Navare
2016-09-01 22:08 ` [PATCH 08/14] drm/i915/dp: Move max. vswing check to it's own function Manasi Navare
2016-09-02 8:05 ` Mika Kahola
2016-09-06 9:58 ` Mika Kahola
2016-09-06 21:25 ` Manasi Navare
2016-09-07 0:13 ` [PATCH v2 8/14] " Manasi Navare
2016-09-07 7:00 ` Mika Kahola
2016-09-07 18:28 ` [PATCH v3 " Manasi Navare
2016-09-08 7:38 ` Mika Kahola
2016-09-13 11:44 ` Jani Nikula
2016-09-01 22:08 ` [PATCH 09/14] drm/dp/i915: Make clock recovery in the link training compliant with DP Spec 1.2 Manasi Navare
2016-09-02 9:16 ` Mika Kahola
2016-09-02 17:55 ` Pandiyan, Dhinakaran
2016-09-07 0:13 ` [PATCH v2 9/14] " Manasi Navare
2016-09-07 7:33 ` Mika Kahola
2016-09-07 18:28 ` [PATCH v3 " Manasi Navare
2016-09-08 8:20 ` Mika Kahola [this message]
2016-09-01 22:08 ` [PATCH 10/14] drm/i915: Make DP link training channel equalization DP 1.2 Spec compliant Manasi Navare
2016-09-02 11:20 ` Mika Kahola
2016-09-02 19:05 ` Pandiyan, Dhinakaran
2016-09-07 7:50 ` Mika Kahola
2016-09-13 16:09 ` Rodrigo Vivi
2016-09-01 22:08 ` [PATCH 11/14] drm/i915: Fallback to lower link rate and lane count during link training Manasi Navare
2016-09-02 12:03 ` David Weinehall
2016-09-06 17:34 ` Manasi Navare
2016-09-02 12:49 ` David Weinehall
2016-09-06 17:54 ` Manasi Navare
2016-09-02 13:00 ` Mika Kahola
2016-09-06 18:01 ` Manasi Navare
2016-09-02 19:52 ` Pandiyan, Dhinakaran
2016-09-02 20:01 ` Jim Bride
2016-09-07 0:13 ` [PATCH v2 " Manasi Navare
2016-09-07 9:47 ` Mika Kahola
2016-09-07 16:47 ` Jim Bride
2016-09-07 16:48 ` Manasi Navare
2016-09-07 18:28 ` [PATCH v3 " Manasi Navare
2016-09-08 0:30 ` [PATCH v4 " Manasi Navare
2016-09-08 9:32 ` Mika Kahola
2016-09-09 1:05 ` Rodrigo Vivi
2016-09-09 7:11 ` Jani Nikula
2016-09-09 7:11 ` Jani Nikula
2016-09-09 17:13 ` Manasi Navare
2016-09-09 23:29 ` [PATCH v5 " Manasi Navare
2016-09-01 22:08 ` [PATCH 12/14] drm/i915: Reverse the loop in intel_dp_compute_config Manasi Navare
2016-09-02 13:08 ` Mika Kahola
2016-09-08 14:47 ` Manasi Navare
2016-09-02 20:24 ` Pandiyan, Dhinakaran
2016-09-08 20:02 ` [PATCH v2 12/14] drm/i915: Remove the link rate and lane count loop in compute config Manasi Navare
2016-09-13 1:14 ` Pandiyan, Dhinakaran
2016-09-14 1:05 ` Manasi Navare
2016-09-01 22:08 ` [PATCH v11 13/14] drm/i915/dp: Enable Upfront link training for typeC DP support on HSW/BDW/SKL/BXT (DDI platforms) Manasi Navare
2016-09-07 0:13 ` [PATCH v12 " Manasi Navare
2016-09-07 18:28 ` [PATCH v13 " Manasi Navare
2016-09-08 12:10 ` Mika Kahola
2016-09-08 15:06 ` Manasi Navare
2016-09-08 17:22 ` [PATCH v14 " Manasi Navare
2016-09-08 20:02 ` [PATCH v15 " Manasi Navare
2016-09-09 7:34 ` Jani Nikula
2016-09-09 23:29 ` [PATCH 13-1/14] drm/i915: Change the placement of some static functions in intel_dp.c Manasi Navare
2016-09-12 23:21 ` Rodrigo Vivi
2016-09-09 23:29 ` [PATCH v16 13-2/14] drm/i915/dp: Enable Upfront link training on HSW/BDW/SKL/BXT Manasi Navare
2016-09-13 0:22 ` Rodrigo Vivi
2016-09-09 7:31 ` [PATCH v14 13/14] drm/i915/dp: Enable Upfront link training for typeC DP support on HSW/BDW/SKL/BXT (DDI platforms) Jani Nikula
2016-09-01 22:08 ` [PATCH 14/14] drm/i915/dp/mst: Add support for upfront link training for DP MST Manasi Navare
2016-09-07 0:13 ` [PATCH v2 " Manasi Navare
2016-09-07 10:53 ` Mika Kahola
2016-09-07 16:40 ` Jim Bride
2016-09-08 10:21 ` Mika Kahola
2016-09-08 11:50 ` Mika Kahola
2016-09-01 22:48 ` ✗ Fi.CI.BAT: failure for Enable upfront link training on DDI platforms (rev3) Patchwork
2016-09-07 0:54 ` ✗ Fi.CI.BAT: warning for Enable upfront link training on DDI platforms (rev8) Patchwork
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=1473322840.28727.29.camel@intel.com \
--to=mika.kahola@intel.com \
--cc=dhinakaran.pandiyan@intel.com \
--cc=intel-gfx@lists.freedesktop.org \
--cc=manasi.d.navare@intel.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).