* [PATCH 2/7] drm/i915/tdr: Modify error handler for per engine hang recovery
2016-09-19 15:30 [PATCH 1/7] drm/i915: Update i915.reset to handle engine resets Matthew Auld
@ 2016-09-19 15:30 ` Matthew Auld
2016-09-19 19:52 ` Chris Wilson
2016-09-19 15:30 ` [PATCH 3/7] drm/i915/tdr: Add support for per engine reset recovery Matthew Auld
` (7 subsequent siblings)
8 siblings, 1 reply; 12+ messages in thread
From: Matthew Auld @ 2016-09-19 15:30 UTC (permalink / raw)
To: intel-gfx; +Cc: Ian Lister, Tomas Elf
From: "arun.siluvery@linux.intel.com" <arun.siluvery@linux.intel.com>
This is a preparatory patch which modifies error handler to do per engine
hang recovery. The actual patch which implements this sequence follows
later in the series. The aim is to prepare existing recovery function to
adapt to this new function where applicable (which fails at this point
because core implementation is lacking) and continue recovery using legacy
full gpu reset.
A helper function is also added to query the availability of engine
reset.
The error events behaviour that are used to notify user of reset are
adapted to engine reset such that it doesn't break users listening to these
events. In legacy we report an error event, a reset event before resetting
the gpu and a reset done event marking the completion of reset. The same
behaviour is adapted but reset event is only dispatched once even when
multiple engines are hung. Finally once reset is complete we send reset
done event as usual.
v2
- rework slightly
- prefer INTEL_GEN
- document engine_mask param
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>
Signed-off-by: Ian Lister <ian.lister@intel.com>
Signed-off-by: Tomas Elf <tomas.elf@intel.com>
Signed-off-by: Arun Siluvery <arun.siluvery@linux.intel.com>
Signed-off-by: Matthew Auld <matthew.auld@intel.com>
---
drivers/gpu/drm/i915/i915_drv.c | 26 +++++++++++++++++++
drivers/gpu/drm/i915/i915_drv.h | 2 ++
drivers/gpu/drm/i915/i915_irq.c | 50 +++++++++++++++++++++++++++++++++----
drivers/gpu/drm/i915/intel_uncore.c | 5 ++++
4 files changed, 78 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 7f4e8ad..99fa690 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -1804,6 +1804,32 @@ error:
goto wakeup;
}
+/**
+ * i915_reset_engine - reset GPU engine to recover from a hang
+ * @engine: engine to reset
+ *
+ * Reset a specific GPU engine. Useful if a hang is detected.
+ * Returns zero on successful reset or otherwise an error code.
+ *
+ * Procedure is fairly simple:
+ * - force engine to idle
+ * - save current state which includes head and current request
+ * - reset engine
+ * - restore saved state and resubmit context
+ */
+int i915_reset_engine(struct intel_engine_cs *engine)
+{
+ int ret;
+ struct drm_i915_private *dev_priv = engine->i915;
+
+ /* FIXME: replace me with engine reset sequence */
+ ret = -ENODEV;
+
+ set_bit(I915_RESET_IN_PROGRESS, &dev_priv->gpu_error.flags);
+
+ return ret;
+}
+
static int i915_pm_suspend(struct device *kdev)
{
struct pci_dev *pdev = to_pci_dev(kdev);
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 4dd307e..79de74d 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -2888,6 +2888,8 @@ extern long i915_compat_ioctl(struct file *filp, unsigned int cmd,
extern int intel_gpu_reset(struct drm_i915_private *dev_priv, u32 engine_mask);
extern bool intel_has_gpu_reset(struct drm_i915_private *dev_priv);
extern void i915_reset(struct drm_i915_private *dev_priv);
+extern bool intel_has_engine_reset(struct drm_i915_private *dev_priv);
+extern int i915_reset_engine(struct intel_engine_cs *engine);
extern int intel_guc_reset(struct drm_i915_private *dev_priv);
extern void intel_engine_init_hangcheck(struct intel_engine_cs *engine);
extern unsigned long i915_chipset_val(struct drm_i915_private *dev_priv);
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index c128fdb..45c5a26 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -2487,11 +2487,13 @@ static void i915_error_wake_up(struct drm_i915_private *dev_priv)
/**
* i915_reset_and_wakeup - do process context error handling work
* @dev_priv: i915 device private
+ * @engine_mask: engines which are marked as hung
*
* Fire an error uevent so userspace can see that a hang or error
* was detected.
*/
-static void i915_reset_and_wakeup(struct drm_i915_private *dev_priv)
+static void i915_reset_and_wakeup(struct drm_i915_private *dev_priv,
+ u32 engine_mask)
{
struct kobject *kobj = &dev_priv->drm.primary->kdev->kobj;
char *error_event[] = { I915_ERROR_UEVENT "=1", NULL };
@@ -2501,6 +2503,15 @@ static void i915_reset_and_wakeup(struct drm_i915_private *dev_priv)
kobject_uevent_env(kobj, KOBJ_CHANGE, error_event);
DRM_DEBUG_DRIVER("resetting chip\n");
+ /*
+ * This event needs to be sent before performing gpu reset. When
+ * engine resets are supported we iterate through all engines and
+ * reset hung engines individually. To keep the event dispatch
+ * mechanism consistent with full gpu reset, this is only sent once
+ * even when multiple engines are hung. It is also safe to move this
+ * here because when we are in this function, we will definitely
+ * perform gpu reset.
+ */
kobject_uevent_env(kobj, KOBJ_CHANGE, reset_event);
/*
@@ -2511,6 +2522,28 @@ static void i915_reset_and_wakeup(struct drm_i915_private *dev_priv)
* simulated reset via debugs, so get an RPM reference.
*/
intel_runtime_pm_get(dev_priv);
+
+ /*
+ * First attempt to reset the engines which are marked as hung. If that
+ * fails then we fallback to doing a full gpu reset.
+ */
+ if (intel_has_engine_reset(dev_priv)) {
+ struct intel_engine_cs *engine;
+ unsigned int tmp;
+ int ret = 0;
+
+ for_each_engine_masked(engine, dev_priv, engine_mask, tmp) {
+ ret = i915_reset_engine(engine);
+ if (ret)
+ break;
+ }
+
+ if (!ret) {
+ DRM_DEBUG_DRIVER("reset hung engines.\n");
+ goto reset_done;
+ }
+ }
+
intel_prepare_reset(dev_priv);
do {
@@ -2532,6 +2565,8 @@ static void i915_reset_and_wakeup(struct drm_i915_private *dev_priv)
HZ));
intel_finish_reset(dev_priv);
+
+reset_done:
intel_runtime_pm_put(dev_priv);
if (!test_bit(I915_WEDGED, &dev_priv->gpu_error.flags))
@@ -2640,6 +2675,8 @@ static void i915_report_and_clear_eir(struct drm_i915_private *dev_priv)
* i915_handle_error - handle a gpu error
* @dev_priv: i915 device private
* @engine_mask: mask representing engines that are hung
+ * @fmt: formatted hang msg that gets logged in captured error state
+ *
* Do some basic checking of register state at error time and
* dump it to the syslog. Also call i915_capture_error_state() to make
* sure we get a record and make it available in debugfs. Fire a uevent
@@ -2664,9 +2701,12 @@ void i915_handle_error(struct drm_i915_private *dev_priv,
if (!engine_mask)
return;
- if (test_and_set_bit(I915_RESET_IN_PROGRESS,
- &dev_priv->gpu_error.flags))
- return;
+ /*
+ * Engine reset support is only available from Gen8 onwards so if
+ * it is not available or explicity disabled, use full gpu reset.
+ */
+ if (!intel_has_engine_reset(dev_priv))
+ set_bit(I915_RESET_IN_PROGRESS, &dev_priv->gpu_error.flags);
/*
* Wakeup waiting processes so that the reset function
@@ -2682,7 +2722,7 @@ void i915_handle_error(struct drm_i915_private *dev_priv,
*/
i915_error_wake_up(dev_priv);
- i915_reset_and_wakeup(dev_priv);
+ i915_reset_and_wakeup(dev_priv, engine_mask);
}
/* Called from drm generic code, passed 'crtc' which
diff --git a/drivers/gpu/drm/i915/intel_uncore.c b/drivers/gpu/drm/i915/intel_uncore.c
index a9b6c93..bfd9b93 100644
--- a/drivers/gpu/drm/i915/intel_uncore.c
+++ b/drivers/gpu/drm/i915/intel_uncore.c
@@ -1769,6 +1769,11 @@ bool intel_has_gpu_reset(struct drm_i915_private *dev_priv)
return intel_get_gpu_reset(dev_priv) != NULL;
}
+bool intel_has_engine_reset(struct drm_i915_private *dev_priv)
+{
+ return (INTEL_GEN(dev_priv) >= 8 && i915.reset == 2);
+}
+
int intel_guc_reset(struct drm_i915_private *dev_priv)
{
int ret;
--
2.7.4
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 12+ messages in thread* Re: [PATCH 2/7] drm/i915/tdr: Modify error handler for per engine hang recovery
2016-09-19 15:30 ` [PATCH 2/7] drm/i915/tdr: Modify error handler for per engine hang recovery Matthew Auld
@ 2016-09-19 19:52 ` Chris Wilson
0 siblings, 0 replies; 12+ messages in thread
From: Chris Wilson @ 2016-09-19 19:52 UTC (permalink / raw)
To: Matthew Auld; +Cc: intel-gfx, Tomas Elf, Ian Lister
On Mon, Sep 19, 2016 at 04:30:14PM +0100, Matthew Auld wrote:
> From: "arun.siluvery@linux.intel.com" <arun.siluvery@linux.intel.com>
>
> This is a preparatory patch which modifies error handler to do per engine
> hang recovery. The actual patch which implements this sequence follows
> later in the series. The aim is to prepare existing recovery function to
> adapt to this new function where applicable (which fails at this point
> because core implementation is lacking) and continue recovery using legacy
> full gpu reset.
>
> A helper function is also added to query the availability of engine
> reset.
>
> The error events behaviour that are used to notify user of reset are
> adapted to engine reset such that it doesn't break users listening to these
> events. In legacy we report an error event, a reset event before resetting
> the gpu and a reset done event marking the completion of reset. The same
> behaviour is adapted but reset event is only dispatched once even when
> multiple engines are hung. Finally once reset is complete we send reset
> done event as usual.
>
> v2
> - rework slightly
> - prefer INTEL_GEN
> - document engine_mask param
>
> Cc: Chris Wilson <chris@chris-wilson.co.uk>
> Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>
> Signed-off-by: Ian Lister <ian.lister@intel.com>
> Signed-off-by: Tomas Elf <tomas.elf@intel.com>
> Signed-off-by: Arun Siluvery <arun.siluvery@linux.intel.com>
> Signed-off-by: Matthew Auld <matthew.auld@intel.com>
> ---
> drivers/gpu/drm/i915/i915_drv.c | 26 +++++++++++++++++++
> drivers/gpu/drm/i915/i915_drv.h | 2 ++
> drivers/gpu/drm/i915/i915_irq.c | 50 +++++++++++++++++++++++++++++++++----
> drivers/gpu/drm/i915/intel_uncore.c | 5 ++++
> 4 files changed, 78 insertions(+), 5 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
> index 7f4e8ad..99fa690 100644
> --- a/drivers/gpu/drm/i915/i915_drv.c
> +++ b/drivers/gpu/drm/i915/i915_drv.c
> @@ -1804,6 +1804,32 @@ error:
> goto wakeup;
> }
>
> +/**
> + * i915_reset_engine - reset GPU engine to recover from a hang
> + * @engine: engine to reset
> + *
> + * Reset a specific GPU engine. Useful if a hang is detected.
> + * Returns zero on successful reset or otherwise an error code.
> + *
> + * Procedure is fairly simple:
> + * - force engine to idle
> + * - save current state which includes head and current request
> + * - reset engine
> + * - restore saved state and resubmit context
> + */
> +int i915_reset_engine(struct intel_engine_cs *engine)
> +{
> + int ret;
> + struct drm_i915_private *dev_priv = engine->i915;
> +
> + /* FIXME: replace me with engine reset sequence */
> + ret = -ENODEV;
> +
> + set_bit(I915_RESET_IN_PROGRESS, &dev_priv->gpu_error.flags);
> +
> + return ret;
> +}
> +
> static int i915_pm_suspend(struct device *kdev)
> {
> struct pci_dev *pdev = to_pci_dev(kdev);
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 4dd307e..79de74d 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -2888,6 +2888,8 @@ extern long i915_compat_ioctl(struct file *filp, unsigned int cmd,
> extern int intel_gpu_reset(struct drm_i915_private *dev_priv, u32 engine_mask);
> extern bool intel_has_gpu_reset(struct drm_i915_private *dev_priv);
> extern void i915_reset(struct drm_i915_private *dev_priv);
> +extern bool intel_has_engine_reset(struct drm_i915_private *dev_priv);
> +extern int i915_reset_engine(struct intel_engine_cs *engine);
> extern int intel_guc_reset(struct drm_i915_private *dev_priv);
> extern void intel_engine_init_hangcheck(struct intel_engine_cs *engine);
> extern unsigned long i915_chipset_val(struct drm_i915_private *dev_priv);
> diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
> index c128fdb..45c5a26 100644
> --- a/drivers/gpu/drm/i915/i915_irq.c
> +++ b/drivers/gpu/drm/i915/i915_irq.c
> @@ -2487,11 +2487,13 @@ static void i915_error_wake_up(struct drm_i915_private *dev_priv)
> /**
> * i915_reset_and_wakeup - do process context error handling work
> * @dev_priv: i915 device private
> + * @engine_mask: engines which are marked as hung
> *
> * Fire an error uevent so userspace can see that a hang or error
> * was detected.
> */
> -static void i915_reset_and_wakeup(struct drm_i915_private *dev_priv)
> +static void i915_reset_and_wakeup(struct drm_i915_private *dev_priv,
> + u32 engine_mask)
> {
> struct kobject *kobj = &dev_priv->drm.primary->kdev->kobj;
> char *error_event[] = { I915_ERROR_UEVENT "=1", NULL };
> @@ -2501,6 +2503,15 @@ static void i915_reset_and_wakeup(struct drm_i915_private *dev_priv)
> kobject_uevent_env(kobj, KOBJ_CHANGE, error_event);
>
> DRM_DEBUG_DRIVER("resetting chip\n");
> + /*
> + * This event needs to be sent before performing gpu reset. When
> + * engine resets are supported we iterate through all engines and
> + * reset hung engines individually. To keep the event dispatch
> + * mechanism consistent with full gpu reset, this is only sent once
> + * even when multiple engines are hung. It is also safe to move this
> + * here because when we are in this function, we will definitely
> + * perform gpu reset.
> + */
> kobject_uevent_env(kobj, KOBJ_CHANGE, reset_event);
>
> /*
> @@ -2511,6 +2522,28 @@ static void i915_reset_and_wakeup(struct drm_i915_private *dev_priv)
> * simulated reset via debugs, so get an RPM reference.
> */
> intel_runtime_pm_get(dev_priv);
> +
> + /*
> + * First attempt to reset the engines which are marked as hung. If that
> + * fails then we fallback to doing a full gpu reset.
> + */
> + if (intel_has_engine_reset(dev_priv)) {
> + struct intel_engine_cs *engine;
> + unsigned int tmp;
> + int ret = 0;
> +
> + for_each_engine_masked(engine, dev_priv, engine_mask, tmp) {
> + ret = i915_reset_engine(engine);
> + if (ret)
> + break;
> + }
> +
> + if (!ret) {
> + DRM_DEBUG_DRIVER("reset hung engines.\n");
> + goto reset_done;
> + }
> + }
> +
> intel_prepare_reset(dev_priv);
>
> do {
> @@ -2532,6 +2565,8 @@ static void i915_reset_and_wakeup(struct drm_i915_private *dev_priv)
> HZ));
>
> intel_finish_reset(dev_priv);
> +
> +reset_done:
> intel_runtime_pm_put(dev_priv);
>
> if (!test_bit(I915_WEDGED, &dev_priv->gpu_error.flags))
> @@ -2640,6 +2675,8 @@ static void i915_report_and_clear_eir(struct drm_i915_private *dev_priv)
> * i915_handle_error - handle a gpu error
> * @dev_priv: i915 device private
> * @engine_mask: mask representing engines that are hung
> + * @fmt: formatted hang msg that gets logged in captured error state
> + *
> * Do some basic checking of register state at error time and
> * dump it to the syslog. Also call i915_capture_error_state() to make
> * sure we get a record and make it available in debugfs. Fire a uevent
> @@ -2664,9 +2701,12 @@ void i915_handle_error(struct drm_i915_private *dev_priv,
> if (!engine_mask)
> return;
>
> - if (test_and_set_bit(I915_RESET_IN_PROGRESS,
> - &dev_priv->gpu_error.flags))
> - return;
No. This is a serialised test for a reason.
-Chris
--
Chris Wilson, Intel Open Source Technology Centre
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 12+ messages in thread
* [PATCH 3/7] drm/i915/tdr: Add support for per engine reset recovery
2016-09-19 15:30 [PATCH 1/7] drm/i915: Update i915.reset to handle engine resets Matthew Auld
2016-09-19 15:30 ` [PATCH 2/7] drm/i915/tdr: Modify error handler for per engine hang recovery Matthew Auld
@ 2016-09-19 15:30 ` Matthew Auld
2016-09-19 19:53 ` Chris Wilson
2016-09-19 15:30 ` [PATCH 4/7] drm/i915: Skip reset request if there is one already Matthew Auld
` (6 subsequent siblings)
8 siblings, 1 reply; 12+ messages in thread
From: Matthew Auld @ 2016-09-19 15:30 UTC (permalink / raw)
To: intel-gfx; +Cc: Tomas Elf
From: "arun.siluvery@linux.intel.com" <arun.siluvery@linux.intel.com>
This change implements support for per-engine reset as an initial, less
intrusive hang recovery option to be attempted before falling back to the
legacy full GPU reset recovery mode if necessary. This is only supported
from Gen8 onwards.
Hangchecker determines which engines are hung and invokes error handler to
recover from it. Error handler schedules recovery for each of those engines
that are hung. The recovery procedure is as follows,
- identifies the request that caused the hang and it is dropped
- force engine to idle: this is done by issuing a reset request
- reset and re-init engine
- restart submissions to the engine
If engine reset fails then we fall back to heavy weight full gpu reset
which resets all engines and reinitiazes complete state of HW and SW.
v2
- rebase
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>
Signed-off-by: Tomas Elf <tomas.elf@intel.com>
Signed-off-by: Arun Siluvery <arun.siluvery@linux.intel.com>
Signed-off-by: Matthew Auld <matthew.auld@intel.com>
---
drivers/gpu/drm/i915/i915_drv.c | 59 +++++++++++++++++++++++++++++++++----
drivers/gpu/drm/i915/i915_drv.h | 3 ++
drivers/gpu/drm/i915/i915_gem.c | 2 +-
drivers/gpu/drm/i915/intel_lrc.c | 10 +++++++
drivers/gpu/drm/i915/intel_lrc.h | 1 +
drivers/gpu/drm/i915/intel_uncore.c | 41 +++++++++++++++++++++++---
6 files changed, 105 insertions(+), 11 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 99fa690..8625207 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -1812,21 +1812,68 @@ error:
* Returns zero on successful reset or otherwise an error code.
*
* Procedure is fairly simple:
- * - force engine to idle
- * - save current state which includes head and current request
- * - reset engine
- * - restore saved state and resubmit context
+ * - identifies the request that caused the hang and it is dropped
+ * - force engine to idle: this is done by issuing a reset request
+ * - reset engine
+ * - restart submissions to the engine
*/
int i915_reset_engine(struct intel_engine_cs *engine)
{
int ret;
struct drm_i915_private *dev_priv = engine->i915;
- /* FIXME: replace me with engine reset sequence */
- ret = -ENODEV;
+ /*
+ * We need to first idle the engine by issuing a reset request,
+ * then perform soft reset and re-initialize hw state, for all of
+ * this GT power need to be awake so ensure it does throughout the
+ * process
+ */
+ intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
+
+ /*
+ * the request that caused the hang is stuck on elsp, identify the
+ * active request and drop it, adjust head to skip the offending
+ * request to resume executing remaining requests in the queue.
+ */
+ i915_gem_reset_engine(engine);
+
+ ret = intel_engine_reset_begin(engine);
+ if (ret) {
+ DRM_ERROR("Failed to disable %s\n", engine->name);
+ goto error;
+ }
+
+ ret = intel_gpu_reset(dev_priv, intel_engine_flag(engine));
+ if (ret) {
+ DRM_ERROR("Failed to reset %s, ret=%d\n", engine->name, ret);
+ intel_engine_reset_cancel(engine);
+ goto error;
+ }
+
+ ret = engine->init_hw(engine);
+ if (ret)
+ goto error;
+
+ intel_engine_reset_cancel(engine);
+ intel_execlists_restart_submission(engine);
+ intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
+ return 0;
+
+error:
+ /* use full gpu reset to recover on error */
set_bit(I915_RESET_IN_PROGRESS, &dev_priv->gpu_error.flags);
+ /* Engine reset is performed without taking struct_mutex, since it
+ * failed we now fallback to full gpu reset. Wakeup any waiters
+ * which should now see the reset_in_progress and release
+ * struct_mutex for us to continue recovery.
+ */
+ rcu_read_lock();
+ intel_engine_wakeup(engine);
+ rcu_read_unlock();
+
+ intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
return ret;
}
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 79de74d..3dcf3f6 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -2889,6 +2889,8 @@ extern int intel_gpu_reset(struct drm_i915_private *dev_priv, u32 engine_mask);
extern bool intel_has_gpu_reset(struct drm_i915_private *dev_priv);
extern void i915_reset(struct drm_i915_private *dev_priv);
extern bool intel_has_engine_reset(struct drm_i915_private *dev_priv);
+extern int intel_engine_reset_begin(struct intel_engine_cs *engine);
+extern int intel_engine_reset_cancel(struct intel_engine_cs *engine);
extern int i915_reset_engine(struct intel_engine_cs *engine);
extern int intel_guc_reset(struct drm_i915_private *dev_priv);
extern void intel_engine_init_hangcheck(struct intel_engine_cs *engine);
@@ -3268,6 +3270,7 @@ static inline u32 i915_reset_count(struct i915_gpu_error *error)
void i915_gem_reset(struct drm_i915_private *dev_priv);
void i915_gem_set_wedged(struct drm_i915_private *dev_priv);
+void i915_gem_reset_engine(struct intel_engine_cs *engine);
bool i915_gem_clflush_object(struct drm_i915_gem_object *obj, bool force);
int __must_check i915_gem_init(struct drm_device *dev);
int __must_check i915_gem_init_hw(struct drm_device *dev);
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index c8bd022..d4f02e7 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -2575,7 +2575,7 @@ static void reset_request(struct drm_i915_gem_request *request)
memset(vaddr + head, 0, request->postfix - head);
}
-static void i915_gem_reset_engine(struct intel_engine_cs *engine)
+void i915_gem_reset_engine(struct intel_engine_cs *engine)
{
struct drm_i915_gem_request *request;
struct i915_gem_context *incomplete_ctx;
diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index 25114336..4a17d6f 100644
--- a/drivers/gpu/drm/i915/intel_lrc.c
+++ b/drivers/gpu/drm/i915/intel_lrc.c
@@ -601,6 +601,16 @@ static void execlists_submit_request(struct drm_i915_gem_request *request)
spin_unlock_irqrestore(&engine->execlist_lock, flags);
}
+void intel_execlists_restart_submission(struct intel_engine_cs *engine)
+{
+ spin_lock_bh(&engine->execlist_lock);
+
+ if (execlists_elsp_idle(engine))
+ tasklet_hi_schedule(&engine->irq_tasklet);
+
+ spin_unlock_bh(&engine->execlist_lock);
+}
+
int intel_logical_ring_alloc_request_extras(struct drm_i915_gem_request *request)
{
struct intel_engine_cs *engine = request->engine;
diff --git a/drivers/gpu/drm/i915/intel_lrc.h b/drivers/gpu/drm/i915/intel_lrc.h
index 4fed816..a509f42 100644
--- a/drivers/gpu/drm/i915/intel_lrc.h
+++ b/drivers/gpu/drm/i915/intel_lrc.h
@@ -95,5 +95,6 @@ uint64_t intel_lr_context_descriptor(struct i915_gem_context *ctx,
int intel_sanitize_enable_execlists(struct drm_i915_private *dev_priv,
int enable_execlists);
void intel_execlists_enable_submission(struct drm_i915_private *dev_priv);
+void intel_execlists_restart_submission(struct intel_engine_cs *engine);
#endif /* _INTEL_LRC_H_ */
diff --git a/drivers/gpu/drm/i915/intel_uncore.c b/drivers/gpu/drm/i915/intel_uncore.c
index bfd9b93..0738ac7 100644
--- a/drivers/gpu/drm/i915/intel_uncore.c
+++ b/drivers/gpu/drm/i915/intel_uncore.c
@@ -1676,7 +1676,7 @@ int intel_wait_for_register(struct drm_i915_private *dev_priv,
return ret;
}
-static int gen8_request_engine_reset(struct intel_engine_cs *engine)
+static int gen8_engine_reset_begin(struct intel_engine_cs *engine)
{
struct drm_i915_private *dev_priv = engine->i915;
int ret;
@@ -1695,7 +1695,7 @@ static int gen8_request_engine_reset(struct intel_engine_cs *engine)
return ret;
}
-static void gen8_unrequest_engine_reset(struct intel_engine_cs *engine)
+static void gen8_engine_reset_cancel(struct intel_engine_cs *engine)
{
struct drm_i915_private *dev_priv = engine->i915;
@@ -1710,14 +1710,14 @@ static int gen8_reset_engines(struct drm_i915_private *dev_priv,
unsigned int tmp;
for_each_engine_masked(engine, dev_priv, engine_mask, tmp)
- if (gen8_request_engine_reset(engine))
+ if (gen8_engine_reset_begin(engine))
goto not_ready;
return gen6_reset_engines(dev_priv, engine_mask);
not_ready:
for_each_engine_masked(engine, dev_priv, engine_mask, tmp)
- gen8_unrequest_engine_reset(engine);
+ gen8_engine_reset_cancel(engine);
return -EIO;
}
@@ -1793,6 +1793,39 @@ int intel_guc_reset(struct drm_i915_private *dev_priv)
return ret;
}
+/*
+ * On gen8+ a reset request has to be issued via the reset control register
+ * before a GPU engine can be reset in order to stop the command streamer
+ * and idle the engine. This replaces the legacy way of stopping an engine
+ * by writing to the stop ring bit in the MI_MODE register.
+ */
+int intel_engine_reset_begin(struct intel_engine_cs *engine)
+{
+ if (!intel_has_engine_reset(engine->i915)) {
+ DRM_ERROR("Engine Reset not supported on Gen%d\n",
+ INTEL_GEN(engine->i915));
+ return -EINVAL;
+ }
+
+ return gen8_engine_reset_begin(engine);
+}
+
+/*
+ * It is possible to back off from a previously issued reset request by simply
+ * clearing the reset request bit in the reset control register.
+ */
+int intel_engine_reset_cancel(struct intel_engine_cs *engine)
+{
+ if (!intel_has_engine_reset(engine->i915)) {
+ DRM_ERROR("Request to clear reset not supported on Gen%d\n",
+ INTEL_GEN(engine->i915));
+ return -EINVAL;
+ }
+
+ gen8_engine_reset_cancel(engine);
+ return 0;
+}
+
bool intel_uncore_unclaimed_mmio(struct drm_i915_private *dev_priv)
{
return check_for_unclaimed_mmio(dev_priv);
--
2.7.4
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^ permalink raw reply related [flat|nested] 12+ messages in thread* Re: [PATCH 3/7] drm/i915/tdr: Add support for per engine reset recovery
2016-09-19 15:30 ` [PATCH 3/7] drm/i915/tdr: Add support for per engine reset recovery Matthew Auld
@ 2016-09-19 19:53 ` Chris Wilson
0 siblings, 0 replies; 12+ messages in thread
From: Chris Wilson @ 2016-09-19 19:53 UTC (permalink / raw)
To: Matthew Auld; +Cc: intel-gfx, Tomas Elf
On Mon, Sep 19, 2016 at 04:30:15PM +0100, Matthew Auld wrote:
> From: "arun.siluvery@linux.intel.com" <arun.siluvery@linux.intel.com>
>
> This change implements support for per-engine reset as an initial, less
> intrusive hang recovery option to be attempted before falling back to the
> legacy full GPU reset recovery mode if necessary. This is only supported
> from Gen8 onwards.
>
> Hangchecker determines which engines are hung and invokes error handler to
> recover from it. Error handler schedules recovery for each of those engines
> that are hung. The recovery procedure is as follows,
> - identifies the request that caused the hang and it is dropped
> - force engine to idle: this is done by issuing a reset request
> - reset and re-init engine
> - restart submissions to the engine
>
> If engine reset fails then we fall back to heavy weight full gpu reset
> which resets all engines and reinitiazes complete state of HW and SW.
>
> v2
> - rebase
>
> Cc: Chris Wilson <chris@chris-wilson.co.uk>
> Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>
> Signed-off-by: Tomas Elf <tomas.elf@intel.com>
> Signed-off-by: Arun Siluvery <arun.siluvery@linux.intel.com>
> Signed-off-by: Matthew Auld <matthew.auld@intel.com>
> ---
> drivers/gpu/drm/i915/i915_drv.c | 59 +++++++++++++++++++++++++++++++++----
> drivers/gpu/drm/i915/i915_drv.h | 3 ++
> drivers/gpu/drm/i915/i915_gem.c | 2 +-
> drivers/gpu/drm/i915/intel_lrc.c | 10 +++++++
> drivers/gpu/drm/i915/intel_lrc.h | 1 +
> drivers/gpu/drm/i915/intel_uncore.c | 41 +++++++++++++++++++++++---
> 6 files changed, 105 insertions(+), 11 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
> index 99fa690..8625207 100644
> --- a/drivers/gpu/drm/i915/i915_drv.c
> +++ b/drivers/gpu/drm/i915/i915_drv.c
> @@ -1812,21 +1812,68 @@ error:
> * Returns zero on successful reset or otherwise an error code.
> *
> * Procedure is fairly simple:
> - * - force engine to idle
> - * - save current state which includes head and current request
> - * - reset engine
> - * - restore saved state and resubmit context
> + * - identifies the request that caused the hang and it is dropped
> + * - force engine to idle: this is done by issuing a reset request
> + * - reset engine
> + * - restart submissions to the engine
> */
> int i915_reset_engine(struct intel_engine_cs *engine)
> {
> int ret;
> struct drm_i915_private *dev_priv = engine->i915;
>
> - /* FIXME: replace me with engine reset sequence */
> - ret = -ENODEV;
> + /*
> + * We need to first idle the engine by issuing a reset request,
> + * then perform soft reset and re-initialize hw state, for all of
> + * this GT power need to be awake so ensure it does throughout the
> + * process
> + */
> + intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
> +
> + /*
> + * the request that caused the hang is stuck on elsp, identify the
> + * active request and drop it, adjust head to skip the offending
> + * request to resume executing remaining requests in the queue.
> + */
> + i915_gem_reset_engine(engine);
> +
> + ret = intel_engine_reset_begin(engine);
> + if (ret) {
> + DRM_ERROR("Failed to disable %s\n", engine->name);
> + goto error;
> + }
> +
> + ret = intel_gpu_reset(dev_priv, intel_engine_flag(engine));
> + if (ret) {
> + DRM_ERROR("Failed to reset %s, ret=%d\n", engine->name, ret);
> + intel_engine_reset_cancel(engine);
> + goto error;
> + }
Ordering is still broken.
> +
> + ret = engine->init_hw(engine);
> + if (ret)
> + goto error;
> +
> + intel_engine_reset_cancel(engine);
> + intel_execlists_restart_submission(engine);
This is broken.
-Chris
--
Chris Wilson, Intel Open Source Technology Centre
_______________________________________________
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 12+ messages in thread
* [PATCH 4/7] drm/i915: Skip reset request if there is one already
2016-09-19 15:30 [PATCH 1/7] drm/i915: Update i915.reset to handle engine resets Matthew Auld
2016-09-19 15:30 ` [PATCH 2/7] drm/i915/tdr: Modify error handler for per engine hang recovery Matthew Auld
2016-09-19 15:30 ` [PATCH 3/7] drm/i915/tdr: Add support for per engine reset recovery Matthew Auld
@ 2016-09-19 15:30 ` Matthew Auld
2016-09-19 15:30 ` [PATCH 5/7] drm/i915/tdr: Add engine reset count to error state Matthew Auld
` (5 subsequent siblings)
8 siblings, 0 replies; 12+ messages in thread
From: Matthew Auld @ 2016-09-19 15:30 UTC (permalink / raw)
To: intel-gfx
From: Mika Kuoppala <mika.kuoppala@linux.intel.com>
To perform engine reset we first disable engine to capture its state. This
is done by issuing a reset request. Because we are reusing existing
infrastructure, again when we actually reset an engine, reset function
checks engine mask and issues reset request again which is unnecessary. To
avoid this we check if the engine is already prepared, if so we just exit
from that point.
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>
Signed-off-by: Mika Kuoppala <mika.kuoppala@linux.intel.com>
Signed-off-by: Arun Siluvery <arun.siluvery@linux.intel.com>
---
drivers/gpu/drm/i915/intel_uncore.c | 9 +++++++--
1 file changed, 7 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_uncore.c b/drivers/gpu/drm/i915/intel_uncore.c
index 0738ac7..34f1658 100644
--- a/drivers/gpu/drm/i915/intel_uncore.c
+++ b/drivers/gpu/drm/i915/intel_uncore.c
@@ -1679,10 +1679,15 @@ int intel_wait_for_register(struct drm_i915_private *dev_priv,
static int gen8_engine_reset_begin(struct intel_engine_cs *engine)
{
struct drm_i915_private *dev_priv = engine->i915;
+ const i915_reg_t reset_ctrl = RING_RESET_CTL(engine->mmio_base);
+ const u32 ready = RESET_CTL_REQUEST_RESET | RESET_CTL_READY_TO_RESET;
int ret;
- I915_WRITE_FW(RING_RESET_CTL(engine->mmio_base),
- _MASKED_BIT_ENABLE(RESET_CTL_REQUEST_RESET));
+ /* If engine has been already prepared, we can shortcut here */
+ if ((I915_READ_FW(reset_ctrl) & ready) == ready)
+ return 0;
+
+ I915_WRITE_FW(reset_ctrl, _MASKED_BIT_ENABLE(RESET_CTL_REQUEST_RESET));
ret = intel_wait_for_register_fw(dev_priv,
RING_RESET_CTL(engine->mmio_base),
--
2.7.4
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 12+ messages in thread* [PATCH 5/7] drm/i915/tdr: Add engine reset count to error state
2016-09-19 15:30 [PATCH 1/7] drm/i915: Update i915.reset to handle engine resets Matthew Auld
` (2 preceding siblings ...)
2016-09-19 15:30 ` [PATCH 4/7] drm/i915: Skip reset request if there is one already Matthew Auld
@ 2016-09-19 15:30 ` Matthew Auld
2016-09-19 15:30 ` [PATCH 6/7] drm/i915/tdr: Export reset count info to debugfs Matthew Auld
` (4 subsequent siblings)
8 siblings, 0 replies; 12+ messages in thread
From: Matthew Auld @ 2016-09-19 15:30 UTC (permalink / raw)
To: intel-gfx
From: "arun.siluvery@linux.intel.com" <arun.siluvery@linux.intel.com>
Driver maintains count of how many times a given engine is reset, useful to
capture this in error state also. It gives an idea of how engine is coping
up with the workloads it is executing before this error state.
v2
- rebase
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>
Signed-off-by: Arun Siluvery <arun.siluvery@linux.intel.com>
Signed-off-by: Matthew Auld <matthew.auld@intel.com>
---
drivers/gpu/drm/i915/i915_drv.c | 1 +
drivers/gpu/drm/i915/i915_drv.h | 9 +++++++++
drivers/gpu/drm/i915/i915_gpu_error.c | 3 +++
3 files changed, 13 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 8625207..0017ab5 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -1857,6 +1857,7 @@ int i915_reset_engine(struct intel_engine_cs *engine)
intel_engine_reset_cancel(engine);
intel_execlists_restart_submission(engine);
+ dev_priv->gpu_error.engine_reset_count[engine->id]++;
intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
return 0;
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 3dcf3f6..722aea3 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -774,6 +774,7 @@ struct drm_i915_error_state {
enum intel_engine_hangcheck_action hangcheck_action;
struct i915_address_space *vm;
int num_requests;
+ u32 reset_count;
/* our own tracking of ring head and tail */
u32 cpu_ring_head;
@@ -1431,6 +1432,8 @@ struct i915_gpu_error {
#define I915_RESET_IN_PROGRESS 0
#define I915_WEDGED (BITS_PER_LONG - 1)
+ unsigned long engine_reset_count[I915_NUM_ENGINES];
+
/**
* Waitqueue to signal when a hang is detected. Used to for waiters
* to release the struct_mutex for the reset to procede.
@@ -3268,6 +3271,12 @@ static inline u32 i915_reset_count(struct i915_gpu_error *error)
return READ_ONCE(error->reset_count);
}
+static inline u32 i915_engine_reset_count(struct i915_gpu_error *error,
+ struct intel_engine_cs *engine)
+{
+ return READ_ONCE(error->engine_reset_count[engine->id]);
+}
+
void i915_gem_reset(struct drm_i915_private *dev_priv);
void i915_gem_set_wedged(struct drm_i915_private *dev_priv);
void i915_gem_reset_engine(struct intel_engine_cs *engine);
diff --git a/drivers/gpu/drm/i915/i915_gpu_error.c b/drivers/gpu/drm/i915/i915_gpu_error.c
index 334f15d..905b649 100644
--- a/drivers/gpu/drm/i915/i915_gpu_error.c
+++ b/drivers/gpu/drm/i915/i915_gpu_error.c
@@ -296,6 +296,7 @@ static void error_print_engine(struct drm_i915_error_state_buf *m,
err_printf(m, " hangcheck: %s [%d]\n",
hangcheck_action_to_str(ee->hangcheck_action),
ee->hangcheck_score);
+ err_printf(m, " engine reset count: %u\n", ee->reset_count);
}
void i915_error_printf(struct drm_i915_error_state_buf *e, const char *f, ...)
@@ -1056,6 +1057,8 @@ static void error_record_engine_registers(struct drm_i915_error_state *error,
ee->hangcheck_score = engine->hangcheck.score;
ee->hangcheck_action = engine->hangcheck.action;
+ ee->reset_count = i915_engine_reset_count(&dev_priv->gpu_error,
+ engine);
if (USES_PPGTT(dev_priv)) {
int i;
--
2.7.4
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 12+ messages in thread* [PATCH 6/7] drm/i915/tdr: Export reset count info to debugfs
2016-09-19 15:30 [PATCH 1/7] drm/i915: Update i915.reset to handle engine resets Matthew Auld
` (3 preceding siblings ...)
2016-09-19 15:30 ` [PATCH 5/7] drm/i915/tdr: Add engine reset count to error state Matthew Auld
@ 2016-09-19 15:30 ` Matthew Auld
2016-09-19 15:30 ` [PATCH 7/7] drm/i915/tdr: Enable Engine reset and recovery support Matthew Auld
` (3 subsequent siblings)
8 siblings, 0 replies; 12+ messages in thread
From: Matthew Auld @ 2016-09-19 15:30 UTC (permalink / raw)
To: intel-gfx
From: "arun.siluvery@linux.intel.com" <arun.siluvery@linux.intel.com>
A new variable is added to export the reset counts to debugfs, this
includes full gpu reset and engine reset count. This is useful for tests
where they areexpected to trigger reset; these counts are checked before
and after the test to ensure the same.
v2
- rebase
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>
Signed-off-by: Arun Siluvery <arun.siluvery@linux.intel.com>
Signed-off-by: Matthew Auld <matthew.auld@intel.com>
---
drivers/gpu/drm/i915/i915_debugfs.c | 19 +++++++++++++++++++
1 file changed, 19 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
index 27b0e34..83c8b02 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -1354,6 +1354,24 @@ static int i915_hangcheck_info(struct seq_file *m, void *unused)
return 0;
}
+static int i915_reset_info(struct seq_file *m, void *unused)
+{
+ struct drm_info_node *node = m->private;
+ struct drm_device *dev = node->minor->dev;
+ struct drm_i915_private *dev_priv = dev->dev_private;
+ struct i915_gpu_error *error = &dev_priv->gpu_error;
+ struct intel_engine_cs *engine;
+
+ seq_printf(m, "full gpu reset = %u\n", i915_reset_count(error));
+
+ for_each_engine(engine, dev_priv) {
+ seq_printf(m, "%s = %u\n", engine->name,
+ i915_engine_reset_count(error, engine));
+ }
+
+ return 0;
+}
+
static int ironlake_drpc_info(struct seq_file *m)
{
struct drm_i915_private *dev_priv = node_to_i915(m->private);
@@ -5263,6 +5281,7 @@ static const struct drm_info_list i915_debugfs_list[] = {
{"i915_guc_log_dump", i915_guc_log_dump, 0},
{"i915_frequency_info", i915_frequency_info, 0},
{"i915_hangcheck_info", i915_hangcheck_info, 0},
+ {"i915_reset_info", i915_reset_info, 0},
{"i915_drpc_info", i915_drpc_info, 0},
{"i915_emon_status", i915_emon_status, 0},
{"i915_ring_freq_table", i915_ring_freq_table, 0},
--
2.7.4
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^ permalink raw reply related [flat|nested] 12+ messages in thread* [PATCH 7/7] drm/i915/tdr: Enable Engine reset and recovery support
2016-09-19 15:30 [PATCH 1/7] drm/i915: Update i915.reset to handle engine resets Matthew Auld
` (4 preceding siblings ...)
2016-09-19 15:30 ` [PATCH 6/7] drm/i915/tdr: Export reset count info to debugfs Matthew Auld
@ 2016-09-19 15:30 ` Matthew Auld
2016-09-19 16:00 ` [PATCH 1/7] drm/i915: Update i915.reset to handle engine resets Joonas Lahtinen
` (2 subsequent siblings)
8 siblings, 0 replies; 12+ messages in thread
From: Matthew Auld @ 2016-09-19 15:30 UTC (permalink / raw)
To: intel-gfx; +Cc: Tomas Elf
From: "arun.siluvery@linux.intel.com" <arun.siluvery@linux.intel.com>
This feature is made available only from Gen8, for previous gen devices
driver uses legacy full gpu reset.
v2
- rebase
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>
Signed-off-by: Tomas Elf <tomas.elf@intel.com>
Signed-off-by: Arun Siluvery <arun.siluvery@linux.intel.com>
Signed-off-by: Matthew Auld <matthew.auld@intel.com>
---
drivers/gpu/drm/i915/i915_params.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_params.c b/drivers/gpu/drm/i915/i915_params.c
index a945ec1..d2a6e83 100644
--- a/drivers/gpu/drm/i915/i915_params.c
+++ b/drivers/gpu/drm/i915/i915_params.c
@@ -46,7 +46,7 @@ struct i915_params i915 __read_mostly = {
.prefault_disable = 0,
.load_detect_test = 0,
.force_reset_modeset_test = 0,
- .reset = 1,
+ .reset = 2,
.invert_brightness = 0,
.disable_display = 0,
.enable_cmd_parser = 1,
@@ -113,7 +113,7 @@ MODULE_PARM_DESC(vbt_sdvo_panel_type,
"(-2=ignore, -1=auto [default], index in VBT BIOS table)");
module_param_named_unsafe(reset, i915.reset, int, 0600);
-MODULE_PARM_DESC(reset, "Attempt GPU resets (0=disabled, 1=full gpu reset [default], 2=engine reset)");
+MODULE_PARM_DESC(reset, "Attempt GPU resets (0=disabled, 1=full gpu reset, 2=engine reset [default])");
module_param_named_unsafe(enable_hangcheck, i915.enable_hangcheck, bool, 0644);
MODULE_PARM_DESC(enable_hangcheck,
--
2.7.4
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^ permalink raw reply related [flat|nested] 12+ messages in thread* Re: [PATCH 1/7] drm/i915: Update i915.reset to handle engine resets
2016-09-19 15:30 [PATCH 1/7] drm/i915: Update i915.reset to handle engine resets Matthew Auld
` (5 preceding siblings ...)
2016-09-19 15:30 ` [PATCH 7/7] drm/i915/tdr: Enable Engine reset and recovery support Matthew Auld
@ 2016-09-19 16:00 ` Joonas Lahtinen
2016-09-19 16:50 ` ✗ Fi.CI.BAT: failure for series starting with [1/7] " Patchwork
2016-09-19 19:55 ` [PATCH 1/7] " Chris Wilson
8 siblings, 0 replies; 12+ messages in thread
From: Joonas Lahtinen @ 2016-09-19 16:00 UTC (permalink / raw)
To: Matthew Auld, intel-gfx
On ma, 2016-09-19 at 16:30 +0100, Matthew Auld wrote:
> From: "arun.siluvery@linux.intel.com" <arun.siluvery@linux.intel.com>
>
I assume "From:" needs to be properly formatted just like
"Signed-off-by:". So in all patches;
From: Arun Siluvery <arun.siluvery@linux.intel.com>
Cover letters are also gaining popularity, and remember to use
--reroll-count=N when submitting new iterations of the same series,
will help people and Patchwork :)
Regards, Joonas
--
Joonas Lahtinen
Open Source Technology Center
Intel Corporation
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^ permalink raw reply [flat|nested] 12+ messages in thread* ✗ Fi.CI.BAT: failure for series starting with [1/7] drm/i915: Update i915.reset to handle engine resets
2016-09-19 15:30 [PATCH 1/7] drm/i915: Update i915.reset to handle engine resets Matthew Auld
` (6 preceding siblings ...)
2016-09-19 16:00 ` [PATCH 1/7] drm/i915: Update i915.reset to handle engine resets Joonas Lahtinen
@ 2016-09-19 16:50 ` Patchwork
2016-09-19 19:55 ` [PATCH 1/7] " Chris Wilson
8 siblings, 0 replies; 12+ messages in thread
From: Patchwork @ 2016-09-19 16:50 UTC (permalink / raw)
To: Matthew Auld; +Cc: intel-gfx
== Series Details ==
Series: series starting with [1/7] drm/i915: Update i915.reset to handle engine resets
URL : https://patchwork.freedesktop.org/series/12651/
State : failure
== Summary ==
Series 12651v1 Series without cover letter
https://patchwork.freedesktop.org/api/1.0/series/12651/revisions/1/mbox/
Test kms_cursor_legacy:
Subgroup basic-flip-after-cursor-varying-size:
skip -> PASS (fi-hsw-4770r)
Test kms_pipe_crc_basic:
Subgroup read-crc-pipe-c-frame-sequence:
skip -> PASS (fi-hsw-4770r)
Subgroup suspend-read-crc-pipe-a:
dmesg-warn -> PASS (fi-skl-6700k)
Subgroup suspend-read-crc-pipe-c:
pass -> INCOMPLETE (fi-hsw-4770k)
fi-bdw-5557u total:244 pass:229 dwarn:0 dfail:0 fail:0 skip:15
fi-bsw-n3050 total:244 pass:202 dwarn:0 dfail:0 fail:0 skip:42
fi-byt-n2820 total:244 pass:208 dwarn:0 dfail:0 fail:1 skip:35
fi-hsw-4770k total:208 pass:191 dwarn:0 dfail:0 fail:0 skip:16
fi-hsw-4770r total:244 pass:222 dwarn:0 dfail:0 fail:0 skip:22
fi-ilk-650 total:244 pass:183 dwarn:0 dfail:0 fail:1 skip:60
fi-ivb-3520m total:244 pass:219 dwarn:0 dfail:0 fail:0 skip:25
fi-ivb-3770 total:244 pass:207 dwarn:0 dfail:0 fail:0 skip:37
fi-skl-6260u total:244 pass:230 dwarn:0 dfail:0 fail:0 skip:14
fi-skl-6700hq total:244 pass:221 dwarn:0 dfail:0 fail:1 skip:22
fi-skl-6700k total:244 pass:219 dwarn:1 dfail:0 fail:0 skip:24
fi-skl-6770hq total:244 pass:228 dwarn:1 dfail:0 fail:1 skip:14
fi-snb-2520m total:244 pass:208 dwarn:0 dfail:0 fail:0 skip:36
fi-snb-2600 total:244 pass:207 dwarn:0 dfail:0 fail:0 skip:37
Results at /archive/results/CI_IGT_test/Patchwork_2555/
0e34cb5b35f0f837219495c402073141481b1b90 drm-intel-nightly: 2016y-09m-19d-15h-38m-53s UTC integration manifest
63084e5 drm/i915/tdr: Enable Engine reset and recovery support
803d39e drm/i915/tdr: Export reset count info to debugfs
c13c4dc drm/i915/tdr: Add engine reset count to error state
1f33769 drm/i915: Skip reset request if there is one already
412f59f drm/i915/tdr: Add support for per engine reset recovery
d95b6e3 drm/i915/tdr: Modify error handler for per engine hang recovery
5768c16 drm/i915: Update i915.reset to handle engine resets
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^ permalink raw reply [flat|nested] 12+ messages in thread* Re: [PATCH 1/7] drm/i915: Update i915.reset to handle engine resets
2016-09-19 15:30 [PATCH 1/7] drm/i915: Update i915.reset to handle engine resets Matthew Auld
` (7 preceding siblings ...)
2016-09-19 16:50 ` ✗ Fi.CI.BAT: failure for series starting with [1/7] " Patchwork
@ 2016-09-19 19:55 ` Chris Wilson
8 siblings, 0 replies; 12+ messages in thread
From: Chris Wilson @ 2016-09-19 19:55 UTC (permalink / raw)
To: Matthew Auld; +Cc: intel-gfx
On Mon, Sep 19, 2016 at 04:30:13PM +0100, Matthew Auld wrote:
> From: "arun.siluvery@linux.intel.com" <arun.siluvery@linux.intel.com>
>
> In preparation for engine reset work update this parameter to handle more
> than one type of reset. Default at the moment is still full gpu reset.
This is not ready yet. Please try integrating into the direct reset and
request recovery. When done properly we won't even need a module option
since it will safely fallback.
-Chris
--
Chris Wilson, Intel Open Source Technology Centre
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^ permalink raw reply [flat|nested] 12+ messages in thread