Re: [PATCH 16/18] drm/i915: Enable multiple timelines

[Joonas Lahtinen <joonas.lahtinen@linux.intel.com>]

On ke, 2016-09-14 at 07:52 +0100, Chris Wilson wrote:
> @@ -315,17 +304,42 @@ submit_notify(struct i915_sw_fence *fence, enum i915_sw_fence_notify state)
>  {
>  	struct drm_i915_gem_request *request =
>  		container_of(fence, typeof(*request), submit);
> +	struct intel_timeline *timeline;
> +	struct intel_engine_cs *engine = request->engine;
> +	unsigned long flags;
> +	u32 seqno;
>  
>  	/* Will be called from irq-context when using foreign DMA fences */
>  
> -	switch (state) {
> -	case FENCE_COMPLETE:
> -		request->engine->submit_request(request);
> -		break;
> +	if (state != FENCE_COMPLETE)
> +		return NOTIFY_DONE;
>  
> -	case FENCE_FREE:
> -		break;
> -	}
> +	timeline = engine->timeline;
> +	GEM_BUG_ON(timeline == request->timeline);

Umm, why this BUG_ON?

> +
> +	spin_lock_irqsave(&timeline->lock, flags);
> +
> +	seqno = timeline_get_seqno(&request->i915->gt.global_timeline);
> +	GEM_BUG_ON(seqno == 0);
> +
> +	request->previous_seqno = timeline->last_submitted_seqno;
> +	timeline->last_submitted_seqno = seqno;
> +
> +	spin_lock_nested(&request->lock, SINGLE_DEPTH_NESTING);

A comment might be in place for the nested locking.

> +	request->global_seqno = seqno;
> +	if (test_bit(FENCE_FLAG_ENABLE_SIGNAL_BIT, &request->fence.flags))
> +		intel_engine_enable_signaling(request);
> +	spin_unlock(&request->lock);
> +
> +	engine->emit_request(request, request->ring->vaddr + request->postfix);

Is it just me or does this look very strange, let's "emit the request"
at "vaddr + request->postfix" offset. Makes no sense. Maybe reconsider
refreshing the vfunc name.

> +
> +	spin_lock_nested(&request->timeline->lock, SINGLE_DEPTH_NESTING);
> +	list_move_tail(&request->link, &timeline->requests);
> +	spin_unlock(&request->timeline->lock);
> +
> +	engine->submit_request(request);
> +
> +	spin_unlock_irqrestore(&timeline->lock, flags);
>  
>  	return NOTIFY_DONE;
>  }
> 

> @@ -685,12 +697,15 @@ void __i915_add_request(struct drm_i915_gem_request *request, bool flush_caches)
> 
>  		i915_sw_fence_await_sw_fence(&request->submit, &prev->submit,
>  					     &request->submitq, GFP_NOWAIT);
>  
> -	request->emitted_jiffies = jiffies;
> -	request->previous_seqno = timeline->last_submitted_seqno;
> +	spin_lock_irq(&timeline->lock);
> +	list_add_tail(&request->link, &timeline->requests);
> +	spin_unlock_irq(&timeline->lock);
> +
>  	timeline->last_submitted_seqno = request->fence.seqno;
>  	i915_gem_active_set(&timeline->last_request, request);
> -	list_add_tail(&request->link, &timeline->requests);
> +
>  	list_add_tail(&request->ring_link, &ring->request_list);
> +	request->emitted_jiffies = jiffies;

Is this assigment really worth delaying here?

Regards, Joonas
-- 
Joonas Lahtinen
Open Source Technology Center
Intel Corporation
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