From: Ander Conselvan de Oliveira <ander.conselvan.de.oliveira@intel.com>
To: intel-gfx@lists.freedesktop.org
Cc: Ander Conselvan de Oliveira <ander.conselvan.de.oliveira@intel.com>
Subject: [PATCH 00/15] Geminilake enabling
Date: Thu, 10 Nov 2016 17:23:05 +0200 [thread overview]
Message-ID: <1478791400-21756-1-git-send-email-ander.conselvan.de.oliveira@intel.com> (raw)
Ander Conselvan de Oliveira (12):
drm/i915/glk: Introduce Geminilake platform definition
drm/i915/glk: Add Geminilake PCI IDs
drm/i915/glk: Add a IS_GEN9_LP() macro
drm/i915/glk: Reuse broxton code for geminilake
drm/i915/glk: Set DDI PHY lane lane optimization for Geminilake too
drm/i915/glk: Add power wells for Geminilake
drm/i915/glk: Implement Geminilake DDI init sequence
drm/i915/glk: Set DDC delay range 2 in PLL enable sequence
drm/i915/glk: Reuse broxton's cdclk code for GLK
drm/i915/glk: Allow dotclock up to 2 * cdclk on geminilake
drm/i915/glk: Implement core display init/uninit sequence for
geminilake
drm/i915/glk: Configure number of sprite planes properly
Madhav Chauhan (1):
drm/i915/glk: Update Port PLL enable sequence for Geminilkae
Rodrigo Vivi (2):
drm/i915: Create a common GEN9_LP_FEATURE.
drm/i915/glk: Force DDI initialization.
drivers/gpu/drm/i915/i915_debugfs.c | 12 +--
drivers/gpu/drm/i915/i915_drv.h | 10 +-
drivers/gpu/drm/i915/i915_gem_gtt.c | 8 +-
drivers/gpu/drm/i915/i915_irq.c | 10 +-
drivers/gpu/drm/i915/i915_pci.c | 55 ++++++-----
drivers/gpu/drm/i915/i915_reg.h | 44 +++++++--
drivers/gpu/drm/i915/intel_bios.c | 2 +-
drivers/gpu/drm/i915/intel_ddi.c | 18 ++--
drivers/gpu/drm/i915/intel_device_info.c | 5 +-
drivers/gpu/drm/i915/intel_display.c | 89 ++++++++++++++---
drivers/gpu/drm/i915/intel_dp.c | 20 ++--
drivers/gpu/drm/i915/intel_dpio_phy.c | 114 ++++++++++++++++++---
drivers/gpu/drm/i915/intel_dpll_mgr.c | 32 +++++-
drivers/gpu/drm/i915/intel_dsi.c | 28 +++---
drivers/gpu/drm/i915/intel_dsi_pll.c | 12 +--
drivers/gpu/drm/i915/intel_hdmi.c | 6 +-
drivers/gpu/drm/i915/intel_i2c.c | 4 +-
drivers/gpu/drm/i915/intel_mocs.c | 2 +-
drivers/gpu/drm/i915/intel_panel.c | 2 +-
drivers/gpu/drm/i915/intel_pm.c | 6 +-
drivers/gpu/drm/i915/intel_runtime_pm.c | 163 +++++++++++++++++++++++++++++--
include/drm/i915_pciids.h | 4 +
22 files changed, 508 insertions(+), 138 deletions(-)
--
2.5.5
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
next reply other threads:[~2016-11-10 15:23 UTC|newest]
Thread overview: 52+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-11-10 15:23 Ander Conselvan de Oliveira [this message]
2016-11-10 15:23 ` [PATCH 01/15] drm/i915: Create a common GEN9_LP_FEATURE Ander Conselvan de Oliveira
2016-11-14 14:19 ` [PATCH v2] " Ander Conselvan de Oliveira
2016-11-30 14:00 ` Imre Deak
2016-12-01 9:33 ` [PATCH v3] " Ander Conselvan de Oliveira
2016-11-10 15:23 ` [PATCH 02/15] drm/i915/glk: Introduce Geminilake platform definition Ander Conselvan de Oliveira
2016-11-10 16:40 ` Jani Nikula
2016-11-10 17:03 ` Rodrigo Vivi
2016-11-11 13:34 ` Ander Conselvan De Oliveira
2016-11-10 23:18 ` Matt Roper
2016-11-14 14:24 ` [PATCH v2 01/13] drm/i915/glk: Add Geminilake PCI IDs Ander Conselvan de Oliveira
2016-11-14 14:29 ` Ander Conselvan De Oliveira
2016-11-14 14:25 ` [PATCH v3] drm/i915/glk: Introduce Geminilake platform definition Ander Conselvan de Oliveira
2016-11-10 15:23 ` [PATCH 03/15] drm/i915/glk: Add Geminilake PCI IDs Ander Conselvan de Oliveira
2016-11-10 17:03 ` Rodrigo Vivi
2016-11-10 15:23 ` [PATCH 04/15] drm/i915/glk: Add a IS_GEN9_LP() macro Ander Conselvan de Oliveira
2016-11-10 15:23 ` [PATCH 05/15] drm/i915/glk: Reuse broxton code for geminilake Ander Conselvan de Oliveira
2016-11-10 17:08 ` Rodrigo Vivi
2016-11-11 13:52 ` [PATCH v2] " Ander Conselvan de Oliveira
2016-11-11 15:26 ` kbuild test robot
2016-11-29 15:47 ` [PATCH v3] " Ander Conselvan de Oliveira
2016-12-02 1:06 ` Rodrigo Vivi
2016-12-02 8:27 ` Ander Conselvan De Oliveira
2016-12-02 18:46 ` Vivi, Rodrigo
2016-11-10 15:23 ` [PATCH 06/15] drm/i915/glk: Force DDI initialization Ander Conselvan de Oliveira
2016-12-02 0:52 ` Rodrigo Vivi
2016-12-02 8:16 ` Ander Conselvan De Oliveira
2016-11-10 15:23 ` [PATCH 07/15] drm/i915/glk: Set DDI PHY lane lane optimization for Geminilake too Ander Conselvan de Oliveira
2016-12-02 0:50 ` Rodrigo Vivi
2016-11-10 15:23 ` [PATCH 08/15] drm/i915/glk: Add power wells for Geminilake Ander Conselvan de Oliveira
2016-12-02 0:48 ` Rodrigo Vivi
2016-11-10 15:23 ` [PATCH 09/15] drm/i915/glk: Implement Geminilake DDI init sequence Ander Conselvan de Oliveira
2016-11-11 1:27 ` Rodrigo Vivi
2016-11-10 15:23 ` [PATCH 10/15] drm/i915/glk: Set DCC delay range 2 in PLL enable sequence Ander Conselvan de Oliveira
2016-11-29 15:48 ` [PATCH v2] " Ander Conselvan de Oliveira
2016-11-29 16:58 ` Vivi, Rodrigo
2016-11-10 15:23 ` [PATCH 11/15] drm/i915/glk: Update Port PLL enable sequence for Geminilkae Ander Conselvan de Oliveira
2016-12-02 0:44 ` Rodrigo Vivi
2016-11-10 15:23 ` [PATCH 12/15] drm/i915/glk: Reuse broxton's cdclk code for GLK Ander Conselvan de Oliveira
2016-12-02 0:43 ` Rodrigo Vivi
2016-11-10 15:23 ` [PATCH 13/15] drm/i915/glk: Allow dotclock up to 2 * cdclk on geminilake Ander Conselvan de Oliveira
2016-12-01 23:59 ` Rodrigo Vivi
2016-11-10 15:23 ` [PATCH 14/15] drm/i915/glk: Implement core display init/uninit sequence for geminilake Ander Conselvan de Oliveira
2016-12-01 23:58 ` Rodrigo Vivi
2016-11-10 15:23 ` [PATCH 15/15] drm/i915/glk: Configure number of sprite planes properly Ander Conselvan de Oliveira
2016-12-01 23:57 ` Rodrigo Vivi
2016-11-10 16:17 ` ✓ Fi.CI.BAT: success for Geminilake enabling Patchwork
2016-11-11 14:45 ` ✓ Fi.CI.BAT: success for Geminilake enabling (rev2) Patchwork
2016-11-14 14:47 ` ✓ Fi.CI.BAT: success for Geminilake enabling (rev5) Patchwork
2016-11-14 16:16 ` Patchwork
2016-12-01 11:15 ` ✓ Fi.CI.BAT: success for Geminilake enabling (rev8) Patchwork
2016-12-01 11:43 ` Ander Conselvan De Oliveira
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=1478791400-21756-1-git-send-email-ander.conselvan.de.oliveira@intel.com \
--to=ander.conselvan.de.oliveira@intel.com \
--cc=intel-gfx@lists.freedesktop.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).