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From: Ander Conselvan de Oliveira <ander.conselvan.de.oliveira@intel.com>
To: intel-gfx@lists.freedesktop.org
Cc: Ander Conselvan de Oliveira <ander.conselvan.de.oliveira@intel.com>
Subject: [PATCH 07/15] drm/i915/glk: Set DDI PHY lane lane optimization for Geminilake too
Date: Thu, 10 Nov 2016 17:23:12 +0200	[thread overview]
Message-ID: <1478791400-21756-8-git-send-email-ander.conselvan.de.oliveira@intel.com> (raw)
In-Reply-To: <1478791400-21756-1-git-send-email-ander.conselvan.de.oliveira@intel.com>

Geminilake uses the same lane latency optimization masks and registers
as Broxton, so reuse the code with that platform too.

Signed-off-by: Ander Conselvan de Oliveira <ander.conselvan.de.oliveira@intel.com>
---
 drivers/gpu/drm/i915/intel_ddi.c | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
index dcad209..aec8265 100644
--- a/drivers/gpu/drm/i915/intel_ddi.c
+++ b/drivers/gpu/drm/i915/intel_ddi.c
@@ -1429,7 +1429,7 @@ bool intel_ddi_get_hw_state(struct intel_encoder *encoder,
 	DRM_DEBUG_KMS("No pipe for ddi port %c found\n", port_name(port));
 
 out:
-	if (ret && IS_BROXTON(dev_priv)) {
+	if (ret && IS_GEN9_LP(dev_priv)) {
 		tmp = I915_READ(BXT_PHY_CTL(port));
 		if ((tmp & (BXT_PHY_LANE_POWERDOWN_ACK |
 			    BXT_PHY_LANE_ENABLED)) != BXT_PHY_LANE_ENABLED)
@@ -2044,7 +2044,7 @@ void intel_ddi_get_config(struct intel_encoder *encoder,
 
 	intel_ddi_clock_get(encoder, pipe_config);
 
-	if (IS_BROXTON(dev_priv))
+	if (IS_GEN9_LP(dev_priv))
 		pipe_config->lane_lat_optim_mask =
 			bxt_ddi_phy_get_lane_lat_optim_mask(encoder);
 }
@@ -2068,7 +2068,7 @@ static bool intel_ddi_compute_config(struct intel_encoder *encoder,
 	else
 		ret = intel_dp_compute_config(encoder, pipe_config, conn_state);
 
-	if (IS_BROXTON(dev_priv) && ret)
+	if (IS_GEN9_LP(dev_priv) && ret)
 		pipe_config->lane_lat_optim_mask =
 			bxt_ddi_phy_calc_lane_lat_optim_mask(encoder,
 							     pipe_config->lane_count);
@@ -2225,7 +2225,7 @@ void intel_ddi_init(struct drm_device *dev, enum port port)
 
 	intel_encoder->compute_config = intel_ddi_compute_config;
 	intel_encoder->enable = intel_enable_ddi;
-	if (IS_BROXTON(dev_priv))
+	if (IS_GEN9_LP(dev_priv))
 		intel_encoder->pre_pll_enable = bxt_ddi_pre_pll_enable;
 	intel_encoder->pre_enable = intel_ddi_pre_enable;
 	intel_encoder->disable = intel_disable_ddi;
-- 
2.5.5

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  parent reply	other threads:[~2016-11-10 15:24 UTC|newest]

Thread overview: 52+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2016-11-10 15:23 [PATCH 00/15] Geminilake enabling Ander Conselvan de Oliveira
2016-11-10 15:23 ` [PATCH 01/15] drm/i915: Create a common GEN9_LP_FEATURE Ander Conselvan de Oliveira
2016-11-14 14:19   ` [PATCH v2] " Ander Conselvan de Oliveira
2016-11-30 14:00     ` Imre Deak
2016-12-01  9:33       ` [PATCH v3] " Ander Conselvan de Oliveira
2016-11-10 15:23 ` [PATCH 02/15] drm/i915/glk: Introduce Geminilake platform definition Ander Conselvan de Oliveira
2016-11-10 16:40   ` Jani Nikula
2016-11-10 17:03     ` Rodrigo Vivi
2016-11-11 13:34       ` Ander Conselvan De Oliveira
2016-11-10 23:18   ` Matt Roper
2016-11-14 14:24     ` [PATCH v2 01/13] drm/i915/glk: Add Geminilake PCI IDs Ander Conselvan de Oliveira
2016-11-14 14:29       ` Ander Conselvan De Oliveira
2016-11-14 14:25     ` [PATCH v3] drm/i915/glk: Introduce Geminilake platform definition Ander Conselvan de Oliveira
2016-11-10 15:23 ` [PATCH 03/15] drm/i915/glk: Add Geminilake PCI IDs Ander Conselvan de Oliveira
2016-11-10 17:03   ` Rodrigo Vivi
2016-11-10 15:23 ` [PATCH 04/15] drm/i915/glk: Add a IS_GEN9_LP() macro Ander Conselvan de Oliveira
2016-11-10 15:23 ` [PATCH 05/15] drm/i915/glk: Reuse broxton code for geminilake Ander Conselvan de Oliveira
2016-11-10 17:08   ` Rodrigo Vivi
2016-11-11 13:52     ` [PATCH v2] " Ander Conselvan de Oliveira
2016-11-11 15:26       ` kbuild test robot
2016-11-29 15:47       ` [PATCH v3] " Ander Conselvan de Oliveira
2016-12-02  1:06         ` Rodrigo Vivi
2016-12-02  8:27           ` Ander Conselvan De Oliveira
2016-12-02 18:46             ` Vivi, Rodrigo
2016-11-10 15:23 ` [PATCH 06/15] drm/i915/glk: Force DDI initialization Ander Conselvan de Oliveira
2016-12-02  0:52   ` Rodrigo Vivi
2016-12-02  8:16     ` Ander Conselvan De Oliveira
2016-11-10 15:23 ` Ander Conselvan de Oliveira [this message]
2016-12-02  0:50   ` [PATCH 07/15] drm/i915/glk: Set DDI PHY lane lane optimization for Geminilake too Rodrigo Vivi
2016-11-10 15:23 ` [PATCH 08/15] drm/i915/glk: Add power wells for Geminilake Ander Conselvan de Oliveira
2016-12-02  0:48   ` Rodrigo Vivi
2016-11-10 15:23 ` [PATCH 09/15] drm/i915/glk: Implement Geminilake DDI init sequence Ander Conselvan de Oliveira
2016-11-11  1:27   ` Rodrigo Vivi
2016-11-10 15:23 ` [PATCH 10/15] drm/i915/glk: Set DCC delay range 2 in PLL enable sequence Ander Conselvan de Oliveira
2016-11-29 15:48   ` [PATCH v2] " Ander Conselvan de Oliveira
2016-11-29 16:58     ` Vivi, Rodrigo
2016-11-10 15:23 ` [PATCH 11/15] drm/i915/glk: Update Port PLL enable sequence for Geminilkae Ander Conselvan de Oliveira
2016-12-02  0:44   ` Rodrigo Vivi
2016-11-10 15:23 ` [PATCH 12/15] drm/i915/glk: Reuse broxton's cdclk code for GLK Ander Conselvan de Oliveira
2016-12-02  0:43   ` Rodrigo Vivi
2016-11-10 15:23 ` [PATCH 13/15] drm/i915/glk: Allow dotclock up to 2 * cdclk on geminilake Ander Conselvan de Oliveira
2016-12-01 23:59   ` Rodrigo Vivi
2016-11-10 15:23 ` [PATCH 14/15] drm/i915/glk: Implement core display init/uninit sequence for geminilake Ander Conselvan de Oliveira
2016-12-01 23:58   ` Rodrigo Vivi
2016-11-10 15:23 ` [PATCH 15/15] drm/i915/glk: Configure number of sprite planes properly Ander Conselvan de Oliveira
2016-12-01 23:57   ` Rodrigo Vivi
2016-11-10 16:17 ` ✓ Fi.CI.BAT: success for Geminilake enabling Patchwork
2016-11-11 14:45 ` ✓ Fi.CI.BAT: success for Geminilake enabling (rev2) Patchwork
2016-11-14 14:47 ` ✓ Fi.CI.BAT: success for Geminilake enabling (rev5) Patchwork
2016-11-14 16:16 ` Patchwork
2016-12-01 11:15 ` ✓ Fi.CI.BAT: success for Geminilake enabling (rev8) Patchwork
2016-12-01 11:43   ` Ander Conselvan De Oliveira

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