From: Ander Conselvan de Oliveira <ander.conselvan.de.oliveira@intel.com>
To: intel-gfx@lists.freedesktop.org
Cc: Ander Conselvan de Oliveira <ander.conselvan.de.oliveira@intel.com>
Subject: [PATCH v3] drm/i915/glk: Introduce Geminilake platform definition
Date: Mon, 14 Nov 2016 16:25:26 +0200 [thread overview]
Message-ID: <1479133526-32389-1-git-send-email-ander.conselvan.de.oliveira@intel.com> (raw)
In-Reply-To: <20161110231808.GW6536@intel.com>
Geminilake is an Intel® Processor containing Intel® HD Graphics
following Broxton.
Let's start by adding the platform definition. PCI IDs and plaform
specific code will follow.
v2: Rebase (don't allow dev to be used with the new macro).
v3: Update ddb size. (Matt)
Rebase on s/preliminary_hw/alpha/
Cc: Matt Roper <matthew.d.roper@intel.com>
Cc: Rodrigo Vivi <rodrigo.vivi@gmail.com>
Signed-off-by: Ander Conselvan de Oliveira <ander.conselvan.de.oliveira@intel.com>
---
drivers/gpu/drm/i915/i915_drv.h | 2 ++
drivers/gpu/drm/i915/i915_pci.c | 7 +++++++
2 files changed, 9 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index c4a14de..29a2d2a 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -654,6 +654,7 @@ struct intel_csr {
func(is_broadwell); \
func(is_skylake); \
func(is_broxton); \
+ func(is_geminilake); \
func(is_kabylake); \
func(is_alpha_support); \
/* Keep has_* in alphabetical order */ \
@@ -2432,6 +2433,7 @@ struct drm_i915_cmd_table {
#define IS_BROADWELL(dev_priv) ((dev_priv)->info.is_broadwell)
#define IS_SKYLAKE(dev_priv) ((dev_priv)->info.is_skylake)
#define IS_BROXTON(dev_priv) ((dev_priv)->info.is_broxton)
+#define IS_GEMINILAKE(dev_priv) ((dev_priv)->info.is_geminilake)
#define IS_KABYLAKE(dev_priv) ((dev_priv)->info.is_kabylake)
#define IS_MOBILE(dev_priv) ((dev_priv)->info.is_mobile)
#define IS_HSW_EARLY_SDV(dev_priv) (IS_HASWELL(dev_priv) && \
diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index f8b93c1..2c9645f 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -372,6 +372,13 @@ static const struct intel_device_info intel_broxton_info = {
.ddb_size = 512,
};
+static const struct intel_device_info intel_geminilake_info = {
+ .is_alpha_support = 1,
+ .is_geminilake = 1,
+ GEN9_LP_FEATURES,
+ .ddb_size = 1024,
+};
+
static const struct intel_device_info intel_kabylake_info = {
BDW_FEATURES,
.is_kabylake = 1,
--
2.5.5
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next prev parent reply other threads:[~2016-11-14 14:25 UTC|newest]
Thread overview: 52+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-11-10 15:23 [PATCH 00/15] Geminilake enabling Ander Conselvan de Oliveira
2016-11-10 15:23 ` [PATCH 01/15] drm/i915: Create a common GEN9_LP_FEATURE Ander Conselvan de Oliveira
2016-11-14 14:19 ` [PATCH v2] " Ander Conselvan de Oliveira
2016-11-30 14:00 ` Imre Deak
2016-12-01 9:33 ` [PATCH v3] " Ander Conselvan de Oliveira
2016-11-10 15:23 ` [PATCH 02/15] drm/i915/glk: Introduce Geminilake platform definition Ander Conselvan de Oliveira
2016-11-10 16:40 ` Jani Nikula
2016-11-10 17:03 ` Rodrigo Vivi
2016-11-11 13:34 ` Ander Conselvan De Oliveira
2016-11-10 23:18 ` Matt Roper
2016-11-14 14:24 ` [PATCH v2 01/13] drm/i915/glk: Add Geminilake PCI IDs Ander Conselvan de Oliveira
2016-11-14 14:29 ` Ander Conselvan De Oliveira
2016-11-14 14:25 ` Ander Conselvan de Oliveira [this message]
2016-11-10 15:23 ` [PATCH 03/15] " Ander Conselvan de Oliveira
2016-11-10 17:03 ` Rodrigo Vivi
2016-11-10 15:23 ` [PATCH 04/15] drm/i915/glk: Add a IS_GEN9_LP() macro Ander Conselvan de Oliveira
2016-11-10 15:23 ` [PATCH 05/15] drm/i915/glk: Reuse broxton code for geminilake Ander Conselvan de Oliveira
2016-11-10 17:08 ` Rodrigo Vivi
2016-11-11 13:52 ` [PATCH v2] " Ander Conselvan de Oliveira
2016-11-11 15:26 ` kbuild test robot
2016-11-29 15:47 ` [PATCH v3] " Ander Conselvan de Oliveira
2016-12-02 1:06 ` Rodrigo Vivi
2016-12-02 8:27 ` Ander Conselvan De Oliveira
2016-12-02 18:46 ` Vivi, Rodrigo
2016-11-10 15:23 ` [PATCH 06/15] drm/i915/glk: Force DDI initialization Ander Conselvan de Oliveira
2016-12-02 0:52 ` Rodrigo Vivi
2016-12-02 8:16 ` Ander Conselvan De Oliveira
2016-11-10 15:23 ` [PATCH 07/15] drm/i915/glk: Set DDI PHY lane lane optimization for Geminilake too Ander Conselvan de Oliveira
2016-12-02 0:50 ` Rodrigo Vivi
2016-11-10 15:23 ` [PATCH 08/15] drm/i915/glk: Add power wells for Geminilake Ander Conselvan de Oliveira
2016-12-02 0:48 ` Rodrigo Vivi
2016-11-10 15:23 ` [PATCH 09/15] drm/i915/glk: Implement Geminilake DDI init sequence Ander Conselvan de Oliveira
2016-11-11 1:27 ` Rodrigo Vivi
2016-11-10 15:23 ` [PATCH 10/15] drm/i915/glk: Set DCC delay range 2 in PLL enable sequence Ander Conselvan de Oliveira
2016-11-29 15:48 ` [PATCH v2] " Ander Conselvan de Oliveira
2016-11-29 16:58 ` Vivi, Rodrigo
2016-11-10 15:23 ` [PATCH 11/15] drm/i915/glk: Update Port PLL enable sequence for Geminilkae Ander Conselvan de Oliveira
2016-12-02 0:44 ` Rodrigo Vivi
2016-11-10 15:23 ` [PATCH 12/15] drm/i915/glk: Reuse broxton's cdclk code for GLK Ander Conselvan de Oliveira
2016-12-02 0:43 ` Rodrigo Vivi
2016-11-10 15:23 ` [PATCH 13/15] drm/i915/glk: Allow dotclock up to 2 * cdclk on geminilake Ander Conselvan de Oliveira
2016-12-01 23:59 ` Rodrigo Vivi
2016-11-10 15:23 ` [PATCH 14/15] drm/i915/glk: Implement core display init/uninit sequence for geminilake Ander Conselvan de Oliveira
2016-12-01 23:58 ` Rodrigo Vivi
2016-11-10 15:23 ` [PATCH 15/15] drm/i915/glk: Configure number of sprite planes properly Ander Conselvan de Oliveira
2016-12-01 23:57 ` Rodrigo Vivi
2016-11-10 16:17 ` ✓ Fi.CI.BAT: success for Geminilake enabling Patchwork
2016-11-11 14:45 ` ✓ Fi.CI.BAT: success for Geminilake enabling (rev2) Patchwork
2016-11-14 14:47 ` ✓ Fi.CI.BAT: success for Geminilake enabling (rev5) Patchwork
2016-11-14 16:16 ` Patchwork
2016-12-01 11:15 ` ✓ Fi.CI.BAT: success for Geminilake enabling (rev8) Patchwork
2016-12-01 11:43 ` Ander Conselvan De Oliveira
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