From: Paulo Zanoni <paulo.r.zanoni@intel.com>
To: Mahesh Kumar <mahesh1.kumar@intel.com>, intel-gfx@lists.freedesktop.org
Cc: "Conselvan De Oliveira,
Ander" <ander.conselvan.de.oliveira@intel.com>,
maarten.lankhorst@intel.com
Subject: Re: [PATCH v5 2/8] drm/i915/bxt: IPC WA for Broxton
Date: Mon, 21 Nov 2016 15:23:36 -0200 [thread overview]
Message-ID: <1479749016.2890.18.camel@intel.com> (raw)
In-Reply-To: <20161118150934.29851-3-mahesh1.kumar@intel.com>
Em Sex, 2016-11-18 às 20:39 +0530, Mahesh Kumar escreveu:
> If IPC is enabled in BXT, display underruns are observed.
> WA: The Line Time programmed in the WM_LINETIME register should be
> half of the actual calculated Line Time.
>
> Programmed Line Time = 1/2*Calculated Line Time
>
> Signed-off-by: Mahesh Kumar <mahesh1.kumar@intel.com>
> ---
> drivers/gpu/drm/i915/i915_drv.c | 2 ++
> drivers/gpu/drm/i915/i915_drv.h | 3 +++
> drivers/gpu/drm/i915/intel_pm.c | 11 +++++++++--
> 3 files changed, 14 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_drv.c
> b/drivers/gpu/drm/i915/i915_drv.c
> index 445fec9..1b0a589 100644
> --- a/drivers/gpu/drm/i915/i915_drv.c
> +++ b/drivers/gpu/drm/i915/i915_drv.c
> @@ -1243,6 +1243,8 @@ int i915_driver_load(struct pci_dev *pdev,
> const struct pci_device_id *ent)
>
> intel_runtime_pm_enable(dev_priv);
>
> + dev_priv->ipc_enabled = false;
> +
> /* Everything is in place, we can now relax! */
> DRM_INFO("Initialized %s %d.%d.%d %s for %s on minor %d\n",
> driver.name, driver.major, driver.minor,
> driver.patchlevel,
> diff --git a/drivers/gpu/drm/i915/i915_drv.h
> b/drivers/gpu/drm/i915/i915_drv.h
> index 63c0ea0..394d7ea 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -2128,6 +2128,9 @@ struct drm_i915_private {
> /* perform PHY state sanity checks? */
> bool chv_phy_assert[2];
>
> + /* To apply IPC WA */
The comment is not exactly necessary since we can just look where
ipc_enabled is used to find out why it's here. As a bonus, whenever we
add more ipc_enabled readers we won't need to update the comment.
> + bool ipc_enabled;
> +
> /* Used to save the pipe-to-encoder mapping for audio */
> struct intel_encoder *av_enc_map[I915_MAX_PIPES];
>
> diff --git a/drivers/gpu/drm/i915/intel_pm.c
> b/drivers/gpu/drm/i915/intel_pm.c
> index 8908736..7090a7c 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -3769,7 +3769,10 @@ skl_compute_wm_level(const struct
> drm_i915_private *dev_priv,
> static uint32_t
> skl_compute_linetime_wm(struct intel_crtc_state *cstate)
> {
> + struct drm_atomic_state *state = cstate->base.state;
> + struct drm_i915_private *dev_priv = to_i915(state->dev);
> uint32_t pixel_rate;
> + uint32_t linetime_wm;
>
> if (!cstate->base.active)
> return 0;
> @@ -3779,8 +3782,12 @@ skl_compute_linetime_wm(struct
> intel_crtc_state *cstate)
> if (WARN_ON(pixel_rate == 0))
> return 0;
>
> - return DIV_ROUND_UP(8 * cstate-
> >base.adjusted_mode.crtc_htotal * 1000,
> - pixel_rate);
> + linetime_wm = DIV_ROUND_UP(8 * cstate-
> >base.adjusted_mode.crtc_htotal *
> + 1000, pixel_rate);
Weird indentation here again. Is your editor configured to show tabs as
4 spaces?
> + if (IS_BROXTON(dev_priv) && dev_priv->ipc_enabled)
Once we merge Gemnilake, we'll need to write a patch checking for it
here.
Anyway, my two suggestions can be fixed while merging, so:
Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
> + linetime_wm = DIV_ROUND_UP(linetime_wm, 2);
> +
> + return linetime_wm;
> }
>
> static void skl_compute_transition_wm(struct intel_crtc_state
> *cstate,
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next prev parent reply other threads:[~2016-11-21 17:23 UTC|newest]
Thread overview: 21+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-11-18 15:09 [PATCH v5 0/8] GEN-9 Arbitrated Bandwidth WM WA's & IPC Mahesh Kumar
2016-11-18 15:09 ` [PATCH v5 1/8] drm/i915/skl: Add variables to check x_tile and y_tile Mahesh Kumar
2016-11-21 16:51 ` Paulo Zanoni
2016-11-18 15:09 ` [PATCH v5 2/8] drm/i915/bxt: IPC WA for Broxton Mahesh Kumar
2016-11-21 17:23 ` Paulo Zanoni [this message]
2016-11-18 15:09 ` [PATCH v5 3/8] drm/i915/kbl: IPC workaround for kabylake Mahesh Kumar
2016-11-21 17:38 ` Paulo Zanoni
2016-11-18 15:09 ` [PATCH v5 4/8] drm/i915/bxt: Enable IPC support Mahesh Kumar
2016-11-21 18:46 ` Paulo Zanoni
2016-11-22 13:35 ` Mahesh Kumar
2016-11-22 14:45 ` Paulo Zanoni
2016-11-23 10:25 ` Mahesh Kumar
2016-12-02 11:51 ` Mahesh Kumar
2016-11-18 15:09 ` [PATCH v5 5/8] drm/i915/skl+: change WM calc to fixed point 16.16 Mahesh Kumar
2016-11-22 12:42 ` Paulo Zanoni
2016-11-22 14:04 ` Mahesh Kumar
2016-11-18 15:09 ` [PATCH v5 6/8] drm/i915: Add intel_atomic_get_existing_crtc_state function Mahesh Kumar
2016-11-21 19:51 ` Paulo Zanoni
2016-11-18 15:09 ` [PATCH v5 7/8] drm/i915: Decode system memory bandwidth Mahesh Kumar
2016-11-18 15:09 ` [PATCH v5 8/8] drm/i915/gen9: WM memory bandwidth related workaround Mahesh Kumar
2016-11-18 16:01 ` ✗ Fi.CI.BAT: failure for GEN-9 Arbitrated Bandwidth WM WA's & IPC Patchwork
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