From: Ander Conselvan De Oliveira <conselvan2@gmail.com>
To: ville.syrjala@linux.intel.com, intel-gfx@lists.freedesktop.org
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Subject: Re: [PATCH v2 10/14] drm/i915: Pass the cdclk state to the set_cdclk() functions
Date: Fri, 23 Dec 2016 15:43:22 +0200 [thread overview]
Message-ID: <1482500602.2633.56.camel@gmail.com> (raw)
In-Reply-To: <20161219172840.31842-11-ville.syrjala@linux.intel.com>
On Mon, 2016-12-19 at 19:28 +0200, ville.syrjala@linux.intel.com wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Rather than passing all the different parameters (cdclk,vco so
> far) sparately to the set_cdclk() functions, just pass the
> entire cdclk state.
>
> v2: Deal with churn
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
> drivers/gpu/drm/i915/intel_cdclk.c | 79 +++++++++++++++++++++++---------------
> 1 file changed, 49 insertions(+), 30 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_cdclk.c b/drivers/gpu/drm/i915/intel_cdclk.c
> index 2e998fa087a9..11a0f3e122c3 100644
> --- a/drivers/gpu/drm/i915/intel_cdclk.c
> +++ b/drivers/gpu/drm/i915/intel_cdclk.c
> @@ -433,8 +433,10 @@ static void vlv_program_pfi_credits(struct drm_i915_private *dev_priv)
> WARN_ON(I915_READ(GCI_CONTROL) & PFI_CREDIT_RESEND);
> }
>
> -static void vlv_set_cdclk(struct drm_i915_private *dev_priv, int cdclk)
> +static void vlv_set_cdclk(struct drm_i915_private *dev_priv,
> + const struct intel_cdclk_state *cdclk_state)
> {
> + int cdclk = cdclk_state->cdclk;
> u32 val, cmd;
>
> if (cdclk >= 320000) /* jump to highest voltage for 400MHz too */
> @@ -495,8 +497,10 @@ static void vlv_set_cdclk(struct drm_i915_private *dev_priv, int cdclk)
> intel_update_cdclk(dev_priv);
> }
>
> -static void chv_set_cdclk(struct drm_i915_private *dev_priv, int cdclk)
> +static void chv_set_cdclk(struct drm_i915_private *dev_priv,
> + const struct intel_cdclk_state *cdclk_state)
> {
> + int cdclk = cdclk_state->cdclk;
> u32 val, cmd;
>
> switch (cdclk) {
> @@ -564,8 +568,10 @@ static void bdw_get_cdclk(struct drm_i915_private *dev_priv,
> cdclk_state->cdclk = 675000;
> }
>
> -static void bdw_set_cdclk(struct drm_i915_private *dev_priv, int cdclk)
> +static void bdw_set_cdclk(struct drm_i915_private *dev_priv,
> + const struct intel_cdclk_state *cdclk_state)
> {
> + int cdclk = cdclk_state->cdclk;
> uint32_t val, data;
> int ret;
>
> @@ -836,8 +842,10 @@ static void skl_dpll0_disable(struct drm_i915_private *dev_priv)
> }
>
> static void skl_set_cdclk(struct drm_i915_private *dev_priv,
> - int cdclk, int vco)
> + const struct intel_cdclk_state *cdclk_state)
> {
> + int cdclk = cdclk_state->cdclk;
> + int vco = cdclk_state->vco;
> u32 freq_select, pcu_ack;
> int ret;
>
> @@ -942,12 +950,17 @@ static void skl_sanitize_cdclk(struct drm_i915_private *dev_priv)
>
> void skl_uninit_cdclk(struct drm_i915_private *dev_priv)
> {
> - skl_set_cdclk(dev_priv, dev_priv->cdclk.hw.ref, 0);
> + struct intel_cdclk_state cdclk_state = dev_priv->cdclk.hw;
> +
> + cdclk_state.cdclk = cdclk_state.ref;
> + cdclk_state.vco = 0;
> +
> + skl_set_cdclk(dev_priv, &cdclk_state);
> }
>
> void skl_init_cdclk(struct drm_i915_private *dev_priv)
> {
> - int cdclk, vco;
> + struct intel_cdclk_state cdclk_state;
>
> skl_sanitize_cdclk(dev_priv);
>
> @@ -963,12 +976,14 @@ void skl_init_cdclk(struct drm_i915_private *dev_priv)
> return;
> }
>
> - vco = dev_priv->skl_preferred_vco_freq;
> - if (vco == 0)
> - vco = 8100000;
> - cdclk = skl_calc_cdclk(0, vco);
> + cdclk_state = dev_priv->cdclk.hw;
We need this assignments to preserve cdclk.ref?
> +
> + cdclk_state.vco = dev_priv->skl_preferred_vco_freq;
> + if (cdclk_state.vco == 0)
> + cdclk_state.vco = 8100000;
> + cdclk_state.cdclk = skl_calc_cdclk(0, cdclk_state.vco);
>
> - skl_set_cdclk(dev_priv, cdclk, vco);
> + skl_set_cdclk(dev_priv, &cdclk_state);
> }
>
> static int bxt_calc_cdclk(int max_pixclk)
> @@ -1132,8 +1147,10 @@ static void bxt_de_pll_enable(struct drm_i915_private *dev_priv, int vco)
> }
>
> static void bxt_set_cdclk(struct drm_i915_private *dev_priv,
> - int cdclk, int vco)
> + const struct intel_cdclk_state *cdclk_state)
> {
> + int cdclk = cdclk_state->cdclk;
> + int vco = cdclk_state->vco;
> u32 val, divider;
> int ret;
>
> @@ -1259,7 +1276,7 @@ static void bxt_sanitize_cdclk(struct drm_i915_private *dev_priv)
>
> void bxt_init_cdclk(struct drm_i915_private *dev_priv)
> {
> - int cdclk, vco;
> + struct intel_cdclk_state cdclk_state;
>
> bxt_sanitize_cdclk(dev_priv);
>
> @@ -1267,25 +1284,33 @@ void bxt_init_cdclk(struct drm_i915_private *dev_priv)
> dev_priv->cdclk.hw.vco != 0)
> return;
>
> + cdclk_state = dev_priv->cdclk.hw;
> +
> /*
> * FIXME:
> * - The initial CDCLK needs to be read from VBT.
> * Need to make this change after VBT has changes for BXT.
> */
> if (IS_GEMINILAKE(dev_priv)) {
> - cdclk = glk_calc_cdclk(0);
> - vco = glk_de_pll_vco(dev_priv, cdclk);
> + cdclk_state.cdclk = glk_calc_cdclk(0);
> + cdclk_state.vco = glk_de_pll_vco(dev_priv, cdclk_state.cdclk);
> } else {
> - cdclk = bxt_calc_cdclk(0);
> - vco = bxt_de_pll_vco(dev_priv, cdclk);
> + cdclk_state.ref = dev_priv->cdclk.hw.ref;
hw.ref was copied above already, no need to do it here. With that fixed,
Reviewed-by: Ander Conselvan de Oliveira <conselvan2@gmail.com>
> + cdclk_state.cdclk = bxt_calc_cdclk(0);
> + cdclk_state.vco = bxt_de_pll_vco(dev_priv, cdclk_state.cdclk);
> }
>
> - bxt_set_cdclk(dev_priv, cdclk, vco);
> + bxt_set_cdclk(dev_priv, &cdclk_state);
> }
>
> void bxt_uninit_cdclk(struct drm_i915_private *dev_priv)
> {
> - bxt_set_cdclk(dev_priv, dev_priv->cdclk.hw.ref, 0);
> + struct intel_cdclk_state cdclk_state = dev_priv->cdclk.hw;
> +
> + cdclk_state.cdclk = cdclk_state.ref;
> + cdclk_state.vco = 0;
> +
> + bxt_set_cdclk(dev_priv, &cdclk_state);
> }
>
> bool intel_cdclk_state_compare(const struct intel_cdclk_state *a,
> @@ -1391,7 +1416,6 @@ static int vlv_modeset_calc_cdclk(struct drm_atomic_state *state)
> static void vlv_modeset_commit_cdclk(struct drm_atomic_state *old_state)
> {
> struct drm_i915_private *dev_priv = to_i915(old_state->dev);
> - unsigned int req_cdclk = dev_priv->cdclk.actual.cdclk;
>
> /*
> * FIXME: We can end up here with all power domains off, yet
> @@ -1405,9 +1429,9 @@ static void vlv_modeset_commit_cdclk(struct drm_atomic_state *old_state)
> intel_display_power_get(dev_priv, POWER_DOMAIN_PIPE_A);
>
> if (IS_CHERRYVIEW(dev_priv))
> - chv_set_cdclk(dev_priv, req_cdclk);
> + chv_set_cdclk(dev_priv, &dev_priv->cdclk.actual);
> else
> - vlv_set_cdclk(dev_priv, req_cdclk);
> + vlv_set_cdclk(dev_priv, &dev_priv->cdclk.actual);
>
> vlv_program_pfi_credits(dev_priv);
>
> @@ -1450,9 +1474,8 @@ static int bdw_modeset_calc_cdclk(struct drm_atomic_state *state)
> static void bdw_modeset_commit_cdclk(struct drm_atomic_state *old_state)
> {
> struct drm_i915_private *dev_priv = to_i915(old_state->dev);
> - unsigned int req_cdclk = dev_priv->cdclk.actual.cdclk;
>
> - bdw_set_cdclk(dev_priv, req_cdclk);
> + bdw_set_cdclk(dev_priv, &dev_priv->cdclk.actual);
> }
>
> static int skl_modeset_calc_cdclk(struct drm_atomic_state *state)
> @@ -1497,10 +1520,8 @@ static int skl_modeset_calc_cdclk(struct drm_atomic_state *state)
> static void skl_modeset_commit_cdclk(struct drm_atomic_state *old_state)
> {
> struct drm_i915_private *dev_priv = to_i915(old_state->dev);
> - unsigned int req_cdclk = dev_priv->cdclk.actual.cdclk;
> - unsigned int req_vco = dev_priv->cdclk.actual.vco;
>
> - skl_set_cdclk(dev_priv, req_cdclk, req_vco);
> + skl_set_cdclk(dev_priv, &dev_priv->cdclk.actual);
> }
>
> static int bxt_modeset_calc_cdclk(struct drm_atomic_state *state)
> @@ -1550,10 +1571,8 @@ static int bxt_modeset_calc_cdclk(struct drm_atomic_state *state)
> static void bxt_modeset_commit_cdclk(struct drm_atomic_state *old_state)
> {
> struct drm_i915_private *dev_priv = to_i915(old_state->dev);
> - unsigned int req_cdclk = dev_priv->cdclk.actual.cdclk;
> - unsigned int req_vco = dev_priv->cdclk.actual.vco;
>
> - bxt_set_cdclk(dev_priv, req_cdclk, req_vco);
> + bxt_set_cdclk(dev_priv, &dev_priv->cdclk.actual);
> }
>
> static int intel_compute_max_dotclk(struct drm_i915_private *dev_priv)
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
next prev parent reply other threads:[~2016-12-23 13:43 UTC|newest]
Thread overview: 39+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-12-19 17:28 [PATCH v2 00/14] drm/i915: Introduce intel_cdclk_state (v2) ville.syrjala
2016-12-19 17:28 ` [PATCH 01/14] drm/i915: Store the pipe pixel rate in the crtc state ville.syrjala
2016-12-20 13:10 ` Ander Conselvan De Oliveira
2016-12-20 13:29 ` Ville Syrjälä
2017-01-12 20:37 ` Rodrigo Vivi
2017-01-13 9:50 ` Ville Syrjälä
2016-12-19 17:28 ` [PATCH 02/14] drm/i915: Nuke intel_mode_max_pixclk() ville.syrjala
2016-12-20 13:22 ` Ander Conselvan De Oliveira
2016-12-19 17:28 ` [PATCH 03/14] drm/i915: s/get_display_clock_speed/get_cdclk/ ville.syrjala
2016-12-20 13:27 ` Ander Conselvan De Oliveira
2016-12-19 17:28 ` [PATCH 04/14] drm/i915: Clean up the .get_cdclk() assignment if ladder ville.syrjala
2016-12-20 13:42 ` Ander Conselvan De Oliveira
2016-12-19 17:28 ` [PATCH 05/14] drm/i915: Move most cdclk/rawclk related code to intel_cdclk.c ville.syrjala
2016-12-22 13:10 ` Ander Conselvan De Oliveira
2016-12-22 13:16 ` Joonas Lahtinen
2016-12-19 17:28 ` [PATCH 06/14] drm/i915: Pass computed vco to bxt_set_cdclk() ville.syrjala
2016-12-22 13:22 ` Ander Conselvan De Oliveira
2016-12-19 17:28 ` [PATCH v2 07/14] drm/i915: Start moving the cdclk stuff into a distinct state structure ville.syrjala
2016-12-22 14:14 ` Ander Conselvan De Oliveira
2016-12-22 14:33 ` Ville Syrjälä
2016-12-23 9:09 ` Ander Conselvan De Oliveira
2016-12-23 12:27 ` Ville Syrjälä
2016-12-23 13:07 ` Ander Conselvan De Oliveira
2016-12-19 17:28 ` [PATCH v2 08/14] drm/i915: Track full cdclk state for the logical and actual cdclk frequencies ville.syrjala
2016-12-23 11:53 ` Ander Conselvan De Oliveira
2016-12-19 17:28 ` [PATCH v2 09/14] drm/i915: Pass dev_priv to remainder of the cdclk functions ville.syrjala
2016-12-23 12:01 ` Ander Conselvan De Oliveira
2016-12-19 17:28 ` [PATCH v2 10/14] drm/i915: Pass the cdclk state to the set_cdclk() functions ville.syrjala
2016-12-23 13:43 ` Ander Conselvan De Oliveira [this message]
2016-12-19 17:28 ` [PATCH 11/14] drm/i915: Move PFI credit reprogramming into vlv/chv_set_cdclk() ville.syrjala
2016-12-23 13:49 ` Ander Conselvan De Oliveira
2016-12-23 14:07 ` Ville Syrjälä
2016-12-19 17:28 ` [PATCH 12/14] drm/i915: Nuke the VLV/CHV PFI programming power domain workaround ville.syrjala
2016-12-23 13:52 ` Ander Conselvan De Oliveira
2016-12-19 17:28 ` [PATCH v2 13/14] drm/i915: Replace the .modeset_commit_cdclk() hook with a more direct .set_cdclk() hook ville.syrjala
2016-12-23 14:03 ` Ander Conselvan De Oliveira
2016-12-19 17:28 ` [PATCH 14/14] drm/i915: Move ilk_pipe_pixel_rate() to intel_display.c ville.syrjala
2016-12-23 14:06 ` Ander Conselvan De Oliveira
2016-12-19 18:15 ` ✓ Fi.CI.BAT: success for drm/i915: Introduce intel_cdclk_state (rev2) Patchwork
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=1482500602.2633.56.camel@gmail.com \
--to=conselvan2@gmail.com \
--cc=intel-gfx@lists.freedesktop.org \
--cc=rodrigo.vivi@intel.com \
--cc=ville.syrjala@linux.intel.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).