[PATCH 0/3] Geminilake pipe CSC

[PATCH 0/3] Geminilake pipe CSC

[Ander Conselvan de Oliveira]

Ander Conselvan de Oliveira (3):
  drm/i915/glk: Load the degamma LUT even in legacy gamma mode
  drm/i915/glk: Enable pipe CSC
  drm/i915: Merge BDW pipe gamma and degamma table code

 drivers/gpu/drm/i915/intel_color.c   | 77 ++++++++++++++----------------------
 drivers/gpu/drm/i915/intel_display.c |  1 +
 drivers/gpu/drm/i915/intel_sprite.c  |  1 +
 3 files changed, 31 insertions(+), 48 deletions(-)

-- 
2.9.3

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[PATCH 1/3] drm/i915/glk: Load the degamma LUT even in legacy gamma mode

[Ander Conselvan de Oliveira]

In Geminilake, the degamma table is enabled or disabled by the pipe CSC
enable bit, so its active even when running in the legacy gamma mode.
So always set sane values for that table, since the default value is all
zeroes.

This fixes blank screens after a suspend/resume cycle while legacy gamma
is in use.

Signed-off-by: Ander Conselvan de Oliveira <ander.conselvan.de.oliveira@intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/intel_color.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/intel_color.c b/drivers/gpu/drm/i915/intel_color.c
index 0627eee..b9e5266d 100644
--- a/drivers/gpu/drm/i915/intel_color.c
+++ b/drivers/gpu/drm/i915/intel_color.c
@@ -483,12 +483,13 @@ static void glk_load_luts(struct drm_crtc_state *state)
 	struct intel_crtc_state *intel_state = to_intel_crtc_state(state);
 	enum pipe pipe = to_intel_crtc(crtc)->pipe;
 
+	glk_load_degamma_lut(state);
+
 	if (crtc_state_is_legacy(state)) {
 		haswell_load_luts(state);
 		return;
 	}
 
-	glk_load_degamma_lut(state);
 	bdw_load_gamma_lut(state, 0);
 
 	intel_state->gamma_mode = GAMMA_MODE_MODE_10BIT;
-- 
2.9.3

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[PATCH 2/3] drm/i915/glk: Enable pipe CSC

[Ander Conselvan de Oliveira]

Now that the pre-csc degamma table is set up correctly in Geminilake,
pipe CSC can be enabled without causing a black screen.

v2: Rebase.
Signed-off-by: Ander Conselvan de Oliveira <ander.conselvan.de.oliveira@intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/intel_display.c | 1 +
 drivers/gpu/drm/i915/intel_sprite.c  | 1 +
 2 files changed, 2 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index b05d9c8..730aee7 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -3327,6 +3327,7 @@ static void skylake_update_primary_plane(struct drm_plane *plane,
 	if (IS_GEMINILAKE(dev_priv)) {
 		I915_WRITE(PLANE_COLOR_CTL(pipe, plane_id),
 			   PLANE_COLOR_PIPE_GAMMA_ENABLE |
+			   PLANE_COLOR_PIPE_CSC_ENABLE |
 			   PLANE_COLOR_PLANE_GAMMA_DISABLE);
 	} else {
 		plane_ctl |=
diff --git a/drivers/gpu/drm/i915/intel_sprite.c b/drivers/gpu/drm/i915/intel_sprite.c
index b16a295..27e0752 100644
--- a/drivers/gpu/drm/i915/intel_sprite.c
+++ b/drivers/gpu/drm/i915/intel_sprite.c
@@ -224,6 +224,7 @@ skl_update_plane(struct drm_plane *drm_plane,
 	if (IS_GEMINILAKE(dev_priv)) {
 		I915_WRITE(PLANE_COLOR_CTL(pipe, plane_id),
 			   PLANE_COLOR_PIPE_GAMMA_ENABLE |
+			   PLANE_COLOR_PIPE_CSC_ENABLE |
 			   PLANE_COLOR_PLANE_GAMMA_DISABLE);
 	} else {
 		plane_ctl |=
-- 
2.9.3

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[PATCH 3/3] drm/i915: Merge BDW pipe gamma and degamma table code

[Ander Conselvan de Oliveira]

The only difference between the code loading the pipe gamma and degamma
tables in BDW is that the gamma code also writes the registers that hold
the maximum values. So we can use the gamma code for the degamma table,
at the expense of writing the maximum value register twice, with
potenttially wrong values in the first time.

v2: Pass PAL_PREC_SPLIT_MODE from the caller. (Ville)
v3: Pass intel_crtc to bdw_load_lut(). (Ville)
    Remove cast in function parameter list. (Ville)
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Ander Conselvan de Oliveira <ander.conselvan.de.oliveira@intel.com>
---
 drivers/gpu/drm/i915/intel_color.c | 74 ++++++++++++++------------------------
 1 file changed, 27 insertions(+), 47 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_color.c b/drivers/gpu/drm/i915/intel_color.c
index b9e5266d..9cb1c14 100644
--- a/drivers/gpu/drm/i915/intel_color.c
+++ b/drivers/gpu/drm/i915/intel_color.c
@@ -340,54 +340,29 @@ static void haswell_load_luts(struct drm_crtc_state *crtc_state)
 		hsw_enable_ips(intel_crtc);
 }
 
-static void bdw_load_degamma_lut(struct drm_crtc_state *state)
+static struct drm_color_lut *
+blob_data_as_lut(struct drm_property_blob *blob)
 {
-	struct drm_i915_private *dev_priv = to_i915(state->crtc->dev);
-	enum pipe pipe = to_intel_crtc(state->crtc)->pipe;
-	uint32_t i, lut_size = INTEL_INFO(dev_priv)->color.degamma_lut_size;
-
-	I915_WRITE(PREC_PAL_INDEX(pipe),
-		   PAL_PREC_SPLIT_MODE | PAL_PREC_AUTO_INCREMENT);
-
-	if (state->degamma_lut) {
-		struct drm_color_lut *lut =
-			(struct drm_color_lut *) state->degamma_lut->data;
-
-		for (i = 0; i < lut_size; i++) {
-			uint32_t word =
-			drm_color_lut_extract(lut[i].red, 10) << 20 |
-			drm_color_lut_extract(lut[i].green, 10) << 10 |
-			drm_color_lut_extract(lut[i].blue, 10);
-
-			I915_WRITE(PREC_PAL_DATA(pipe), word);
-		}
-	} else {
-		for (i = 0; i < lut_size; i++) {
-			uint32_t v = (i * ((1 << 10) - 1)) / (lut_size - 1);
+	if (!blob)
+		return NULL;
 
-			I915_WRITE(PREC_PAL_DATA(pipe),
-				   (v << 20) | (v << 10) | v);
-		}
-	}
+	return (struct drm_color_lut *) blob->data;
 }
 
-static void bdw_load_gamma_lut(struct drm_crtc_state *state, u32 offset)
+static void bdw_load_lut(struct intel_crtc *crtc, u32 offset,
+			 struct drm_color_lut *lut, u32 lut_size,
+			 u32 flags)
 {
-	struct drm_i915_private *dev_priv = to_i915(state->crtc->dev);
-	enum pipe pipe = to_intel_crtc(state->crtc)->pipe;
-	uint32_t i, lut_size = INTEL_INFO(dev_priv)->color.gamma_lut_size;
+	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
+	enum pipe pipe = crtc->pipe;
+	uint32_t i;
 
 	WARN_ON(offset & ~PAL_PREC_INDEX_VALUE_MASK);
 
 	I915_WRITE(PREC_PAL_INDEX(pipe),
-		   (offset ? PAL_PREC_SPLIT_MODE : 0) |
-		   PAL_PREC_AUTO_INCREMENT |
-		   offset);
-
-	if (state->gamma_lut) {
-		struct drm_color_lut *lut =
-			(struct drm_color_lut *) state->gamma_lut->data;
+		   flags | PAL_PREC_AUTO_INCREMENT | offset);
 
+	if (lut) {
 		for (i = 0; i < lut_size; i++) {
 			uint32_t word =
 			(drm_color_lut_extract(lut[i].red, 10) << 20) |
@@ -423,16 +398,21 @@ static void broadwell_load_luts(struct drm_crtc_state *state)
 {
 	struct drm_i915_private *dev_priv = to_i915(state->crtc->dev);
 	struct intel_crtc_state *intel_state = to_intel_crtc_state(state);
-	enum pipe pipe = to_intel_crtc(state->crtc)->pipe;
+	struct intel_crtc *crtc = to_intel_crtc(state->crtc);
+	enum pipe pipe = crtc->pipe;
 
 	if (crtc_state_is_legacy(state)) {
 		haswell_load_luts(state);
 		return;
 	}
 
-	bdw_load_degamma_lut(state);
-	bdw_load_gamma_lut(state,
-			   INTEL_INFO(dev_priv)->color.degamma_lut_size);
+	bdw_load_lut(crtc, 0, blob_data_as_lut(state->degamma_lut),
+		     INTEL_INFO(dev_priv)->color.degamma_lut_size,
+		     PAL_PREC_SPLIT_MODE);
+	bdw_load_lut(crtc, INTEL_INFO(dev_priv)->color.degamma_lut_size,
+		     blob_data_as_lut(state->gamma_lut),
+		     INTEL_INFO(dev_priv)->color.gamma_lut_size,
+		     PAL_PREC_SPLIT_MODE);
 
 	intel_state->gamma_mode = GAMMA_MODE_MODE_SPLIT;
 	I915_WRITE(GAMMA_MODE(pipe), GAMMA_MODE_MODE_SPLIT);
@@ -477,11 +457,10 @@ static void glk_load_degamma_lut(struct drm_crtc_state *state)
 
 static void glk_load_luts(struct drm_crtc_state *state)
 {
-	struct drm_crtc *crtc = state->crtc;
-	struct drm_device *dev = crtc->dev;
-	struct drm_i915_private *dev_priv = to_i915(dev);
+	struct drm_i915_private *dev_priv = to_i915(state->crtc->dev);
 	struct intel_crtc_state *intel_state = to_intel_crtc_state(state);
-	enum pipe pipe = to_intel_crtc(crtc)->pipe;
+	struct intel_crtc *crtc = to_intel_crtc(state->crtc);
+	enum pipe pipe = crtc->pipe;
 
 	glk_load_degamma_lut(state);
 
@@ -490,7 +469,8 @@ static void glk_load_luts(struct drm_crtc_state *state)
 		return;
 	}
 
-	bdw_load_gamma_lut(state, 0);
+	bdw_load_lut(crtc, 0, blob_data_as_lut(state->gamma_lut),
+		     INTEL_INFO(dev_priv)->color.gamma_lut_size, 0);
 
 	intel_state->gamma_mode = GAMMA_MODE_MODE_10BIT;
 	I915_WRITE(GAMMA_MODE(pipe), GAMMA_MODE_MODE_10BIT);
-- 
2.9.3

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✓ Fi.CI.BAT: success for Geminilake pipe CSC (rev4)

[Patchwork]

== Series Details ==

Series: Geminilake pipe CSC (rev4)
URL   : https://patchwork.freedesktop.org/series/18596/
State : success

== Summary ==

Series 18596v4 Geminilake pipe CSC
https://patchwork.freedesktop.org/api/1.0/series/18596/revisions/4/mbox/

fi-bdw-5557u     total:252  pass:241  dwarn:0   dfail:0   fail:0   skip:11 
fi-bsw-n3050     total:252  pass:213  dwarn:0   dfail:0   fail:0   skip:39 
fi-bxt-j4205     total:252  pass:233  dwarn:0   dfail:0   fail:0   skip:19 
fi-bxt-t5700     total:83   pass:70   dwarn:0   dfail:0   fail:0   skip:12 
fi-byt-j1900     total:252  pass:225  dwarn:0   dfail:0   fail:0   skip:27 
fi-byt-n2820     total:252  pass:221  dwarn:0   dfail:0   fail:0   skip:31 
fi-hsw-4770      total:252  pass:236  dwarn:0   dfail:0   fail:0   skip:16 
fi-hsw-4770r     total:252  pass:236  dwarn:0   dfail:0   fail:0   skip:16 
fi-ilk-650       total:252  pass:202  dwarn:0   dfail:0   fail:0   skip:50 
fi-ivb-3520m     total:252  pass:234  dwarn:0   dfail:0   fail:0   skip:18 
fi-ivb-3770      total:252  pass:234  dwarn:0   dfail:0   fail:0   skip:18 
fi-kbl-7500u     total:252  pass:234  dwarn:0   dfail:0   fail:0   skip:18 
fi-skl-6260u     total:252  pass:242  dwarn:0   dfail:0   fail:0   skip:10 
fi-skl-6700hq    total:252  pass:235  dwarn:0   dfail:0   fail:0   skip:17 
fi-skl-6700k     total:252  pass:230  dwarn:4   dfail:0   fail:0   skip:18 
fi-skl-6770hq    total:252  pass:242  dwarn:0   dfail:0   fail:0   skip:10 
fi-snb-2520m     total:252  pass:224  dwarn:0   dfail:0   fail:0   skip:28 
fi-snb-2600      total:252  pass:223  dwarn:0   dfail:0   fail:0   skip:29 

2b7ce9512d9770350bc2a59652cc7bf469bc544a drm-tip: 2017y-02m-17d-12h-20m-31s UTC integration manifest
b780a42 drm/i915: Merge BDW pipe gamma and degamma table code
03a10bc drm/i915/glk: Enable pipe CSC
0a5d181 drm/i915/glk: Load the degamma LUT even in legacy gamma mode

== Logs ==

For more details see: https://intel-gfx-ci.01.org/CI/Patchwork_3877/
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Re: [PATCH 2/3] drm/i915/glk: Enable pipe CSC

[Ander Conselvan De Oliveira]

On Fri, 2017-02-17 at 14:06 +0200, Ander Conselvan de Oliveira wrote:
> Now that the pre-csc degamma table is set up correctly in Geminilake,
> pipe CSC can be enabled without causing a black screen.
> 
> v2: Rebase.
> Signed-off-by: Ander Conselvan de Oliveira <ander.conselvan.de.oliveira@intel.com>
> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

Pushed up to here. Thanks for the reviews.

Ander

> ---
>  drivers/gpu/drm/i915/intel_display.c | 1 +
>  drivers/gpu/drm/i915/intel_sprite.c  | 1 +
>  2 files changed, 2 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index b05d9c8..730aee7 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -3327,6 +3327,7 @@ static void skylake_update_primary_plane(struct drm_plane *plane,
>  	if (IS_GEMINILAKE(dev_priv)) {
>  		I915_WRITE(PLANE_COLOR_CTL(pipe, plane_id),
>  			   PLANE_COLOR_PIPE_GAMMA_ENABLE |
> +			   PLANE_COLOR_PIPE_CSC_ENABLE |
>  			   PLANE_COLOR_PLANE_GAMMA_DISABLE);
>  	} else {
>  		plane_ctl |=
> diff --git a/drivers/gpu/drm/i915/intel_sprite.c b/drivers/gpu/drm/i915/intel_sprite.c
> index b16a295..27e0752 100644
> --- a/drivers/gpu/drm/i915/intel_sprite.c
> +++ b/drivers/gpu/drm/i915/intel_sprite.c
> @@ -224,6 +224,7 @@ skl_update_plane(struct drm_plane *drm_plane,
>  	if (IS_GEMINILAKE(dev_priv)) {
>  		I915_WRITE(PLANE_COLOR_CTL(pipe, plane_id),
>  			   PLANE_COLOR_PIPE_GAMMA_ENABLE |
> +			   PLANE_COLOR_PIPE_CSC_ENABLE |
>  			   PLANE_COLOR_PLANE_GAMMA_DISABLE);
>  	} else {
>  		plane_ctl |=
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