[PATCH v2 0/5] drm/i915: Fix clearing of BIOS power well requests

[PATCH v2 0/5] drm/i915: Fix clearing of BIOS power well requests

[Imre Deak]

This is v2 of [1], addressing Ander's comments.

[1]
https://lists.freedesktop.org/archives/intel-gfx/2017-February/120006.html

Cc: Ander Conselvan de Oliveira <conselvan2@gmail.com>
Cc: David Weinehall <david.weinehall@linux.intel.com>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>

Imre Deak (5):
  drm/i915: Remove redundant toggling from the power well sync_hw hooks
  drm/i915: Call the sync_hw hook for power wells without a domain
  drm/i915/gen9: Fix clearing of the BIOS power well request register
  drm/i915: Preserve the state of power wells not explicitly enabled
  drm/i915: Add power well SW/HW state verification

 drivers/gpu/drm/i915/i915_drv.h         |  20 ++++
 drivers/gpu/drm/i915/intel_display.c    |   2 +
 drivers/gpu/drm/i915/intel_drv.h        |   1 +
 drivers/gpu/drm/i915/intel_runtime_pm.c | 188 +++++++++++++++++++-------------
 4 files changed, 138 insertions(+), 73 deletions(-)

-- 
2.5.0
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[PATCH v2 1/5] drm/i915: Remove redundant toggling from the power well sync_hw hooks

[Imre Deak]

Doing an explicit enable/disable in the power well sync_hw hook based on
the power well's reference count is redundant, since by the time these
hooks are called all the power wells are enabled and have a reference.
So remove the redundant toggling.

This is needed by a follow-up patchset that adds power wells which we
can't enable/disable during power domain initialization and so want to
preserve their state until modeset init time.

Cc: Ander Conselvan de Oliveira <conselvan2@gmail.com>
Cc: David Weinehall <david.weinehall@linux.intel.com>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Imre Deak <imre.deak@intel.com>
Reviewed-by: Ander Conselvan de Oliveira <conselvan2@gmail.com>
---
 drivers/gpu/drm/i915/intel_runtime_pm.c | 52 +++++++--------------------------
 1 file changed, 10 insertions(+), 42 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c b/drivers/gpu/drm/i915/intel_runtime_pm.c
index 8795679..0f64bc1 100644
--- a/drivers/gpu/drm/i915/intel_runtime_pm.c
+++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
@@ -847,8 +847,6 @@ static void skl_set_power_well(struct drm_i915_private *dev_priv,
 static void hsw_power_well_sync_hw(struct drm_i915_private *dev_priv,
 				   struct i915_power_well *power_well)
 {
-	hsw_set_power_well(dev_priv, power_well, power_well->count > 0);
-
 	/*
 	 * We're taking over the BIOS, so clear any requests made by it since
 	 * the driver is in charge now.
@@ -881,8 +879,6 @@ static bool skl_power_well_enabled(struct drm_i915_private *dev_priv,
 static void skl_power_well_sync_hw(struct drm_i915_private *dev_priv,
 				struct i915_power_well *power_well)
 {
-	skl_set_power_well(dev_priv, power_well, power_well->count > 0);
-
 	/* Clear any request made by BIOS as driver is taking over */
 	I915_WRITE(HSW_PWR_WELL_BIOS, 0);
 }
@@ -917,16 +913,6 @@ static bool bxt_dpio_cmn_power_well_enabled(struct drm_i915_private *dev_priv,
 	return bxt_ddi_phy_is_enabled(dev_priv, power_well->data);
 }
 
-static void bxt_dpio_cmn_power_well_sync_hw(struct drm_i915_private *dev_priv,
-					    struct i915_power_well *power_well)
-{
-	if (power_well->count > 0)
-		bxt_dpio_cmn_power_well_enable(dev_priv, power_well);
-	else
-		bxt_dpio_cmn_power_well_disable(dev_priv, power_well);
-}
-
-
 static void bxt_verify_ddi_phy_power_wells(struct drm_i915_private *dev_priv)
 {
 	struct i915_power_well *power_well;
@@ -989,13 +975,9 @@ static void gen9_dc_off_power_well_disable(struct drm_i915_private *dev_priv,
 		gen9_enable_dc5(dev_priv);
 }
 
-static void gen9_dc_off_power_well_sync_hw(struct drm_i915_private *dev_priv,
-					   struct i915_power_well *power_well)
+static void i9xx_power_well_sync_hw_noop(struct drm_i915_private *dev_priv,
+					 struct i915_power_well *power_well)
 {
-	if (power_well->count > 0)
-		gen9_dc_off_power_well_enable(dev_priv, power_well);
-	else
-		gen9_dc_off_power_well_disable(dev_priv, power_well);
 }
 
 static void i9xx_always_on_power_well_noop(struct drm_i915_private *dev_priv,
@@ -1045,12 +1027,6 @@ static void vlv_set_power_well(struct drm_i915_private *dev_priv,
 	mutex_unlock(&dev_priv->rps.hw_lock);
 }
 
-static void vlv_power_well_sync_hw(struct drm_i915_private *dev_priv,
-				   struct i915_power_well *power_well)
-{
-	vlv_set_power_well(dev_priv, power_well, power_well->count > 0);
-}
-
 static void vlv_power_well_enable(struct drm_i915_private *dev_priv,
 				  struct i915_power_well *power_well)
 {
@@ -1661,14 +1637,6 @@ static void chv_set_pipe_power_well(struct drm_i915_private *dev_priv,
 	mutex_unlock(&dev_priv->rps.hw_lock);
 }
 
-static void chv_pipe_power_well_sync_hw(struct drm_i915_private *dev_priv,
-					struct i915_power_well *power_well)
-{
-	WARN_ON_ONCE(power_well->id != PIPE_A);
-
-	chv_set_pipe_power_well(dev_priv, power_well, power_well->count > 0);
-}
-
 static void chv_pipe_power_well_enable(struct drm_i915_private *dev_priv,
 				       struct i915_power_well *power_well)
 {
@@ -1914,21 +1882,21 @@ void intel_display_power_put(struct drm_i915_private *dev_priv,
 	BIT_ULL(POWER_DOMAIN_INIT))
 
 static const struct i915_power_well_ops i9xx_always_on_power_well_ops = {
-	.sync_hw = i9xx_always_on_power_well_noop,
+	.sync_hw = i9xx_power_well_sync_hw_noop,
 	.enable = i9xx_always_on_power_well_noop,
 	.disable = i9xx_always_on_power_well_noop,
 	.is_enabled = i9xx_always_on_power_well_enabled,
 };
 
 static const struct i915_power_well_ops chv_pipe_power_well_ops = {
-	.sync_hw = chv_pipe_power_well_sync_hw,
+	.sync_hw = i9xx_power_well_sync_hw_noop,
 	.enable = chv_pipe_power_well_enable,
 	.disable = chv_pipe_power_well_disable,
 	.is_enabled = chv_pipe_power_well_enabled,
 };
 
 static const struct i915_power_well_ops chv_dpio_cmn_power_well_ops = {
-	.sync_hw = vlv_power_well_sync_hw,
+	.sync_hw = i9xx_power_well_sync_hw_noop,
 	.enable = chv_dpio_cmn_power_well_enable,
 	.disable = chv_dpio_cmn_power_well_disable,
 	.is_enabled = vlv_power_well_enabled,
@@ -1958,14 +1926,14 @@ static const struct i915_power_well_ops skl_power_well_ops = {
 };
 
 static const struct i915_power_well_ops gen9_dc_off_power_well_ops = {
-	.sync_hw = gen9_dc_off_power_well_sync_hw,
+	.sync_hw = i9xx_power_well_sync_hw_noop,
 	.enable = gen9_dc_off_power_well_enable,
 	.disable = gen9_dc_off_power_well_disable,
 	.is_enabled = gen9_dc_off_power_well_enabled,
 };
 
 static const struct i915_power_well_ops bxt_dpio_cmn_power_well_ops = {
-	.sync_hw = bxt_dpio_cmn_power_well_sync_hw,
+	.sync_hw = i9xx_power_well_sync_hw_noop,
 	.enable = bxt_dpio_cmn_power_well_enable,
 	.disable = bxt_dpio_cmn_power_well_disable,
 	.is_enabled = bxt_dpio_cmn_power_well_enabled,
@@ -2000,21 +1968,21 @@ static struct i915_power_well bdw_power_wells[] = {
 };
 
 static const struct i915_power_well_ops vlv_display_power_well_ops = {
-	.sync_hw = vlv_power_well_sync_hw,
+	.sync_hw = i9xx_power_well_sync_hw_noop,
 	.enable = vlv_display_power_well_enable,
 	.disable = vlv_display_power_well_disable,
 	.is_enabled = vlv_power_well_enabled,
 };
 
 static const struct i915_power_well_ops vlv_dpio_cmn_power_well_ops = {
-	.sync_hw = vlv_power_well_sync_hw,
+	.sync_hw = i9xx_power_well_sync_hw_noop,
 	.enable = vlv_dpio_cmn_power_well_enable,
 	.disable = vlv_dpio_cmn_power_well_disable,
 	.is_enabled = vlv_power_well_enabled,
 };
 
 static const struct i915_power_well_ops vlv_dpio_power_well_ops = {
-	.sync_hw = vlv_power_well_sync_hw,
+	.sync_hw = i9xx_power_well_sync_hw_noop,
 	.enable = vlv_power_well_enable,
 	.disable = vlv_power_well_disable,
 	.is_enabled = vlv_power_well_enabled,
-- 
2.5.0

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[PATCH v2 2/5] drm/i915: Call the sync_hw hook for power wells without a domain

[Imre Deak]

So far the sync_hw hook wasn't called for power wells not belonging to
any power domain, that is the GEN9 PW1 and MISC_IO power wells. This
wasn't a problem so far since the goal of the sync_hw hook - to clear
the corresponding BIOS request bit - was guaranteed by clearing the
whole BIOS request register elsewhere. This will change with the next
patch, so fix up the inconsistency.

While at it clean up the power well iterator helpers and move them to
the rest of iterators.

v2:
- Clean up the power well iterator helpers. (Ander)
- Move the helpers to i915_drv.h.

Cc: Ander Conselvan de Oliveira <conselvan2@gmail.com>
Cc: David Weinehall <david.weinehall@linux.intel.com>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Imre Deak <imre.deak@intel.com>
Reviewed-by: Ander Conselvan de Oliveira <conselvan2@gmail.com> (v1)
---
 drivers/gpu/drm/i915/i915_drv.h         | 20 ++++++++++++++++++++
 drivers/gpu/drm/i915/intel_runtime_pm.c | 28 ++++------------------------
 2 files changed, 24 insertions(+), 24 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index b5f150b..d138508 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -500,6 +500,26 @@ struct i915_hotplug {
 	for ((domain) = 0; (domain) < POWER_DOMAIN_NUM; (domain)++)	\
 		for_each_if (BIT_ULL(domain) & (mask))
 
+#define for_each_power_well(__dev_priv, __power_well)				\
+	for ((__power_well) = (__dev_priv)->power_domains.power_wells;	\
+	     (__power_well) - (__dev_priv)->power_domains.power_wells <	\
+		(__dev_priv)->power_domains.power_well_count;		\
+	     (__power_well)++)
+
+#define for_each_power_well_rev(__dev_priv, __power_well)			\
+	for ((__power_well) = (__dev_priv)->power_domains.power_wells +		\
+			      (__dev_priv)->power_domains.power_well_count - 1;	\
+	     (__power_well) - (__dev_priv)->power_domains.power_wells >= 0;	\
+	     (__power_well)--)
+
+#define for_each_power_domain_well(__dev_priv, __power_well, __domain_mask)	\
+	for_each_power_well(__dev_priv, __power_well)				\
+		for_each_if ((__power_well)->domains & (__domain_mask))
+
+#define for_each_power_domain_well_rev(__dev_priv, __power_well, __domain_mask) \
+	for_each_power_well_rev(__dev_priv, __power_well)		        \
+		for_each_if ((__power_well)->domains & (__domain_mask))
+
 struct drm_i915_private;
 struct i915_mm_struct;
 struct i915_mmu_object;
diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c b/drivers/gpu/drm/i915/intel_runtime_pm.c
index 0f64bc1..9bbbdbc 100644
--- a/drivers/gpu/drm/i915/intel_runtime_pm.c
+++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
@@ -49,19 +49,6 @@
  * present for a given platform.
  */
 
-#define for_each_power_well(i, power_well, domain_mask, power_domains)	\
-	for (i = 0;							\
-	     i < (power_domains)->power_well_count &&			\
-		 ((power_well) = &(power_domains)->power_wells[i]);	\
-	     i++)							\
-		for_each_if ((power_well)->domains & (domain_mask))
-
-#define for_each_power_well_rev(i, power_well, domain_mask, power_domains) \
-	for (i = (power_domains)->power_well_count - 1;			 \
-	     i >= 0 && ((power_well) = &(power_domains)->power_wells[i]);\
-	     i--)							 \
-		for_each_if ((power_well)->domains & (domain_mask))
-
 bool intel_display_power_well_is_enabled(struct drm_i915_private *dev_priv,
 				    int power_well_id);
 
@@ -198,19 +185,15 @@ static bool hsw_power_well_enabled(struct drm_i915_private *dev_priv,
 bool __intel_display_power_is_enabled(struct drm_i915_private *dev_priv,
 				      enum intel_display_power_domain domain)
 {
-	struct i915_power_domains *power_domains;
 	struct i915_power_well *power_well;
 	bool is_enabled;
-	int i;
 
 	if (dev_priv->pm.suspended)
 		return false;
 
-	power_domains = &dev_priv->power_domains;
-
 	is_enabled = true;
 
-	for_each_power_well_rev(i, power_well, BIT_ULL(domain), power_domains) {
+	for_each_power_domain_well_rev(dev_priv, power_well, BIT_ULL(domain)) {
 		if (power_well->always_on)
 			continue;
 
@@ -1663,9 +1646,8 @@ __intel_display_power_get_domain(struct drm_i915_private *dev_priv,
 {
 	struct i915_power_domains *power_domains = &dev_priv->power_domains;
 	struct i915_power_well *power_well;
-	int i;
 
-	for_each_power_well(i, power_well, BIT_ULL(domain), power_domains)
+	for_each_power_domain_well(dev_priv, power_well, BIT_ULL(domain))
 		intel_power_well_get(dev_priv, power_well);
 
 	power_domains->domain_use_count[domain]++;
@@ -1749,7 +1731,6 @@ void intel_display_power_put(struct drm_i915_private *dev_priv,
 {
 	struct i915_power_domains *power_domains;
 	struct i915_power_well *power_well;
-	int i;
 
 	power_domains = &dev_priv->power_domains;
 
@@ -1760,7 +1741,7 @@ void intel_display_power_put(struct drm_i915_private *dev_priv,
 	     intel_display_power_domain_str(domain));
 	power_domains->domain_use_count[domain]--;
 
-	for_each_power_well_rev(i, power_well, BIT_ULL(domain), power_domains)
+	for_each_power_domain_well_rev(dev_priv, power_well, BIT_ULL(domain))
 		intel_power_well_put(dev_priv, power_well);
 
 	mutex_unlock(&power_domains->lock);
@@ -2424,10 +2405,9 @@ static void intel_power_domains_sync_hw(struct drm_i915_private *dev_priv)
 {
 	struct i915_power_domains *power_domains = &dev_priv->power_domains;
 	struct i915_power_well *power_well;
-	int i;
 
 	mutex_lock(&power_domains->lock);
-	for_each_power_well(i, power_well, POWER_DOMAIN_MASK, power_domains) {
+	for_each_power_well(dev_priv, power_well) {
 		power_well->ops->sync_hw(dev_priv, power_well);
 		power_well->hw_enabled = power_well->ops->is_enabled(dev_priv,
 								     power_well);
-- 
2.5.0

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Re: [PATCH v2 2/5] drm/i915: Call the sync_hw hook for power wells without a domain

[Ander Conselvan De Oliveira]

On Fri, 2017-02-17 at 17:39 +0200, Imre Deak wrote:
> So far the sync_hw hook wasn't called for power wells not belonging to
> any power domain, that is the GEN9 PW1 and MISC_IO power wells. This
> wasn't a problem so far since the goal of the sync_hw hook - to clear
> the corresponding BIOS request bit - was guaranteed by clearing the
> whole BIOS request register elsewhere. This will change with the next
> patch, so fix up the inconsistency.
> 
> While at it clean up the power well iterator helpers and move them to
> the rest of iterators.
> 
> v2:
> - Clean up the power well iterator helpers. (Ander)
> - Move the helpers to i915_drv.h.
> 
> Cc: Ander Conselvan de Oliveira <conselvan2@gmail.com>
> Cc: David Weinehall <david.weinehall@linux.intel.com>
> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> Signed-off-by: Imre Deak <imre.deak@intel.com>
> Reviewed-by: Ander Conselvan de Oliveira <conselvan2@gmail.com> (v1)

s/(v1)//

Ander

> ---
>  drivers/gpu/drm/i915/i915_drv.h         | 20 ++++++++++++++++++++
>  drivers/gpu/drm/i915/intel_runtime_pm.c | 28 ++++------------------------
>  2 files changed, 24 insertions(+), 24 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index b5f150b..d138508 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -500,6 +500,26 @@ struct i915_hotplug {
>  	for ((domain) = 0; (domain) < POWER_DOMAIN_NUM; (domain)++)	\
>  		for_each_if (BIT_ULL(domain) & (mask))
>  
> +#define for_each_power_well(__dev_priv, __power_well)				\
> +	for ((__power_well) = (__dev_priv)->power_domains.power_wells;	\
> +	     (__power_well) - (__dev_priv)->power_domains.power_wells <	\
> +		(__dev_priv)->power_domains.power_well_count;		\
> +	     (__power_well)++)
> +
> +#define for_each_power_well_rev(__dev_priv, __power_well)			\
> +	for ((__power_well) = (__dev_priv)->power_domains.power_wells +		\
> +			      (__dev_priv)->power_domains.power_well_count - 1;	\
> +	     (__power_well) - (__dev_priv)->power_domains.power_wells >= 0;	\
> +	     (__power_well)--)
> +
> +#define for_each_power_domain_well(__dev_priv, __power_well, __domain_mask)	\
> +	for_each_power_well(__dev_priv, __power_well)				\
> +		for_each_if ((__power_well)->domains & (__domain_mask))
> +
> +#define for_each_power_domain_well_rev(__dev_priv, __power_well, __domain_mask) \
> +	for_each_power_well_rev(__dev_priv, __power_well)		        \
> +		for_each_if ((__power_well)->domains & (__domain_mask))
> +
>  struct drm_i915_private;
>  struct i915_mm_struct;
>  struct i915_mmu_object;
> diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c b/drivers/gpu/drm/i915/intel_runtime_pm.c
> index 0f64bc1..9bbbdbc 100644
> --- a/drivers/gpu/drm/i915/intel_runtime_pm.c
> +++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
> @@ -49,19 +49,6 @@
>   * present for a given platform.
>   */
>  
> -#define for_each_power_well(i, power_well, domain_mask, power_domains)	\
> -	for (i = 0;							\
> -	     i < (power_domains)->power_well_count &&			\
> -		 ((power_well) = &(power_domains)->power_wells[i]);	\
> -	     i++)							\
> -		for_each_if ((power_well)->domains & (domain_mask))
> -
> -#define for_each_power_well_rev(i, power_well, domain_mask, power_domains) \
> -	for (i = (power_domains)->power_well_count - 1;			 \
> -	     i >= 0 && ((power_well) = &(power_domains)->power_wells[i]);\
> -	     i--)							 \
> -		for_each_if ((power_well)->domains & (domain_mask))
> -
>  bool intel_display_power_well_is_enabled(struct drm_i915_private *dev_priv,
>  				    int power_well_id);
>  
> @@ -198,19 +185,15 @@ static bool hsw_power_well_enabled(struct drm_i915_private *dev_priv,
>  bool __intel_display_power_is_enabled(struct drm_i915_private *dev_priv,
>  				      enum intel_display_power_domain domain)
>  {
> -	struct i915_power_domains *power_domains;
>  	struct i915_power_well *power_well;
>  	bool is_enabled;
> -	int i;
>  
>  	if (dev_priv->pm.suspended)
>  		return false;
>  
> -	power_domains = &dev_priv->power_domains;
> -
>  	is_enabled = true;
>  
> -	for_each_power_well_rev(i, power_well, BIT_ULL(domain), power_domains) {
> +	for_each_power_domain_well_rev(dev_priv, power_well, BIT_ULL(domain)) {
>  		if (power_well->always_on)
>  			continue;
>  
> @@ -1663,9 +1646,8 @@ __intel_display_power_get_domain(struct drm_i915_private *dev_priv,
>  {
>  	struct i915_power_domains *power_domains = &dev_priv->power_domains;
>  	struct i915_power_well *power_well;
> -	int i;
>  
> -	for_each_power_well(i, power_well, BIT_ULL(domain), power_domains)
> +	for_each_power_domain_well(dev_priv, power_well, BIT_ULL(domain))
>  		intel_power_well_get(dev_priv, power_well);
>  
>  	power_domains->domain_use_count[domain]++;
> @@ -1749,7 +1731,6 @@ void intel_display_power_put(struct drm_i915_private *dev_priv,
>  {
>  	struct i915_power_domains *power_domains;
>  	struct i915_power_well *power_well;
> -	int i;
>  
>  	power_domains = &dev_priv->power_domains;
>  
> @@ -1760,7 +1741,7 @@ void intel_display_power_put(struct drm_i915_private *dev_priv,
>  	     intel_display_power_domain_str(domain));
>  	power_domains->domain_use_count[domain]--;
>  
> -	for_each_power_well_rev(i, power_well, BIT_ULL(domain), power_domains)
> +	for_each_power_domain_well_rev(dev_priv, power_well, BIT_ULL(domain))
>  		intel_power_well_put(dev_priv, power_well);
>  
>  	mutex_unlock(&power_domains->lock);
> @@ -2424,10 +2405,9 @@ static void intel_power_domains_sync_hw(struct drm_i915_private *dev_priv)
>  {
>  	struct i915_power_domains *power_domains = &dev_priv->power_domains;
>  	struct i915_power_well *power_well;
> -	int i;
>  
>  	mutex_lock(&power_domains->lock);
> -	for_each_power_well(i, power_well, POWER_DOMAIN_MASK, power_domains) {
> +	for_each_power_well(dev_priv, power_well) {
>  		power_well->ops->sync_hw(dev_priv, power_well);
>  		power_well->hw_enabled = power_well->ops->is_enabled(dev_priv,
>  								     power_well);
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[PATCH v2 3/5] drm/i915/gen9: Fix clearing of the BIOS power well request register

[Imre Deak]

Atm, in the power well sync_hw hook we are clearing all BIOS request
bits, not just the one corresponding to the given power well. This could
turn off an unrelated power well inadvertently if it didn't have a
request bit set in the driver request register.

This didn't cause a problem so far, since we enabled all power wells
explicitly before clearing the BIOS request register. A follow-up
patchset will add power wells that won't get enabled this way, so fix up
the inconsistency.

Note that this patch only makes the clearing of the BIOS req register
more logical. Power wells without a reference would still get disabled
by the end of power domain initialization, that is fixed by the next
patch.

v2:
- Clarify in the commit log that this patch doesn't address the case of
  power wells without a reference. (Ander)

Cc: Ander Conselvan de Oliveira <conselvan2@gmail.com>
Cc: David Weinehall <david.weinehall@linux.intel.com>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Imre Deak <imre.deak@intel.com>
Reviewed-by: Ander Conselvan de Oliveira <conselvan2@gmail.com>
---
 drivers/gpu/drm/i915/intel_runtime_pm.c | 7 ++++++-
 1 file changed, 6 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c b/drivers/gpu/drm/i915/intel_runtime_pm.c
index 9bbbdbc..62c99a9 100644
--- a/drivers/gpu/drm/i915/intel_runtime_pm.c
+++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
@@ -862,8 +862,13 @@ static bool skl_power_well_enabled(struct drm_i915_private *dev_priv,
 static void skl_power_well_sync_hw(struct drm_i915_private *dev_priv,
 				struct i915_power_well *power_well)
 {
+	uint32_t mask = SKL_POWER_WELL_REQ(power_well->id);
+	uint32_t bios_req = I915_READ(HSW_PWR_WELL_BIOS);
+
 	/* Clear any request made by BIOS as driver is taking over */
-	I915_WRITE(HSW_PWR_WELL_BIOS, 0);
+	if (bios_req & mask) {
+		I915_WRITE(HSW_PWR_WELL_BIOS, bios_req & ~mask);
+	}
 }
 
 static void skl_power_well_enable(struct drm_i915_private *dev_priv,
-- 
2.5.0

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[PATCH v2 4/5] drm/i915: Preserve the state of power wells not explicitly enabled

[Imre Deak]

Atm, power wells that BIOS has enabled, but which we don't explicitly
enable during power domain initialization would get disabled as we clear
the BIOS request bit in the given power well sync_hw hook. To prevent
this copy over any set request bits in the BIOS request register to the
driver request register and clear the BIOS request bit only afterwards.

This doesn't make a difference now, since we enable all power wells
during power domain initialization. A follow-up patchset will add power
wells for which this isn't true, so fix up the inconsistency.

Cc: Ander Conselvan de Oliveira <conselvan2@gmail.com>
Cc: David Weinehall <david.weinehall@linux.intel.com>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Imre Deak <imre.deak@intel.com>
---
 drivers/gpu/drm/i915/intel_runtime_pm.c | 18 ++++++++++++------
 1 file changed, 12 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c b/drivers/gpu/drm/i915/intel_runtime_pm.c
index 62c99a9..44d4da3 100644
--- a/drivers/gpu/drm/i915/intel_runtime_pm.c
+++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
@@ -830,12 +830,14 @@ static void skl_set_power_well(struct drm_i915_private *dev_priv,
 static void hsw_power_well_sync_hw(struct drm_i915_private *dev_priv,
 				   struct i915_power_well *power_well)
 {
-	/*
-	 * We're taking over the BIOS, so clear any requests made by it since
-	 * the driver is in charge now.
-	 */
-	if (I915_READ(HSW_PWR_WELL_BIOS) & HSW_PWR_WELL_ENABLE_REQUEST)
+	/* Take over the request bit if set by BIOS. */
+	if (I915_READ(HSW_PWR_WELL_BIOS) & HSW_PWR_WELL_ENABLE_REQUEST) {
+		if (!(I915_READ(HSW_PWR_WELL_DRIVER) &
+		      HSW_PWR_WELL_ENABLE_REQUEST))
+			I915_WRITE(HSW_PWR_WELL_DRIVER,
+				   HSW_PWR_WELL_ENABLE_REQUEST);
 		I915_WRITE(HSW_PWR_WELL_BIOS, 0);
+	}
 }
 
 static void hsw_power_well_enable(struct drm_i915_private *dev_priv,
@@ -865,8 +867,12 @@ static void skl_power_well_sync_hw(struct drm_i915_private *dev_priv,
 	uint32_t mask = SKL_POWER_WELL_REQ(power_well->id);
 	uint32_t bios_req = I915_READ(HSW_PWR_WELL_BIOS);
 
-	/* Clear any request made by BIOS as driver is taking over */
+	/* Take over the request bit if set by BIOS. */
 	if (bios_req & mask) {
+		uint32_t drv_req = I915_READ(HSW_PWR_WELL_DRIVER);
+
+		if (!(drv_req & mask))
+			I915_WRITE(HSW_PWR_WELL_DRIVER, drv_req | mask);
 		I915_WRITE(HSW_PWR_WELL_BIOS, bios_req & ~mask);
 	}
 }
-- 
2.5.0

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Re: [PATCH v2 4/5] drm/i915: Preserve the state of power wells not explicitly enabled

[Ander Conselvan De Oliveira]

On Fri, 2017-02-17 at 17:39 +0200, Imre Deak wrote:
> Atm, power wells that BIOS has enabled, but which we don't explicitly
> enable during power domain initialization would get disabled as we clear
> the BIOS request bit in the given power well sync_hw hook. To prevent
> this copy over any set request bits in the BIOS request register to the
> driver request register and clear the BIOS request bit only afterwards.
> 
> This doesn't make a difference now, since we enable all power wells
> during power domain initialization. A follow-up patchset will add power
> wells for which this isn't true, so fix up the inconsistency.
> 
> Cc: Ander Conselvan de Oliveira <conselvan2@gmail.com>
> Cc: David Weinehall <david.weinehall@linux.intel.com>
> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> Signed-off-by: Imre Deak <imre.deak@intel.com>

Reviewed-by: Ander Conselvan de Oliveira <conselvan2@gmail.com>

> ---
>  drivers/gpu/drm/i915/intel_runtime_pm.c | 18 ++++++++++++------
>  1 file changed, 12 insertions(+), 6 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c b/drivers/gpu/drm/i915/intel_runtime_pm.c
> index 62c99a9..44d4da3 100644
> --- a/drivers/gpu/drm/i915/intel_runtime_pm.c
> +++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
> @@ -830,12 +830,14 @@ static void skl_set_power_well(struct drm_i915_private *dev_priv,
>  static void hsw_power_well_sync_hw(struct drm_i915_private *dev_priv,
>  				   struct i915_power_well *power_well)
>  {
> -	/*
> -	 * We're taking over the BIOS, so clear any requests made by it since
> -	 * the driver is in charge now.
> -	 */
> -	if (I915_READ(HSW_PWR_WELL_BIOS) & HSW_PWR_WELL_ENABLE_REQUEST)
> +	/* Take over the request bit if set by BIOS. */
> +	if (I915_READ(HSW_PWR_WELL_BIOS) & HSW_PWR_WELL_ENABLE_REQUEST) {
> +		if (!(I915_READ(HSW_PWR_WELL_DRIVER) &
> +		      HSW_PWR_WELL_ENABLE_REQUEST))
> +			I915_WRITE(HSW_PWR_WELL_DRIVER,
> +				   HSW_PWR_WELL_ENABLE_REQUEST);
>  		I915_WRITE(HSW_PWR_WELL_BIOS, 0);
> +	}
>  }
>  
>  static void hsw_power_well_enable(struct drm_i915_private *dev_priv,
> @@ -865,8 +867,12 @@ static void skl_power_well_sync_hw(struct drm_i915_private *dev_priv,
>  	uint32_t mask = SKL_POWER_WELL_REQ(power_well->id);
>  	uint32_t bios_req = I915_READ(HSW_PWR_WELL_BIOS);
>  
> -	/* Clear any request made by BIOS as driver is taking over */
> +	/* Take over the request bit if set by BIOS. */
>  	if (bios_req & mask) {
> +		uint32_t drv_req = I915_READ(HSW_PWR_WELL_DRIVER);
> +
> +		if (!(drv_req & mask))
> +			I915_WRITE(HSW_PWR_WELL_DRIVER, drv_req | mask);
>  		I915_WRITE(HSW_PWR_WELL_BIOS, bios_req & ~mask);
>  	}
>  }
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[PATCH v2 5/5] drm/i915: Add power well SW/HW state verification

[Imre Deak]

Verify that the refcount of all power wells match their HW enabled
state at the end of modeset HW state readout.

Also add documentation on how the reference count for each power well is
supposed to be acquired during initialization and HW state readout.

Suggested by Ander.

Cc: Ander Conselvan de Oliveira <conselvan2@gmail.com>
Cc: David Weinehall <david.weinehall@linux.intel.com>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Imre Deak <imre.deak@intel.com>
---
 drivers/gpu/drm/i915/intel_display.c    |  2 +
 drivers/gpu/drm/i915/intel_drv.h        |  1 +
 drivers/gpu/drm/i915/intel_runtime_pm.c | 85 ++++++++++++++++++++++++++++++++-
 3 files changed, 87 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 88b7d96..00c3fd8 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -15572,6 +15572,8 @@ intel_modeset_setup_hw_state(struct drm_device *dev)
 	}
 	intel_display_set_init_power(dev_priv, false);
 
+	intel_power_domains_verify_state(dev_priv);
+
 	intel_fbc_init_pipe_state(dev_priv);
 }
 
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 6e37fba..50c9329 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -1695,6 +1695,7 @@ int intel_power_domains_init(struct drm_i915_private *);
 void intel_power_domains_fini(struct drm_i915_private *);
 void intel_power_domains_init_hw(struct drm_i915_private *dev_priv, bool resume);
 void intel_power_domains_suspend(struct drm_i915_private *dev_priv);
+void intel_power_domains_verify_state(struct drm_i915_private *dev_priv);
 void bxt_display_core_init(struct drm_i915_private *dev_priv, bool resume);
 void bxt_display_core_uninit(struct drm_i915_private *dev_priv);
 void intel_runtime_pm_enable(struct drm_i915_private *dev_priv);
diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c b/drivers/gpu/drm/i915/intel_runtime_pm.c
index 44d4da3..6b52258 100644
--- a/drivers/gpu/drm/i915/intel_runtime_pm.c
+++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
@@ -2683,7 +2683,10 @@ static void vlv_cmnlane_wa(struct drm_i915_private *dev_priv)
  * @resume: Called from resume code paths or not
  *
  * This function initializes the hardware power domain state and enables all
- * power domains using intel_display_set_init_power().
+ * power wells belonging to the INIT power domain. Power wells in other
+ * domains (and not in the INIT domain) are referenced or disabled during the
+ * modeset state HW readout. After that the reference count of each power well
+ * must match its HW enabled state, see intel_power_domains_verify_state().
  */
 void intel_power_domains_init_hw(struct drm_i915_private *dev_priv, bool resume)
 {
@@ -2736,6 +2739,86 @@ void intel_power_domains_suspend(struct drm_i915_private *dev_priv)
 		bxt_display_core_uninit(dev_priv);
 }
 
+static void intel_power_domains_dump_info(struct drm_i915_private *dev_priv)
+{
+	struct i915_power_domains *power_domains = &dev_priv->power_domains;
+	struct i915_power_well *power_well;
+
+	for_each_power_well(dev_priv, power_well) {
+		enum intel_display_power_domain domain;
+
+		DRM_DEBUG_DRIVER("%-25s %d\n",
+				 power_well->name, power_well->count);
+
+		for_each_power_domain(domain, power_well->domains)
+			DRM_DEBUG_DRIVER("  %-23s %d\n",
+					 intel_display_power_domain_str(domain),
+					 power_domains->domain_use_count[domain]);
+	}
+}
+
+/**
+ * intel_power_domains_verify_state - verify the HW/SW state for all power wells
+ * @dev_priv: i915 device instance
+ *
+ * Verify if the reference count of each power well matches its HW enabled
+ * state and the total refcount of the domains it belongs to. This must be
+ * called after modeset HW state sanitization, which is responsible for
+ * acquiring reference counts for any power wells in use and disabling the
+ * ones left on by BIOS but not required by any active output.
+ */
+void intel_power_domains_verify_state(struct drm_i915_private *dev_priv)
+{
+	struct i915_power_domains *power_domains = &dev_priv->power_domains;
+	struct i915_power_well *power_well;
+	bool dump_domain_info;
+
+	mutex_lock(&power_domains->lock);
+
+	dump_domain_info = false;
+	for_each_power_well(dev_priv, power_well) {
+		enum intel_display_power_domain domain;
+		int domains_count;
+		bool enabled;
+
+		/*
+		 * Power wells not belonging to any domain (like the MISC_IO
+		 * and PW1 power wells) are under FW control, so ignore them,
+		 * since their state can change asynchronously.
+		 */
+		if (!power_well->domains)
+			continue;
+
+		enabled = power_well->ops->is_enabled(dev_priv, power_well);
+		if ((power_well->count || power_well->always_on) != enabled)
+			DRM_ERROR("power well %s state mismatch (refcount %d/enabled %d)",
+				  power_well->name, power_well->count, enabled);
+
+		domains_count = 0;
+		for_each_power_domain(domain, power_well->domains)
+			domains_count += power_domains->domain_use_count[domain];
+
+		if (power_well->count != domains_count) {
+			DRM_ERROR("power well %s refcount/domain refcount mismatch "
+				  "(refcount %d/domains refcount %d)\n",
+				  power_well->name, power_well->count,
+				  domains_count);
+			dump_domain_info = true;
+		}
+	}
+
+	if (dump_domain_info) {
+		static bool dumped;
+
+		if (!dumped) {
+			intel_power_domains_dump_info(dev_priv);
+			dumped = true;
+		}
+	}
+
+	mutex_unlock(&power_domains->lock);
+}
+
 /**
  * intel_runtime_pm_get - grab a runtime pm reference
  * @dev_priv: i915 device instance
-- 
2.5.0

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Re: [PATCH v2 5/5] drm/i915: Add power well SW/HW state verification

[Ander Conselvan De Oliveira]

On Fri, 2017-02-17 at 17:39 +0200, Imre Deak wrote:
> Verify that the refcount of all power wells match their HW enabled
> state at the end of modeset HW state readout.
> 
> Also add documentation on how the reference count for each power well is
> supposed to be acquired during initialization and HW state readout.
> 
> Suggested by Ander.
> 
> Cc: Ander Conselvan de Oliveira <conselvan2@gmail.com>
> Cc: David Weinehall <david.weinehall@linux.intel.com>
> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> Signed-off-by: Imre Deak <imre.deak@intel.com>

Reviewed-by: Ander Conselvan de Oliveira <conselvan2@gmail.com>

> ---
>  drivers/gpu/drm/i915/intel_display.c    |  2 +
>  drivers/gpu/drm/i915/intel_drv.h        |  1 +
>  drivers/gpu/drm/i915/intel_runtime_pm.c | 85 ++++++++++++++++++++++++++++++++-
>  3 files changed, 87 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index 88b7d96..00c3fd8 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -15572,6 +15572,8 @@ intel_modeset_setup_hw_state(struct drm_device *dev)
>  	}
>  	intel_display_set_init_power(dev_priv, false);
>  
> +	intel_power_domains_verify_state(dev_priv);
> +
>  	intel_fbc_init_pipe_state(dev_priv);
>  }
>  
> diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
> index 6e37fba..50c9329 100644
> --- a/drivers/gpu/drm/i915/intel_drv.h
> +++ b/drivers/gpu/drm/i915/intel_drv.h
> @@ -1695,6 +1695,7 @@ int intel_power_domains_init(struct drm_i915_private *);
>  void intel_power_domains_fini(struct drm_i915_private *);
>  void intel_power_domains_init_hw(struct drm_i915_private *dev_priv, bool resume);
>  void intel_power_domains_suspend(struct drm_i915_private *dev_priv);
> +void intel_power_domains_verify_state(struct drm_i915_private *dev_priv);
>  void bxt_display_core_init(struct drm_i915_private *dev_priv, bool resume);
>  void bxt_display_core_uninit(struct drm_i915_private *dev_priv);
>  void intel_runtime_pm_enable(struct drm_i915_private *dev_priv);
> diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c b/drivers/gpu/drm/i915/intel_runtime_pm.c
> index 44d4da3..6b52258 100644
> --- a/drivers/gpu/drm/i915/intel_runtime_pm.c
> +++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
> @@ -2683,7 +2683,10 @@ static void vlv_cmnlane_wa(struct drm_i915_private *dev_priv)
>   * @resume: Called from resume code paths or not
>   *
>   * This function initializes the hardware power domain state and enables all
> - * power domains using intel_display_set_init_power().
> + * power wells belonging to the INIT power domain. Power wells in other
> + * domains (and not in the INIT domain) are referenced or disabled during the
> + * modeset state HW readout. After that the reference count of each power well
> + * must match its HW enabled state, see intel_power_domains_verify_state().
>   */
>  void intel_power_domains_init_hw(struct drm_i915_private *dev_priv, bool resume)
>  {
> @@ -2736,6 +2739,86 @@ void intel_power_domains_suspend(struct drm_i915_private *dev_priv)
>  		bxt_display_core_uninit(dev_priv);
>  }
>  
> +static void intel_power_domains_dump_info(struct drm_i915_private *dev_priv)
> +{
> +	struct i915_power_domains *power_domains = &dev_priv->power_domains;
> +	struct i915_power_well *power_well;
> +
> +	for_each_power_well(dev_priv, power_well) {
> +		enum intel_display_power_domain domain;
> +
> +		DRM_DEBUG_DRIVER("%-25s %d\n",
> +				 power_well->name, power_well->count);
> +
> +		for_each_power_domain(domain, power_well->domains)
> +			DRM_DEBUG_DRIVER("  %-23s %d\n",
> +					 intel_display_power_domain_str(domain),
> +					 power_domains->domain_use_count[domain]);
> +	}
> +}
> +
> +/**
> + * intel_power_domains_verify_state - verify the HW/SW state for all power wells
> + * @dev_priv: i915 device instance
> + *
> + * Verify if the reference count of each power well matches its HW enabled
> + * state and the total refcount of the domains it belongs to. This must be
> + * called after modeset HW state sanitization, which is responsible for
> + * acquiring reference counts for any power wells in use and disabling the
> + * ones left on by BIOS but not required by any active output.
> + */
> +void intel_power_domains_verify_state(struct drm_i915_private *dev_priv)
> +{
> +	struct i915_power_domains *power_domains = &dev_priv->power_domains;
> +	struct i915_power_well *power_well;
> +	bool dump_domain_info;
> +
> +	mutex_lock(&power_domains->lock);
> +
> +	dump_domain_info = false;
> +	for_each_power_well(dev_priv, power_well) {
> +		enum intel_display_power_domain domain;
> +		int domains_count;
> +		bool enabled;
> +
> +		/*
> +		 * Power wells not belonging to any domain (like the MISC_IO
> +		 * and PW1 power wells) are under FW control, so ignore them,
> +		 * since their state can change asynchronously.
> +		 */
> +		if (!power_well->domains)
> +			continue;
> +
> +		enabled = power_well->ops->is_enabled(dev_priv, power_well);
> +		if ((power_well->count || power_well->always_on) != enabled)
> +			DRM_ERROR("power well %s state mismatch (refcount %d/enabled %d)",
> +				  power_well->name, power_well->count, enabled);
> +
> +		domains_count = 0;
> +		for_each_power_domain(domain, power_well->domains)
> +			domains_count += power_domains->domain_use_count[domain];
> +
> +		if (power_well->count != domains_count) {
> +			DRM_ERROR("power well %s refcount/domain refcount mismatch "
> +				  "(refcount %d/domains refcount %d)\n",
> +				  power_well->name, power_well->count,
> +				  domains_count);
> +			dump_domain_info = true;
> +		}
> +	}
> +
> +	if (dump_domain_info) {
> +		static bool dumped;
> +
> +		if (!dumped) {
> +			intel_power_domains_dump_info(dev_priv);
> +			dumped = true;
> +		}
> +	}
> +
> +	mutex_unlock(&power_domains->lock);
> +}
> +
>  /**
>   * intel_runtime_pm_get - grab a runtime pm reference
>   * @dev_priv: i915 device instance
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✓ Fi.CI.BAT: success for drm/i915: Fix clearing of BIOS power well requests (rev2)

[Patchwork]

== Series Details ==

Series: drm/i915: Fix clearing of BIOS power well requests (rev2)
URL   : https://patchwork.freedesktop.org/series/19699/
State : success

== Summary ==

Series 19699v2 drm/i915: Fix clearing of BIOS power well requests
https://patchwork.freedesktop.org/api/1.0/series/19699/revisions/2/mbox/

fi-bdw-5557u     total:252  pass:241  dwarn:0   dfail:0   fail:0   skip:11 
fi-bsw-n3050     total:252  pass:213  dwarn:0   dfail:0   fail:0   skip:39 
fi-bxt-j4205     total:252  pass:233  dwarn:0   dfail:0   fail:0   skip:19 
fi-bxt-t5700     total:83   pass:70   dwarn:0   dfail:0   fail:0   skip:12 
fi-byt-j1900     total:252  pass:225  dwarn:0   dfail:0   fail:0   skip:27 
fi-byt-n2820     total:252  pass:221  dwarn:0   dfail:0   fail:0   skip:31 
fi-hsw-4770      total:252  pass:236  dwarn:0   dfail:0   fail:0   skip:16 
fi-hsw-4770r     total:252  pass:236  dwarn:0   dfail:0   fail:0   skip:16 
fi-ilk-650       total:252  pass:202  dwarn:0   dfail:0   fail:0   skip:50 
fi-ivb-3520m     total:252  pass:234  dwarn:0   dfail:0   fail:0   skip:18 
fi-ivb-3770      total:252  pass:234  dwarn:0   dfail:0   fail:0   skip:18 
fi-kbl-7500u     total:252  pass:234  dwarn:0   dfail:0   fail:0   skip:18 
fi-skl-6260u     total:252  pass:242  dwarn:0   dfail:0   fail:0   skip:10 
fi-skl-6700hq    total:252  pass:235  dwarn:0   dfail:0   fail:0   skip:17 
fi-skl-6700k     total:252  pass:230  dwarn:4   dfail:0   fail:0   skip:18 
fi-skl-6770hq    total:252  pass:242  dwarn:0   dfail:0   fail:0   skip:10 
fi-snb-2520m     total:252  pass:224  dwarn:0   dfail:0   fail:0   skip:28 
fi-snb-2600      total:252  pass:223  dwarn:0   dfail:0   fail:0   skip:29 

02022d17a5787709617b7897de3906970e2b0721 drm-tip: 2017y-02m-17d-15h-15m-45s UTC integration manifest
0499ce8 drm/i915: Add power well SW/HW state verification
4cce996 drm/i915: Preserve the state of power wells not explicitly enabled
1c709db drm/i915/gen9: Fix clearing of the BIOS power well request register
28f7e95 drm/i915: Call the sync_hw hook for power wells without a domain
c059f6b drm/i915: Remove redundant toggling from the power well sync_hw hooks

== Logs ==

For more details see: https://intel-gfx-ci.01.org/CI/Patchwork_3887/
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Re: ✓ Fi.CI.BAT: success for drm/i915: Fix clearing of BIOS power well requests (rev2)

[Imre Deak]

On Fri, Feb 17, 2017 at 07:52:12PM +0000, Patchwork wrote:
> == Series Details ==
> 
> Series: drm/i915: Fix clearing of BIOS power well requests (rev2)
> URL   : https://patchwork.freedesktop.org/series/19699/
> State : success

Pushed to dinq, thanks for the review.

--Imre

> 
> == Summary ==
> 
> Series 19699v2 drm/i915: Fix clearing of BIOS power well requests
> https://patchwork.freedesktop.org/api/1.0/series/19699/revisions/2/mbox/
> 
> fi-bdw-5557u     total:252  pass:241  dwarn:0   dfail:0   fail:0   skip:11 
> fi-bsw-n3050     total:252  pass:213  dwarn:0   dfail:0   fail:0   skip:39 
> fi-bxt-j4205     total:252  pass:233  dwarn:0   dfail:0   fail:0   skip:19 
> fi-bxt-t5700     total:83   pass:70   dwarn:0   dfail:0   fail:0   skip:12 
> fi-byt-j1900     total:252  pass:225  dwarn:0   dfail:0   fail:0   skip:27 
> fi-byt-n2820     total:252  pass:221  dwarn:0   dfail:0   fail:0   skip:31 
> fi-hsw-4770      total:252  pass:236  dwarn:0   dfail:0   fail:0   skip:16 
> fi-hsw-4770r     total:252  pass:236  dwarn:0   dfail:0   fail:0   skip:16 
> fi-ilk-650       total:252  pass:202  dwarn:0   dfail:0   fail:0   skip:50 
> fi-ivb-3520m     total:252  pass:234  dwarn:0   dfail:0   fail:0   skip:18 
> fi-ivb-3770      total:252  pass:234  dwarn:0   dfail:0   fail:0   skip:18 
> fi-kbl-7500u     total:252  pass:234  dwarn:0   dfail:0   fail:0   skip:18 
> fi-skl-6260u     total:252  pass:242  dwarn:0   dfail:0   fail:0   skip:10 
> fi-skl-6700hq    total:252  pass:235  dwarn:0   dfail:0   fail:0   skip:17 
> fi-skl-6700k     total:252  pass:230  dwarn:4   dfail:0   fail:0   skip:18 
> fi-skl-6770hq    total:252  pass:242  dwarn:0   dfail:0   fail:0   skip:10 
> fi-snb-2520m     total:252  pass:224  dwarn:0   dfail:0   fail:0   skip:28 
> fi-snb-2600      total:252  pass:223  dwarn:0   dfail:0   fail:0   skip:29 
> 
> 02022d17a5787709617b7897de3906970e2b0721 drm-tip: 2017y-02m-17d-15h-15m-45s UTC integration manifest
> 0499ce8 drm/i915: Add power well SW/HW state verification
> 4cce996 drm/i915: Preserve the state of power wells not explicitly enabled
> 1c709db drm/i915/gen9: Fix clearing of the BIOS power well request register
> 28f7e95 drm/i915: Call the sync_hw hook for power wells without a domain
> c059f6b drm/i915: Remove redundant toggling from the power well sync_hw hooks
> 
> == Logs ==
> 
> For more details see: https://intel-gfx-ci.01.org/CI/Patchwork_3887/
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