[PATCH 01/67] drm/i915/cnp: Introduce Cannonpoint PCH.

[PATCH 01/67] drm/i915/cnp: Introduce Cannonpoint PCH.

[Rodrigo Vivi]

Most of south engine display that is in PCH is still the
same as SPT and KBP, except for this key differences:

- Backlight: Backlight programming changed in CNP PCH.
- Panel Power: Sligh programming changed in CNP PCH.
- GMBUS and GPIO: The pin mapping has changed in CNP PCH.

All of these changes follow more the BXT style.

v2: Update definition to use dev_priv isntead of dev (Tvrtko).

Cc: Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
---
 drivers/gpu/drm/i915/i915_drv.c | 3 +++
 drivers/gpu/drm/i915/i915_drv.h | 3 +++
 drivers/gpu/drm/i915/i915_irq.c | 6 ++++--
 3 files changed, 10 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index bd85e38..05e3f3f 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -216,6 +216,9 @@ static void intel_detect_pch(struct drm_i915_private *dev_priv)
 				DRM_DEBUG_KMS("Found KabyPoint PCH\n");
 				WARN_ON(!IS_SKYLAKE(dev_priv) &&
 					!IS_KABYLAKE(dev_priv));
+			} else if (id == INTEL_PCH_CNP_DEVICE_ID_TYPE) {
+				dev_priv->pch_type = PCH_CNP;
+				DRM_DEBUG_KMS("Found CannonPoint PCH\n");
 			} else if ((id == INTEL_PCH_P2X_DEVICE_ID_TYPE) ||
 				   (id == INTEL_PCH_P3X_DEVICE_ID_TYPE) ||
 				   ((id == INTEL_PCH_QEMU_DEVICE_ID_TYPE) &&
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index c9b0949..d798976 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1209,6 +1209,7 @@ enum intel_pch {
 	PCH_LPT,	/* Lynxpoint PCH */
 	PCH_SPT,        /* Sunrisepoint PCH */
 	PCH_KBP,        /* Kabypoint PCH */
+	PCH_CNP,        /* Cannonpoint PCH */
 	PCH_NOP,
 };
 
@@ -2948,11 +2949,13 @@ static inline struct scatterlist *__sg_next(struct scatterlist *sg)
 #define INTEL_PCH_SPT_DEVICE_ID_TYPE		0xA100
 #define INTEL_PCH_SPT_LP_DEVICE_ID_TYPE		0x9D00
 #define INTEL_PCH_KBP_DEVICE_ID_TYPE		0xA200
+#define INTEL_PCH_CNP_DEVICE_ID_TYPE		0xA300
 #define INTEL_PCH_P2X_DEVICE_ID_TYPE		0x7100
 #define INTEL_PCH_P3X_DEVICE_ID_TYPE		0x7000
 #define INTEL_PCH_QEMU_DEVICE_ID_TYPE		0x2900 /* qemu q35 has 2918 */
 
 #define INTEL_PCH_TYPE(dev_priv) ((dev_priv)->pch_type)
+#define HAS_PCH_CNP(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_CNP)
 #define HAS_PCH_KBP(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_KBP)
 #define HAS_PCH_SPT(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_SPT)
 #define HAS_PCH_LPT(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_LPT)
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index d9d1969..698eb76 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -2582,7 +2582,8 @@ static void bxt_hpd_irq_handler(struct drm_i915_private *dev_priv,
 			I915_WRITE(SDEIIR, iir);
 			ret = IRQ_HANDLED;
 
-			if (HAS_PCH_SPT(dev_priv) || HAS_PCH_KBP(dev_priv))
+			if (HAS_PCH_SPT(dev_priv) || HAS_PCH_KBP(dev_priv) ||
+			    HAS_PCH_CNP(dev_priv))
 				spt_irq_handler(dev_priv, iir);
 			else
 				cpt_irq_handler(dev_priv, iir);
@@ -4322,7 +4323,8 @@ void intel_irq_init(struct drm_i915_private *dev_priv)
 		dev->driver->disable_vblank = gen8_disable_vblank;
 		if (IS_GEN9_LP(dev_priv))
 			dev_priv->display.hpd_irq_setup = bxt_hpd_irq_setup;
-		else if (HAS_PCH_SPT(dev_priv) || HAS_PCH_KBP(dev_priv))
+		else if (HAS_PCH_SPT(dev_priv) || HAS_PCH_KBP(dev_priv) ||
+			 HAS_PCH_CNP(dev_priv))
 			dev_priv->display.hpd_irq_setup = spt_hpd_irq_setup;
 		else
 			dev_priv->display.hpd_irq_setup = ilk_hpd_irq_setup;
-- 
1.9.1

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[PATCH 02/67] drm/i915/cnp: Add PCI ID for Cannonpoint LP PCH

[Rodrigo Vivi]

From: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>

The first two bytes of PCI ID for CNP_LP PCH are the same as that of
SPT_LP. We should really be looking at the first 9 bits instead of the
first 8 to identify platforms, although this seems to have not caused any
problems on earlier platforms. Introduce a 9 bit extended mask for SPT and
CNP while not touching the code for any of the other platforms.

v2: (Rodrigo) Make platform agnostic and fix commit message.

Signed-off-by: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
---
 drivers/gpu/drm/i915/i915_drv.c | 7 ++++++-
 drivers/gpu/drm/i915/i915_drv.h | 4 ++++
 2 files changed, 10 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 05e3f3f..836db0d 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -170,6 +170,8 @@ static void intel_detect_pch(struct drm_i915_private *dev_priv)
 	while ((pch = pci_get_class(PCI_CLASS_BRIDGE_ISA << 8, pch))) {
 		if (pch->vendor == PCI_VENDOR_ID_INTEL) {
 			unsigned short id = pch->device & INTEL_PCH_DEVICE_ID_MASK;
+			unsigned short id_ext = pch->device & INTEL_PCH_DEVICE_ID_MASK_EXT;
+
 			dev_priv->pch_id = id;
 
 			if (id == INTEL_PCH_IBX_DEVICE_ID_TYPE) {
@@ -206,7 +208,7 @@ static void intel_detect_pch(struct drm_i915_private *dev_priv)
 				DRM_DEBUG_KMS("Found SunrisePoint PCH\n");
 				WARN_ON(!IS_SKYLAKE(dev_priv) &&
 					!IS_KABYLAKE(dev_priv));
-			} else if (id == INTEL_PCH_SPT_LP_DEVICE_ID_TYPE) {
+			} else if (id_ext == INTEL_PCH_SPT_LP_DEVICE_ID_TYPE) {
 				dev_priv->pch_type = PCH_SPT;
 				DRM_DEBUG_KMS("Found SunrisePoint LP PCH\n");
 				WARN_ON(!IS_SKYLAKE(dev_priv) &&
@@ -219,6 +221,9 @@ static void intel_detect_pch(struct drm_i915_private *dev_priv)
 			} else if (id == INTEL_PCH_CNP_DEVICE_ID_TYPE) {
 				dev_priv->pch_type = PCH_CNP;
 				DRM_DEBUG_KMS("Found CannonPoint PCH\n");
+			} else if (id_ext == INTEL_PCH_CNP_LP_DEVICE_ID_TYPE) {
+				dev_priv->pch_type = PCH_CNP;
+				DRM_DEBUG_KMS("Found CannonPoint LP PCH\n");
 			} else if ((id == INTEL_PCH_P2X_DEVICE_ID_TYPE) ||
 				   (id == INTEL_PCH_P3X_DEVICE_ID_TYPE) ||
 				   ((id == INTEL_PCH_QEMU_DEVICE_ID_TYPE) &&
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index d798976..2685f12 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -2941,6 +2941,7 @@ static inline struct scatterlist *__sg_next(struct scatterlist *sg)
 #define HAS_POOLED_EU(dev_priv)	((dev_priv)->info.has_pooled_eu)
 
 #define INTEL_PCH_DEVICE_ID_MASK		0xff00
+#define INTEL_PCH_DEVICE_ID_MASK_EXT		0xff80
 #define INTEL_PCH_IBX_DEVICE_ID_TYPE		0x3b00
 #define INTEL_PCH_CPT_DEVICE_ID_TYPE		0x1c00
 #define INTEL_PCH_PPT_DEVICE_ID_TYPE		0x1e00
@@ -2950,12 +2951,15 @@ static inline struct scatterlist *__sg_next(struct scatterlist *sg)
 #define INTEL_PCH_SPT_LP_DEVICE_ID_TYPE		0x9D00
 #define INTEL_PCH_KBP_DEVICE_ID_TYPE		0xA200
 #define INTEL_PCH_CNP_DEVICE_ID_TYPE		0xA300
+#define INTEL_PCH_CNP_LP_DEVICE_ID_TYPE		0x9D80
 #define INTEL_PCH_P2X_DEVICE_ID_TYPE		0x7100
 #define INTEL_PCH_P3X_DEVICE_ID_TYPE		0x7000
 #define INTEL_PCH_QEMU_DEVICE_ID_TYPE		0x2900 /* qemu q35 has 2918 */
 
 #define INTEL_PCH_TYPE(dev_priv) ((dev_priv)->pch_type)
 #define HAS_PCH_CNP(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_CNP)
+#define HAS_PCH_CNP_LP(dev_priv) \
+	((dev_priv)->pch_id == INTEL_PCH_CNP_LP_DEVICE_ID_TYPE)
 #define HAS_PCH_KBP(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_KBP)
 #define HAS_PCH_SPT(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_SPT)
 #define HAS_PCH_LPT(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_LPT)
-- 
1.9.1

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Re: [PATCH 02/67] drm/i915/cnp: Add PCI ID for Cannonpoint LP PCH

[Srivatsa, Anusha]

>-----Original Message-----
>From: Intel-gfx [mailto:intel-gfx-bounces@lists.freedesktop.org] On Behalf Of
>Rodrigo Vivi
>Sent: Thursday, April 6, 2017 12:15 PM
>To: intel-gfx@lists.freedesktop.org
>Cc: Pandiyan, Dhinakaran <dhinakaran.pandiyan@intel.com>; Vivi, Rodrigo
><rodrigo.vivi@intel.com>
>Subject: [Intel-gfx] [PATCH 02/67] drm/i915/cnp: Add PCI ID for Cannonpoint LP
>PCH
>
>From: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
>
>The first two bytes of PCI ID for CNP_LP PCH are the same as that of SPT_LP. We
>should really be looking at the first 9 bits instead of the first 8 to identify
>platforms, although this seems to have not caused any problems on earlier
>platforms. Introduce a 9 bit extended mask for SPT and CNP while not touching
>the code for any of the other platforms.
>
>v2: (Rodrigo) Make platform agnostic and fix commit message.
>
>Signed-off-by: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
>Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Reviewed-by: Anusha Srivatsa <anusha.srivatsa@intel.com>

> drivers/gpu/drm/i915/i915_drv.c | 7 ++++++-  drivers/gpu/drm/i915/i915_drv.h |
>4 ++++
> 2 files changed, 10 insertions(+), 1 deletion(-)
>
>diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
>index 05e3f3f..836db0d 100644
>--- a/drivers/gpu/drm/i915/i915_drv.c
>+++ b/drivers/gpu/drm/i915/i915_drv.c
>@@ -170,6 +170,8 @@ static void intel_detect_pch(struct drm_i915_private
>*dev_priv)
> 	while ((pch = pci_get_class(PCI_CLASS_BRIDGE_ISA << 8, pch))) {
> 		if (pch->vendor == PCI_VENDOR_ID_INTEL) {
> 			unsigned short id = pch->device &
>INTEL_PCH_DEVICE_ID_MASK;
>+			unsigned short id_ext = pch->device &
>INTEL_PCH_DEVICE_ID_MASK_EXT;
>+
> 			dev_priv->pch_id = id;
>
> 			if (id == INTEL_PCH_IBX_DEVICE_ID_TYPE) { @@ -206,7
>+208,7 @@ static void intel_detect_pch(struct drm_i915_private *dev_priv)
> 				DRM_DEBUG_KMS("Found SunrisePoint
>PCH\n");
> 				WARN_ON(!IS_SKYLAKE(dev_priv) &&
> 					!IS_KABYLAKE(dev_priv));
>-			} else if (id == INTEL_PCH_SPT_LP_DEVICE_ID_TYPE) {
>+			} else if (id_ext == INTEL_PCH_SPT_LP_DEVICE_ID_TYPE)
>{
> 				dev_priv->pch_type = PCH_SPT;
> 				DRM_DEBUG_KMS("Found SunrisePoint LP
>PCH\n");
> 				WARN_ON(!IS_SKYLAKE(dev_priv) &&
>@@ -219,6 +221,9 @@ static void intel_detect_pch(struct drm_i915_private
>*dev_priv)
> 			} else if (id == INTEL_PCH_CNP_DEVICE_ID_TYPE) {
> 				dev_priv->pch_type = PCH_CNP;
> 				DRM_DEBUG_KMS("Found CannonPoint
>PCH\n");
>+			} else if (id_ext ==
>INTEL_PCH_CNP_LP_DEVICE_ID_TYPE) {
>+				dev_priv->pch_type = PCH_CNP;
>+				DRM_DEBUG_KMS("Found CannonPoint LP
>PCH\n");
> 			} else if ((id == INTEL_PCH_P2X_DEVICE_ID_TYPE) ||
> 				   (id == INTEL_PCH_P3X_DEVICE_ID_TYPE) ||
> 				   ((id == INTEL_PCH_QEMU_DEVICE_ID_TYPE)
>&& diff --git a/drivers/gpu/drm/i915/i915_drv.h
>b/drivers/gpu/drm/i915/i915_drv.h index d798976..2685f12 100644
>--- a/drivers/gpu/drm/i915/i915_drv.h
>+++ b/drivers/gpu/drm/i915/i915_drv.h
>@@ -2941,6 +2941,7 @@ static inline struct scatterlist *__sg_next(struct
>scatterlist *sg)
> #define HAS_POOLED_EU(dev_priv)	((dev_priv)->info.has_pooled_eu)
>
> #define INTEL_PCH_DEVICE_ID_MASK		0xff00
>+#define INTEL_PCH_DEVICE_ID_MASK_EXT		0xff80
> #define INTEL_PCH_IBX_DEVICE_ID_TYPE		0x3b00
> #define INTEL_PCH_CPT_DEVICE_ID_TYPE		0x1c00
> #define INTEL_PCH_PPT_DEVICE_ID_TYPE		0x1e00
>@@ -2950,12 +2951,15 @@ static inline struct scatterlist *__sg_next(struct
>scatterlist *sg)
> #define INTEL_PCH_SPT_LP_DEVICE_ID_TYPE		0x9D00
> #define INTEL_PCH_KBP_DEVICE_ID_TYPE		0xA200
> #define INTEL_PCH_CNP_DEVICE_ID_TYPE		0xA300
>+#define INTEL_PCH_CNP_LP_DEVICE_ID_TYPE		0x9D80
> #define INTEL_PCH_P2X_DEVICE_ID_TYPE		0x7100
> #define INTEL_PCH_P3X_DEVICE_ID_TYPE		0x7000
> #define INTEL_PCH_QEMU_DEVICE_ID_TYPE		0x2900 /* qemu q35
>has 2918 */
>
> #define INTEL_PCH_TYPE(dev_priv) ((dev_priv)->pch_type)  #define
>HAS_PCH_CNP(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_CNP)
>+#define HAS_PCH_CNP_LP(dev_priv) \
>+	((dev_priv)->pch_id == INTEL_PCH_CNP_LP_DEVICE_ID_TYPE)
> #define HAS_PCH_KBP(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_KBP)
>#define HAS_PCH_SPT(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_SPT)
>#define HAS_PCH_LPT(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_LPT)
>--
>1.9.1
>
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[PATCH 03/67] drm/i915/cnp: Get/set proper Raw clock frequency on CNP.

[Rodrigo Vivi]

RAWCLK_FREQ register has changed for platforms with CNP+.

[29:26] This field provides the denominator for the fractional
	part of the microsecond counter divider.  The numerator
	is fixed at 1. Program this field to the denominator of
	the fractional portion of reference frequency minus one.
	If the fraction is 0, program to 0.
	0100b = Fraction .2 MHz = Fraction 1/5.
	0000b = Fraction .0 MHz.

[25:16] This field provides the integer part of the microsecond
	counter divider. Program this field to the integer portion
	of the reference frequenct minus one.

Also this register tells us that proper raw clock should be read
from SFUSE_STRAP and programmed to this register. Up to this point
on other platforms we are reading instead of programming it so
probably relying on whatever BIOS had configured here.

Now on let's follow the spec and also program this register
fetching the right value from SFUSE_STRAP as Spec tells us to do.

v2: Read from SFUSE_STRAP and Program RAWCLK_FREQ instead of
    reading the value relying someone else will program that
    for us.
v3: Add missing else. (Jani)
v4: Addressing all Ville's catches:
    Use macro for shift bits instead of defining shift.
    Remove shift from the cleaning bits with mask that already
    has it.
    Add missing I915_WRITE to actually write the reg.
    Stop using useless DIV_ROUND_* on divider that is exact
    dividion and use DIV_ROUND_CLOSEST for the fraction part.
v5: Remove useless Read-Modify-Write on raclk_freq reg. (Ville).
v6: Change is per PCH instead of per platform.

Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Cc: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h    |  5 +++++
 drivers/gpu/drm/i915/intel_cdclk.c | 29 ++++++++++++++++++++++++++++-
 2 files changed, 33 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 11b12f4..6826547 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -6836,6 +6836,10 @@ enum {
 #define  FDL_TP2_TIMER_SHIFT    10
 #define  FDL_TP2_TIMER_MASK     (3<<10)
 #define  RAWCLK_FREQ_MASK       0x3ff
+#define  CNP_RAWCLK_DIV_MASK	(0x3ff << 16)
+#define  CNP_RAWCLK_DIV(div)	((div) << 16)
+#define  CNP_RAWCLK_FRAC_MASK	(0xf << 26)
+#define  CNP_RAWCLK_FRAC(frac)	((frac) << 26)
 
 #define PCH_DPLL_TMR_CFG        _MMIO(0xc6208)
 
@@ -8146,6 +8150,7 @@ enum {
 /* SFUSE_STRAP */
 #define SFUSE_STRAP			_MMIO(0xc2014)
 #define  SFUSE_STRAP_FUSE_LOCK		(1<<13)
+#define  SFUSE_STRAP_RAW_FREQUENCY	(1<<8)
 #define  SFUSE_STRAP_DISPLAY_DISABLED	(1<<7)
 #define  SFUSE_STRAP_CRT_DISABLED	(1<<6)
 #define  SFUSE_STRAP_DDIB_DETECTED	(1<<2)
diff --git a/drivers/gpu/drm/i915/intel_cdclk.c b/drivers/gpu/drm/i915/intel_cdclk.c
index 763010f..4745596 100644
--- a/drivers/gpu/drm/i915/intel_cdclk.c
+++ b/drivers/gpu/drm/i915/intel_cdclk.c
@@ -1780,6 +1780,30 @@ void intel_update_cdclk(struct drm_i915_private *dev_priv)
 			   DIV_ROUND_UP(dev_priv->cdclk.hw.cdclk, 1000));
 }
 
+static int cnp_rawclk(struct drm_i915_private *dev_priv)
+{
+	u32 rawclk;
+	int divider, fraction;
+
+	if (I915_READ(SFUSE_STRAP) & SFUSE_STRAP_RAW_FREQUENCY) {
+		/* 24 MHz */
+		divider = 24000;
+		fraction = 0;
+	} else {
+		/* 19.2 MHz */
+		divider = 19000;
+		fraction = 200;
+	}
+
+	rawclk = CNP_RAWCLK_DIV((divider / 1000) - 1);
+	if (fraction)
+		rawclk |= CNP_RAWCLK_FRAC(DIV_ROUND_CLOSEST(1000,
+							    fraction) - 1);
+
+	I915_WRITE(PCH_RAWCLK_FREQ, rawclk);
+	return divider + fraction;
+}
+
 static int pch_rawclk(struct drm_i915_private *dev_priv)
 {
 	return (I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK) * 1000;
@@ -1829,7 +1853,10 @@ static int g4x_hrawclk(struct drm_i915_private *dev_priv)
  */
 void intel_update_rawclk(struct drm_i915_private *dev_priv)
 {
-	if (HAS_PCH_SPLIT(dev_priv))
+
+	if (HAS_PCH_CNP(dev_priv))
+		dev_priv->rawclk_freq = cnp_rawclk(dev_priv);
+	else if (HAS_PCH_SPLIT(dev_priv))
 		dev_priv->rawclk_freq = pch_rawclk(dev_priv);
 	else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
 		dev_priv->rawclk_freq = vlv_hrawclk(dev_priv);
-- 
1.9.1

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Re: [PATCH 03/67] drm/i915/cnp: Get/set proper Raw clock frequency on CNP.

[Ville Syrjälä]

On Thu, Apr 06, 2017 at 12:14:59PM -0700, Rodrigo Vivi wrote:
> RAWCLK_FREQ register has changed for platforms with CNP+.
> 
> [29:26] This field provides the denominator for the fractional
> 	part of the microsecond counter divider.  The numerator
> 	is fixed at 1. Program this field to the denominator of
> 	the fractional portion of reference frequency minus one.
> 	If the fraction is 0, program to 0.
> 	0100b = Fraction .2 MHz = Fraction 1/5.
> 	0000b = Fraction .0 MHz.
> 
> [25:16] This field provides the integer part of the microsecond
> 	counter divider. Program this field to the integer portion
> 	of the reference frequenct minus one.
> 
> Also this register tells us that proper raw clock should be read
> from SFUSE_STRAP and programmed to this register. Up to this point
> on other platforms we are reading instead of programming it so
> probably relying on whatever BIOS had configured here.
> 
> Now on let's follow the spec and also program this register
> fetching the right value from SFUSE_STRAP as Spec tells us to do.
> 
> v2: Read from SFUSE_STRAP and Program RAWCLK_FREQ instead of
>     reading the value relying someone else will program that
>     for us.
> v3: Add missing else. (Jani)
> v4: Addressing all Ville's catches:
>     Use macro for shift bits instead of defining shift.
>     Remove shift from the cleaning bits with mask that already
>     has it.
>     Add missing I915_WRITE to actually write the reg.
>     Stop using useless DIV_ROUND_* on divider that is exact
>     dividion and use DIV_ROUND_CLOSEST for the fraction part.
> v5: Remove useless Read-Modify-Write on raclk_freq reg. (Ville).
> v6: Change is per PCH instead of per platform.
> 
> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> Cc: Jani Nikula <jani.nikula@intel.com>
> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>

Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

> ---
>  drivers/gpu/drm/i915/i915_reg.h    |  5 +++++
>  drivers/gpu/drm/i915/intel_cdclk.c | 29 ++++++++++++++++++++++++++++-
>  2 files changed, 33 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 11b12f4..6826547 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -6836,6 +6836,10 @@ enum {
>  #define  FDL_TP2_TIMER_SHIFT    10
>  #define  FDL_TP2_TIMER_MASK     (3<<10)
>  #define  RAWCLK_FREQ_MASK       0x3ff
> +#define  CNP_RAWCLK_DIV_MASK	(0x3ff << 16)
> +#define  CNP_RAWCLK_DIV(div)	((div) << 16)
> +#define  CNP_RAWCLK_FRAC_MASK	(0xf << 26)
> +#define  CNP_RAWCLK_FRAC(frac)	((frac) << 26)
>  
>  #define PCH_DPLL_TMR_CFG        _MMIO(0xc6208)
>  
> @@ -8146,6 +8150,7 @@ enum {
>  /* SFUSE_STRAP */
>  #define SFUSE_STRAP			_MMIO(0xc2014)
>  #define  SFUSE_STRAP_FUSE_LOCK		(1<<13)
> +#define  SFUSE_STRAP_RAW_FREQUENCY	(1<<8)
>  #define  SFUSE_STRAP_DISPLAY_DISABLED	(1<<7)
>  #define  SFUSE_STRAP_CRT_DISABLED	(1<<6)
>  #define  SFUSE_STRAP_DDIB_DETECTED	(1<<2)
> diff --git a/drivers/gpu/drm/i915/intel_cdclk.c b/drivers/gpu/drm/i915/intel_cdclk.c
> index 763010f..4745596 100644
> --- a/drivers/gpu/drm/i915/intel_cdclk.c
> +++ b/drivers/gpu/drm/i915/intel_cdclk.c
> @@ -1780,6 +1780,30 @@ void intel_update_cdclk(struct drm_i915_private *dev_priv)
>  			   DIV_ROUND_UP(dev_priv->cdclk.hw.cdclk, 1000));
>  }
>  
> +static int cnp_rawclk(struct drm_i915_private *dev_priv)
> +{
> +	u32 rawclk;
> +	int divider, fraction;
> +
> +	if (I915_READ(SFUSE_STRAP) & SFUSE_STRAP_RAW_FREQUENCY) {
> +		/* 24 MHz */
> +		divider = 24000;
> +		fraction = 0;
> +	} else {
> +		/* 19.2 MHz */
> +		divider = 19000;
> +		fraction = 200;
> +	}
> +
> +	rawclk = CNP_RAWCLK_DIV((divider / 1000) - 1);
> +	if (fraction)
> +		rawclk |= CNP_RAWCLK_FRAC(DIV_ROUND_CLOSEST(1000,
> +							    fraction) - 1);
> +
> +	I915_WRITE(PCH_RAWCLK_FREQ, rawclk);
> +	return divider + fraction;
> +}
> +
>  static int pch_rawclk(struct drm_i915_private *dev_priv)
>  {
>  	return (I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK) * 1000;
> @@ -1829,7 +1853,10 @@ static int g4x_hrawclk(struct drm_i915_private *dev_priv)
>   */
>  void intel_update_rawclk(struct drm_i915_private *dev_priv)
>  {
> -	if (HAS_PCH_SPLIT(dev_priv))
> +
> +	if (HAS_PCH_CNP(dev_priv))
> +		dev_priv->rawclk_freq = cnp_rawclk(dev_priv);
> +	else if (HAS_PCH_SPLIT(dev_priv))
>  		dev_priv->rawclk_freq = pch_rawclk(dev_priv);
>  	else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
>  		dev_priv->rawclk_freq = vlv_hrawclk(dev_priv);
> -- 
> 1.9.1

-- 
Ville Syrjälä
Intel OTC
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[PATCH 04/67] drm/i915/cnp: Add Backlight support to CNP PCH.

[Rodrigo Vivi]

Backlight support on Cannonpoint is a lot
likely Broxton, but with only one controller (0).

Also other main changes/differences:

- PWM clock frequency = Raw clock frequency = 19.2 MHz or
  24 MHz.  Value is found in SFUSE_STRAP.
- PWM increment = 1

v2: Reuse BXT functions with controller 0 instead of
    redefining it. (Jani).
    Use dev_priv->rawclk_freq instead of getting the value
    from SFUSE_STRAP.
v3: Avoid setup backligh controller along with hooks and
    fully reuse hooks setup as suggested by Jani.
v4: Clean up commit message.
v5: Implement per PCH instead per platform.

Cc: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
---
 drivers/gpu/drm/i915/intel_panel.c | 19 +++++++++++++++++--
 1 file changed, 17 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_panel.c b/drivers/gpu/drm/i915/intel_panel.c
index cb50c52..1978bec 100644
--- a/drivers/gpu/drm/i915/intel_panel.c
+++ b/drivers/gpu/drm/i915/intel_panel.c
@@ -1247,6 +1247,18 @@ static u32 bxt_hz_to_pwm(struct intel_connector *connector, u32 pwm_freq_hz)
 }
 
 /*
+ * CNP: PWM clock frequency is 19.2 MHz or 24 MHz.
+ *      Value is found in SFUSE_STRAP.
+ *      PWM increment = 1
+ */
+static u32 cnp_hz_to_pwm(struct intel_connector *connector, u32 pwm_freq_hz)
+{
+	struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
+
+	return DIV_ROUND_CLOSEST(KHz(dev_priv->rawclk_freq), pwm_freq_hz);
+}
+
+/*
  * SPT: This value represents the period of the PWM stream in clock periods
  * multiplied by 16 (default increment) or 128 (alternate increment selected in
  * SCHICKEN_1 bit 0). PWM clock is 24 MHz.
@@ -1742,13 +1754,16 @@ void intel_panel_destroy_backlight(struct drm_connector *connector)
 	    intel_dsi_dcs_init_backlight_funcs(connector) == 0)
 		return;
 
-	if (IS_GEN9_LP(dev_priv)) {
+	if (IS_GEN9_LP(dev_priv) || HAS_PCH_CNP(dev_priv)) {
 		panel->backlight.setup = bxt_setup_backlight;
 		panel->backlight.enable = bxt_enable_backlight;
 		panel->backlight.disable = bxt_disable_backlight;
 		panel->backlight.set = bxt_set_backlight;
 		panel->backlight.get = bxt_get_backlight;
-		panel->backlight.hz_to_pwm = bxt_hz_to_pwm;
+		if (IS_GEN9_LP(dev_priv))
+			panel->backlight.hz_to_pwm = bxt_hz_to_pwm;
+		else
+			panel->backlight.hz_to_pwm = cnp_hz_to_pwm;
 	} else if (HAS_PCH_LPT(dev_priv) || HAS_PCH_SPT(dev_priv) ||
 		   HAS_PCH_KBP(dev_priv)) {
 		panel->backlight.setup = lpt_setup_backlight;
-- 
1.9.1

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Re: [PATCH 04/67] drm/i915/cnp: Add Backlight support to CNP PCH.

[Ville Syrjälä]

On Thu, Apr 06, 2017 at 12:15:00PM -0700, Rodrigo Vivi wrote:
> Backlight support on Cannonpoint is a lot
> likely Broxton, but with only one controller (0).

This being the PCH backlight obviously. I guess we still don't have any
use for the CPU backlight?

Oh, since the utility pin is on the CPU I think we should perhaps add
HAS_PCH_SPLIT checks around the useage of the utility pin in the BXT
backlight functions, or some comments. Or perhaps even split out CNP+
vs. BXT entirely? Otherwise I think people might get confused by the
utility pin references.

> 
> Also other main changes/differences:
> 
> - PWM clock frequency = Raw clock frequency = 19.2 MHz or
>   24 MHz.  Value is found in SFUSE_STRAP.
> - PWM increment = 1
> 
> v2: Reuse BXT functions with controller 0 instead of
>     redefining it. (Jani).
>     Use dev_priv->rawclk_freq instead of getting the value
>     from SFUSE_STRAP.
> v3: Avoid setup backligh controller along with hooks and
>     fully reuse hooks setup as suggested by Jani.
> v4: Clean up commit message.
> v5: Implement per PCH instead per platform.
> 
> Cc: Jani Nikula <jani.nikula@intel.com>
> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
> ---
>  drivers/gpu/drm/i915/intel_panel.c | 19 +++++++++++++++++--
>  1 file changed, 17 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_panel.c b/drivers/gpu/drm/i915/intel_panel.c
> index cb50c52..1978bec 100644
> --- a/drivers/gpu/drm/i915/intel_panel.c
> +++ b/drivers/gpu/drm/i915/intel_panel.c
> @@ -1247,6 +1247,18 @@ static u32 bxt_hz_to_pwm(struct intel_connector *connector, u32 pwm_freq_hz)
>  }
>  
>  /*
> + * CNP: PWM clock frequency is 19.2 MHz or 24 MHz.
> + *      Value is found in SFUSE_STRAP.
> + *      PWM increment = 1
> + */
> +static u32 cnp_hz_to_pwm(struct intel_connector *connector, u32 pwm_freq_hz)
> +{
> +	struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
> +
> +	return DIV_ROUND_CLOSEST(KHz(dev_priv->rawclk_freq), pwm_freq_hz);
> +}
> +
> +/*
>   * SPT: This value represents the period of the PWM stream in clock periods
>   * multiplied by 16 (default increment) or 128 (alternate increment selected in
>   * SCHICKEN_1 bit 0). PWM clock is 24 MHz.
> @@ -1742,13 +1754,16 @@ void intel_panel_destroy_backlight(struct drm_connector *connector)
>  	    intel_dsi_dcs_init_backlight_funcs(connector) == 0)
>  		return;
>  
> -	if (IS_GEN9_LP(dev_priv)) {
> +	if (IS_GEN9_LP(dev_priv) || HAS_PCH_CNP(dev_priv)) {
>  		panel->backlight.setup = bxt_setup_backlight;
>  		panel->backlight.enable = bxt_enable_backlight;
>  		panel->backlight.disable = bxt_disable_backlight;
>  		panel->backlight.set = bxt_set_backlight;
>  		panel->backlight.get = bxt_get_backlight;
> -		panel->backlight.hz_to_pwm = bxt_hz_to_pwm;
> +		if (IS_GEN9_LP(dev_priv))
> +			panel->backlight.hz_to_pwm = bxt_hz_to_pwm;
> +		else
> +			panel->backlight.hz_to_pwm = cnp_hz_to_pwm;
>  	} else if (HAS_PCH_LPT(dev_priv) || HAS_PCH_SPT(dev_priv) ||
>  		   HAS_PCH_KBP(dev_priv)) {
>  		panel->backlight.setup = lpt_setup_backlight;
> -- 
> 1.9.1
> 
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
Ville Syrjälä
Intel OTC
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Re: [PATCH 04/67] drm/i915/cnp: Add Backlight support to CNP PCH.

[Jani Nikula]

On Fri, 07 Apr 2017, Ville Syrjälä <ville.syrjala@linux.intel.com> wrote:
> On Thu, Apr 06, 2017 at 12:15:00PM -0700, Rodrigo Vivi wrote:
>> Backlight support on Cannonpoint is a lot
>> likely Broxton, but with only one controller (0).
>
> This being the PCH backlight obviously. I guess we still don't have any
> use for the CPU backlight?
>
> Oh, since the utility pin is on the CPU I think we should perhaps add
> HAS_PCH_SPLIT checks around the useage of the utility pin in the BXT
> backlight functions, or some comments. Or perhaps even split out CNP+
> vs. BXT entirely? Otherwise I think people might get confused by the
> utility pin references.

Please split out. This is what I've been doing and promoting in
intel_panel.c.

BR,
Jani.

>
>> 
>> Also other main changes/differences:
>> 
>> - PWM clock frequency = Raw clock frequency = 19.2 MHz or
>>   24 MHz.  Value is found in SFUSE_STRAP.
>> - PWM increment = 1
>> 
>> v2: Reuse BXT functions with controller 0 instead of
>>     redefining it. (Jani).
>>     Use dev_priv->rawclk_freq instead of getting the value
>>     from SFUSE_STRAP.
>> v3: Avoid setup backligh controller along with hooks and
>>     fully reuse hooks setup as suggested by Jani.
>> v4: Clean up commit message.
>> v5: Implement per PCH instead per platform.
>> 
>> Cc: Jani Nikula <jani.nikula@intel.com>
>> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
>> ---
>>  drivers/gpu/drm/i915/intel_panel.c | 19 +++++++++++++++++--
>>  1 file changed, 17 insertions(+), 2 deletions(-)
>> 
>> diff --git a/drivers/gpu/drm/i915/intel_panel.c b/drivers/gpu/drm/i915/intel_panel.c
>> index cb50c52..1978bec 100644
>> --- a/drivers/gpu/drm/i915/intel_panel.c
>> +++ b/drivers/gpu/drm/i915/intel_panel.c
>> @@ -1247,6 +1247,18 @@ static u32 bxt_hz_to_pwm(struct intel_connector *connector, u32 pwm_freq_hz)
>>  }
>>  
>>  /*
>> + * CNP: PWM clock frequency is 19.2 MHz or 24 MHz.
>> + *      Value is found in SFUSE_STRAP.
>> + *      PWM increment = 1
>> + */
>> +static u32 cnp_hz_to_pwm(struct intel_connector *connector, u32 pwm_freq_hz)
>> +{
>> +	struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
>> +
>> +	return DIV_ROUND_CLOSEST(KHz(dev_priv->rawclk_freq), pwm_freq_hz);
>> +}
>> +
>> +/*
>>   * SPT: This value represents the period of the PWM stream in clock periods
>>   * multiplied by 16 (default increment) or 128 (alternate increment selected in
>>   * SCHICKEN_1 bit 0). PWM clock is 24 MHz.
>> @@ -1742,13 +1754,16 @@ void intel_panel_destroy_backlight(struct drm_connector *connector)
>>  	    intel_dsi_dcs_init_backlight_funcs(connector) == 0)
>>  		return;
>>  
>> -	if (IS_GEN9_LP(dev_priv)) {
>> +	if (IS_GEN9_LP(dev_priv) || HAS_PCH_CNP(dev_priv)) {
>>  		panel->backlight.setup = bxt_setup_backlight;
>>  		panel->backlight.enable = bxt_enable_backlight;
>>  		panel->backlight.disable = bxt_disable_backlight;
>>  		panel->backlight.set = bxt_set_backlight;
>>  		panel->backlight.get = bxt_get_backlight;
>> -		panel->backlight.hz_to_pwm = bxt_hz_to_pwm;
>> +		if (IS_GEN9_LP(dev_priv))
>> +			panel->backlight.hz_to_pwm = bxt_hz_to_pwm;
>> +		else
>> +			panel->backlight.hz_to_pwm = cnp_hz_to_pwm;
>>  	} else if (HAS_PCH_LPT(dev_priv) || HAS_PCH_SPT(dev_priv) ||
>>  		   HAS_PCH_KBP(dev_priv)) {
>>  		panel->backlight.setup = lpt_setup_backlight;
>> -- 
>> 1.9.1
>> 
>> _______________________________________________
>> Intel-gfx mailing list
>> Intel-gfx@lists.freedesktop.org
>> https://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
Jani Nikula, Intel Open Source Technology Center
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[PATCH 05/67] drm/i915/cnp: add CNP gmbus support

[Rodrigo Vivi]

On CNP PCH based platforms the gmbus is on the south display that
is on PCH. The existing implementation for previous platforms
already covers the need for CNP expect for the pin pair configuration
that follows similar definitions that we had on BXT.

v2: Don't drop "_BXT" as the indicator of the first platform
    supporting this pin numbers. Suggested by Daniel.
v3: Add missing else and fix register table since CNP GPIO_CTL
    starts on 0xC5014.
v4: Fix pin number and map according to the current available VBT.
    Re-add pin 4 for port D. Lost during some rebase.

Cc: Daniel Vetter <daniel.vetter@intel.com>
Cc: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h   |  3 ++-
 drivers/gpu/drm/i915/intel_hdmi.c |  8 +++++---
 drivers/gpu/drm/i915/intel_i2c.c  | 20 ++++++++++++++++++--
 3 files changed, 25 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 6826547..efbbeb8 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -2618,9 +2618,10 @@ enum skl_disp_power_wells {
 #define   GMBUS_PIN_DPB		5 /* SDVO, HDMIB */
 #define   GMBUS_PIN_DPD		6 /* HDMID */
 #define   GMBUS_PIN_RESERVED	7 /* 7 reserved */
-#define   GMBUS_PIN_1_BXT	1
+#define   GMBUS_PIN_1_BXT	1 /* BXT+ (atom) and CNP+ (big core) */
 #define   GMBUS_PIN_2_BXT	2
 #define   GMBUS_PIN_3_BXT	3
+#define   GMBUS_PIN_4_CNP	4
 #define   GMBUS_NUM_PINS	7 /* including 0 */
 #define GMBUS1			_MMIO(dev_priv->gpio_mmio_base + 0x5104) /* command/status */
 #define   GMBUS_SW_CLR_INT	(1<<31)
diff --git a/drivers/gpu/drm/i915/intel_hdmi.c b/drivers/gpu/drm/i915/intel_hdmi.c
index 6efc3cb..f8c40ae 100644
--- a/drivers/gpu/drm/i915/intel_hdmi.c
+++ b/drivers/gpu/drm/i915/intel_hdmi.c
@@ -1892,19 +1892,21 @@ static u8 intel_hdmi_ddc_pin(struct drm_i915_private *dev_priv,
 
 	switch (port) {
 	case PORT_B:
-		if (IS_GEN9_LP(dev_priv))
+		if (IS_GEN9_LP(dev_priv) || HAS_PCH_CNP(dev_priv))
 			ddc_pin = GMBUS_PIN_1_BXT;
 		else
 			ddc_pin = GMBUS_PIN_DPB;
 		break;
 	case PORT_C:
-		if (IS_GEN9_LP(dev_priv))
+		if (IS_GEN9_LP(dev_priv) || HAS_PCH_CNP(dev_priv))
 			ddc_pin = GMBUS_PIN_2_BXT;
 		else
 			ddc_pin = GMBUS_PIN_DPC;
 		break;
 	case PORT_D:
-		if (IS_CHERRYVIEW(dev_priv))
+		if (HAS_PCH_CNP(dev_priv))
+			ddc_pin = GMBUS_PIN_4_CNP;
+		else if (IS_CHERRYVIEW(dev_priv))
 			ddc_pin = GMBUS_PIN_DPD_CHV;
 		else
 			ddc_pin = GMBUS_PIN_DPD;
diff --git a/drivers/gpu/drm/i915/intel_i2c.c b/drivers/gpu/drm/i915/intel_i2c.c
index b6401e8..d7eabab 100644
--- a/drivers/gpu/drm/i915/intel_i2c.c
+++ b/drivers/gpu/drm/i915/intel_i2c.c
@@ -68,11 +68,25 @@ struct gmbus_pin {
 	[GMBUS_PIN_3_BXT] = { "misc", GPIOD },
 };
 
+/*
+ * FIXME: Spec maps 3-misc-0xc541c and 4-portd-0xc5420.
+ * However, current available pre-prod VBT maps:
+ * portD to pin 3 using 0xc5420.
+*/
+static const struct gmbus_pin gmbus_pins_cnp[] = {
+	[GMBUS_PIN_1_BXT] = { "dpb", GPIOB },
+	[GMBUS_PIN_2_BXT] = { "dpc", GPIOC },
+	[GMBUS_PIN_3_BXT] = { "misc", GPIOE },
+	[GMBUS_PIN_4_CNP] = { "dpd", GPIOD },
+};
+
 /* pin is expected to be valid */
 static const struct gmbus_pin *get_gmbus_pin(struct drm_i915_private *dev_priv,
 					     unsigned int pin)
 {
-	if (IS_GEN9_LP(dev_priv))
+	if (HAS_PCH_CNP(dev_priv))
+		return &gmbus_pins_cnp[pin];
+	else if (IS_GEN9_LP(dev_priv))
 		return &gmbus_pins_bxt[pin];
 	else if (IS_GEN9_BC(dev_priv))
 		return &gmbus_pins_skl[pin];
@@ -87,7 +101,9 @@ bool intel_gmbus_is_valid_pin(struct drm_i915_private *dev_priv,
 {
 	unsigned int size;
 
-	if (IS_GEN9_LP(dev_priv))
+	if (HAS_PCH_CNP(dev_priv))
+		size = ARRAY_SIZE(gmbus_pins_cnp);
+	else if (IS_GEN9_LP(dev_priv))
 		size = ARRAY_SIZE(gmbus_pins_bxt);
 	else if (IS_GEN9_BC(dev_priv))
 		size = ARRAY_SIZE(gmbus_pins_skl);
-- 
1.9.1

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[PATCH] drm/i915/cnp: add CNP gmbus support

[Rodrigo Vivi]

On CNP PCH based platforms the gmbus is on the south display that
is on PCH. The existing implementation for previous platforms
already covers the need for CNP expect for the pin pair configuration
that follows similar definitions that we had on BXT.

v2: Don't drop "_BXT" as the indicator of the first platform
    supporting this pin numbers. Suggested by Daniel.
v3: Add missing else and fix register table since CNP GPIO_CTL
    starts on 0xC5014.
v4: Fix pin number and map according to the current available VBT.
    Re-add pin 4 for port D. Lost during some rebase.
v5: Use table as spec. If VBT is wrong it should be ignored.

Cc: Daniel Vetter <daniel.vetter@intel.com>
Cc: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h   |  3 ++-
 drivers/gpu/drm/i915/intel_hdmi.c |  8 +++++---
 drivers/gpu/drm/i915/intel_i2c.c  | 15 +++++++++++++--
 3 files changed, 20 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 6826547..efbbeb8 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -2618,9 +2618,10 @@ enum skl_disp_power_wells {
 #define   GMBUS_PIN_DPB		5 /* SDVO, HDMIB */
 #define   GMBUS_PIN_DPD		6 /* HDMID */
 #define   GMBUS_PIN_RESERVED	7 /* 7 reserved */
-#define   GMBUS_PIN_1_BXT	1
+#define   GMBUS_PIN_1_BXT	1 /* BXT+ (atom) and CNP+ (big core) */
 #define   GMBUS_PIN_2_BXT	2
 #define   GMBUS_PIN_3_BXT	3
+#define   GMBUS_PIN_4_CNP	4
 #define   GMBUS_NUM_PINS	7 /* including 0 */
 #define GMBUS1			_MMIO(dev_priv->gpio_mmio_base + 0x5104) /* command/status */
 #define   GMBUS_SW_CLR_INT	(1<<31)
diff --git a/drivers/gpu/drm/i915/intel_hdmi.c b/drivers/gpu/drm/i915/intel_hdmi.c
index 6efc3cb..f8c40ae 100644
--- a/drivers/gpu/drm/i915/intel_hdmi.c
+++ b/drivers/gpu/drm/i915/intel_hdmi.c
@@ -1892,19 +1892,21 @@ static u8 intel_hdmi_ddc_pin(struct drm_i915_private *dev_priv,
 
 	switch (port) {
 	case PORT_B:
-		if (IS_GEN9_LP(dev_priv))
+		if (IS_GEN9_LP(dev_priv) || HAS_PCH_CNP(dev_priv))
 			ddc_pin = GMBUS_PIN_1_BXT;
 		else
 			ddc_pin = GMBUS_PIN_DPB;
 		break;
 	case PORT_C:
-		if (IS_GEN9_LP(dev_priv))
+		if (IS_GEN9_LP(dev_priv) || HAS_PCH_CNP(dev_priv))
 			ddc_pin = GMBUS_PIN_2_BXT;
 		else
 			ddc_pin = GMBUS_PIN_DPC;
 		break;
 	case PORT_D:
-		if (IS_CHERRYVIEW(dev_priv))
+		if (HAS_PCH_CNP(dev_priv))
+			ddc_pin = GMBUS_PIN_4_CNP;
+		else if (IS_CHERRYVIEW(dev_priv))
 			ddc_pin = GMBUS_PIN_DPD_CHV;
 		else
 			ddc_pin = GMBUS_PIN_DPD;
diff --git a/drivers/gpu/drm/i915/intel_i2c.c b/drivers/gpu/drm/i915/intel_i2c.c
index b6401e8..3c9e00d 100644
--- a/drivers/gpu/drm/i915/intel_i2c.c
+++ b/drivers/gpu/drm/i915/intel_i2c.c
@@ -68,11 +68,20 @@ struct gmbus_pin {
 	[GMBUS_PIN_3_BXT] = { "misc", GPIOD },
 };
 
+static const struct gmbus_pin gmbus_pins_cnp[] = {
+	[GMBUS_PIN_1_BXT] = { "dpb", GPIOB },
+	[GMBUS_PIN_2_BXT] = { "dpc", GPIOC },
+	[GMBUS_PIN_3_BXT] = { "misc", GPIOD },
+	[GMBUS_PIN_4_CNP] = { "dpd", GPIOE },
+};
+
 /* pin is expected to be valid */
 static const struct gmbus_pin *get_gmbus_pin(struct drm_i915_private *dev_priv,
 					     unsigned int pin)
 {
-	if (IS_GEN9_LP(dev_priv))
+	if (HAS_PCH_CNP(dev_priv))
+		return &gmbus_pins_cnp[pin];
+	else if (IS_GEN9_LP(dev_priv))
 		return &gmbus_pins_bxt[pin];
 	else if (IS_GEN9_BC(dev_priv))
 		return &gmbus_pins_skl[pin];
@@ -87,7 +96,9 @@ bool intel_gmbus_is_valid_pin(struct drm_i915_private *dev_priv,
 {
 	unsigned int size;
 
-	if (IS_GEN9_LP(dev_priv))
+	if (HAS_PCH_CNP(dev_priv))
+		size = ARRAY_SIZE(gmbus_pins_cnp);
+	else if (IS_GEN9_LP(dev_priv))
 		size = ARRAY_SIZE(gmbus_pins_bxt);
 	else if (IS_GEN9_BC(dev_priv))
 		size = ARRAY_SIZE(gmbus_pins_skl);
-- 
1.9.1

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Re: [PATCH] drm/i915/cnp: add CNP gmbus support

[kbuild test robot]

[-- Attachment #1: Type: text/plain, Size: 3300 bytes --]

Hi Rodrigo,

[auto build test ERROR on drm-intel/for-linux-next]
[also build test ERROR on v4.11-rc5]
[if your patch is applied to the wrong git tree, please drop us a note to help improve the system]

url:    https://github.com/0day-ci/linux/commits/Rodrigo-Vivi/drm-i915-cnp-add-CNP-gmbus-support/20170408-020453
base:   git://anongit.freedesktop.org/drm-intel for-linux-next
config: i386-randconfig-x012-201714 (attached as .config)
compiler: gcc-6 (Debian 6.2.0-3) 6.2.0 20160901
reproduce:
        # save the attached .config to linux build tree
        make ARCH=i386 

All error/warnings (new ones prefixed by >>):

   In file included from include/uapi/linux/stddef.h:1:0,
                    from include/linux/stddef.h:4,
                    from include/uapi/linux/posix_types.h:4,
                    from include/uapi/linux/types.h:13,
                    from include/linux/types.h:5,
                    from include/linux/mod_devicetable.h:11,
                    from include/linux/i2c.h:29,
                    from drivers/gpu/drm/i915/intel_hdmi.c:29:
   drivers/gpu/drm/i915/intel_hdmi.c: In function 'intel_hdmi_ddc_pin':
>> drivers/gpu/drm/i915/intel_hdmi.c:1895:31: error: implicit declaration of function 'HAS_PCH_CNP' [-Werror=implicit-function-declaration]
      if (IS_GEN9_LP(dev_priv) || HAS_PCH_CNP(dev_priv))
                                  ^
   include/linux/compiler.h:160:30: note: in definition of macro '__trace_if'
     if (__builtin_constant_p(!!(cond)) ? !!(cond) :   \
                                 ^~~~
>> drivers/gpu/drm/i915/intel_hdmi.c:1895:3: note: in expansion of macro 'if'
      if (IS_GEN9_LP(dev_priv) || HAS_PCH_CNP(dev_priv))
      ^~
   cc1: some warnings being treated as errors
--
   In file included from include/uapi/linux/stddef.h:1:0,
                    from include/linux/stddef.h:4,
                    from include/uapi/linux/posix_types.h:4,
                    from include/uapi/linux/types.h:13,
                    from include/linux/types.h:5,
                    from include/linux/mod_devicetable.h:11,
                    from include/linux/i2c.h:29,
                    from drivers/gpu/drm/i915/intel_i2c.c:29:
   drivers/gpu/drm/i915/intel_i2c.c: In function 'get_gmbus_pin':
>> drivers/gpu/drm/i915/intel_i2c.c:82:6: error: implicit declaration of function 'HAS_PCH_CNP' [-Werror=implicit-function-declaration]
     if (HAS_PCH_CNP(dev_priv))
         ^
   include/linux/compiler.h:160:30: note: in definition of macro '__trace_if'
     if (__builtin_constant_p(!!(cond)) ? !!(cond) :   \
                                 ^~~~
>> drivers/gpu/drm/i915/intel_i2c.c:82:2: note: in expansion of macro 'if'
     if (HAS_PCH_CNP(dev_priv))
     ^~
   cc1: some warnings being treated as errors

vim +/HAS_PCH_CNP +1895 drivers/gpu/drm/i915/intel_hdmi.c

  1889				      info->alternate_ddc_pin, port_name(port));
  1890			return info->alternate_ddc_pin;
  1891		}
  1892	
  1893		switch (port) {
  1894		case PORT_B:
> 1895			if (IS_GEN9_LP(dev_priv) || HAS_PCH_CNP(dev_priv))
  1896				ddc_pin = GMBUS_PIN_1_BXT;
  1897			else
  1898				ddc_pin = GMBUS_PIN_DPB;

---
0-DAY kernel test infrastructure                Open Source Technology Center
https://lists.01.org/pipermail/kbuild-all                   Intel Corporation

[-- Attachment #2: .config.gz --]
[-- Type: application/gzip, Size: 24975 bytes --]

[-- Attachment #3: Type: text/plain, Size: 160 bytes --]

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Re: [PATCH 05/67] drm/i915/cnp: add CNP gmbus support

[Srivatsa, Anusha]

>-----Original Message-----
>From: Intel-gfx [mailto:intel-gfx-bounces@lists.freedesktop.org] On Behalf Of
>Rodrigo Vivi
>Sent: Thursday, April 6, 2017 12:15 PM
>To: intel-gfx@lists.freedesktop.org
>Cc: Nikula, Jani <jani.nikula@intel.com>; Vetter, Daniel
><daniel.vetter@intel.com>; Vivi, Rodrigo <rodrigo.vivi@intel.com>
>Subject: [Intel-gfx] [PATCH 05/67] drm/i915/cnp: add CNP gmbus support
>
>On CNP PCH based platforms the gmbus is on the south display that is on PCH.
>The existing implementation for previous platforms already covers the need for
>CNP expect for the pin pair configuration that follows similar definitions that we
>had on BXT.
>
>v2: Don't drop "_BXT" as the indicator of the first platform
>    supporting this pin numbers. Suggested by Daniel.
>v3: Add missing else and fix register table since CNP GPIO_CTL
>    starts on 0xC5014.
>v4: Fix pin number and map according to the current available VBT.
>    Re-add pin 4 for port D. Lost during some rebase.
>
>Cc: Daniel Vetter <daniel.vetter@intel.com>
>Cc: Jani Nikula <jani.nikula@intel.com>
>Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Reviewed-by: Anusha Srivatsa <anusha.srivatsa@intel.com>

> drivers/gpu/drm/i915/i915_reg.h   |  3 ++-
> drivers/gpu/drm/i915/intel_hdmi.c |  8 +++++---
>drivers/gpu/drm/i915/intel_i2c.c  | 20 ++++++++++++++++++--
> 3 files changed, 25 insertions(+), 6 deletions(-)
>
>diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
>index 6826547..efbbeb8 100644
>--- a/drivers/gpu/drm/i915/i915_reg.h
>+++ b/drivers/gpu/drm/i915/i915_reg.h
>@@ -2618,9 +2618,10 @@ enum skl_disp_power_wells {
> #define   GMBUS_PIN_DPB		5 /* SDVO, HDMIB */
> #define   GMBUS_PIN_DPD		6 /* HDMID */
> #define   GMBUS_PIN_RESERVED	7 /* 7 reserved */
>-#define   GMBUS_PIN_1_BXT	1
>+#define   GMBUS_PIN_1_BXT	1 /* BXT+ (atom) and CNP+ (big core) */
> #define   GMBUS_PIN_2_BXT	2
> #define   GMBUS_PIN_3_BXT	3
>+#define   GMBUS_PIN_4_CNP	4
> #define   GMBUS_NUM_PINS	7 /* including 0 */
> #define GMBUS1			_MMIO(dev_priv->gpio_mmio_base +
>0x5104) /* command/status */
> #define   GMBUS_SW_CLR_INT	(1<<31)
>diff --git a/drivers/gpu/drm/i915/intel_hdmi.c
>b/drivers/gpu/drm/i915/intel_hdmi.c
>index 6efc3cb..f8c40ae 100644
>--- a/drivers/gpu/drm/i915/intel_hdmi.c
>+++ b/drivers/gpu/drm/i915/intel_hdmi.c
>@@ -1892,19 +1892,21 @@ static u8 intel_hdmi_ddc_pin(struct
>drm_i915_private *dev_priv,
>
> 	switch (port) {
> 	case PORT_B:
>-		if (IS_GEN9_LP(dev_priv))
>+		if (IS_GEN9_LP(dev_priv) || HAS_PCH_CNP(dev_priv))
> 			ddc_pin = GMBUS_PIN_1_BXT;
> 		else
> 			ddc_pin = GMBUS_PIN_DPB;
> 		break;
> 	case PORT_C:
>-		if (IS_GEN9_LP(dev_priv))
>+		if (IS_GEN9_LP(dev_priv) || HAS_PCH_CNP(dev_priv))
> 			ddc_pin = GMBUS_PIN_2_BXT;
> 		else
> 			ddc_pin = GMBUS_PIN_DPC;
> 		break;
> 	case PORT_D:
>-		if (IS_CHERRYVIEW(dev_priv))
>+		if (HAS_PCH_CNP(dev_priv))
>+			ddc_pin = GMBUS_PIN_4_CNP;
>+		else if (IS_CHERRYVIEW(dev_priv))
> 			ddc_pin = GMBUS_PIN_DPD_CHV;
> 		else
> 			ddc_pin = GMBUS_PIN_DPD;
>diff --git a/drivers/gpu/drm/i915/intel_i2c.c b/drivers/gpu/drm/i915/intel_i2c.c
>index b6401e8..d7eabab 100644
>--- a/drivers/gpu/drm/i915/intel_i2c.c
>+++ b/drivers/gpu/drm/i915/intel_i2c.c
>@@ -68,11 +68,25 @@ struct gmbus_pin {
> 	[GMBUS_PIN_3_BXT] = { "misc", GPIOD },  };
>
>+/*
>+ * FIXME: Spec maps 3-misc-0xc541c and 4-portd-0xc5420.
>+ * However, current available pre-prod VBT maps:
>+ * portD to pin 3 using 0xc5420.
>+*/
>+static const struct gmbus_pin gmbus_pins_cnp[] = {
>+	[GMBUS_PIN_1_BXT] = { "dpb", GPIOB },
>+	[GMBUS_PIN_2_BXT] = { "dpc", GPIOC },
>+	[GMBUS_PIN_3_BXT] = { "misc", GPIOE },
>+	[GMBUS_PIN_4_CNP] = { "dpd", GPIOD },
>+};
>+
> /* pin is expected to be valid */
> static const struct gmbus_pin *get_gmbus_pin(struct drm_i915_private
>*dev_priv,
> 					     unsigned int pin)
> {
>-	if (IS_GEN9_LP(dev_priv))
>+	if (HAS_PCH_CNP(dev_priv))
>+		return &gmbus_pins_cnp[pin];
>+	else if (IS_GEN9_LP(dev_priv))
> 		return &gmbus_pins_bxt[pin];
> 	else if (IS_GEN9_BC(dev_priv))
> 		return &gmbus_pins_skl[pin];
>@@ -87,7 +101,9 @@ bool intel_gmbus_is_valid_pin(struct drm_i915_private
>*dev_priv,  {
> 	unsigned int size;
>
>-	if (IS_GEN9_LP(dev_priv))
>+	if (HAS_PCH_CNP(dev_priv))
>+		size = ARRAY_SIZE(gmbus_pins_cnp);
>+	else if (IS_GEN9_LP(dev_priv))
> 		size = ARRAY_SIZE(gmbus_pins_bxt);
> 	else if (IS_GEN9_BC(dev_priv))
> 		size = ARRAY_SIZE(gmbus_pins_skl);
>--
>1.9.1
>
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[PATCH 06/67] drm/i915/cnp: Panel Power sequence changes for CNP PCH.

[Rodrigo Vivi]

As for BXT, PP_DIVISOR was removed from CNP PCH and power
cycle delay has been moved to PP_CONTROL.

Cc: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
---
 drivers/gpu/drm/i915/intel_dp.c | 10 +++++-----
 1 file changed, 5 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index b38cba7..da111cb 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -788,7 +788,7 @@ static void intel_pps_get_registers(struct drm_i915_private *dev_priv,
 	regs->pp_stat = PP_STATUS(pps_idx);
 	regs->pp_on = PP_ON_DELAYS(pps_idx);
 	regs->pp_off = PP_OFF_DELAYS(pps_idx);
-	if (!IS_GEN9_LP(dev_priv))
+	if (!IS_GEN9_LP(dev_priv) && !HAS_PCH_CNP(dev_priv))
 		regs->pp_div = PP_DIVISOR(pps_idx);
 }
 
@@ -5198,7 +5198,7 @@ static void intel_dp_init_panel_power_timestamps(struct intel_dp *intel_dp)
 
 	pp_on = I915_READ(regs.pp_on);
 	pp_off = I915_READ(regs.pp_off);
-	if (!IS_GEN9_LP(dev_priv)) {
+	if (!IS_GEN9_LP(dev_priv) && !HAS_PCH_CNP(dev_priv)) {
 		I915_WRITE(regs.pp_ctrl, pp_ctl);
 		pp_div = I915_READ(regs.pp_div);
 	}
@@ -5216,7 +5216,7 @@ static void intel_dp_init_panel_power_timestamps(struct intel_dp *intel_dp)
 	seq->t10 = (pp_off & PANEL_POWER_DOWN_DELAY_MASK) >>
 		   PANEL_POWER_DOWN_DELAY_SHIFT;
 
-	if (IS_GEN9_LP(dev_priv)) {
+	if (IS_GEN9_LP(dev_priv) || HAS_PCH_CNP(dev_priv)) {
 		u16 tmp = (pp_ctl & BXT_POWER_CYCLE_DELAY_MASK) >>
 			BXT_POWER_CYCLE_DELAY_SHIFT;
 		if (tmp > 0)
@@ -5373,7 +5373,7 @@ static void intel_dp_init_panel_power_timestamps(struct intel_dp *intel_dp)
 		 (seq->t10 << PANEL_POWER_DOWN_DELAY_SHIFT);
 	/* Compute the divisor for the pp clock, simply match the Bspec
 	 * formula. */
-	if (IS_GEN9_LP(dev_priv)) {
+	if (IS_GEN9_LP(dev_priv) || HAS_PCH_CNP(dev_priv)) {
 		pp_div = I915_READ(regs.pp_ctrl);
 		pp_div &= ~BXT_POWER_CYCLE_DELAY_MASK;
 		pp_div |= (DIV_ROUND_UP((seq->t11_t12 + 1), 1000)
@@ -5407,7 +5407,7 @@ static void intel_dp_init_panel_power_timestamps(struct intel_dp *intel_dp)
 	DRM_DEBUG_KMS("panel power sequencer register settings: PP_ON %#x, PP_OFF %#x, PP_DIV %#x\n",
 		      I915_READ(regs.pp_on),
 		      I915_READ(regs.pp_off),
-		      IS_GEN9_LP(dev_priv) ?
+		      (IS_GEN9_LP(dev_priv) || HAS_PCH_CNP(dev_priv)) ?
 		      (I915_READ(regs.pp_ctrl) & BXT_POWER_CYCLE_DELAY_MASK) :
 		      I915_READ(regs.pp_div));
 }
-- 
1.9.1

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Re: [PATCH 06/67] drm/i915/cnp: Panel Power sequence changes for CNP PCH.

[Ville Syrjälä]

On Thu, Apr 06, 2017 at 12:15:02PM -0700, Rodrigo Vivi wrote:
> As for BXT, PP_DIVISOR was removed from CNP PCH and power
> cycle delay has been moved to PP_CONTROL.
> 
> Cc: Jani Nikula <jani.nikula@intel.com>
> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
> ---
>  drivers/gpu/drm/i915/intel_dp.c | 10 +++++-----
>  1 file changed, 5 insertions(+), 5 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> index b38cba7..da111cb 100644
> --- a/drivers/gpu/drm/i915/intel_dp.c
> +++ b/drivers/gpu/drm/i915/intel_dp.c
> @@ -788,7 +788,7 @@ static void intel_pps_get_registers(struct drm_i915_private *dev_priv,
>  	regs->pp_stat = PP_STATUS(pps_idx);
>  	regs->pp_on = PP_ON_DELAYS(pps_idx);
>  	regs->pp_off = PP_OFF_DELAYS(pps_idx);
> -	if (!IS_GEN9_LP(dev_priv))
> +	if (!IS_GEN9_LP(dev_priv) && !HAS_PCH_CNP(dev_priv))

GEN >= 10 all over might be more future proof.

>  		regs->pp_div = PP_DIVISOR(pps_idx);
>  }
>  
> @@ -5198,7 +5198,7 @@ static void intel_dp_init_panel_power_timestamps(struct intel_dp *intel_dp)
>  
>  	pp_on = I915_READ(regs.pp_on);
>  	pp_off = I915_READ(regs.pp_off);
> -	if (!IS_GEN9_LP(dev_priv)) {
> +	if (!IS_GEN9_LP(dev_priv) && !HAS_PCH_CNP(dev_priv)) {
>  		I915_WRITE(regs.pp_ctrl, pp_ctl);

Slightly unrelated, but I wonder what this write is doing in the BXT+
branch. I'm thinking it should either be done unconditionally, or we
should just nuke it since I think Imre's early pps unlock thing should
have already done it if needed, I think.

>  		pp_div = I915_READ(regs.pp_div);
>  	}
> @@ -5216,7 +5216,7 @@ static void intel_dp_init_panel_power_timestamps(struct intel_dp *intel_dp)
>  	seq->t10 = (pp_off & PANEL_POWER_DOWN_DELAY_MASK) >>
>  		   PANEL_POWER_DOWN_DELAY_SHIFT;
>  
> -	if (IS_GEN9_LP(dev_priv)) {
> +	if (IS_GEN9_LP(dev_priv) || HAS_PCH_CNP(dev_priv)) {
>  		u16 tmp = (pp_ctl & BXT_POWER_CYCLE_DELAY_MASK) >>
>  			BXT_POWER_CYCLE_DELAY_SHIFT;
>  		if (tmp > 0)
> @@ -5373,7 +5373,7 @@ static void intel_dp_init_panel_power_timestamps(struct intel_dp *intel_dp)
>  		 (seq->t10 << PANEL_POWER_DOWN_DELAY_SHIFT);
>  	/* Compute the divisor for the pp clock, simply match the Bspec
>  	 * formula. */
> -	if (IS_GEN9_LP(dev_priv)) {
> +	if (IS_GEN9_LP(dev_priv) || HAS_PCH_CNP(dev_priv)) {
>  		pp_div = I915_READ(regs.pp_ctrl);
>  		pp_div &= ~BXT_POWER_CYCLE_DELAY_MASK;
>  		pp_div |= (DIV_ROUND_UP((seq->t11_t12 + 1), 1000)
> @@ -5407,7 +5407,7 @@ static void intel_dp_init_panel_power_timestamps(struct intel_dp *intel_dp)
>  	DRM_DEBUG_KMS("panel power sequencer register settings: PP_ON %#x, PP_OFF %#x, PP_DIV %#x\n",
>  		      I915_READ(regs.pp_on),
>  		      I915_READ(regs.pp_off),
> -		      IS_GEN9_LP(dev_priv) ?
> +		      (IS_GEN9_LP(dev_priv) || HAS_PCH_CNP(dev_priv)) ?
>  		      (I915_READ(regs.pp_ctrl) & BXT_POWER_CYCLE_DELAY_MASK) :
>  		      I915_READ(regs.pp_div));
>  }
> -- 
> 1.9.1
> 
> _______________________________________________
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> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
Ville Syrjälä
Intel OTC
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Re: [PATCH 06/67] drm/i915/cnp: Panel Power sequence changes for CNP PCH.

[Vivi, Rodrigo]

On Fri, 2017-04-07 at 17:48 +0300, Ville Syrjälä wrote:
> On Thu, Apr 06, 2017 at 12:15:02PM -0700, Rodrigo Vivi wrote:
> > As for BXT, PP_DIVISOR was removed from CNP PCH and power
> > cycle delay has been moved to PP_CONTROL.
> > 
> > Cc: Jani Nikula <jani.nikula@intel.com>
> > Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
> > ---
> >  drivers/gpu/drm/i915/intel_dp.c | 10 +++++-----
> >  1 file changed, 5 insertions(+), 5 deletions(-)
> > 
> > diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> > index b38cba7..da111cb 100644
> > --- a/drivers/gpu/drm/i915/intel_dp.c
> > +++ b/drivers/gpu/drm/i915/intel_dp.c
> > @@ -788,7 +788,7 @@ static void intel_pps_get_registers(struct drm_i915_private *dev_priv,
> >  	regs->pp_stat = PP_STATUS(pps_idx);
> >  	regs->pp_on = PP_ON_DELAYS(pps_idx);
> >  	regs->pp_off = PP_OFF_DELAYS(pps_idx);
> > -	if (!IS_GEN9_LP(dev_priv))
> > +	if (!IS_GEN9_LP(dev_priv) && !HAS_PCH_CNP(dev_priv))
> 
> GEN >= 10 all over might be more future proof.

True, but I didn't want to loose the track that this part is on the PCH.
for the core....

Could we let it like this and in the future if we decide that this is
the case we change?!

> 
> >  		regs->pp_div = PP_DIVISOR(pps_idx);
> >  }
> >  
> > @@ -5198,7 +5198,7 @@ static void intel_dp_init_panel_power_timestamps(struct intel_dp *intel_dp)
> >  
> >  	pp_on = I915_READ(regs.pp_on);
> >  	pp_off = I915_READ(regs.pp_off);
> > -	if (!IS_GEN9_LP(dev_priv)) {
> > +	if (!IS_GEN9_LP(dev_priv) && !HAS_PCH_CNP(dev_priv)) {
> >  		I915_WRITE(regs.pp_ctrl, pp_ctl);
> 
> Slightly unrelated, but I wonder what this write is doing in the BXT+
> branch. I'm thinking it should either be done unconditionally, or we
> should just nuke it since I think Imre's early pps unlock thing should
> have already done it if needed, I think.
> 
> >  		pp_div = I915_READ(regs.pp_div);
> >  	}
> > @@ -5216,7 +5216,7 @@ static void intel_dp_init_panel_power_timestamps(struct intel_dp *intel_dp)
> >  	seq->t10 = (pp_off & PANEL_POWER_DOWN_DELAY_MASK) >>
> >  		   PANEL_POWER_DOWN_DELAY_SHIFT;
> >  
> > -	if (IS_GEN9_LP(dev_priv)) {
> > +	if (IS_GEN9_LP(dev_priv) || HAS_PCH_CNP(dev_priv)) {
> >  		u16 tmp = (pp_ctl & BXT_POWER_CYCLE_DELAY_MASK) >>
> >  			BXT_POWER_CYCLE_DELAY_SHIFT;
> >  		if (tmp > 0)
> > @@ -5373,7 +5373,7 @@ static void intel_dp_init_panel_power_timestamps(struct intel_dp *intel_dp)
> >  		 (seq->t10 << PANEL_POWER_DOWN_DELAY_SHIFT);
> >  	/* Compute the divisor for the pp clock, simply match the Bspec
> >  	 * formula. */
> > -	if (IS_GEN9_LP(dev_priv)) {
> > +	if (IS_GEN9_LP(dev_priv) || HAS_PCH_CNP(dev_priv)) {
> >  		pp_div = I915_READ(regs.pp_ctrl);
> >  		pp_div &= ~BXT_POWER_CYCLE_DELAY_MASK;
> >  		pp_div |= (DIV_ROUND_UP((seq->t11_t12 + 1), 1000)
> > @@ -5407,7 +5407,7 @@ static void intel_dp_init_panel_power_timestamps(struct intel_dp *intel_dp)
> >  	DRM_DEBUG_KMS("panel power sequencer register settings: PP_ON %#x, PP_OFF %#x, PP_DIV %#x\n",
> >  		      I915_READ(regs.pp_on),
> >  		      I915_READ(regs.pp_off),
> > -		      IS_GEN9_LP(dev_priv) ?
> > +		      (IS_GEN9_LP(dev_priv) || HAS_PCH_CNP(dev_priv)) ?
> >  		      (I915_READ(regs.pp_ctrl) & BXT_POWER_CYCLE_DELAY_MASK) :
> >  		      I915_READ(regs.pp_div));
> >  }
> > -- 
> > 1.9.1
> > 
> > _______________________________________________
> > Intel-gfx mailing list
> > Intel-gfx@lists.freedesktop.org
> > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
> 

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Re: [PATCH 06/67] drm/i915/cnp: Panel Power sequence changes for CNP PCH.

[Ville Syrjälä]

On Thu, Apr 13, 2017 at 11:48:41PM +0000, Vivi, Rodrigo wrote:
> On Fri, 2017-04-07 at 17:48 +0300, Ville Syrjälä wrote:
> > On Thu, Apr 06, 2017 at 12:15:02PM -0700, Rodrigo Vivi wrote:
> > > As for BXT, PP_DIVISOR was removed from CNP PCH and power
> > > cycle delay has been moved to PP_CONTROL.
> > > 
> > > Cc: Jani Nikula <jani.nikula@intel.com>
> > > Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
> > > ---
> > >  drivers/gpu/drm/i915/intel_dp.c | 10 +++++-----
> > >  1 file changed, 5 insertions(+), 5 deletions(-)
> > > 
> > > diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> > > index b38cba7..da111cb 100644
> > > --- a/drivers/gpu/drm/i915/intel_dp.c
> > > +++ b/drivers/gpu/drm/i915/intel_dp.c
> > > @@ -788,7 +788,7 @@ static void intel_pps_get_registers(struct drm_i915_private *dev_priv,
> > >  	regs->pp_stat = PP_STATUS(pps_idx);
> > >  	regs->pp_on = PP_ON_DELAYS(pps_idx);
> > >  	regs->pp_off = PP_OFF_DELAYS(pps_idx);
> > > -	if (!IS_GEN9_LP(dev_priv))
> > > +	if (!IS_GEN9_LP(dev_priv) && !HAS_PCH_CNP(dev_priv))
> > 
> > GEN >= 10 all over might be more future proof.
> 
> True, but I didn't want to loose the track that this part is on the PCH.
> for the core....
> 
> Could we let it like this and in the future if we decide that this is
> the case we change?!

Sorry, I dropped this discussion through the cracks somehow. IIRC the
patch didn't seem to have any real issues, so I think we can go with
it as is, so

Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

> 
> > 
> > >  		regs->pp_div = PP_DIVISOR(pps_idx);
> > >  }
> > >  
> > > @@ -5198,7 +5198,7 @@ static void intel_dp_init_panel_power_timestamps(struct intel_dp *intel_dp)
> > >  
> > >  	pp_on = I915_READ(regs.pp_on);
> > >  	pp_off = I915_READ(regs.pp_off);
> > > -	if (!IS_GEN9_LP(dev_priv)) {
> > > +	if (!IS_GEN9_LP(dev_priv) && !HAS_PCH_CNP(dev_priv)) {
> > >  		I915_WRITE(regs.pp_ctrl, pp_ctl);
> > 
> > Slightly unrelated, but I wonder what this write is doing in the BXT+
> > branch. I'm thinking it should either be done unconditionally, or we
> > should just nuke it since I think Imre's early pps unlock thing should
> > have already done it if needed, I think.
> > 
> > >  		pp_div = I915_READ(regs.pp_div);
> > >  	}
> > > @@ -5216,7 +5216,7 @@ static void intel_dp_init_panel_power_timestamps(struct intel_dp *intel_dp)
> > >  	seq->t10 = (pp_off & PANEL_POWER_DOWN_DELAY_MASK) >>
> > >  		   PANEL_POWER_DOWN_DELAY_SHIFT;
> > >  
> > > -	if (IS_GEN9_LP(dev_priv)) {
> > > +	if (IS_GEN9_LP(dev_priv) || HAS_PCH_CNP(dev_priv)) {
> > >  		u16 tmp = (pp_ctl & BXT_POWER_CYCLE_DELAY_MASK) >>
> > >  			BXT_POWER_CYCLE_DELAY_SHIFT;
> > >  		if (tmp > 0)
> > > @@ -5373,7 +5373,7 @@ static void intel_dp_init_panel_power_timestamps(struct intel_dp *intel_dp)
> > >  		 (seq->t10 << PANEL_POWER_DOWN_DELAY_SHIFT);
> > >  	/* Compute the divisor for the pp clock, simply match the Bspec
> > >  	 * formula. */
> > > -	if (IS_GEN9_LP(dev_priv)) {
> > > +	if (IS_GEN9_LP(dev_priv) || HAS_PCH_CNP(dev_priv)) {
> > >  		pp_div = I915_READ(regs.pp_ctrl);
> > >  		pp_div &= ~BXT_POWER_CYCLE_DELAY_MASK;
> > >  		pp_div |= (DIV_ROUND_UP((seq->t11_t12 + 1), 1000)
> > > @@ -5407,7 +5407,7 @@ static void intel_dp_init_panel_power_timestamps(struct intel_dp *intel_dp)
> > >  	DRM_DEBUG_KMS("panel power sequencer register settings: PP_ON %#x, PP_OFF %#x, PP_DIV %#x\n",
> > >  		      I915_READ(regs.pp_on),
> > >  		      I915_READ(regs.pp_off),
> > > -		      IS_GEN9_LP(dev_priv) ?
> > > +		      (IS_GEN9_LP(dev_priv) || HAS_PCH_CNP(dev_priv)) ?
> > >  		      (I915_READ(regs.pp_ctrl) & BXT_POWER_CYCLE_DELAY_MASK) :
> > >  		      I915_READ(regs.pp_div));
> > >  }
> > > -- 
> > > 1.9.1
> > > 
> > > _______________________________________________
> > > Intel-gfx mailing list
> > > Intel-gfx@lists.freedesktop.org
> > > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
> > 
> 

-- 
Ville Syrjälä
Intel OTC
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[PATCH 07/67] drm/i915/cnl: Introduce Cannonlake platform defition.

[Rodrigo Vivi]

Cannonlake is a Intel® Processor containing Intel® HD Graphics
following Kabylake.

It is Gen10.

Let's start by adding the platform definition based on previous
platforms but yet as alpha_support.

On following patches we will start adding PCI IDs and the
platform specific changes.

Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
---
 drivers/gpu/drm/i915/i915_drv.h          | 3 +++
 drivers/gpu/drm/i915/i915_pci.c          | 8 ++++++++
 drivers/gpu/drm/i915/intel_device_info.c | 1 +
 3 files changed, 12 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 2685f12..a357862 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -887,6 +887,7 @@ enum intel_platform {
 	INTEL_BROXTON,
 	INTEL_KABYLAKE,
 	INTEL_GEMINILAKE,
+	INTEL_CANNONLAKE,
 	INTEL_MAX_PLATFORMS
 };
 
@@ -2751,6 +2752,7 @@ static inline struct scatterlist *__sg_next(struct scatterlist *sg)
 #define IS_BROXTON(dev_priv)	((dev_priv)->info.platform == INTEL_BROXTON)
 #define IS_KABYLAKE(dev_priv)	((dev_priv)->info.platform == INTEL_KABYLAKE)
 #define IS_GEMINILAKE(dev_priv)	((dev_priv)->info.platform == INTEL_GEMINILAKE)
+#define IS_CANNONLAKE(dev_priv)	((dev_priv)->info.platform == INTEL_CANNONLAKE)
 #define IS_MOBILE(dev_priv)	((dev_priv)->info.is_mobile)
 #define IS_HSW_EARLY_SDV(dev_priv) (IS_HASWELL(dev_priv) && \
 				    (INTEL_DEVID(dev_priv) & 0xFF00) == 0x0C00)
@@ -2842,6 +2844,7 @@ static inline struct scatterlist *__sg_next(struct scatterlist *sg)
 #define IS_GEN7(dev_priv)	(!!((dev_priv)->info.gen_mask & BIT(6)))
 #define IS_GEN8(dev_priv)	(!!((dev_priv)->info.gen_mask & BIT(7)))
 #define IS_GEN9(dev_priv)	(!!((dev_priv)->info.gen_mask & BIT(8)))
+#define IS_GEN10(dev_priv)	(!!((dev_priv)->info.gen_mask & BIT(9)))
 
 #define IS_LP(dev_priv)	(INTEL_INFO(dev_priv)->is_lp)
 #define IS_GEN9_LP(dev_priv)	(IS_GEN9(dev_priv) && IS_LP(dev_priv))
diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index f87b0c4..a2a4b2f 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -431,6 +431,14 @@
 	.ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING | BSD2_RING,
 };
 
+static const struct intel_device_info intel_cannonlake_info = {
+	BDW_FEATURES,
+	.is_alpha_support = 1,
+	.platform = INTEL_CANNONLAKE,
+	.gen = 10,
+	.ddb_size = 896,
+};
+
 /*
  * Make sure any device matches here are from most specific to most
  * general.  For example, since the Quanta match is based on the subsystem
diff --git a/drivers/gpu/drm/i915/intel_device_info.c b/drivers/gpu/drm/i915/intel_device_info.c
index 7d01dfe..6b09a82 100644
--- a/drivers/gpu/drm/i915/intel_device_info.c
+++ b/drivers/gpu/drm/i915/intel_device_info.c
@@ -51,6 +51,7 @@
 	PLATFORM_NAME(BROXTON),
 	PLATFORM_NAME(KABYLAKE),
 	PLATFORM_NAME(GEMINILAKE),
+	PLATFORM_NAME(CANNONLAKE),
 };
 #undef PLATFORM_NAME
 
-- 
1.9.1

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Re: [PATCH 07/67] drm/i915/cnl: Introduce Cannonlake platform defition.

[Ander Conselvan De Oliveira]

On Thu, 2017-04-06 at 12:15 -0700, Rodrigo Vivi wrote:
> Cannonlake is a Intel® Processor containing Intel® HD Graphics
> following Kabylake.
> 
> It is Gen10.
> 
> Let's start by adding the platform definition based on previous
> platforms but yet as alpha_support.
> 
> On following patches we will start adding PCI IDs and the
> platform specific changes.
> 
> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
> ---
>  drivers/gpu/drm/i915/i915_drv.h          | 3 +++
>  drivers/gpu/drm/i915/i915_pci.c          | 8 ++++++++
>  drivers/gpu/drm/i915/intel_device_info.c | 1 +
>  3 files changed, 12 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 2685f12..a357862 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -887,6 +887,7 @@ enum intel_platform {
>  	INTEL_BROXTON,
>  	INTEL_KABYLAKE,
>  	INTEL_GEMINILAKE,
> +	INTEL_CANNONLAKE,
>  	INTEL_MAX_PLATFORMS
>  };
>  
> @@ -2751,6 +2752,7 @@ static inline struct scatterlist *__sg_next(struct scatterlist *sg)
>  #define IS_BROXTON(dev_priv)	((dev_priv)->info.platform == INTEL_BROXTON)
>  #define IS_KABYLAKE(dev_priv)	((dev_priv)->info.platform == INTEL_KABYLAKE)
>  #define IS_GEMINILAKE(dev_priv)	((dev_priv)->info.platform == INTEL_GEMINILAKE)
> +#define IS_CANNONLAKE(dev_priv)	((dev_priv)->info.platform == INTEL_CANNONLAKE)
>  #define IS_MOBILE(dev_priv)	((dev_priv)->info.is_mobile)
>  #define IS_HSW_EARLY_SDV(dev_priv) (IS_HASWELL(dev_priv) && \
>  				    (INTEL_DEVID(dev_priv) & 0xFF00) == 0x0C00)
> @@ -2842,6 +2844,7 @@ static inline struct scatterlist *__sg_next(struct scatterlist *sg)
>  #define IS_GEN7(dev_priv)	(!!((dev_priv)->info.gen_mask & BIT(6)))
>  #define IS_GEN8(dev_priv)	(!!((dev_priv)->info.gen_mask & BIT(7)))
>  #define IS_GEN9(dev_priv)	(!!((dev_priv)->info.gen_mask & BIT(8)))
> +#define IS_GEN10(dev_priv)	(!!((dev_priv)->info.gen_mask & BIT(9)))
>  
>  #define IS_LP(dev_priv)	(INTEL_INFO(dev_priv)->is_lp)
>  #define IS_GEN9_LP(dev_priv)	(IS_GEN9(dev_priv) && IS_LP(dev_priv))
> diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
> index f87b0c4..a2a4b2f 100644
> --- a/drivers/gpu/drm/i915/i915_pci.c
> +++ b/drivers/gpu/drm/i915/i915_pci.c
> @@ -431,6 +431,14 @@
>  	.ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING | BSD2_RING,
>  };
>  
> +static const struct intel_device_info intel_cannonlake_info = {
> +	BDW_FEATURES,
> +	.is_alpha_support = 1,
> +	.platform = INTEL_CANNONLAKE,
> +	.gen = 10,
> +	.ddb_size = 896,
> +};
> +

I think it makes sense to squash patch 17 with this one. No point in adding
.ddb_size with the wrong value. If there's a reason not squash, I'd say is
better to leave this as zero, so that the WARN_ON(ddb_size == 0) in intel_pm.c
will remind us to fix it. With one of these suggestions,

Reviewed-by: Ander Conselvan de Oliveira <conselvan2@gmail.com>

>  /*
>   * Make sure any device matches here are from most specific to most
>   * general.  For example, since the Quanta match is based on the subsystem
> diff --git a/drivers/gpu/drm/i915/intel_device_info.c b/drivers/gpu/drm/i915/intel_device_info.c
> index 7d01dfe..6b09a82 100644
> --- a/drivers/gpu/drm/i915/intel_device_info.c
> +++ b/drivers/gpu/drm/i915/intel_device_info.c
> @@ -51,6 +51,7 @@
>  	PLATFORM_NAME(BROXTON),
>  	PLATFORM_NAME(KABYLAKE),
>  	PLATFORM_NAME(GEMINILAKE),
> +	PLATFORM_NAME(CANNONLAKE),
>  };
>  #undef PLATFORM_NAME
>  
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[PATCH 08/67] drm/i915/cnl: Cannonlake uses CNP PCH.

[Rodrigo Vivi]

Avoid warning when CNP is detected with CNL.

Also let's force it on the virtual detection.

Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
---
 drivers/gpu/drm/i915/i915_drv.c | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 836db0d..ff4f2f9 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -139,6 +139,8 @@ static enum intel_pch intel_virt_detect_pch(struct drm_i915_private *dev_priv)
 	} else if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) {
 		ret = PCH_SPT;
 		DRM_DEBUG_KMS("Assuming SunrisePoint PCH\n");
+	} else if (IS_CANNONLAKE(dev_priv)) {
+		ret = PCH_CNP;
 	}
 
 	return ret;
@@ -221,9 +223,11 @@ static void intel_detect_pch(struct drm_i915_private *dev_priv)
 			} else if (id == INTEL_PCH_CNP_DEVICE_ID_TYPE) {
 				dev_priv->pch_type = PCH_CNP;
 				DRM_DEBUG_KMS("Found CannonPoint PCH\n");
+				WARN_ON(!IS_CANNONLAKE(dev_priv));
 			} else if (id_ext == INTEL_PCH_CNP_LP_DEVICE_ID_TYPE) {
 				dev_priv->pch_type = PCH_CNP;
 				DRM_DEBUG_KMS("Found CannonPoint LP PCH\n");
+				WARN_ON(!IS_CANNONLAKE(dev_priv));
 			} else if ((id == INTEL_PCH_P2X_DEVICE_ID_TYPE) ||
 				   (id == INTEL_PCH_P3X_DEVICE_ID_TYPE) ||
 				   ((id == INTEL_PCH_QEMU_DEVICE_ID_TYPE) &&
-- 
1.9.1

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Re: [PATCH 08/67] drm/i915/cnl: Cannonlake uses CNP PCH.

[Srivatsa, Anusha]

>-----Original Message-----
>From: Intel-gfx [mailto:intel-gfx-bounces@lists.freedesktop.org] On Behalf Of
>Rodrigo Vivi
>Sent: Thursday, April 6, 2017 12:15 PM
>To: intel-gfx@lists.freedesktop.org
>Cc: Vivi, Rodrigo <rodrigo.vivi@intel.com>
>Subject: [Intel-gfx] [PATCH 08/67] drm/i915/cnl: Cannonlake uses CNP PCH.
>
>Avoid warning when CNP is detected with CNL.
>
>Also let's force it on the virtual detection.

Reviewed-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
>Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
>---
> drivers/gpu/drm/i915/i915_drv.c | 4 ++++
> 1 file changed, 4 insertions(+)
>
>diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
>index 836db0d..ff4f2f9 100644
>--- a/drivers/gpu/drm/i915/i915_drv.c
>+++ b/drivers/gpu/drm/i915/i915_drv.c
>@@ -139,6 +139,8 @@ static enum intel_pch intel_virt_detect_pch(struct
>drm_i915_private *dev_priv)
> 	} else if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) {
> 		ret = PCH_SPT;
> 		DRM_DEBUG_KMS("Assuming SunrisePoint PCH\n");
>+	} else if (IS_CANNONLAKE(dev_priv)) {
>+		ret = PCH_CNP;
> 	}
>
> 	return ret;
>@@ -221,9 +223,11 @@ static void intel_detect_pch(struct drm_i915_private
>*dev_priv)
> 			} else if (id == INTEL_PCH_CNP_DEVICE_ID_TYPE) {
> 				dev_priv->pch_type = PCH_CNP;
> 				DRM_DEBUG_KMS("Found CannonPoint
>PCH\n");
>+				WARN_ON(!IS_CANNONLAKE(dev_priv));
> 			} else if (id_ext ==
>INTEL_PCH_CNP_LP_DEVICE_ID_TYPE) {
> 				dev_priv->pch_type = PCH_CNP;
> 				DRM_DEBUG_KMS("Found CannonPoint LP
>PCH\n");
>+				WARN_ON(!IS_CANNONLAKE(dev_priv));
> 			} else if ((id == INTEL_PCH_P2X_DEVICE_ID_TYPE) ||
> 				   (id == INTEL_PCH_P3X_DEVICE_ID_TYPE) ||
> 				   ((id == INTEL_PCH_QEMU_DEVICE_ID_TYPE)
>&&
>--
>1.9.1
>
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[PATCH 09/67] drm/i915/cnl: Add Cannonlake PCI IDs for U-skus.

[Rodrigo Vivi]

Platform enabling and its power-on are organized in different
skus (U x Y x S x H, etc). So instead of organizing it in
GT1 x GT2 x GT3 let's also use the platform sku.

This is also the new Spec style what makes the review much
more easy and straightforward.

v2: Really include the PCI IDs to the picidlist[];
v3: Remove PCI IDs not present in spec.
v4: Rebase.

Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
---
 drivers/gpu/drm/i915/i915_pci.c |  1 +
 include/drm/i915_pciids.h       | 10 ++++++++++
 2 files changed, 11 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index a2a4b2f..cb01822 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -483,6 +483,7 @@
 	INTEL_KBL_GT2_IDS(&intel_kabylake_info),
 	INTEL_KBL_GT3_IDS(&intel_kabylake_gt3_info),
 	INTEL_KBL_GT4_IDS(&intel_kabylake_gt3_info),
+	INTEL_CNL_IDS(&intel_cannonlake_info),
 	{0, 0, 0}
 };
 MODULE_DEVICE_TABLE(pci, pciidlist);
diff --git a/include/drm/i915_pciids.h b/include/drm/i915_pciids.h
index 27e0dba..7f1bb3b 100644
--- a/include/drm/i915_pciids.h
+++ b/include/drm/i915_pciids.h
@@ -334,4 +334,14 @@
 	INTEL_KBL_GT3_IDS(info), \
 	INTEL_KBL_GT4_IDS(info)
 
+/* CNL U 2+2 */
+#define INTEL_CNL_U_GT2_IDS(info) \
+	INTEL_VGA_DEVICE(0x5A52, info), \
+	INTEL_VGA_DEVICE(0x5A5A, info), \
+	INTEL_VGA_DEVICE(0x5A42, info), \
+	INTEL_VGA_DEVICE(0x5A4A, info)
+
+#define INTEL_CNL_IDS(info) \
+	INTEL_CNL_U_GT2_IDS(info)
+
 #endif /* _I915_PCIIDS_H */
-- 
1.9.1

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Re: [PATCH 09/67] drm/i915/cnl: Add Cannonlake PCI IDs for U-skus.

[Clint Taylor]

On 04/06/2017 12:15 PM, Rodrigo Vivi wrote:
> Platform enabling and its power-on are organized in different
> skus (U x Y x S x H, etc). So instead of organizing it in
> GT1 x GT2 x GT3 let's also use the platform sku.
>
> This is also the new Spec style what makes the review much
> more easy and straightforward.
>
> v2: Really include the PCI IDs to the picidlist[];
> v3: Remove PCI IDs not present in spec.
> v4: Rebase.
Matches latest version of the available U SKU ID's

Reviewed-by: Clinton Taylor <clinton.a.taylor@intel.com>

> Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
> ---
>   drivers/gpu/drm/i915/i915_pci.c |  1 +
>   include/drm/i915_pciids.h       | 10 ++++++++++
>   2 files changed, 11 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
> index a2a4b2f..cb01822 100644
> --- a/drivers/gpu/drm/i915/i915_pci.c
> +++ b/drivers/gpu/drm/i915/i915_pci.c
> @@ -483,6 +483,7 @@
>   	INTEL_KBL_GT2_IDS(&intel_kabylake_info),
>   	INTEL_KBL_GT3_IDS(&intel_kabylake_gt3_info),
>   	INTEL_KBL_GT4_IDS(&intel_kabylake_gt3_info),
> +	INTEL_CNL_IDS(&intel_cannonlake_info),
>   	{0, 0, 0}
>   };
>   MODULE_DEVICE_TABLE(pci, pciidlist);
> diff --git a/include/drm/i915_pciids.h b/include/drm/i915_pciids.h
> index 27e0dba..7f1bb3b 100644
> --- a/include/drm/i915_pciids.h
> +++ b/include/drm/i915_pciids.h
> @@ -334,4 +334,14 @@
>   	INTEL_KBL_GT3_IDS(info), \
>   	INTEL_KBL_GT4_IDS(info)
>   
> +/* CNL U 2+2 */
> +#define INTEL_CNL_U_GT2_IDS(info) \
> +	INTEL_VGA_DEVICE(0x5A52, info), \
> +	INTEL_VGA_DEVICE(0x5A5A, info), \
> +	INTEL_VGA_DEVICE(0x5A42, info), \
> +	INTEL_VGA_DEVICE(0x5A4A, info)
> +
> +#define INTEL_CNL_IDS(info) \
> +	INTEL_CNL_U_GT2_IDS(info)
> +
>   #endif /* _I915_PCIIDS_H */

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[PATCH 10/67] drm/i915/cnl: Add Cannonlake PCI IDs for Y-skus.

[Rodrigo Vivi]

By the Spec all CNL Y skus are 2+2, i.e. GT2.

v2: Really include the PCI IDs to the picidlist[];

Reviewed-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
---
 include/drm/i915_pciids.h | 12 +++++++++++-
 1 file changed, 11 insertions(+), 1 deletion(-)

diff --git a/include/drm/i915_pciids.h b/include/drm/i915_pciids.h
index 7f1bb3b..7d2696a 100644
--- a/include/drm/i915_pciids.h
+++ b/include/drm/i915_pciids.h
@@ -341,7 +341,17 @@
 	INTEL_VGA_DEVICE(0x5A42, info), \
 	INTEL_VGA_DEVICE(0x5A4A, info)
 
+/* CNL Y 2+2 */
+#define INTEL_CNL_Y_GT2_IDS(info) \
+	INTEL_VGA_DEVICE(0x5A51, info), \
+	INTEL_VGA_DEVICE(0x5A59, info), \
+	INTEL_VGA_DEVICE(0x5A41, info), \
+	INTEL_VGA_DEVICE(0x5A49, info), \
+	INTEL_VGA_DEVICE(0x5A71, info), \
+	INTEL_VGA_DEVICE(0x5A79, info)
+
 #define INTEL_CNL_IDS(info) \
-	INTEL_CNL_U_GT2_IDS(info)
+	INTEL_CNL_U_GT2_IDS(info), \
+	INTEL_CNL_Y_GT2_IDS(info)
 
 #endif /* _I915_PCIIDS_H */
-- 
1.9.1

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[PATCH 11/67] drm/i915/cnl: add IS_CNL_REVID macro

[Rodrigo Vivi]

From: Paulo Zanoni <paulo.r.zanoni@intel.com>

We're going to use it in the next commits.

Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
---
 drivers/gpu/drm/i915/i915_drv.h | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index a357862..7dda202 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -2830,6 +2830,12 @@ static inline struct scatterlist *__sg_next(struct scatterlist *sg)
 #define IS_GLK_REVID(dev_priv, since, until) \
 	(IS_GEMINILAKE(dev_priv) && IS_REVID(dev_priv, since, until))
 
+#define CNL_REVID_A0		0x0
+#define CNL_REVID_B0		0x1
+
+#define IS_CNL_REVID(p, since, until) \
+	(IS_CANNONLAKE(p) && IS_REVID(p, since, until))
+
 /*
  * The genX designation typically refers to the render engine, so render
  * capability related checks should use IS_GEN, while display and other checks
-- 
1.9.1

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Re: [PATCH 11/67] drm/i915/cnl: add IS_CNL_REVID macro

[Jim Bride]

On Thu, Apr 06, 2017 at 12:15:07PM -0700, Rodrigo Vivi wrote:
> From: Paulo Zanoni <paulo.r.zanoni@intel.com>
> 
> We're going to use it in the next commits.
> 
> Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>

Reviewed-by: Jim Bride <jim.bride@linux.intel.com>

> ---
>  drivers/gpu/drm/i915/i915_drv.h | 6 ++++++
>  1 file changed, 6 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index a357862..7dda202 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -2830,6 +2830,12 @@ static inline struct scatterlist *__sg_next(struct scatterlist *sg)
>  #define IS_GLK_REVID(dev_priv, since, until) \
>  	(IS_GEMINILAKE(dev_priv) && IS_REVID(dev_priv, since, until))
>  
> +#define CNL_REVID_A0		0x0
> +#define CNL_REVID_B0		0x1
> +
> +#define IS_CNL_REVID(p, since, until) \
> +	(IS_CANNONLAKE(p) && IS_REVID(p, since, until))
> +
>  /*
>   * The genX designation typically refers to the render engine, so render
>   * capability related checks should use IS_GEN, while display and other checks
> -- 
> 1.9.1
> 
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[PATCH 12/67] drm/i915/cnl: Introduce initial Cannonlake Workarounds.

[Rodrigo Vivi]

Let's inherit workarounds from previous platforms that
according to wa_database and BSpec are still valid for
Cannonlake.

v2: Add missed workarounds.
v3: Rebase

Cc: Mika Kuoppala <mika.kuoppala@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
---
 drivers/gpu/drm/i915/i915_gem_gtt.c    |  4 ++--
 drivers/gpu/drm/i915/i915_reg.h        |  6 +++++
 drivers/gpu/drm/i915/intel_engine_cs.c | 26 ++++++++++++++++++++
 drivers/gpu/drm/i915/intel_lrc.c       |  1 +
 drivers/gpu/drm/i915/intel_pm.c        | 44 +++++++++++++++++++++++++++++-----
 5 files changed, 73 insertions(+), 8 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c
index 8bab4ae..3c8457d 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -1881,12 +1881,12 @@ static void gtt_write_workarounds(struct drm_i915_private *dev_priv)
 	 * called on driver load and after a GPU reset, so you can place
 	 * workarounds here even if they get overwritten by GPU reset.
 	 */
-	/* WaIncreaseDefaultTLBEntries:chv,bdw,skl,bxt,kbl,glk */
+	/* WaIncreaseDefaultTLBEntries:chv,bdw,skl,bxt,kbl,glk,cnl */
 	if (IS_BROADWELL(dev_priv))
 		I915_WRITE(GEN8_L3_LRA_1_GPGPU, GEN8_L3_LRA_1_GPGPU_DEFAULT_VALUE_BDW);
 	else if (IS_CHERRYVIEW(dev_priv))
 		I915_WRITE(GEN8_L3_LRA_1_GPGPU, GEN8_L3_LRA_1_GPGPU_DEFAULT_VALUE_CHV);
-	else if (IS_GEN9_BC(dev_priv))
+	else if (IS_GEN9_BC(dev_priv) || IS_GEN10(dev_priv))
 		I915_WRITE(GEN8_L3_LRA_1_GPGPU, GEN9_L3_LRA_1_GPGPU_DEFAULT_VALUE_SKL);
 	else if (IS_GEN9_LP(dev_priv))
 		I915_WRITE(GEN8_L3_LRA_1_GPGPU, GEN9_L3_LRA_1_GPGPU_DEFAULT_VALUE_BXT);
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index efbbeb8..a09a0d7 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -3424,6 +3424,12 @@ enum {
 #define   PWM1_GATING_DIS		(1 << 13)
 
 /*
+ * GEN10 clock gating regs
+ */
+#define SLICE_UNIT_LEVEL_CLKGATE	_MMIO(0x94d4)
+#define  SARBUNIT_CLKGATE_DIS		(1 << 5)
+
+/*
  * Display engine regs
  */
 
diff --git a/drivers/gpu/drm/i915/intel_engine_cs.c b/drivers/gpu/drm/i915/intel_engine_cs.c
index 854e8e0..da819a7 100644
--- a/drivers/gpu/drm/i915/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/intel_engine_cs.c
@@ -946,6 +946,30 @@ static int bxt_init_workarounds(struct intel_engine_cs *engine)
 	return 0;
 }
 
+static int cnl_init_workarounds(struct intel_engine_cs *engine)
+{
+	struct drm_i915_private *dev_priv = engine->i915;
+	int ret;
+
+	/* WaInPlaceDecompressionHang:cnl */
+	WA_SET_BIT(GEN9_GAMT_ECO_REG_RW_IA,
+		   GAMT_ECO_ENABLE_IN_PLACE_DECOMPRESS);
+
+	/* WaEnablePreemptionGranularityControlByUMD:cnl */
+	ret= wa_ring_whitelist_reg(engine, GEN8_CS_CHICKEN1);
+	if (ret)
+		return ret;
+
+	/* WaAllowUMDToModifyHDCChicken1:cnl (pre-prod) */
+	if (IS_CNL_REVID(dev_priv, CNL_REVID_A0, CNL_REVID_A0)) {
+		ret = wa_ring_whitelist_reg(engine, GEN8_HDC_CHICKEN1);
+		if (ret)
+			return ret;
+	}
+
+	return 0;
+}
+
 static int kbl_init_workarounds(struct intel_engine_cs *engine)
 {
 	struct drm_i915_private *dev_priv = engine->i915;
@@ -1032,6 +1056,8 @@ int init_workarounds_ring(struct intel_engine_cs *engine)
 		err = kbl_init_workarounds(engine);
 	else if (IS_GEMINILAKE(dev_priv))
 		err =  glk_init_workarounds(engine);
+	else if (IS_CANNONLAKE(dev_priv))
+		err = cnl_init_workarounds(engine);
 	else
 		err = 0;
 	if (err)
diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index 0dc1cc4..23e2bed 100644
--- a/drivers/gpu/drm/i915/intel_lrc.c
+++ b/drivers/gpu/drm/i915/intel_lrc.c
@@ -1093,6 +1093,7 @@ static int intel_init_workaround_bb(struct intel_engine_cs *engine)
 		return -EINVAL;
 
 	switch (INTEL_GEN(engine->i915)) {
+	case 10:
 	case 9:
 		wa_bb_fn[0] = gen9_init_indirectctx_bb;
 		wa_bb_fn[1] = gen9_init_perctx_bb;
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 55e1e88..b6ecab9 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -58,24 +58,24 @@
 
 static void gen9_init_clock_gating(struct drm_i915_private *dev_priv)
 {
-	/* See Bspec note for PSR2_CTL bit 31, Wa#828:skl,bxt,kbl */
+	/* See Bspec note for PSR2_CTL bit 31, Wa#828:skl,bxt,kbl,cnl */
 	I915_WRITE(CHICKEN_PAR1_1,
 		   I915_READ(CHICKEN_PAR1_1) | SKL_EDP_PSR_FIX_RDWRAP);
 
 	I915_WRITE(GEN8_CONFIG0,
 		   I915_READ(GEN8_CONFIG0) | GEN9_DEFAULT_FIXES);
 
-	/* WaEnableChickenDCPR:skl,bxt,kbl,glk */
+	/* WaEnableChickenDCPR:skl,bxt,kbl,glk,cnl */
 	I915_WRITE(GEN8_CHICKEN_DCPR_1,
 		   I915_READ(GEN8_CHICKEN_DCPR_1) | MASK_WAKEMEM);
 
-	/* WaFbcTurnOffFbcWatermark:skl,bxt,kbl */
-	/* WaFbcWakeMemOn:skl,bxt,kbl,glk */
+	/* WaFbcTurnOffFbcWatermark:skl,bxt,kbl,cnl */
+	/* WaFbcWakeMemOn:skl,bxt,kbl,glk,cnl */
 	I915_WRITE(DISP_ARB_CTL, I915_READ(DISP_ARB_CTL) |
 		   DISP_FBC_WM_DIS |
 		   DISP_FBC_MEMORY_WAKE);
 
-	/* WaFbcHighMemBwCorruptionAvoidance:skl,bxt,kbl */
+	/* WaFbcHighMemBwCorruptionAvoidance:skl,bxt,kbl,cnl */
 	I915_WRITE(ILK_DPFC_CHICKEN, I915_READ(ILK_DPFC_CHICKEN) |
 		   ILK_DPFC_DISABLE_DUMMY0);
 }
@@ -5428,8 +5428,19 @@ int intel_set_rps(struct drm_i915_private *dev_priv, u8 val)
 
 static void gen9_disable_rc6(struct drm_i915_private *dev_priv)
 {
+	gen9_init_clock_gating(dev_priv);
+
 	I915_WRITE(GEN6_RC_CONTROL, 0);
 	I915_WRITE(GEN9_PG_ENABLE, 0);
+
+	/* WaDisableGamClockGating:cnl (pre-prod) */
+	if (IS_CNL_REVID(dev_priv, CNL_REVID_A0, CNL_REVID_A0))
+		I915_WRITE(GEN6_UCGCTL1, I915_READ(GEN6_UCGCTL1) |
+			   GEN6_GAMUNIT_CLOCK_GATE_DISABLE);
+
+	/* WaFbcNukeOnHostModify:cnl */
+	I915_WRITE(ILK_DPFC_CHICKEN, I915_READ(ILK_DPFC_CHICKEN) |
+		   ILK_DPFC_NUKE_ON_ANY_MODIFICATION);
 }
 
 static void gen9_disable_rps(struct drm_i915_private *dev_priv)
@@ -7474,6 +7485,25 @@ static void gen8_set_l3sqc_credits(struct drm_i915_private *dev_priv,
 	I915_WRITE(GEN7_MISCCPCTL, misccpctl);
 }
 
+static void cannonlake_init_clock_gating(struct drm_i915_private *dev_priv)
+{
+	gen9_init_clock_gating(dev_priv);
+
+	/* WaDisableGamClockGating:cnl (pre-prod) */
+	if (IS_CNL_REVID(dev_priv, CNL_REVID_A0, CNL_REVID_A0))
+	        I915_WRITE(GEN6_UCGCTL1, I915_READ(GEN6_UCGCTL1) |
+			   GEN6_GAMUNIT_CLOCK_GATE_DISABLE);
+
+	/* WaFbcNukeOnHostModify:cnl */
+	I915_WRITE(ILK_DPFC_CHICKEN, I915_READ(ILK_DPFC_CHICKEN) |
+		   ILK_DPFC_NUKE_ON_ANY_MODIFICATION);
+
+	/* WaSarbUnitClockGatingDisable:cnl (pre-prod) */
+	if (IS_CNL_REVID(dev_priv, CNL_REVID_A0, CNL_REVID_B0))
+		I915_WRITE(SLICE_UNIT_LEVEL_CLKGATE, I915_READ(SLICE_UNIT_LEVEL_CLKGATE) |
+			   SARBUNIT_CLKGATE_DIS);
+}
+
 static void kabylake_init_clock_gating(struct drm_i915_private *dev_priv)
 {
 	gen9_init_clock_gating(dev_priv);
@@ -7954,7 +7984,9 @@ static void nop_init_clock_gating(struct drm_i915_private *dev_priv)
  */
 void intel_init_clock_gating_hooks(struct drm_i915_private *dev_priv)
 {
-	if (IS_SKYLAKE(dev_priv))
+	if (IS_CANNONLAKE(dev_priv))
+		dev_priv->display.init_clock_gating = cannonlake_init_clock_gating;
+	else if (IS_SKYLAKE(dev_priv))
 		dev_priv->display.init_clock_gating = skylake_init_clock_gating;
 	else if (IS_KABYLAKE(dev_priv))
 		dev_priv->display.init_clock_gating = kabylake_init_clock_gating;
-- 
1.9.1

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Re: [PATCH 12/67] drm/i915/cnl: Introduce initial Cannonlake Workarounds.

[Oscar Mateo]

On 04/06/2017 07:15 PM, Rodrigo Vivi wrote:
> Let's inherit workarounds from previous platforms that
> according to wa_database and BSpec are still valid for
> Cannonlake.
>
> v2: Add missed workarounds.
> v3: Rebase
>
> Cc: Mika Kuoppala <mika.kuoppala@intel.com>
> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
> ---
>   drivers/gpu/drm/i915/i915_gem_gtt.c    |  4 ++--
>   drivers/gpu/drm/i915/i915_reg.h        |  6 +++++
>   drivers/gpu/drm/i915/intel_engine_cs.c | 26 ++++++++++++++++++++
>   drivers/gpu/drm/i915/intel_lrc.c       |  1 +
>   drivers/gpu/drm/i915/intel_pm.c        | 44 +++++++++++++++++++++++++++++-----
>   5 files changed, 73 insertions(+), 8 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c
> index 8bab4ae..3c8457d 100644
> --- a/drivers/gpu/drm/i915/i915_gem_gtt.c
> +++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
> @@ -1881,12 +1881,12 @@ static void gtt_write_workarounds(struct drm_i915_private *dev_priv)
>   	 * called on driver load and after a GPU reset, so you can place
>   	 * workarounds here even if they get overwritten by GPU reset.
>   	 */
> -	/* WaIncreaseDefaultTLBEntries:chv,bdw,skl,bxt,kbl,glk */
> +	/* WaIncreaseDefaultTLBEntries:chv,bdw,skl,bxt,kbl,glk,cnl */
>   	if (IS_BROADWELL(dev_priv))
>   		I915_WRITE(GEN8_L3_LRA_1_GPGPU, GEN8_L3_LRA_1_GPGPU_DEFAULT_VALUE_BDW);
>   	else if (IS_CHERRYVIEW(dev_priv))
>   		I915_WRITE(GEN8_L3_LRA_1_GPGPU, GEN8_L3_LRA_1_GPGPU_DEFAULT_VALUE_CHV);
> -	else if (IS_GEN9_BC(dev_priv))
> +	else if (IS_GEN9_BC(dev_priv) || IS_GEN10(dev_priv))
>   		I915_WRITE(GEN8_L3_LRA_1_GPGPU, GEN9_L3_LRA_1_GPGPU_DEFAULT_VALUE_SKL);
>   	else if (IS_GEN9_LP(dev_priv))
>   		I915_WRITE(GEN8_L3_LRA_1_GPGPU, GEN9_L3_LRA_1_GPGPU_DEFAULT_VALUE_BXT);
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index efbbeb8..a09a0d7 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -3424,6 +3424,12 @@ enum {
>   #define   PWM1_GATING_DIS		(1 << 13)
>   
>   /*
> + * GEN10 clock gating regs
> + */
> +#define SLICE_UNIT_LEVEL_CLKGATE	_MMIO(0x94d4)
> +#define  SARBUNIT_CLKGATE_DIS		(1 << 5)
> +
> +/*
>    * Display engine regs
>    */
>   
> diff --git a/drivers/gpu/drm/i915/intel_engine_cs.c b/drivers/gpu/drm/i915/intel_engine_cs.c
> index 854e8e0..da819a7 100644
> --- a/drivers/gpu/drm/i915/intel_engine_cs.c
> +++ b/drivers/gpu/drm/i915/intel_engine_cs.c
> @@ -946,6 +946,30 @@ static int bxt_init_workarounds(struct intel_engine_cs *engine)
>   	return 0;
>   }
>   
> +static int cnl_init_workarounds(struct intel_engine_cs *engine)
> +{
> +	struct drm_i915_private *dev_priv = engine->i915;
> +	int ret;
> +
> +	/* WaInPlaceDecompressionHang:cnl */
> +	WA_SET_BIT(GEN9_GAMT_ECO_REG_RW_IA,
> +		   GAMT_ECO_ENABLE_IN_PLACE_DECOMPRESS);
> +
> +	/* WaEnablePreemptionGranularityControlByUMD:cnl */
> +	ret= wa_ring_whitelist_reg(engine, GEN8_CS_CHICKEN1);
> +	if (ret)
> +		return ret;
> +
> +	/* WaAllowUMDToModifyHDCChicken1:cnl (pre-prod) */
> +	if (IS_CNL_REVID(dev_priv, CNL_REVID_A0, CNL_REVID_A0)) {
> +		ret = wa_ring_whitelist_reg(engine, GEN8_HDC_CHICKEN1);
> +		if (ret)
> +			return ret;
> +	}
> +
> +	return 0;
> +}
> +
>   static int kbl_init_workarounds(struct intel_engine_cs *engine)
>   {
>   	struct drm_i915_private *dev_priv = engine->i915;
> @@ -1032,6 +1056,8 @@ int init_workarounds_ring(struct intel_engine_cs *engine)
>   		err = kbl_init_workarounds(engine);
>   	else if (IS_GEMINILAKE(dev_priv))
>   		err =  glk_init_workarounds(engine);
> +	else if (IS_CANNONLAKE(dev_priv))
> +		err = cnl_init_workarounds(engine);
>   	else
>   		err = 0;
>   	if (err)
> diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
> index 0dc1cc4..23e2bed 100644
> --- a/drivers/gpu/drm/i915/intel_lrc.c
> +++ b/drivers/gpu/drm/i915/intel_lrc.c
> @@ -1093,6 +1093,7 @@ static int intel_init_workaround_bb(struct intel_engine_cs *engine)
>   		return -EINVAL;
>   
>   	switch (INTEL_GEN(engine->i915)) {
> +	case 10:

Are you sure this is what you want? gen9_init_perctx_bb is just an empty 
batchbuffer, but gen9_init_indirectctx_bb introduces some WAs that do 
not apply to CNL (WaFlushCoherentL3CacheLinesAtContextSwitch, 
WaClearSlmSpaceAtContextSwitch, etc...)

>   	case 9:
>   		wa_bb_fn[0] = gen9_init_indirectctx_bb;
>   		wa_bb_fn[1] = gen9_init_perctx_bb;
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index 55e1e88..b6ecab9 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -58,24 +58,24 @@
>   
>   static void gen9_init_clock_gating(struct drm_i915_private *dev_priv)
>   {
> -	/* See Bspec note for PSR2_CTL bit 31, Wa#828:skl,bxt,kbl */
> +	/* See Bspec note for PSR2_CTL bit 31, Wa#828:skl,bxt,kbl,cnl */
>   	I915_WRITE(CHICKEN_PAR1_1,
>   		   I915_READ(CHICKEN_PAR1_1) | SKL_EDP_PSR_FIX_RDWRAP);
>   
>   	I915_WRITE(GEN8_CONFIG0,
>   		   I915_READ(GEN8_CONFIG0) | GEN9_DEFAULT_FIXES);
>   
> -	/* WaEnableChickenDCPR:skl,bxt,kbl,glk */
> +	/* WaEnableChickenDCPR:skl,bxt,kbl,glk,cnl */
>   	I915_WRITE(GEN8_CHICKEN_DCPR_1,
>   		   I915_READ(GEN8_CHICKEN_DCPR_1) | MASK_WAKEMEM);
>   
> -	/* WaFbcTurnOffFbcWatermark:skl,bxt,kbl */
> -	/* WaFbcWakeMemOn:skl,bxt,kbl,glk */
> +	/* WaFbcTurnOffFbcWatermark:skl,bxt,kbl,cnl */
> +	/* WaFbcWakeMemOn:skl,bxt,kbl,glk,cnl */
>   	I915_WRITE(DISP_ARB_CTL, I915_READ(DISP_ARB_CTL) |
>   		   DISP_FBC_WM_DIS |
>   		   DISP_FBC_MEMORY_WAKE);
>   
> -	/* WaFbcHighMemBwCorruptionAvoidance:skl,bxt,kbl */
> +	/* WaFbcHighMemBwCorruptionAvoidance:skl,bxt,kbl,cnl */
>   	I915_WRITE(ILK_DPFC_CHICKEN, I915_READ(ILK_DPFC_CHICKEN) |
>   		   ILK_DPFC_DISABLE_DUMMY0);
>   }
> @@ -5428,8 +5428,19 @@ int intel_set_rps(struct drm_i915_private *dev_priv, u8 val)
>   
>   static void gen9_disable_rc6(struct drm_i915_private *dev_priv)
>   {
> +	gen9_init_clock_gating(dev_priv);
> +
>   	I915_WRITE(GEN6_RC_CONTROL, 0);
>   	I915_WRITE(GEN9_PG_ENABLE, 0);
> +
> +	/* WaDisableGamClockGating:cnl (pre-prod) */
> +	if (IS_CNL_REVID(dev_priv, CNL_REVID_A0, CNL_REVID_A0))
> +		I915_WRITE(GEN6_UCGCTL1, I915_READ(GEN6_UCGCTL1) |
> +			   GEN6_GAMUNIT_CLOCK_GATE_DISABLE);
> +
> +	/* WaFbcNukeOnHostModify:cnl */
> +	I915_WRITE(ILK_DPFC_CHICKEN, I915_READ(ILK_DPFC_CHICKEN) |
> +		   ILK_DPFC_NUKE_ON_ANY_MODIFICATION);
>   }
>   
>   static void gen9_disable_rps(struct drm_i915_private *dev_priv)
> @@ -7474,6 +7485,25 @@ static void gen8_set_l3sqc_credits(struct drm_i915_private *dev_priv,
>   	I915_WRITE(GEN7_MISCCPCTL, misccpctl);
>   }
>   
> +static void cannonlake_init_clock_gating(struct drm_i915_private *dev_priv)
> +{
> +	gen9_init_clock_gating(dev_priv);
> +
> +	/* WaDisableGamClockGating:cnl (pre-prod) */
> +	if (IS_CNL_REVID(dev_priv, CNL_REVID_A0, CNL_REVID_A0))
> +	        I915_WRITE(GEN6_UCGCTL1, I915_READ(GEN6_UCGCTL1) |
> +			   GEN6_GAMUNIT_CLOCK_GATE_DISABLE);
> +
> +	/* WaFbcNukeOnHostModify:cnl */
> +	I915_WRITE(ILK_DPFC_CHICKEN, I915_READ(ILK_DPFC_CHICKEN) |
> +		   ILK_DPFC_NUKE_ON_ANY_MODIFICATION);
> +
> +	/* WaSarbUnitClockGatingDisable:cnl (pre-prod) */
> +	if (IS_CNL_REVID(dev_priv, CNL_REVID_A0, CNL_REVID_B0))
> +		I915_WRITE(SLICE_UNIT_LEVEL_CLKGATE, I915_READ(SLICE_UNIT_LEVEL_CLKGATE) |
> +			   SARBUNIT_CLKGATE_DIS);
> +}
> +
>   static void kabylake_init_clock_gating(struct drm_i915_private *dev_priv)
>   {
>   	gen9_init_clock_gating(dev_priv);
> @@ -7954,7 +7984,9 @@ static void nop_init_clock_gating(struct drm_i915_private *dev_priv)
>    */
>   void intel_init_clock_gating_hooks(struct drm_i915_private *dev_priv)
>   {
> -	if (IS_SKYLAKE(dev_priv))
> +	if (IS_CANNONLAKE(dev_priv))
> +		dev_priv->display.init_clock_gating = cannonlake_init_clock_gating;
> +	else if (IS_SKYLAKE(dev_priv))
>   		dev_priv->display.init_clock_gating = skylake_init_clock_gating;
>   	else if (IS_KABYLAKE(dev_priv))
>   		dev_priv->display.init_clock_gating = kabylake_init_clock_gating;

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Re: [PATCH 12/67] drm/i915/cnl: Introduce initial Cannonlake Workarounds.

[Ander Conselvan De Oliveira]

On Thu, 2017-04-06 at 12:15 -0700, Rodrigo Vivi wrote:
> Let's inherit workarounds from previous platforms that
> according to wa_database and BSpec are still valid for
> Cannonlake.
> 
> v2: Add missed workarounds.
> v3: Rebase
> 
> Cc: Mika Kuoppala <mika.kuoppala@intel.com>
> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
> ---
>  drivers/gpu/drm/i915/i915_gem_gtt.c    |  4 ++--
>  drivers/gpu/drm/i915/i915_reg.h        |  6 +++++
>  drivers/gpu/drm/i915/intel_engine_cs.c | 26 ++++++++++++++++++++
>  drivers/gpu/drm/i915/intel_lrc.c       |  1 +
>  drivers/gpu/drm/i915/intel_pm.c        | 44 +++++++++++++++++++++++++++++-----
>  5 files changed, 73 insertions(+), 8 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c
> index 8bab4ae..3c8457d 100644
> --- a/drivers/gpu/drm/i915/i915_gem_gtt.c
> +++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
> @@ -1881,12 +1881,12 @@ static void gtt_write_workarounds(struct drm_i915_private *dev_priv)
>  	 * called on driver load and after a GPU reset, so you can place
>  	 * workarounds here even if they get overwritten by GPU reset.
>  	 */
> -	/* WaIncreaseDefaultTLBEntries:chv,bdw,skl,bxt,kbl,glk */
> +	/* WaIncreaseDefaultTLBEntries:chv,bdw,skl,bxt,kbl,glk,cnl */
>  	if (IS_BROADWELL(dev_priv))
>  		I915_WRITE(GEN8_L3_LRA_1_GPGPU, GEN8_L3_LRA_1_GPGPU_DEFAULT_VALUE_BDW);
>  	else if (IS_CHERRYVIEW(dev_priv))
>  		I915_WRITE(GEN8_L3_LRA_1_GPGPU, GEN8_L3_LRA_1_GPGPU_DEFAULT_VALUE_CHV);
> -	else if (IS_GEN9_BC(dev_priv))
> +	else if (IS_GEN9_BC(dev_priv) || IS_GEN10(dev_priv))
>  		I915_WRITE(GEN8_L3_LRA_1_GPGPU, GEN9_L3_LRA_1_GPGPU_DEFAULT_VALUE_SKL);
>  	else if (IS_GEN9_LP(dev_priv))
>  		I915_WRITE(GEN8_L3_LRA_1_GPGPU, GEN9_L3_LRA_1_GPGPU_DEFAULT_VALUE_BXT);
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index efbbeb8..a09a0d7 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -3424,6 +3424,12 @@ enum {
>  #define   PWM1_GATING_DIS		(1 << 13)
>  
>  /*
> + * GEN10 clock gating regs
> + */
> +#define SLICE_UNIT_LEVEL_CLKGATE	_MMIO(0x94d4)
> +#define  SARBUNIT_CLKGATE_DIS		(1 << 5)
> +
> +/*
>   * Display engine regs
>   */
>  
> diff --git a/drivers/gpu/drm/i915/intel_engine_cs.c b/drivers/gpu/drm/i915/intel_engine_cs.c
> index 854e8e0..da819a7 100644
> --- a/drivers/gpu/drm/i915/intel_engine_cs.c
> +++ b/drivers/gpu/drm/i915/intel_engine_cs.c
> @@ -946,6 +946,30 @@ static int bxt_init_workarounds(struct intel_engine_cs *engine)
>  	return 0;
>  }
>  
> +static int cnl_init_workarounds(struct intel_engine_cs *engine)
> +{
> +	struct drm_i915_private *dev_priv = engine->i915;
> +	int ret;
> +
> +	/* WaInPlaceDecompressionHang:cnl */
> +	WA_SET_BIT(GEN9_GAMT_ECO_REG_RW_IA,
> +		   GAMT_ECO_ENABLE_IN_PLACE_DECOMPRESS);
> +
> +	/* WaEnablePreemptionGranularityControlByUMD:cnl */
> +	ret= wa_ring_whitelist_reg(engine, GEN8_CS_CHICKEN1);
> +	if (ret)
> +		return ret;
> +
> +	/* WaAllowUMDToModifyHDCChicken1:cnl (pre-prod) */
> +	if (IS_CNL_REVID(dev_priv, CNL_REVID_A0, CNL_REVID_A0)) {
> +		ret = wa_ring_whitelist_reg(engine, GEN8_HDC_CHICKEN1);
> +		if (ret)
> +			return ret;
> +	}
> +
> +	return 0;
> +}
> +
>  static int kbl_init_workarounds(struct intel_engine_cs *engine)
>  {
>  	struct drm_i915_private *dev_priv = engine->i915;
> @@ -1032,6 +1056,8 @@ int init_workarounds_ring(struct intel_engine_cs *engine)
>  		err = kbl_init_workarounds(engine);
>  	else if (IS_GEMINILAKE(dev_priv))
>  		err =  glk_init_workarounds(engine);
> +	else if (IS_CANNONLAKE(dev_priv))
> +		err = cnl_init_workarounds(engine);
>  	else
>  		err = 0;
>  	if (err)
> diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
> index 0dc1cc4..23e2bed 100644
> --- a/drivers/gpu/drm/i915/intel_lrc.c
> +++ b/drivers/gpu/drm/i915/intel_lrc.c
> @@ -1093,6 +1093,7 @@ static int intel_init_workaround_bb(struct intel_engine_cs *engine)
>  		return -EINVAL;
>  
>  	switch (INTEL_GEN(engine->i915)) {
> +	case 10:
>  	case 9:
>  		wa_bb_fn[0] = gen9_init_indirectctx_bb;
>  		wa_bb_fn[1] = gen9_init_perctx_bb;
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index 55e1e88..b6ecab9 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -58,24 +58,24 @@
>  
>  static void gen9_init_clock_gating(struct drm_i915_private *dev_priv)
>  {
> -	/* See Bspec note for PSR2_CTL bit 31, Wa#828:skl,bxt,kbl */
> +	/* See Bspec note for PSR2_CTL bit 31, Wa#828:skl,bxt,kbl,cnl */
>  	I915_WRITE(CHICKEN_PAR1_1,
>  		   I915_READ(CHICKEN_PAR1_1) | SKL_EDP_PSR_FIX_RDWRAP);
>  
>  	I915_WRITE(GEN8_CONFIG0,
>  		   I915_READ(GEN8_CONFIG0) | GEN9_DEFAULT_FIXES);
>  
> -	/* WaEnableChickenDCPR:skl,bxt,kbl,glk */
> +	/* WaEnableChickenDCPR:skl,bxt,kbl,glk,cnl */
>  	I915_WRITE(GEN8_CHICKEN_DCPR_1,
>  		   I915_READ(GEN8_CHICKEN_DCPR_1) | MASK_WAKEMEM);
>  
> -	/* WaFbcTurnOffFbcWatermark:skl,bxt,kbl */
> -	/* WaFbcWakeMemOn:skl,bxt,kbl,glk */
> +	/* WaFbcTurnOffFbcWatermark:skl,bxt,kbl,cnl */
> +	/* WaFbcWakeMemOn:skl,bxt,kbl,glk,cnl */
>  	I915_WRITE(DISP_ARB_CTL, I915_READ(DISP_ARB_CTL) |
>  		   DISP_FBC_WM_DIS |
>  		   DISP_FBC_MEMORY_WAKE);
>  
> -	/* WaFbcHighMemBwCorruptionAvoidance:skl,bxt,kbl */
> +	/* WaFbcHighMemBwCorruptionAvoidance:skl,bxt,kbl,cnl */
>  	I915_WRITE(ILK_DPFC_CHICKEN, I915_READ(ILK_DPFC_CHICKEN) |
>  		   ILK_DPFC_DISABLE_DUMMY0);
>  }
> @@ -5428,8 +5428,19 @@ int intel_set_rps(struct drm_i915_private *dev_priv, u8 val)
>  
>  static void gen9_disable_rc6(struct drm_i915_private *dev_priv)
>  {
> +	gen9_init_clock_gating(dev_priv);
> +


This may be called from i915_drm_resume_early() through

	intel_uncore_sanitize()
	intel_sanitize_gt_powersave()
	intel_disable_gt_powersave()

at which point power wells haven't been initialized yet. This may cause problems
at least with ILK_DPFC_CHICKEN registers, which requires power well 1 in gen9
devices.

Ander
	

>  	I915_WRITE(GEN6_RC_CONTROL, 0);
>  	I915_WRITE(GEN9_PG_ENABLE, 0);
> +
> +	/* WaDisableGamClockGating:cnl (pre-prod) */
> +	if (IS_CNL_REVID(dev_priv, CNL_REVID_A0, CNL_REVID_A0))
> +		I915_WRITE(GEN6_UCGCTL1, I915_READ(GEN6_UCGCTL1) |
> +			   GEN6_GAMUNIT_CLOCK_GATE_DISABLE);
> +
> +	/* WaFbcNukeOnHostModify:cnl */
> +	I915_WRITE(ILK_DPFC_CHICKEN, I915_READ(ILK_DPFC_CHICKEN) |
> +		   ILK_DPFC_NUKE_ON_ANY_MODIFICATION);
>  }
>  
>  static void gen9_disable_rps(struct drm_i915_private *dev_priv)
> @@ -7474,6 +7485,25 @@ static void gen8_set_l3sqc_credits(struct drm_i915_private *dev_priv,
>  	I915_WRITE(GEN7_MISCCPCTL, misccpctl);
>  }
>  
> +static void cannonlake_init_clock_gating(struct drm_i915_private *dev_priv)
> +{
> +	gen9_init_clock_gating(dev_priv);
> +
> +	/* WaDisableGamClockGating:cnl (pre-prod) */
> +	if (IS_CNL_REVID(dev_priv, CNL_REVID_A0, CNL_REVID_A0))
> +	        I915_WRITE(GEN6_UCGCTL1, I915_READ(GEN6_UCGCTL1) |
> +			   GEN6_GAMUNIT_CLOCK_GATE_DISABLE);
> +
> +	/* WaFbcNukeOnHostModify:cnl */
> +	I915_WRITE(ILK_DPFC_CHICKEN, I915_READ(ILK_DPFC_CHICKEN) |
> +		   ILK_DPFC_NUKE_ON_ANY_MODIFICATION);
> +
> +	/* WaSarbUnitClockGatingDisable:cnl (pre-prod) */
> +	if (IS_CNL_REVID(dev_priv, CNL_REVID_A0, CNL_REVID_B0))
> +		I915_WRITE(SLICE_UNIT_LEVEL_CLKGATE, I915_READ(SLICE_UNIT_LEVEL_CLKGATE) |
> +			   SARBUNIT_CLKGATE_DIS);
> +}
> +
>  static void kabylake_init_clock_gating(struct drm_i915_private *dev_priv)
>  {
>  	gen9_init_clock_gating(dev_priv);
> @@ -7954,7 +7984,9 @@ static void nop_init_clock_gating(struct drm_i915_private *dev_priv)
>   */
>  void intel_init_clock_gating_hooks(struct drm_i915_private *dev_priv)
>  {
> -	if (IS_SKYLAKE(dev_priv))
> +	if (IS_CANNONLAKE(dev_priv))
> +		dev_priv->display.init_clock_gating = cannonlake_init_clock_gating;
> +	else if (IS_SKYLAKE(dev_priv))
>  		dev_priv->display.init_clock_gating = skylake_init_clock_gating;
>  	else if (IS_KABYLAKE(dev_priv))
>  		dev_priv->display.init_clock_gating = kabylake_init_clock_gating;
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[PATCH] drm/i915/cnl: Introduce initial Cannonlake Workarounds.

[Rodrigo Vivi]

Let's inherit workarounds from previous platforms that
according to wa_database and BSpec are still valid for
Cannonlake.

v2: Add missed workarounds.
v3: Rebase
v4: Remove bad chunk that was added to rc6 disable. (Ander)
    Also remove A0 W/a that are not needed anymore.

Cc: Ander Conselvan De Oliveira <ander.conselvan.de.oliveira@intel.com>
Cc: Mika Kuoppala <mika.kuoppala@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
---
 drivers/gpu/drm/i915/i915_gem_gtt.c    |  4 ++--
 drivers/gpu/drm/i915/i915_reg.h        |  6 ++++++
 drivers/gpu/drm/i915/intel_engine_cs.c | 26 ++++++++++++++++++++++++++
 drivers/gpu/drm/i915/intel_lrc.c       |  1 +
 drivers/gpu/drm/i915/intel_pm.c        | 28 ++++++++++++++++++++++------
 5 files changed, 57 insertions(+), 8 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c
index 4ff854e..2166625 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -1884,12 +1884,12 @@ static void gtt_write_workarounds(struct drm_i915_private *dev_priv)
 	 * called on driver load and after a GPU reset, so you can place
 	 * workarounds here even if they get overwritten by GPU reset.
 	 */
-	/* WaIncreaseDefaultTLBEntries:chv,bdw,skl,bxt,kbl,glk */
+	/* WaIncreaseDefaultTLBEntries:chv,bdw,skl,bxt,kbl,glk,cnl */
 	if (IS_BROADWELL(dev_priv))
 		I915_WRITE(GEN8_L3_LRA_1_GPGPU, GEN8_L3_LRA_1_GPGPU_DEFAULT_VALUE_BDW);
 	else if (IS_CHERRYVIEW(dev_priv))
 		I915_WRITE(GEN8_L3_LRA_1_GPGPU, GEN8_L3_LRA_1_GPGPU_DEFAULT_VALUE_CHV);
-	else if (IS_GEN9_BC(dev_priv))
+	else if (IS_GEN9_BC(dev_priv) || IS_GEN10(dev_priv))
 		I915_WRITE(GEN8_L3_LRA_1_GPGPU, GEN9_L3_LRA_1_GPGPU_DEFAULT_VALUE_SKL);
 	else if (IS_GEN9_LP(dev_priv))
 		I915_WRITE(GEN8_L3_LRA_1_GPGPU, GEN9_L3_LRA_1_GPGPU_DEFAULT_VALUE_BXT);
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 48e0b8e..23c82fb 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -3453,6 +3453,12 @@ enum {
 #define   PWM1_GATING_DIS		(1 << 13)
 
 /*
+ * GEN10 clock gating regs
+ */
+#define SLICE_UNIT_LEVEL_CLKGATE	_MMIO(0x94d4)
+#define  SARBUNIT_CLKGATE_DIS		(1 << 5)
+
+/*
  * Display engine regs
  */
 
diff --git a/drivers/gpu/drm/i915/intel_engine_cs.c b/drivers/gpu/drm/i915/intel_engine_cs.c
index bc38bd1..e4a7181 100644
--- a/drivers/gpu/drm/i915/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/intel_engine_cs.c
@@ -1076,6 +1076,30 @@ static int bxt_init_workarounds(struct intel_engine_cs *engine)
 	return 0;
 }
 
+static int cnl_init_workarounds(struct intel_engine_cs *engine)
+{
+	struct drm_i915_private *dev_priv = engine->i915;
+	int ret;
+
+	/* WaInPlaceDecompressionHang:cnl */
+	WA_SET_BIT(GEN9_GAMT_ECO_REG_RW_IA,
+		   GAMT_ECO_ENABLE_IN_PLACE_DECOMPRESS);
+
+	/* WaEnablePreemptionGranularityControlByUMD:cnl */
+	ret= wa_ring_whitelist_reg(engine, GEN8_CS_CHICKEN1);
+	if (ret)
+		return ret;
+
+	/* WaAllowUMDToModifyHDCChicken1:cnl (pre-prod) */
+	if (IS_CNL_REVID(dev_priv, CNL_REVID_A0, CNL_REVID_A0)) {
+		ret = wa_ring_whitelist_reg(engine, GEN8_HDC_CHICKEN1);
+		if (ret)
+			return ret;
+	}
+
+	return 0;
+}
+
 static int kbl_init_workarounds(struct intel_engine_cs *engine)
 {
 	struct drm_i915_private *dev_priv = engine->i915;
@@ -1162,6 +1186,8 @@ int init_workarounds_ring(struct intel_engine_cs *engine)
 		err = kbl_init_workarounds(engine);
 	else if (IS_GEMINILAKE(dev_priv))
 		err =  glk_init_workarounds(engine);
+	else if (IS_CANNONLAKE(dev_priv))
+		err = cnl_init_workarounds(engine);
 	else
 		err = 0;
 	if (err)
diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index d49dbaa..1601ebf 100644
--- a/drivers/gpu/drm/i915/intel_lrc.c
+++ b/drivers/gpu/drm/i915/intel_lrc.c
@@ -1175,6 +1175,7 @@ static int intel_init_workaround_bb(struct intel_engine_cs *engine)
 		return -EINVAL;
 
 	switch (INTEL_GEN(engine->i915)) {
+	case 10:
 	case 9:
 		wa_bb_fn[0] = gen9_init_indirectctx_bb;
 		wa_bb_fn[1] = gen9_init_perctx_bb;
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index aa9d8ce..250e4f0 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -58,24 +58,24 @@
 
 static void gen9_init_clock_gating(struct drm_i915_private *dev_priv)
 {
-	/* See Bspec note for PSR2_CTL bit 31, Wa#828:skl,bxt,kbl */
+	/* See Bspec note for PSR2_CTL bit 31, Wa#828:skl,bxt,kbl,cnl */
 	I915_WRITE(CHICKEN_PAR1_1,
 		   I915_READ(CHICKEN_PAR1_1) | SKL_EDP_PSR_FIX_RDWRAP);
 
 	I915_WRITE(GEN8_CONFIG0,
 		   I915_READ(GEN8_CONFIG0) | GEN9_DEFAULT_FIXES);
 
-	/* WaEnableChickenDCPR:skl,bxt,kbl,glk */
+	/* WaEnableChickenDCPR:skl,bxt,kbl,glk,cnl */
 	I915_WRITE(GEN8_CHICKEN_DCPR_1,
 		   I915_READ(GEN8_CHICKEN_DCPR_1) | MASK_WAKEMEM);
 
-	/* WaFbcTurnOffFbcWatermark:skl,bxt,kbl */
-	/* WaFbcWakeMemOn:skl,bxt,kbl,glk */
+	/* WaFbcTurnOffFbcWatermark:skl,bxt,kbl,cnl */
+	/* WaFbcWakeMemOn:skl,bxt,kbl,glk,cnl */
 	I915_WRITE(DISP_ARB_CTL, I915_READ(DISP_ARB_CTL) |
 		   DISP_FBC_WM_DIS |
 		   DISP_FBC_MEMORY_WAKE);
 
-	/* WaFbcHighMemBwCorruptionAvoidance:skl,bxt,kbl */
+	/* WaFbcHighMemBwCorruptionAvoidance:skl,bxt,kbl,cnl */
 	I915_WRITE(ILK_DPFC_CHICKEN, I915_READ(ILK_DPFC_CHICKEN) |
 		   ILK_DPFC_DISABLE_DUMMY0);
 }
@@ -8298,6 +8298,20 @@ static void gen8_set_l3sqc_credits(struct drm_i915_private *dev_priv,
 	I915_WRITE(GEN7_MISCCPCTL, misccpctl);
 }
 
+static void cannonlake_init_clock_gating(struct drm_i915_private *dev_priv)
+{
+	gen9_init_clock_gating(dev_priv);
+
+	/* WaFbcNukeOnHostModify:cnl */
+	I915_WRITE(ILK_DPFC_CHICKEN, I915_READ(ILK_DPFC_CHICKEN) |
+		   ILK_DPFC_NUKE_ON_ANY_MODIFICATION);
+
+	/* WaSarbUnitClockGatingDisable:cnl (pre-prod) */
+	if (IS_CNL_REVID(dev_priv, CNL_REVID_A0, CNL_REVID_B0))
+		I915_WRITE(SLICE_UNIT_LEVEL_CLKGATE, I915_READ(SLICE_UNIT_LEVEL_CLKGATE) |
+			   SARBUNIT_CLKGATE_DIS);
+}
+
 static void kabylake_init_clock_gating(struct drm_i915_private *dev_priv)
 {
 	gen9_init_clock_gating(dev_priv);
@@ -8778,7 +8792,9 @@ static void nop_init_clock_gating(struct drm_i915_private *dev_priv)
  */
 void intel_init_clock_gating_hooks(struct drm_i915_private *dev_priv)
 {
-	if (IS_SKYLAKE(dev_priv))
+	if (IS_CANNONLAKE(dev_priv))
+		dev_priv->display.init_clock_gating = cannonlake_init_clock_gating;
+	else if (IS_SKYLAKE(dev_priv))
 		dev_priv->display.init_clock_gating = skylake_init_clock_gating;
 	else if (IS_KABYLAKE(dev_priv))
 		dev_priv->display.init_clock_gating = kabylake_init_clock_gating;
-- 
1.9.1

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Re: [PATCH] drm/i915/cnl: Introduce initial Cannonlake Workarounds.

[kbuild test robot]

[-- Attachment #1: Type: text/plain, Size: 3884 bytes --]

Hi Rodrigo,

[auto build test ERROR on drm-intel/for-linux-next]
[also build test ERROR on v4.12-rc4 next-20170607]
[if your patch is applied to the wrong git tree, please drop us a note to help improve the system]

url:    https://github.com/0day-ci/linux/commits/Rodrigo-Vivi/drm-i915-cnl-Introduce-initial-Cannonlake-Workarounds/20170608-041443
base:   git://anongit.freedesktop.org/drm-intel for-linux-next
config: x86_64-randconfig-x014-201723 (attached as .config)
compiler: gcc-6 (Debian 6.2.0-3) 6.2.0 20160901
reproduce:
        # save the attached .config to linux build tree
        make ARCH=x86_64 

All errors (new ones prefixed by >>):

   drivers/gpu//drm/i915/intel_pm.c: In function 'cannonlake_init_clock_gating':
>> drivers/gpu//drm/i915/intel_pm.c:8298:6: error: implicit declaration of function 'IS_CNL_REVID' [-Werror=implicit-function-declaration]
     if (IS_CNL_REVID(dev_priv, CNL_REVID_A0, CNL_REVID_B0))
         ^~~~~~~~~~~~
>> drivers/gpu//drm/i915/intel_pm.c:8298:29: error: 'CNL_REVID_A0' undeclared (first use in this function)
     if (IS_CNL_REVID(dev_priv, CNL_REVID_A0, CNL_REVID_B0))
                                ^~~~~~~~~~~~
   drivers/gpu//drm/i915/intel_pm.c:8298:29: note: each undeclared identifier is reported only once for each function it appears in
>> drivers/gpu//drm/i915/intel_pm.c:8298:43: error: 'CNL_REVID_B0' undeclared (first use in this function)
     if (IS_CNL_REVID(dev_priv, CNL_REVID_A0, CNL_REVID_B0))
                                              ^~~~~~~~~~~~
   drivers/gpu//drm/i915/intel_pm.c: In function 'intel_init_clock_gating_hooks':
>> drivers/gpu//drm/i915/intel_pm.c:8783:6: error: implicit declaration of function 'IS_CANNONLAKE' [-Werror=implicit-function-declaration]
     if (IS_CANNONLAKE(dev_priv))
         ^~~~~~~~~~~~~
   cc1: some warnings being treated as errors
--
   drivers/gpu//drm/i915/i915_gem_gtt.c: In function 'gtt_write_workarounds':
>> drivers/gpu//drm/i915/i915_gem_gtt.c:1892:35: error: implicit declaration of function 'IS_GEN10' [-Werror=implicit-function-declaration]
     else if (IS_GEN9_BC(dev_priv) || IS_GEN10(dev_priv))
                                      ^~~~~~~~
   cc1: some warnings being treated as errors
--
   drivers/gpu//drm/i915/intel_engine_cs.c: In function 'cnl_init_workarounds':
>> drivers/gpu//drm/i915/intel_engine_cs.c:1094:6: error: implicit declaration of function 'IS_CNL_REVID' [-Werror=implicit-function-declaration]
     if (IS_CNL_REVID(dev_priv, CNL_REVID_A0, CNL_REVID_A0)) {
         ^~~~~~~~~~~~
>> drivers/gpu//drm/i915/intel_engine_cs.c:1094:29: error: 'CNL_REVID_A0' undeclared (first use in this function)
     if (IS_CNL_REVID(dev_priv, CNL_REVID_A0, CNL_REVID_A0)) {
                                ^~~~~~~~~~~~
   drivers/gpu//drm/i915/intel_engine_cs.c:1094:29: note: each undeclared identifier is reported only once for each function it appears in
   drivers/gpu//drm/i915/intel_engine_cs.c: In function 'init_workarounds_ring':
>> drivers/gpu//drm/i915/intel_engine_cs.c:1189:11: error: implicit declaration of function 'IS_CANNONLAKE' [-Werror=implicit-function-declaration]
     else if (IS_CANNONLAKE(dev_priv))
              ^~~~~~~~~~~~~
   cc1: some warnings being treated as errors

vim +/IS_CNL_REVID +8298 drivers/gpu//drm/i915/intel_pm.c

  8292	
  8293		/* WaFbcNukeOnHostModify:cnl */
  8294		I915_WRITE(ILK_DPFC_CHICKEN, I915_READ(ILK_DPFC_CHICKEN) |
  8295			   ILK_DPFC_NUKE_ON_ANY_MODIFICATION);
  8296	
  8297		/* WaSarbUnitClockGatingDisable:cnl (pre-prod) */
> 8298		if (IS_CNL_REVID(dev_priv, CNL_REVID_A0, CNL_REVID_B0))
  8299			I915_WRITE(SLICE_UNIT_LEVEL_CLKGATE, I915_READ(SLICE_UNIT_LEVEL_CLKGATE) |
  8300				   SARBUNIT_CLKGATE_DIS);
  8301	}

---
0-DAY kernel test infrastructure                Open Source Technology Center
https://lists.01.org/pipermail/kbuild-all                   Intel Corporation

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[-- Attachment #3: Type: text/plain, Size: 160 bytes --]

_______________________________________________
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Re: [PATCH] drm/i915/cnl: Introduce initial Cannonlake Workarounds.

[kbuild test robot]

[-- Attachment #1: Type: text/plain, Size: 8716 bytes --]

Hi Rodrigo,

[auto build test WARNING on drm-intel/for-linux-next]
[also build test WARNING on v4.12-rc4 next-20170607]
[if your patch is applied to the wrong git tree, please drop us a note to help improve the system]

url:    https://github.com/0day-ci/linux/commits/Rodrigo-Vivi/drm-i915-cnl-Introduce-initial-Cannonlake-Workarounds/20170608-041443
base:   git://anongit.freedesktop.org/drm-intel for-linux-next
config: x86_64-randconfig-x011-201723 (attached as .config)
compiler: gcc-6 (Debian 6.2.0-3) 6.2.0 20160901
reproduce:
        # save the attached .config to linux build tree
        make ARCH=x86_64 

All warnings (new ones prefixed by >>):

   In file included from include/linux/err.h:4:0,
                    from include/linux/clk.h:15,
                    from include/linux/cpufreq.h:14,
                    from drivers/gpu/drm/i915/intel_pm.c:28:
   drivers/gpu/drm/i915/intel_pm.c: In function 'cannonlake_init_clock_gating':
   drivers/gpu/drm/i915/intel_pm.c:8298:6: error: implicit declaration of function 'IS_CNL_REVID' [-Werror=implicit-function-declaration]
     if (IS_CNL_REVID(dev_priv, CNL_REVID_A0, CNL_REVID_B0))
         ^
   include/linux/compiler.h:160:30: note: in definition of macro '__trace_if'
     if (__builtin_constant_p(!!(cond)) ? !!(cond) :   \
                                 ^~~~
>> drivers/gpu/drm/i915/intel_pm.c:8298:2: note: in expansion of macro 'if'
     if (IS_CNL_REVID(dev_priv, CNL_REVID_A0, CNL_REVID_B0))
     ^~
   drivers/gpu/drm/i915/intel_pm.c:8298:29: error: 'CNL_REVID_A0' undeclared (first use in this function)
     if (IS_CNL_REVID(dev_priv, CNL_REVID_A0, CNL_REVID_B0))
                                ^
   include/linux/compiler.h:160:30: note: in definition of macro '__trace_if'
     if (__builtin_constant_p(!!(cond)) ? !!(cond) :   \
                                 ^~~~
>> drivers/gpu/drm/i915/intel_pm.c:8298:2: note: in expansion of macro 'if'
     if (IS_CNL_REVID(dev_priv, CNL_REVID_A0, CNL_REVID_B0))
     ^~
   drivers/gpu/drm/i915/intel_pm.c:8298:29: note: each undeclared identifier is reported only once for each function it appears in
     if (IS_CNL_REVID(dev_priv, CNL_REVID_A0, CNL_REVID_B0))
                                ^
   include/linux/compiler.h:160:30: note: in definition of macro '__trace_if'
     if (__builtin_constant_p(!!(cond)) ? !!(cond) :   \
                                 ^~~~
>> drivers/gpu/drm/i915/intel_pm.c:8298:2: note: in expansion of macro 'if'
     if (IS_CNL_REVID(dev_priv, CNL_REVID_A0, CNL_REVID_B0))
     ^~
   drivers/gpu/drm/i915/intel_pm.c:8298:43: error: 'CNL_REVID_B0' undeclared (first use in this function)
     if (IS_CNL_REVID(dev_priv, CNL_REVID_A0, CNL_REVID_B0))
                                              ^
   include/linux/compiler.h:160:30: note: in definition of macro '__trace_if'
     if (__builtin_constant_p(!!(cond)) ? !!(cond) :   \
                                 ^~~~
>> drivers/gpu/drm/i915/intel_pm.c:8298:2: note: in expansion of macro 'if'
     if (IS_CNL_REVID(dev_priv, CNL_REVID_A0, CNL_REVID_B0))
     ^~
   drivers/gpu/drm/i915/intel_pm.c: In function 'intel_init_clock_gating_hooks':
   drivers/gpu/drm/i915/intel_pm.c:8783:6: error: implicit declaration of function 'IS_CANNONLAKE' [-Werror=implicit-function-declaration]
     if (IS_CANNONLAKE(dev_priv))
         ^
   include/linux/compiler.h:160:30: note: in definition of macro '__trace_if'
     if (__builtin_constant_p(!!(cond)) ? !!(cond) :   \
                                 ^~~~
   drivers/gpu/drm/i915/intel_pm.c:8783:2: note: in expansion of macro 'if'
     if (IS_CANNONLAKE(dev_priv))
     ^~
   cc1: some warnings being treated as errors
--
   In file included from include/asm-generic/bug.h:4:0,
                    from arch/x86/include/asm/bug.h:81,
                    from include/linux/bug.h:4,
                    from include/linux/mmdebug.h:4,
                    from include/linux/gfp.h:4,
                    from include/linux/slab.h:14,
                    from drivers/gpu/drm/i915/i915_gem_gtt.c:26:
   drivers/gpu/drm/i915/i915_gem_gtt.c: In function 'gtt_write_workarounds':
   drivers/gpu/drm/i915/i915_gem_gtt.c:1892:35: error: implicit declaration of function 'IS_GEN10' [-Werror=implicit-function-declaration]
     else if (IS_GEN9_BC(dev_priv) || IS_GEN10(dev_priv))
                                      ^
   include/linux/compiler.h:160:30: note: in definition of macro '__trace_if'
     if (__builtin_constant_p(!!(cond)) ? !!(cond) :   \
                                 ^~~~
>> drivers/gpu/drm/i915/i915_gem_gtt.c:1892:7: note: in expansion of macro 'if'
     else if (IS_GEN9_BC(dev_priv) || IS_GEN10(dev_priv))
          ^~
   cc1: some warnings being treated as errors
--
   In file included from include/uapi/linux/stddef.h:1:0,
                    from include/linux/stddef.h:4,
                    from include/uapi/linux/posix_types.h:4,
                    from include/uapi/linux/types.h:13,
                    from include/linux/types.h:5,
                    from include/uapi/drm/drm.h:41,
                    from include/uapi/drm/i915_drm.h:30,
                    from drivers/gpu/drm/i915/i915_drv.h:33,
                    from drivers/gpu/drm/i915/intel_engine_cs.c:25:
   drivers/gpu/drm/i915/intel_engine_cs.c: In function 'cnl_init_workarounds':
   drivers/gpu/drm/i915/intel_engine_cs.c:1094:6: error: implicit declaration of function 'IS_CNL_REVID' [-Werror=implicit-function-declaration]
     if (IS_CNL_REVID(dev_priv, CNL_REVID_A0, CNL_REVID_A0)) {
         ^
   include/linux/compiler.h:160:30: note: in definition of macro '__trace_if'
     if (__builtin_constant_p(!!(cond)) ? !!(cond) :   \
                                 ^~~~
>> drivers/gpu/drm/i915/intel_engine_cs.c:1094:2: note: in expansion of macro 'if'
     if (IS_CNL_REVID(dev_priv, CNL_REVID_A0, CNL_REVID_A0)) {
     ^~
   drivers/gpu/drm/i915/intel_engine_cs.c:1094:29: error: 'CNL_REVID_A0' undeclared (first use in this function)
     if (IS_CNL_REVID(dev_priv, CNL_REVID_A0, CNL_REVID_A0)) {
                                ^
   include/linux/compiler.h:160:30: note: in definition of macro '__trace_if'
     if (__builtin_constant_p(!!(cond)) ? !!(cond) :   \
                                 ^~~~
>> drivers/gpu/drm/i915/intel_engine_cs.c:1094:2: note: in expansion of macro 'if'
     if (IS_CNL_REVID(dev_priv, CNL_REVID_A0, CNL_REVID_A0)) {
     ^~
   drivers/gpu/drm/i915/intel_engine_cs.c:1094:29: note: each undeclared identifier is reported only once for each function it appears in
     if (IS_CNL_REVID(dev_priv, CNL_REVID_A0, CNL_REVID_A0)) {
                                ^
   include/linux/compiler.h:160:30: note: in definition of macro '__trace_if'
     if (__builtin_constant_p(!!(cond)) ? !!(cond) :   \
                                 ^~~~
>> drivers/gpu/drm/i915/intel_engine_cs.c:1094:2: note: in expansion of macro 'if'
     if (IS_CNL_REVID(dev_priv, CNL_REVID_A0, CNL_REVID_A0)) {
     ^~
   drivers/gpu/drm/i915/intel_engine_cs.c: In function 'init_workarounds_ring':
   drivers/gpu/drm/i915/intel_engine_cs.c:1189:11: error: implicit declaration of function 'IS_CANNONLAKE' [-Werror=implicit-function-declaration]
     else if (IS_CANNONLAKE(dev_priv))
              ^
   include/linux/compiler.h:160:30: note: in definition of macro '__trace_if'
     if (__builtin_constant_p(!!(cond)) ? !!(cond) :   \
                                 ^~~~
   drivers/gpu/drm/i915/intel_engine_cs.c:1189:7: note: in expansion of macro 'if'
     else if (IS_CANNONLAKE(dev_priv))
          ^~
   cc1: some warnings being treated as errors

vim +/if +8298 drivers/gpu/drm/i915/intel_pm.c

  8282		 * See the definition of L3SQCREG1 in BSpec.
  8283		 */
  8284		POSTING_READ(GEN8_L3SQCREG1);
  8285		udelay(1);
  8286		I915_WRITE(GEN7_MISCCPCTL, misccpctl);
  8287	}
  8288	
  8289	static void cannonlake_init_clock_gating(struct drm_i915_private *dev_priv)
  8290	{
  8291		gen9_init_clock_gating(dev_priv);
  8292	
  8293		/* WaFbcNukeOnHostModify:cnl */
  8294		I915_WRITE(ILK_DPFC_CHICKEN, I915_READ(ILK_DPFC_CHICKEN) |
  8295			   ILK_DPFC_NUKE_ON_ANY_MODIFICATION);
  8296	
  8297		/* WaSarbUnitClockGatingDisable:cnl (pre-prod) */
> 8298		if (IS_CNL_REVID(dev_priv, CNL_REVID_A0, CNL_REVID_B0))
  8299			I915_WRITE(SLICE_UNIT_LEVEL_CLKGATE, I915_READ(SLICE_UNIT_LEVEL_CLKGATE) |
  8300				   SARBUNIT_CLKGATE_DIS);
  8301	}
  8302	
  8303	static void kabylake_init_clock_gating(struct drm_i915_private *dev_priv)
  8304	{
  8305		gen9_init_clock_gating(dev_priv);
  8306	

---
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[PATCH 13/67] drm/i915/cnl: Add WaDisableReplayBufferBankArbitrationOptimization

[Rodrigo Vivi]

WA to disable replay buffer destination buffer arbitration optimization.

Same Wa on previous platforms has a different name: WaToEnableHwFixForPushConstHWBug

Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
---
 drivers/gpu/drm/i915/intel_engine_cs.c | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_engine_cs.c b/drivers/gpu/drm/i915/intel_engine_cs.c
index da819a7..7a3c8ab 100644
--- a/drivers/gpu/drm/i915/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/intel_engine_cs.c
@@ -951,6 +951,10 @@ static int cnl_init_workarounds(struct intel_engine_cs *engine)
 	struct drm_i915_private *dev_priv = engine->i915;
 	int ret;
 
+	/* WaDisableReplayBufferBankArbitrationOptimization:cnl */
+	WA_SET_BIT_MASKED(COMMON_SLICE_CHICKEN2,
+			  GEN8_SBE_DISABLE_REPLAY_BUF_OPTIMIZATION);
+
 	/* WaInPlaceDecompressionHang:cnl */
 	WA_SET_BIT(GEN9_GAMT_ECO_REG_RW_IA,
 		   GAMT_ECO_ENABLE_IN_PLACE_DECOMPRESS);
-- 
1.9.1

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Re: [PATCH 13/67] drm/i915/cnl: Add WaDisableReplayBufferBankArbitrationOptimization

[Mika Kuoppala]

Rodrigo Vivi <rodrigo.vivi@intel.com> writes:

> WA to disable replay buffer destination buffer arbitration optimization.
>
> Same Wa on previous platforms has a different name: WaToEnableHwFixForPushConstHWBug
>
> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
> ---
>  drivers/gpu/drm/i915/intel_engine_cs.c | 4 ++++
>  1 file changed, 4 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/intel_engine_cs.c b/drivers/gpu/drm/i915/intel_engine_cs.c
> index da819a7..7a3c8ab 100644
> --- a/drivers/gpu/drm/i915/intel_engine_cs.c
> +++ b/drivers/gpu/drm/i915/intel_engine_cs.c
> @@ -951,6 +951,10 @@ static int cnl_init_workarounds(struct intel_engine_cs *engine)
>  	struct drm_i915_private *dev_priv = engine->i915;
>  	int ret;
>
> +	/* WaDisableReplayBufferBankArbitrationOptimization:cnl */
> +	WA_SET_BIT_MASKED(COMMON_SLICE_CHICKEN2,
> +			  GEN8_SBE_DISABLE_REPLAY_BUF_OPTIMIZATION);
> +

It is from B0 ->
But I dont think it hurts to have this blanket approach.

Reviewed-by: Mika Kuoppala <mika.kuoppala@intel.com>

>  	/* WaInPlaceDecompressionHang:cnl */
>  	WA_SET_BIT(GEN9_GAMT_ECO_REG_RW_IA,
>  		   GAMT_ECO_ENABLE_IN_PLACE_DECOMPRESS);
> -- 
> 1.9.1
>
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> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
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Re: [PATCH 13/67] drm/i915/cnl: Add WaDisableReplayBufferBankArbitrationOptimization

[Vivi, Rodrigo]

On Thu, 2017-06-08 at 19:54 +0300, Mika Kuoppala wrote:
> Rodrigo Vivi <rodrigo.vivi@intel.com> writes:
> 
> > WA to disable replay buffer destination buffer arbitration optimization.
> >
> > Same Wa on previous platforms has a different name: WaToEnableHwFixForPushConstHWBug
> >
> > Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
> > ---
> >  drivers/gpu/drm/i915/intel_engine_cs.c | 4 ++++
> >  1 file changed, 4 insertions(+)
> >
> > diff --git a/drivers/gpu/drm/i915/intel_engine_cs.c b/drivers/gpu/drm/i915/intel_engine_cs.c
> > index da819a7..7a3c8ab 100644
> > --- a/drivers/gpu/drm/i915/intel_engine_cs.c
> > +++ b/drivers/gpu/drm/i915/intel_engine_cs.c
> > @@ -951,6 +951,10 @@ static int cnl_init_workarounds(struct intel_engine_cs *engine)
> >  	struct drm_i915_private *dev_priv = engine->i915;
> >  	int ret;
> >
> > +	/* WaDisableReplayBufferBankArbitrationOptimization:cnl */
> > +	WA_SET_BIT_MASKED(COMMON_SLICE_CHICKEN2,
> > +			  GEN8_SBE_DISABLE_REPLAY_BUF_OPTIMIZATION);
> > +
> 
> It is from B0 ->
> But I dont think it hurts to have this blanket approach.

we will never see an A0, so it is ok ;)

> 
> Reviewed-by: Mika Kuoppala <mika.kuoppala@intel.com>

Thanks

> 
> >  	/* WaInPlaceDecompressionHang:cnl */
> >  	WA_SET_BIT(GEN9_GAMT_ECO_REG_RW_IA,
> >  		   GAMT_ECO_ENABLE_IN_PLACE_DECOMPRESS);
> > -- 
> > 1.9.1
> >
> > _______________________________________________
> > Intel-gfx mailing list
> > Intel-gfx@lists.freedesktop.org
> > https://lists.freedesktop.org/mailman/listinfo/intel-gfx

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[PATCH 14/67] drm/i915/cnl: WaDisableEnhancedSBEVertexCaching

[Rodrigo Vivi]

WA forTDS handle reallocation getting dropped by SDE,
which may result in PS attribute corruption.

Disable enhanced SBE vertex caching in COMMON_SLICE_CHICKEN2 offset.

Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
---
 drivers/gpu/drm/i915/intel_engine_cs.c | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_engine_cs.c b/drivers/gpu/drm/i915/intel_engine_cs.c
index 7a3c8ab..b5599fa 100644
--- a/drivers/gpu/drm/i915/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/intel_engine_cs.c
@@ -955,6 +955,10 @@ static int cnl_init_workarounds(struct intel_engine_cs *engine)
 	WA_SET_BIT_MASKED(COMMON_SLICE_CHICKEN2,
 			  GEN8_SBE_DISABLE_REPLAY_BUF_OPTIMIZATION);
 
+	/* WaDisableEnhancedSBEVertexCaching:cnl */
+	WA_SET_BIT_MASKED(COMMON_SLICE_CHICKEN2,
+			  GEN8_CSC2_SBE_VUE_CACHE_CONSERVATIVE);
+
 	/* WaInPlaceDecompressionHang:cnl */
 	WA_SET_BIT(GEN9_GAMT_ECO_REG_RW_IA,
 		   GAMT_ECO_ENABLE_IN_PLACE_DECOMPRESS);
-- 
1.9.1

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Re: [PATCH 14/67] drm/i915/cnl: WaDisableEnhancedSBEVertexCaching

[Mika Kuoppala]

Rodrigo Vivi <rodrigo.vivi@intel.com> writes:

> WA forTDS handle reallocation getting dropped by SDE,
> which may result in PS attribute corruption.
>
> Disable enhanced SBE vertex caching in COMMON_SLICE_CHICKEN2 offset.
>
> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
> ---
>  drivers/gpu/drm/i915/intel_engine_cs.c | 4 ++++
>  1 file changed, 4 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/intel_engine_cs.c b/drivers/gpu/drm/i915/intel_engine_cs.c
> index 7a3c8ab..b5599fa 100644
> --- a/drivers/gpu/drm/i915/intel_engine_cs.c
> +++ b/drivers/gpu/drm/i915/intel_engine_cs.c
> @@ -955,6 +955,10 @@ static int cnl_init_workarounds(struct intel_engine_cs *engine)
>  	WA_SET_BIT_MASKED(COMMON_SLICE_CHICKEN2,
>  			  GEN8_SBE_DISABLE_REPLAY_BUF_OPTIMIZATION);
>  
> +	/* WaDisableEnhancedSBEVertexCaching:cnl */
> +	WA_SET_BIT_MASKED(COMMON_SLICE_CHICKEN2,
> +			  GEN8_CSC2_SBE_VUE_CACHE_CONSERVATIVE);
> +

+ if (IS_CNL_REVID(dev_priv, 0, B0)

Let's trust the documentation in this case and hope we don't need to
regret.

With that changed,

Reviewed-by: Mika Kuoppala <mika.kuoppala@intel.com>


>  	/* WaInPlaceDecompressionHang:cnl */
>  	WA_SET_BIT(GEN9_GAMT_ECO_REG_RW_IA,
>  		   GAMT_ECO_ENABLE_IN_PLACE_DECOMPRESS);
> -- 
> 1.9.1
>
> _______________________________________________
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> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
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[PATCH 15/67] drm/i915/cnl: Apply large line width optimization

[Rodrigo Vivi]

From: Ben Widawsky <ben@bwidawsk.net>

This bit enables hardware that will change the approximation used for distances
calculations for AA wide lines so that they are rendered more accurately.

The default value for this bit leaves the legacy behavior. There is no good
reason to not enable the new approximation except if comparing to previous GEN
rendered images.

Signed-off-by: Ben Widawsky <benjamin.widawsky@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h | 1 +
 drivers/gpu/drm/i915/intel_pm.c | 3 +++
 2 files changed, 4 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index a09a0d7..98e89e6 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -2105,6 +2105,7 @@ enum skl_disp_power_wells {
 # define _3D_CHICKEN2_WM_READ_PIPELINED			(1 << 14)
 #define _3D_CHICKEN3	_MMIO(0x2090)
 #define  _3D_CHICKEN_SF_DISABLE_OBJEND_CULL		(1 << 10)
+#define  _3D_CHICKEN3_AA_LINE_QUALITY_FIX_ENABLE	(1 << 5)
 #define  _3D_CHICKEN3_SF_DISABLE_FASTCLIP_CULL		(1 << 5)
 #define  _3D_CHICKEN_SDE_LIMIT_FIFO_POLY_DEPTH(x)	((x)<<1) /* gen8+ */
 #define  _3D_CHICKEN3_SF_DISABLE_PIPELINED_ATTR_FETCH	(1 << 1) /* gen6 */
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index b6ecab9..798e55f 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -7489,6 +7489,9 @@ static void cannonlake_init_clock_gating(struct drm_i915_private *dev_priv)
 {
 	gen9_init_clock_gating(dev_priv);
 
+	I915_WRITE(_3D_CHICKEN3,
+		   _MASKED_BIT_ENABLE(_3D_CHICKEN3_AA_LINE_QUALITY_FIX_ENABLE));
+
 	/* WaDisableGamClockGating:cnl (pre-prod) */
 	if (IS_CNL_REVID(dev_priv, CNL_REVID_A0, CNL_REVID_A0))
 	        I915_WRITE(GEN6_UCGCTL1, I915_READ(GEN6_UCGCTL1) |
-- 
1.9.1

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[PATCH 16/67] drm/i915/cnl: Cannonlake has 4 planes (3 sprites) per pipe

[Rodrigo Vivi]

From: James Irwin <james.irwin@intel.com>

Issue: VIZ-4525

Reviewed-by: Damien Lespiau <damien.lespiau@intel.com>
Signed-off-by: James Irwin <james.irwin@intel.com>
Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
---
 drivers/gpu/drm/i915/intel_device_info.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/intel_device_info.c b/drivers/gpu/drm/i915/intel_device_info.c
index 6b09a82..3cc8cdb 100644
--- a/drivers/gpu/drm/i915/intel_device_info.c
+++ b/drivers/gpu/drm/i915/intel_device_info.c
@@ -328,7 +328,7 @@ void intel_device_info_runtime_init(struct drm_i915_private *dev_priv)
 	 * we don't expose the topmost plane at all to prevent ABI breakage
 	 * down the line.
 	 */
-	if (IS_GEMINILAKE(dev_priv))
+	if (IS_GEN10(dev_priv) || IS_GEMINILAKE(dev_priv))
 		for_each_pipe(dev_priv, pipe)
 			info->num_sprites[pipe] = 3;
 	else if (IS_BROXTON(dev_priv)) {
-- 
1.9.1

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Re: [PATCH 16/67] drm/i915/cnl: Cannonlake has 4 planes (3 sprites) per pipe

[Ander Conselvan De Oliveira]

On Thu, 2017-04-06 at 12:15 -0700, Rodrigo Vivi wrote:
> From: James Irwin <james.irwin@intel.com>
> 
> Issue: VIZ-4525
> 
> Reviewed-by: Damien Lespiau <damien.lespiau@intel.com>
> Signed-off-by: James Irwin <james.irwin@intel.com>
> Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>

Reviewed-by: Ander Conselvan de Oliveira <conselvan2@gmail.com>

> ---
>  drivers/gpu/drm/i915/intel_device_info.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_device_info.c b/drivers/gpu/drm/i915/intel_device_info.c
> index 6b09a82..3cc8cdb 100644
> --- a/drivers/gpu/drm/i915/intel_device_info.c
> +++ b/drivers/gpu/drm/i915/intel_device_info.c
> @@ -328,7 +328,7 @@ void intel_device_info_runtime_init(struct drm_i915_private *dev_priv)
>  	 * we don't expose the topmost plane at all to prevent ABI breakage
>  	 * down the line.
>  	 */
> -	if (IS_GEMINILAKE(dev_priv))
> +	if (IS_GEN10(dev_priv) || IS_GEMINILAKE(dev_priv))
>  		for_each_pipe(dev_priv, pipe)
>  			info->num_sprites[pipe] = 3;
>  	else if (IS_BROXTON(dev_priv)) {
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[PATCH 17/67] drm/i915/cnl: CNL has an increased DDB size

[Rodrigo Vivi]

From: Damien Lespiau <damien.lespiau@intel.com>

Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
---
 drivers/gpu/drm/i915/i915_pci.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index cb01822..c84ef7c 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -436,7 +436,7 @@
 	.is_alpha_support = 1,
 	.platform = INTEL_CANNONLAKE,
 	.gen = 10,
-	.ddb_size = 896,
+	.ddb_size = 1024,
 };
 
 /*
-- 
1.9.1

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[PATCH 18/67] drm/i915/cnl: Add initial gen10 golden states.

[Rodrigo Vivi]

XXX: based on gen9 render commands at this point.

Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
---
 drivers/gpu/drm/i915/Makefile                  |   3 +-
 drivers/gpu/drm/i915/i915_gem_render_state.c   |   2 +
 drivers/gpu/drm/i915/intel_renderstate.h       |   1 +
 drivers/gpu/drm/i915/intel_renderstate_gen10.c | 974 +++++++++++++++++++++++++
 4 files changed, 979 insertions(+), 1 deletion(-)
 create mode 100644 drivers/gpu/drm/i915/intel_renderstate_gen10.c

diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index 2cf0450..fc99c81 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -66,7 +66,8 @@ i915-y += intel_uc.o \
 i915-y += intel_renderstate_gen6.o \
 	  intel_renderstate_gen7.o \
 	  intel_renderstate_gen8.o \
-	  intel_renderstate_gen9.o
+	  intel_renderstate_gen9.o \
+	  intel_renderstate_gen10.o
 
 # modesetting core code
 i915-y += intel_audio.o \
diff --git a/drivers/gpu/drm/i915/i915_gem_render_state.c b/drivers/gpu/drm/i915/i915_gem_render_state.c
index 7032c54..12d7036 100644
--- a/drivers/gpu/drm/i915/i915_gem_render_state.c
+++ b/drivers/gpu/drm/i915/i915_gem_render_state.c
@@ -49,6 +49,8 @@ struct intel_render_state {
 		return &gen8_null_state;
 	case 9:
 		return &gen9_null_state;
+	case 10:
+		return &gen10_null_state;
 	}
 
 	return NULL;
diff --git a/drivers/gpu/drm/i915/intel_renderstate.h b/drivers/gpu/drm/i915/intel_renderstate.h
index 08f6fea..3ee3641 100644
--- a/drivers/gpu/drm/i915/intel_renderstate.h
+++ b/drivers/gpu/drm/i915/intel_renderstate.h
@@ -43,5 +43,6 @@ struct intel_renderstate_rodata {
 extern const struct intel_renderstate_rodata gen7_null_state;
 extern const struct intel_renderstate_rodata gen8_null_state;
 extern const struct intel_renderstate_rodata gen9_null_state;
+extern const struct intel_renderstate_rodata gen10_null_state;
 
 #endif /* INTEL_RENDERSTATE_H */
diff --git a/drivers/gpu/drm/i915/intel_renderstate_gen10.c b/drivers/gpu/drm/i915/intel_renderstate_gen10.c
new file mode 100644
index 0000000..9c00339
--- /dev/null
+++ b/drivers/gpu/drm/i915/intel_renderstate_gen10.c
@@ -0,0 +1,974 @@
+#include "intel_renderstate.h"
+
+static const u32 gen10_null_state_relocs[] = {
+	0x000007a8,
+	0x000007b4,
+	0x000007bc,
+	0x000007cc,
+	-1,
+};
+
+static const u32 gen10_null_state_batch[] = {
+	0x7a000004,
+	0x01000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x69040300,
+	0x78140000,
+	0x04000000,
+	0x7820000a,
+	0x00000000,
+	0x00000000,
+	0x80000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x78130002,
+	0x00000000,
+	0x00000000,
+	0x02001808,
+	0x781f0004,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x78510009,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x78100007,
+	0x00000000,
+	0x00000000,
+	0x00010000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x781b0007,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000800,
+	0x00000000,
+	0x78110008,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x781e0003,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x781d0009,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x78120002,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x78500003,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x781c0002,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x780c0000,
+	0x00000000,
+	0x78520003,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x78300000,
+	0x08010040,
+	0x78310000,
+	0x1e000000,
+	0x78320000,
+	0x1e000000,
+	0x78330000,
+	0x1e000000,
+	0x79190002,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x791a0002,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x791b0002,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x79120000,
+	0x00000000,
+	0x79130000,
+	0x00000000,
+	0x79140000,
+	0x00000000,
+	0x79150000,
+	0x00000000,
+	0x79160000,
+	0x00000000,
+	0x78150009,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x78190009,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x781a0009,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x78160009,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x78170009,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x78490001,
+	0x00000000,
+	0x00000000,
+	0x784a0000,
+	0x00000000,
+	0x784b0000,
+	0x00000004,
+	0x79170101,
+	0x00000000,
+	0x00000080,
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+	0x00000000,
+	0x00000000,
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+	0x00000000,
+	0x00000000,
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+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x79180006,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x79180006,
+	0x20000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x79180006,
+	0x40000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x79180006,
+	0x60000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x61010011,
+	0x00000001,	 /* reloc */
+	0x00000000,
+	0x00000000,
+	0x00000001,	 /* reloc */
+	0x00000000,
+	0x00000001,	 /* reloc */
+	0x00000000,
+	0x00000001,
+	0x00000000,
+	0x00000001,	 /* reloc */
+	0x00000000,
+	0x00001001,
+	0x00001001,
+	0x00000001,
+	0x00001001,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x61020001,
+	0x00000000,
+	0x00000000,
+	0x79000002,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x78050006,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x79040002,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x79040002,
+	0x40000000,
+	0x00000000,
+	0x00000000,
+	0x79040002,
+	0x80000000,
+	0x00000000,
+	0x00000000,
+	0x79040002,
+	0xc0000000,
+	0x00000000,
+	0x00000000,
+	0x79080001,
+	0x00000000,
+	0x00000000,
+	0x790a0001,
+	0x00000000,
+	0x00000000,
+	0x78060003,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x78070003,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x78040001,
+	0x00000000,
+	0x00000000,
+	0x79110000,
+	0x00000000,
+	0x780d0000,
+	0x00000000,
+	0x79060000,
+	0x00000000,
+	0x7907001f,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
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+	0x00000000,
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+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x7902000f,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x790c000f,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x780a0003,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x78080083,
+	0x00004000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x04004000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x08004000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x0c004000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x10004000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x14004000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x18004000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x1c004000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x20004000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x24004000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x28004000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x2c004000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x30004000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x34004000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x38004000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x3c004000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x40004000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x44004000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x48004000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x4c004000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x50004000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x54004000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x58004000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x5c004000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x60004000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x64004000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x68004000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x6c004000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x70004000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x74004000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x78004000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x7c004000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x80004000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x78090043,
+	0x02000000,
+	0x22220000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x78550003,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x680b0001,
+	0x780e0000,
+	0x00000e01,
+	0x78240000,
+	0x00000e41,
+	0x784f0000,
+	0x80000100,
+	0x784d0000,
+	0x40000000,
+	0x782b0000,
+	0x00000000,
+	0x782c0000,
+	0x00000000,
+	0x782d0000,
+	0x00000000,
+	0x782e0000,
+	0x00000000,
+	0x782f0000,
+	0x00000000,
+	0x780f0000,
+	0x00000000,
+	0x78230000,
+	0x00000ea0,
+	0x78210000,
+	0x00000ec0,
+	0x78260000,
+	0x00000000,
+	0x78270000,
+	0x00000000,
+	0x78280000,
+	0x00000000,
+	0x78290000,
+	0x00000000,
+	0x782a0000,
+	0x00000000,
+	0x7b000005,
+	0x00000004,
+	0x00000001,
+	0x00000000,
+	0x00000001,
+	0x00000000,
+	0x00000000,
+	0x05000000,	 /* cmds end */
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,	 /* state start */
+	0x00000000,
+	0x3f800000,
+	0x3f800000,
+	0x3f800000,
+	0x3f800000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,	 /* state end */
+};
+
+RO_RENDERSTATE(10);
-- 
1.9.1

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[PATCH 19/67] drm/i915/cnl: Configure EU slice power gating.

[Rodrigo Vivi]

Cannonlake also supports slice power gating on devices with more
than one slice as SKL. Let's assume that this is the same for SKL+
and exclude BXT only.

v2: Also remove KBL.

Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
---
 drivers/gpu/drm/i915/intel_device_info.c | 7 +++----
 1 file changed, 3 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_device_info.c b/drivers/gpu/drm/i915/intel_device_info.c
index 3cc8cdb..5ae9a80 100644
--- a/drivers/gpu/drm/i915/intel_device_info.c
+++ b/drivers/gpu/drm/i915/intel_device_info.c
@@ -184,16 +184,15 @@ static void gen9_sseu_info_init(struct drm_i915_private *dev_priv)
 				DIV_ROUND_UP(sseu->eu_total,
 					     sseu_subslice_total(sseu)) : 0;
 	/*
-	 * SKL supports slice power gating on devices with more than
+	 * SKL+ supports slice power gating on devices with more than
 	 * one slice, and supports EU power gating on devices with
-	 * more than one EU pair per subslice. BXT supports subslice
+	 * more than one EU pair per subslice. BXT+ supports subslice
 	 * power gating on devices with more than one subslice, and
 	 * supports EU power gating on devices with more than one EU
 	 * pair per subslice.
 	*/
 	sseu->has_slice_pg =
-		(IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) &&
-		hweight8(sseu->slice_mask) > 1;
+		!IS_GEN9_LP(dev_priv) && hweight8(sseu->slice_mask) > 1;
 	sseu->has_subslice_pg =
 		IS_GEN9_LP(dev_priv) && sseu_subslice_total(sseu) > 1;
 	sseu->has_eu_pg = sseu->eu_per_subslice > 2;
-- 
1.9.1

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Re: [PATCH 19/67] drm/i915/cnl: Configure EU slice power gating.

[Joonas Lahtinen]

On to, 2017-04-06 at 12:15 -0700, Rodrigo Vivi wrote:
> Cannonlake also supports slice power gating on devices with more
> than one slice as SKL. Let's assume that this is the same for SKL+
> and exclude BXT only.
> 
> v2: Also remove KBL.
> 

Bspec: 12566

> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>

Reviewed-by: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>

Regards, Joonas
-- 
Joonas Lahtinen
Open Source Technology Center
Intel Corporation
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[PATCH 20/67] drm/i915/cnl: Cannonlake has same MOCS table than Skylake.

[Rodrigo Vivi]

All registers and default configuration are the same for Skylake
and Cannonlake.

v2: Don't apply Wa for platforms without MOCS. (Paulo)

Cc: Paulo Zanoni <paulo.r.zanoni@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
---
 drivers/gpu/drm/i915/intel_mocs.c | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_mocs.c b/drivers/gpu/drm/i915/intel_mocs.c
index 92e461c..4143b12 100644
--- a/drivers/gpu/drm/i915/intel_mocs.c
+++ b/drivers/gpu/drm/i915/intel_mocs.c
@@ -178,7 +178,7 @@ static bool get_mocs_settings(struct drm_i915_private *dev_priv,
 {
 	bool result = false;
 
-	if (IS_GEN9_BC(dev_priv)) {
+	if (IS_GEN9_BC(dev_priv) || IS_CANNONLAKE(dev_priv)) {
 		table->size  = ARRAY_SIZE(skylake_mocs_table);
 		table->table = skylake_mocs_table;
 		result = true;
@@ -191,8 +191,8 @@ static bool get_mocs_settings(struct drm_i915_private *dev_priv,
 			  "Platform that should have a MOCS table does not.\n");
 	}
 
-	/* WaDisableSkipCaching:skl,bxt,kbl,glk */
-	if (IS_GEN9(dev_priv)) {
+	/* WaDisableSkipCaching:skl,bxt,kbl,glk,cnl */
+	if (IS_GEN9(dev_priv) || IS_CANNONLAKE(dev_priv)) {
 		int i;
 
 		for (i = 0; i < table->size; i++)
-- 
1.9.1

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Re: [PATCH 20/67] drm/i915/cnl: Cannonlake has same MOCS table than Skylake.

[Joonas Lahtinen]

On to, 2017-04-06 at 12:15 -0700, Rodrigo Vivi wrote:
> All registers and default configuration are the same for Skylake
> and Cannonlake.
> 
> v2: Don't apply Wa for platforms without MOCS. (Paulo)
> 
> Cc: Paulo Zanoni <paulo.r.zanoni@intel.com>
> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>

Bspec: 12239

> @@ -191,8 +191,8 @@ static bool get_mocs_settings(struct drm_i915_private *dev_priv,
>  			  "Platform that should have a MOCS table does not.\n");
>  	}
>  
> -	/* WaDisableSkipCaching:skl,bxt,kbl,glk */
> -	if (IS_GEN9(dev_priv)) {
> +	/* WaDisableSkipCaching:skl,bxt,kbl,glk,cnl */
> +	if (IS_GEN9(dev_priv) || IS_CANNONLAKE(dev_priv)) {

This is not applicable (or spec needs to be fixed). With just applying
the mocs table;

Reviewed-by: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>

Regards, Joonas
-- 
Joonas Lahtinen
Open Source Technology Center
Intel Corporation
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[PATCH 21/67] drm/i915/cnl: Update the context size

[Rodrigo Vivi]

From: Ben Widawsky <benjamin.widawsky@intel.com>

The docs are not yet correct, so I cannot provide a reference to it. In the
current docs, the size is actually smaller than SKL. This seems unlikely given
that in another part of the docs there are clearly more engines stored within
the context image.

!UPSTREAM: I got this number from the Windows driver, but we should add the right
reference to the docs when we have it..

v2: (Rodrigo) Fixup the missing break identified by Tvrtko.

Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Signed-off-by: Ben Widawsky <benjamin.widawsky@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
---
 drivers/gpu/drm/i915/intel_lrc.c | 14 ++++++++++++--
 1 file changed, 12 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index 23e2bed..058d5f2 100644
--- a/drivers/gpu/drm/i915/intel_lrc.c
+++ b/drivers/gpu/drm/i915/intel_lrc.c
@@ -138,6 +138,7 @@
 #include "i915_drv.h"
 #include "intel_mocs.h"
 
+#define GEN10_LR_CONTEXT_RENDER_SIZE ((1 + 33) * PAGE_SIZE)
 #define GEN9_LR_CONTEXT_RENDER_SIZE (22 * PAGE_SIZE)
 #define GEN8_LR_CONTEXT_RENDER_SIZE (20 * PAGE_SIZE)
 #define GEN8_LR_CONTEXT_OTHER_SIZE (2 * PAGE_SIZE)
@@ -1930,10 +1931,19 @@ uint32_t intel_lr_context_size(struct intel_engine_cs *engine)
 
 	switch (engine->id) {
 	case RCS:
-		if (INTEL_GEN(engine->i915) >= 9)
+		switch (INTEL_GEN(engine->i915)) {
+		default:
+			DRM_ERROR("Unknown context size for GEN\n");
+		case 10:
+			ret = GEN10_LR_CONTEXT_RENDER_SIZE;
+			break;
+		case 9:
 			ret = GEN9_LR_CONTEXT_RENDER_SIZE;
-		else
+			break;
+		case 8:
 			ret = GEN8_LR_CONTEXT_RENDER_SIZE;
+			break;
+		}
 		break;
 	case VCS:
 	case BCS:
-- 
1.9.1

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Re: [PATCH 21/67] drm/i915/cnl: Update the context size

[Chris Wilson]

On Thu, Apr 06, 2017 at 12:15:17PM -0700, Rodrigo Vivi wrote:
> From: Ben Widawsky <benjamin.widawsky@intel.com>
> 
> The docs are not yet correct, so I cannot provide a reference to it. In the
> current docs, the size is actually smaller than SKL. This seems unlikely given
> that in another part of the docs there are clearly more engines stored within
> the context image.
> 
> !UPSTREAM: I got this number from the Windows driver, but we should add the right
> reference to the docs when we have it..
> 
> v2: (Rodrigo) Fixup the missing break identified by Tvrtko.
> 
> Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
> Signed-off-by: Ben Widawsky <benjamin.widawsky@intel.com>
> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
> ---
>  drivers/gpu/drm/i915/intel_lrc.c | 14 ++++++++++++--
>  1 file changed, 12 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
> index 23e2bed..058d5f2 100644
> --- a/drivers/gpu/drm/i915/intel_lrc.c
> +++ b/drivers/gpu/drm/i915/intel_lrc.c
> @@ -138,6 +138,7 @@
>  #include "i915_drv.h"
>  #include "intel_mocs.h"
>  
> +#define GEN10_LR_CONTEXT_RENDER_SIZE ((1 + 33) * PAGE_SIZE)
>  #define GEN9_LR_CONTEXT_RENDER_SIZE (22 * PAGE_SIZE)
>  #define GEN8_LR_CONTEXT_RENDER_SIZE (20 * PAGE_SIZE)
>  #define GEN8_LR_CONTEXT_OTHER_SIZE (2 * PAGE_SIZE)
> @@ -1930,10 +1931,19 @@ uint32_t intel_lr_context_size(struct intel_engine_cs *engine)
>  
>  	switch (engine->id) {
>  	case RCS:
> -		if (INTEL_GEN(engine->i915) >= 9)
> +		switch (INTEL_GEN(engine->i915)) {
> +		default:
> +			DRM_ERROR("Unknown context size for GEN\n");

MISSING_CASE(INTEL_GEN(engine->i915));
/* fall through */

> +		case 10:
> +			ret = GEN10_LR_CONTEXT_RENDER_SIZE;
> +			break;
> +		case 9:
>  			ret = GEN9_LR_CONTEXT_RENDER_SIZE;
> -		else
> +			break;
> +		case 8:
>  			ret = GEN8_LR_CONTEXT_RENDER_SIZE;
> +			break;
> +		}
>  		break;
>  	case VCS:
>  	case BCS:
> -- 
> 1.9.1
> 
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
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Re: [PATCH 21/67] drm/i915/cnl: Update the context size

[Daniele Ceraolo Spurio]

On 06/04/17 12:15, Rodrigo Vivi wrote:
> From: Ben Widawsky <benjamin.widawsky@intel.com>
>
> The docs are not yet correct, so I cannot provide a reference to it. In the
> current docs, the size is actually smaller than SKL. This seems unlikely given
> that in another part of the docs there are clearly more engines stored within
> the context image.
>
> !UPSTREAM: I got this number from the Windows driver, but we should add the right
> reference to the docs when we have it..
>
> v2: (Rodrigo) Fixup the missing break identified by Tvrtko.
>
> Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
> Signed-off-by: Ben Widawsky <benjamin.widawsky@intel.com>
> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
> ---
>  drivers/gpu/drm/i915/intel_lrc.c | 14 ++++++++++++--
>  1 file changed, 12 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
> index 23e2bed..058d5f2 100644
> --- a/drivers/gpu/drm/i915/intel_lrc.c
> +++ b/drivers/gpu/drm/i915/intel_lrc.c
> @@ -138,6 +138,7 @@
>  #include "i915_drv.h"
>  #include "intel_mocs.h"
>
> +#define GEN10_LR_CONTEXT_RENDER_SIZE ((1 + 33) * PAGE_SIZE)

1+33 looks really big compared to what's in the specs. I agree that the 
specs are unclear, but something around 1+18 should still be a safe 
setting. Unfortunately I don't have a setup to verify, so I'm happy to 
merge this as it is as long as we remember to come and re-assess it 
(maybe add a TODO?)

Thanks,
Daniele

>  #define GEN9_LR_CONTEXT_RENDER_SIZE (22 * PAGE_SIZE)
>  #define GEN8_LR_CONTEXT_RENDER_SIZE (20 * PAGE_SIZE)
>  #define GEN8_LR_CONTEXT_OTHER_SIZE (2 * PAGE_SIZE)
> @@ -1930,10 +1931,19 @@ uint32_t intel_lr_context_size(struct intel_engine_cs *engine)
>
>  	switch (engine->id) {
>  	case RCS:
> -		if (INTEL_GEN(engine->i915) >= 9)
> +		switch (INTEL_GEN(engine->i915)) {
> +		default:
> +			DRM_ERROR("Unknown context size for GEN\n");
> +		case 10:
> +			ret = GEN10_LR_CONTEXT_RENDER_SIZE;
> +			break;
> +		case 9:
>  			ret = GEN9_LR_CONTEXT_RENDER_SIZE;
> -		else
> +			break;
> +		case 8:
>  			ret = GEN8_LR_CONTEXT_RENDER_SIZE;
> +			break;
> +		}
>  		break;
>  	case VCS:
>  	case BCS:
>
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Re: [PATCH 21/67] drm/i915/cnl: Update the context size

[Ben Widawsky]

On 17-04-06 14:53:50, Ceraolo Spurio, Daniele wrote:
>
>
>On 06/04/17 12:15, Rodrigo Vivi wrote:
>>From: Ben Widawsky <benjamin.widawsky@intel.com>
>>
>>The docs are not yet correct, so I cannot provide a reference to it. In the
>>current docs, the size is actually smaller than SKL. This seems unlikely given
>>that in another part of the docs there are clearly more engines stored within
>>the context image.
>>
>>!UPSTREAM: I got this number from the Windows driver, but we should add the right
>>reference to the docs when we have it..
>>
>>v2: (Rodrigo) Fixup the missing break identified by Tvrtko.
>>
>>Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
>>Signed-off-by: Ben Widawsky <benjamin.widawsky@intel.com>
>>Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
>>---
>> drivers/gpu/drm/i915/intel_lrc.c | 14 ++++++++++++--
>> 1 file changed, 12 insertions(+), 2 deletions(-)
>>
>>diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
>>index 23e2bed..058d5f2 100644
>>--- a/drivers/gpu/drm/i915/intel_lrc.c
>>+++ b/drivers/gpu/drm/i915/intel_lrc.c
>>@@ -138,6 +138,7 @@
>> #include "i915_drv.h"
>> #include "intel_mocs.h"
>>
>>+#define GEN10_LR_CONTEXT_RENDER_SIZE ((1 + 33) * PAGE_SIZE)
>
>1+33 looks really big compared to what's in the specs. I agree that 
>the specs are unclear, but something around 1+18 should still be a 
>safe setting. Unfortunately I don't have a setup to verify, so I'm 
>happy to merge this as it is as long as we remember to come and 
>re-assess it (maybe add a TODO?)
>
>Thanks,
>Daniele
>

It's fine with me. The original number was very generous.

>> #define GEN9_LR_CONTEXT_RENDER_SIZE (22 * PAGE_SIZE)
>> #define GEN8_LR_CONTEXT_RENDER_SIZE (20 * PAGE_SIZE)
>> #define GEN8_LR_CONTEXT_OTHER_SIZE (2 * PAGE_SIZE)
>>@@ -1930,10 +1931,19 @@ uint32_t intel_lr_context_size(struct intel_engine_cs *engine)
>>
>> 	switch (engine->id) {
>> 	case RCS:
>>-		if (INTEL_GEN(engine->i915) >= 9)
>>+		switch (INTEL_GEN(engine->i915)) {
>>+		default:
>>+			DRM_ERROR("Unknown context size for GEN\n");
>>+		case 10:
>>+			ret = GEN10_LR_CONTEXT_RENDER_SIZE;
>>+			break;
>>+		case 9:
>> 			ret = GEN9_LR_CONTEXT_RENDER_SIZE;
>>-		else
>>+			break;
>>+		case 8:
>> 			ret = GEN8_LR_CONTEXT_RENDER_SIZE;
>>+			break;
>>+		}
>> 		break;
>> 	case VCS:
>> 	case BCS:
>>

-- 
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[PATCH 22/67] drm/i915/cnl: Add RT cache flush pipe control w/a

[Rodrigo Vivi]

From: Ben Widawsky <benjamin.widawsky@intel.com>

Signed-off-by: Ben Widawsky <benjamin.widawsky@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
---
 drivers/gpu/drm/i915/intel_lrc.c | 19 +++++++++++++++----
 1 file changed, 15 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index 058d5f2..f2d57b4 100644
--- a/drivers/gpu/drm/i915/intel_lrc.c
+++ b/drivers/gpu/drm/i915/intel_lrc.c
@@ -1389,7 +1389,7 @@ static int gen8_emit_flush_render(struct drm_i915_gem_request *request,
 	struct intel_engine_cs *engine = request->engine;
 	u32 scratch_addr =
 		i915_ggtt_offset(engine->scratch) + 2 * CACHELINE_BYTES;
-	bool vf_flush_wa = false, dc_flush_wa = false;
+	bool vf_flush_wa = false, dc_flush_wa = false, rt_flush_wa = false;
 	u32 *cs, flags = 0;
 	int len;
 
@@ -1400,6 +1400,15 @@ static int gen8_emit_flush_render(struct drm_i915_gem_request *request,
 		flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;
 		flags |= PIPE_CONTROL_DC_FLUSH_ENABLE;
 		flags |= PIPE_CONTROL_FLUSH_ENABLE;
+
+		/*
+		 * "Before sending a PIPE_CONTROL command with bit 12 set, SW
+		 * must issue another PIPE_CONTROL with Render Target Cache
+		 * Flush Enable (bit 12) = 0 and Pipe Control Flush Enable (bit
+		 * 7) = 1."
+		 */
+		if (IS_GEN10(request->i915))
+			rt_flush_wa = true;
 	}
 
 	if (mode & EMIT_INVALIDATE) {
@@ -1426,7 +1435,7 @@ static int gen8_emit_flush_render(struct drm_i915_gem_request *request,
 
 	len = 6;
 
-	if (vf_flush_wa)
+	if (vf_flush_wa || rt_flush_wa)
 		len += 6;
 
 	if (dc_flush_wa)
@@ -1436,8 +1445,10 @@ static int gen8_emit_flush_render(struct drm_i915_gem_request *request,
 	if (IS_ERR(cs))
 		return PTR_ERR(cs);
 
-	if (vf_flush_wa)
-		cs = gen8_emit_pipe_control(cs, 0, 0);
+	if (vf_flush_wa || rt_flush_wa) {
+		u32 pc_flags = rt_flush_wa ? PIPE_CONTROL_FLUSH_ENABLE : 0;
+		cs = gen8_emit_pipe_control(cs, pc_flags, 0);
+	}
 
 	if (dc_flush_wa)
 		cs = gen8_emit_pipe_control(cs, PIPE_CONTROL_DC_FLUSH_ENABLE,
-- 
1.9.1

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Re: [PATCH 22/67] drm/i915/cnl: Add RT cache flush pipe control w/a

[Tvrtko Ursulin]

On 06/04/2017 20:15, Rodrigo Vivi wrote:
> From: Ben Widawsky <benjamin.widawsky@intel.com>

Some commit message is needed, maybe just copy&paste the comment from below.

> 
> Signed-off-by: Ben Widawsky <benjamin.widawsky@intel.com>
> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
> ---
>   drivers/gpu/drm/i915/intel_lrc.c | 19 +++++++++++++++----
>   1 file changed, 15 insertions(+), 4 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
> index 058d5f2..f2d57b4 100644
> --- a/drivers/gpu/drm/i915/intel_lrc.c
> +++ b/drivers/gpu/drm/i915/intel_lrc.c
> @@ -1389,7 +1389,7 @@ static int gen8_emit_flush_render(struct drm_i915_gem_request *request,
>   	struct intel_engine_cs *engine = request->engine;
>   	u32 scratch_addr =
>   		i915_ggtt_offset(engine->scratch) + 2 * CACHELINE_BYTES;
> -	bool vf_flush_wa = false, dc_flush_wa = false;
> +	bool vf_flush_wa = false, dc_flush_wa = false, rt_flush_wa = false;
>   	u32 *cs, flags = 0;
>   	int len;
>   
> @@ -1400,6 +1400,15 @@ static int gen8_emit_flush_render(struct drm_i915_gem_request *request,
>   		flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;
>   		flags |= PIPE_CONTROL_DC_FLUSH_ENABLE;
>   		flags |= PIPE_CONTROL_FLUSH_ENABLE;
> +
> +		/*
> +		 * "Before sending a PIPE_CONTROL command with bit 12 set, SW
> +		 * must issue another PIPE_CONTROL with Render Target Cache
> +		 * Flush Enable (bit 12) = 0 and Pipe Control Flush Enable (bit
> +		 * 7) = 1."
> +		 */

Is there a "Wa***:platform" designation for this one?

> +		if (IS_GEN10(request->i915))
> +			rt_flush_wa = true;
>   	}
>   
>   	if (mode & EMIT_INVALIDATE) {
> @@ -1426,7 +1435,7 @@ static int gen8_emit_flush_render(struct drm_i915_gem_request *request,
>   
>   	len = 6;
>   
> -	if (vf_flush_wa)
> +	if (vf_flush_wa || rt_flush_wa)
>   		len += 6;
>   
>   	if (dc_flush_wa)
> @@ -1436,8 +1445,10 @@ static int gen8_emit_flush_render(struct drm_i915_gem_request *request,
>   	if (IS_ERR(cs))
>   		return PTR_ERR(cs);
>   
> -	if (vf_flush_wa)
> -		cs = gen8_emit_pipe_control(cs, 0, 0);
> +	if (vf_flush_wa || rt_flush_wa) {
> +		u32 pc_flags = rt_flush_wa ? PIPE_CONTROL_FLUSH_ENABLE : 0;
> +		cs = gen8_emit_pipe_control(cs, pc_flags, 0);

Maybe we could save a conditional by renaming vf_flush_wa to flush_wa, 
enabling it in both relevant cases, and adding u32 flush_wa_flags at the 
top level, defaulting to zero and setting it to 
PIPE_CONTROL_FLUSH_ENABLE. Could be worth trying but can be a followup 
as well since gains would be marginal.

> +	}
>   
>   	if (dc_flush_wa)
>   		cs = gen8_emit_pipe_control(cs, PIPE_CONTROL_DC_FLUSH_ENABLE,
> 

Otherwise looks fine - just needs a commit msg and I'm wondering if the 
official Wa designation exists.

Regards,

Tvrtko
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Re: [PATCH 22/67] drm/i915/cnl: Add RT cache flush pipe control w/a

[Vivi, Rodrigo]

On Fri, 2017-06-02 at 11:01 +0100, Tvrtko Ursulin wrote:
> On 06/04/2017 20:15, Rodrigo Vivi wrote:
> > From: Ben Widawsky <benjamin.widawsky@intel.com>
> 
> Some commit message is needed, maybe just copy&paste the comment from below.


> > 
> > Signed-off-by: Ben Widawsky <benjamin.widawsky@intel.com>
> > Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
> > ---
> >   drivers/gpu/drm/i915/intel_lrc.c | 19 +++++++++++++++----
> >   1 file changed, 15 insertions(+), 4 deletions(-)
> > 
> > diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
> > index 058d5f2..f2d57b4 100644
> > --- a/drivers/gpu/drm/i915/intel_lrc.c
> > +++ b/drivers/gpu/drm/i915/intel_lrc.c
> > @@ -1389,7 +1389,7 @@ static int gen8_emit_flush_render(struct drm_i915_gem_request *request,
> >   	struct intel_engine_cs *engine = request->engine;
> >   	u32 scratch_addr =
> >   		i915_ggtt_offset(engine->scratch) + 2 * CACHELINE_BYTES;
> > -	bool vf_flush_wa = false, dc_flush_wa = false;
> > +	bool vf_flush_wa = false, dc_flush_wa = false, rt_flush_wa = false;
> >   	u32 *cs, flags = 0;
> >   	int len;
> >   
> > @@ -1400,6 +1400,15 @@ static int gen8_emit_flush_render(struct drm_i915_gem_request *request,
> >   		flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;
> >   		flags |= PIPE_CONTROL_DC_FLUSH_ENABLE;
> >   		flags |= PIPE_CONTROL_FLUSH_ENABLE;
> > +
> > +		/*
> > +		 * "Before sending a PIPE_CONTROL command with bit 12 set, SW
> > +		 * must issue another PIPE_CONTROL with Render Target Cache
> > +		 * Flush Enable (bit 12) = 0 and Pipe Control Flush Enable (bit
> > +		 * 7) = 1."
> > +		 */
> 
> Is there a "Wa***:platform" designation for this one?

Wa:#1034
WaPCFlushBeforeRTCacheFlush

But Oh! It is only for A0. So just ignore this patch for now...
I will re-test without this patch and probably skip it.

> 
> > +		if (IS_GEN10(request->i915))
> > +			rt_flush_wa = true;
> >   	}
> >   
> >   	if (mode & EMIT_INVALIDATE) {
> > @@ -1426,7 +1435,7 @@ static int gen8_emit_flush_render(struct drm_i915_gem_request *request,
> >   
> >   	len = 6;
> >   
> > -	if (vf_flush_wa)
> > +	if (vf_flush_wa || rt_flush_wa)
> >   		len += 6;
> >   
> >   	if (dc_flush_wa)
> > @@ -1436,8 +1445,10 @@ static int gen8_emit_flush_render(struct drm_i915_gem_request *request,
> >   	if (IS_ERR(cs))
> >   		return PTR_ERR(cs);
> >   
> > -	if (vf_flush_wa)
> > -		cs = gen8_emit_pipe_control(cs, 0, 0);
> > +	if (vf_flush_wa || rt_flush_wa) {
> > +		u32 pc_flags = rt_flush_wa ? PIPE_CONTROL_FLUSH_ENABLE : 0;
> > +		cs = gen8_emit_pipe_control(cs, pc_flags, 0);
> 
> Maybe we could save a conditional by renaming vf_flush_wa to flush_wa, 
> enabling it in both relevant cases, and adding u32 flush_wa_flags at the 
> top level, defaulting to zero and setting it to 
> PIPE_CONTROL_FLUSH_ENABLE. Could be worth trying but can be a followup 
> as well since gains would be marginal.
> 
> > +	}
> >   
> >   	if (dc_flush_wa)
> >   		cs = gen8_emit_pipe_control(cs, PIPE_CONTROL_DC_FLUSH_ENABLE,
> > 
> 
> Otherwise looks fine - just needs a commit msg and I'm wondering if the 
> official Wa designation exists.
> 
> Regards,
> 
> Tvrtko

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[PATCH 23/67] drm/i915/gen10: Set value of Indirect Context Offset for gen10

[Rodrigo Vivi]

From: Michel Thierry <michel.thierry@intel.com>

v2: rebased to intel_lr_indirect_ctx_offset

Signed-off-by: Michel Thierry <michel.thierry@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
---
 drivers/gpu/drm/i915/intel_lrc.c | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index f2d57b4..ac38469 100644
--- a/drivers/gpu/drm/i915/intel_lrc.c
+++ b/drivers/gpu/drm/i915/intel_lrc.c
@@ -209,6 +209,7 @@
 
 #define GEN8_CTX_RCS_INDIRECT_CTX_OFFSET_DEFAULT	0x17
 #define GEN9_CTX_RCS_INDIRECT_CTX_OFFSET_DEFAULT	0x26
+#define GEN10_CTX_RCS_INDIRECT_CTX_OFFSET_DEFAULT	0x19
 
 /* Typical size of the average request (2 pipecontrols and a MI_BB) */
 #define EXECLISTS_REQUEST_SIZE 64 /* bytes */
@@ -1787,6 +1788,10 @@ static u32 intel_lr_indirect_ctx_offset(struct intel_engine_cs *engine)
 	default:
 		MISSING_CASE(INTEL_GEN(engine->i915));
 		/* fall through */
+	case 10:
+		indirect_ctx_offset =
+			GEN10_CTX_RCS_INDIRECT_CTX_OFFSET_DEFAULT;
+		break;
 	case 9:
 		indirect_ctx_offset =
 			GEN9_CTX_RCS_INDIRECT_CTX_OFFSET_DEFAULT;
-- 
1.9.1

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Re: [PATCH 23/67] drm/i915/gen10: Set value of Indirect Context Offset for gen10

[Tvrtko Ursulin]

On 06/04/2017 20:15, Rodrigo Vivi wrote:
> From: Michel Thierry <michel.thierry@intel.com>
> 

Some commit message needed just to satisfy the form.

> v2: rebased to intel_lr_indirect_ctx_offset
> 
> Signed-off-by: Michel Thierry <michel.thierry@intel.com>
> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
> ---
>   drivers/gpu/drm/i915/intel_lrc.c | 5 +++++
>   1 file changed, 5 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
> index f2d57b4..ac38469 100644
> --- a/drivers/gpu/drm/i915/intel_lrc.c
> +++ b/drivers/gpu/drm/i915/intel_lrc.c
> @@ -209,6 +209,7 @@
>   
>   #define GEN8_CTX_RCS_INDIRECT_CTX_OFFSET_DEFAULT	0x17
>   #define GEN9_CTX_RCS_INDIRECT_CTX_OFFSET_DEFAULT	0x26
> +#define GEN10_CTX_RCS_INDIRECT_CTX_OFFSET_DEFAULT	0x19
>   
>   /* Typical size of the average request (2 pipecontrols and a MI_BB) */
>   #define EXECLISTS_REQUEST_SIZE 64 /* bytes */
> @@ -1787,6 +1788,10 @@ static u32 intel_lr_indirect_ctx_offset(struct intel_engine_cs *engine)
>   	default:
>   		MISSING_CASE(INTEL_GEN(engine->i915));
>   		/* fall through */
> +	case 10:
> +		indirect_ctx_offset =
> +			GEN10_CTX_RCS_INDIRECT_CTX_OFFSET_DEFAULT;
> +		break;
>   	case 9:
>   		indirect_ctx_offset =
>   			GEN9_CTX_RCS_INDIRECT_CTX_OFFSET_DEFAULT;
> 

After some documentation and commit log traversing to find the relevant 
page, and with a short sentence in the commit message:

Reviewed-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>

Regards,

Tvrtko
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Re: [PATCH 23/67] drm/i915/gen10: Set value of Indirect Context Offset for gen10

[Vivi, Rodrigo]

On Fri, 2017-06-02 at 10:50 +0100, Tvrtko Ursulin wrote:
> On 06/04/2017 20:15, Rodrigo Vivi wrote:
> > From: Michel Thierry <michel.thierry@intel.com>
> > 
> 
> Some commit message needed just to satisfy the form.

What about:

Indirect Context Offset Pointer has changed for Cannonlake.

INDIRECT_CTX_OFFSET[15:6] valid value for CNL is 19h per Spec.

> 
> > v2: rebased to intel_lr_indirect_ctx_offset
> > 
> > Signed-off-by: Michel Thierry <michel.thierry@intel.com>
> > Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
> > ---
> >   drivers/gpu/drm/i915/intel_lrc.c | 5 +++++
> >   1 file changed, 5 insertions(+)
> > 
> > diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
> > index f2d57b4..ac38469 100644
> > --- a/drivers/gpu/drm/i915/intel_lrc.c
> > +++ b/drivers/gpu/drm/i915/intel_lrc.c
> > @@ -209,6 +209,7 @@
> >   
> >   #define GEN8_CTX_RCS_INDIRECT_CTX_OFFSET_DEFAULT	0x17
> >   #define GEN9_CTX_RCS_INDIRECT_CTX_OFFSET_DEFAULT	0x26
> > +#define GEN10_CTX_RCS_INDIRECT_CTX_OFFSET_DEFAULT	0x19
> >   
> >   /* Typical size of the average request (2 pipecontrols and a MI_BB) */
> >   #define EXECLISTS_REQUEST_SIZE 64 /* bytes */
> > @@ -1787,6 +1788,10 @@ static u32 intel_lr_indirect_ctx_offset(struct intel_engine_cs *engine)
> >   	default:
> >   		MISSING_CASE(INTEL_GEN(engine->i915));
> >   		/* fall through */
> > +	case 10:
> > +		indirect_ctx_offset =
> > +			GEN10_CTX_RCS_INDIRECT_CTX_OFFSET_DEFAULT;
> > +		break;
> >   	case 9:
> >   		indirect_ctx_offset =
> >   			GEN9_CTX_RCS_INDIRECT_CTX_OFFSET_DEFAULT;
> > 
> 
> After some documentation and commit log traversing to find the relevant 
> page, and with a short sentence in the commit message:

is the above enough?

Bspec index/11740
or CNL:BUG:1929753

> 
> Reviewed-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
> 
> Regards,
> 
> Tvrtko

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Re: [PATCH 23/67] drm/i915/gen10: Set value of Indirect Context Offset for gen10

[Tvrtko Ursulin]

On 05/06/2017 18:11, Vivi, Rodrigo wrote:
> On Fri, 2017-06-02 at 10:50 +0100, Tvrtko Ursulin wrote:
>> On 06/04/2017 20:15, Rodrigo Vivi wrote:
>>> From: Michel Thierry <michel.thierry@intel.com>
>>>
>>
>> Some commit message needed just to satisfy the form.
> 
> What about:
> 
> Indirect Context Offset Pointer has changed for Cannonlake.
> 
> INDIRECT_CTX_OFFSET[15:6] valid value for CNL is 19h per Spec.

Completely fine.

>>
>>> v2: rebased to intel_lr_indirect_ctx_offset
>>>
>>> Signed-off-by: Michel Thierry <michel.thierry@intel.com>
>>> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
>>> ---
>>>    drivers/gpu/drm/i915/intel_lrc.c | 5 +++++
>>>    1 file changed, 5 insertions(+)
>>>
>>> diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
>>> index f2d57b4..ac38469 100644
>>> --- a/drivers/gpu/drm/i915/intel_lrc.c
>>> +++ b/drivers/gpu/drm/i915/intel_lrc.c
>>> @@ -209,6 +209,7 @@
>>>    
>>>    #define GEN8_CTX_RCS_INDIRECT_CTX_OFFSET_DEFAULT	0x17
>>>    #define GEN9_CTX_RCS_INDIRECT_CTX_OFFSET_DEFAULT	0x26
>>> +#define GEN10_CTX_RCS_INDIRECT_CTX_OFFSET_DEFAULT	0x19
>>>    
>>>    /* Typical size of the average request (2 pipecontrols and a MI_BB) */
>>>    #define EXECLISTS_REQUEST_SIZE 64 /* bytes */
>>> @@ -1787,6 +1788,10 @@ static u32 intel_lr_indirect_ctx_offset(struct intel_engine_cs *engine)
>>>    	default:
>>>    		MISSING_CASE(INTEL_GEN(engine->i915));
>>>    		/* fall through */
>>> +	case 10:
>>> +		indirect_ctx_offset =
>>> +			GEN10_CTX_RCS_INDIRECT_CTX_OFFSET_DEFAULT;
>>> +		break;
>>>    	case 9:
>>>    		indirect_ctx_offset =
>>>    			GEN9_CTX_RCS_INDIRECT_CTX_OFFSET_DEFAULT;
>>>
>>
>> After some documentation and commit log traversing to find the relevant
>> page, and with a short sentence in the commit message:
> 
> is the above enough?
> 
> Bspec index/11740
> or CNL:BUG:1929753

If we have decided to start putting in those that's fine by me.

Regards,

Tvrtko

> 
>>
>> Reviewed-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
>>
>> Regards,
>>
>> Tvrtko
> 
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Re: [PATCH 23/67] drm/i915/gen10: Set value of Indirect Context Offset for gen10

[Vivi, Rodrigo]

On Tue, 2017-06-06 at 07:48 +0100, Tvrtko Ursulin wrote:
> On 05/06/2017 18:11, Vivi, Rodrigo wrote:
> > On Fri, 2017-06-02 at 10:50 +0100, Tvrtko Ursulin wrote:
> >> On 06/04/2017 20:15, Rodrigo Vivi wrote:
> >>> From: Michel Thierry <michel.thierry@intel.com>
> >>>
> >>
> >> Some commit message needed just to satisfy the form.
> > 
> > What about:
> > 
> > Indirect Context Offset Pointer has changed for Cannonlake.
> > 
> > INDIRECT_CTX_OFFSET[15:6] valid value for CNL is 19h per Spec.
> 
> Completely fine.
> 
> >>
> >>> v2: rebased to intel_lr_indirect_ctx_offset
> >>>
> >>> Signed-off-by: Michel Thierry <michel.thierry@intel.com>
> >>> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
> >>> ---
> >>>    drivers/gpu/drm/i915/intel_lrc.c | 5 +++++
> >>>    1 file changed, 5 insertions(+)
> >>>
> >>> diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
> >>> index f2d57b4..ac38469 100644
> >>> --- a/drivers/gpu/drm/i915/intel_lrc.c
> >>> +++ b/drivers/gpu/drm/i915/intel_lrc.c
> >>> @@ -209,6 +209,7 @@
> >>>    
> >>>    #define GEN8_CTX_RCS_INDIRECT_CTX_OFFSET_DEFAULT	0x17
> >>>    #define GEN9_CTX_RCS_INDIRECT_CTX_OFFSET_DEFAULT	0x26
> >>> +#define GEN10_CTX_RCS_INDIRECT_CTX_OFFSET_DEFAULT	0x19
> >>>    
> >>>    /* Typical size of the average request (2 pipecontrols and a MI_BB) */
> >>>    #define EXECLISTS_REQUEST_SIZE 64 /* bytes */
> >>> @@ -1787,6 +1788,10 @@ static u32 intel_lr_indirect_ctx_offset(struct intel_engine_cs *engine)
> >>>    	default:
> >>>    		MISSING_CASE(INTEL_GEN(engine->i915));
> >>>    		/* fall through */
> >>> +	case 10:
> >>> +		indirect_ctx_offset =
> >>> +			GEN10_CTX_RCS_INDIRECT_CTX_OFFSET_DEFAULT;
> >>> +		break;
> >>>    	case 9:
> >>>    		indirect_ctx_offset =
> >>>    			GEN9_CTX_RCS_INDIRECT_CTX_OFFSET_DEFAULT;
> >>>
> >>
> >> After some documentation and commit log traversing to find the relevant
> >> page, and with a short sentence in the commit message:
> > 
> > is the above enough?
> > 
> > Bspec index/11740
> > or CNL:BUG:1929753
> 
> If we have decided to start putting in those that's fine by me.

No, I don't believe it is good to add those...
Just sent for your quickly reference/access to the spec...

> 
> Regards,
> 
> Tvrtko
> 
> > 
> >>
> >> Reviewed-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
> >>
> >> Regards,
> >>
> >> Tvrtko
> > 

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[PATCH 24/67] drm/i915/cnl: Add force wake for gen10.

[Rodrigo Vivi]

By spec there is no change on force wake registers
for Cannonlake. Let's reuse gen9 one.

v2: Adding missing case for the write part. (Tvrtko)
v3: Rebase on recent tree.

Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
---
 drivers/gpu/drm/i915/intel_uncore.c | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_uncore.c b/drivers/gpu/drm/i915/intel_uncore.c
index 6d1ea26..034b728 100644
--- a/drivers/gpu/drm/i915/intel_uncore.c
+++ b/drivers/gpu/drm/i915/intel_uncore.c
@@ -642,7 +642,8 @@ static int fw_range_cmp(u32 offset, const struct intel_forcewake_range *entry)
 	{ .start = (s), .end = (e), .domains = (d) }
 
 #define HAS_FWTABLE(dev_priv) \
-	(IS_GEN9(dev_priv) || \
+	(IS_GEN10(dev_priv) || \
+	 IS_GEN9(dev_priv) || \
 	 IS_CHERRYVIEW(dev_priv) || \
 	 IS_VALLEYVIEW(dev_priv))
 
@@ -1177,7 +1178,7 @@ static void intel_uncore_fw_domains_init(struct drm_i915_private *dev_priv)
 		dev_priv->uncore.fw_clear = _MASKED_BIT_DISABLE(FORCEWAKE_KERNEL);
 	}
 
-	if (IS_GEN9(dev_priv)) {
+	if (IS_GEN9(dev_priv) || IS_GEN10(dev_priv)) {
 		dev_priv->uncore.funcs.force_wake_get = fw_domains_get;
 		dev_priv->uncore.funcs.force_wake_put = fw_domains_put;
 		fw_domain_init(dev_priv, FW_DOMAIN_ID_RENDER,
-- 
1.9.1

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Re: [PATCH 24/67] drm/i915/cnl: Add force wake for gen10.

[Joonas Lahtinen]

On to, 2017-04-06 at 12:15 -0700, Rodrigo Vivi wrote:
> By spec there is no change on force wake registers
> for Cannonlake. Let's reuse gen9 one.
> 
> v2: Adding missing case for the write part. (Tvrtko)
> v3: Rebase on recent tree.
> 
> Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>

Bspec: 18331

> +++ b/drivers/gpu/drm/i915/intel_uncore.c
> @@ -642,7 +642,8 @@ static int fw_range_cmp(u32 offset, const struct intel_forcewake_range *entry)
>  	{ .start = (s), .end = (e), .domains = (d) }
>  
>  #define HAS_FWTABLE(dev_priv) \
> -	(IS_GEN9(dev_priv) || \
> +	(IS_GEN10(dev_priv) || \

May I suggest INTEL_GEN(dev_priv) >= 9 ?

> +	 IS_GEN9(dev_priv) || \
>  	 IS_CHERRYVIEW(dev_priv) || \
>  	 IS_VALLEYVIEW(dev_priv))
>  
> @@ -1177,7 +1178,7 @@ static void intel_uncore_fw_domains_init(struct drm_i915_private *dev_priv)
>  		dev_priv->uncore.fw_clear = _MASKED_BIT_DISABLE(FORCEWAKE_KERNEL);
>  	}
>  
> -	if (IS_GEN9(dev_priv)) {
> +	if (IS_GEN9(dev_priv) || IS_GEN10(dev_priv)) {

Ditto. With those, this is:

Reviewed-by: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>

Regards, Joonas
-- 
Joonas Lahtinen
Open Source Technology Center
Intel Corporation
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[PATCH 25/67] drm/i915/cnl: Inherit RPS stuff from previous platforms.

[Rodrigo Vivi]

Apparently no change on RPS stuff from previous platforms.

v2: Merging to rps related patches in one and also adding
    missed cases.

Cc: David Weinehall <david.weinehall@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
---
 drivers/gpu/drm/i915/i915_debugfs.c | 20 ++++++++++++--------
 drivers/gpu/drm/i915/i915_reg.h     |  4 ++--
 drivers/gpu/drm/i915/i915_sysfs.c   |  2 +-
 drivers/gpu/drm/i915/intel_pm.c     | 18 +++++++++---------
 4 files changed, 24 insertions(+), 20 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
index d689e51..da22aba 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -1155,7 +1155,7 @@ static int i915_frequency_info(struct seq_file *m, void *unused)
 		intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
 
 		reqf = I915_READ(GEN6_RPNSWREQ);
-		if (IS_GEN9(dev_priv))
+		if (INTEL_GEN(dev_priv) >= 9)
 			reqf >>= 23;
 		else {
 			reqf &= ~GEN6_TURBO_DISABLE;
@@ -1177,7 +1177,7 @@ static int i915_frequency_info(struct seq_file *m, void *unused)
 		rpdownei = I915_READ(GEN6_RP_CUR_DOWN_EI) & GEN6_CURIAVG_MASK;
 		rpcurdown = I915_READ(GEN6_RP_CUR_DOWN) & GEN6_CURBSYTAVG_MASK;
 		rpprevdown = I915_READ(GEN6_RP_PREV_DOWN) & GEN6_CURBSYTAVG_MASK;
-		if (IS_GEN9(dev_priv))
+		if (INTEL_GEN(dev_priv) >= 9)
 			cagf = (rpstat & GEN9_CAGF_MASK) >> GEN9_CAGF_SHIFT;
 		else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
 			cagf = (rpstat & HSW_CAGF_MASK) >> HSW_CAGF_SHIFT;
@@ -1206,7 +1206,7 @@ static int i915_frequency_info(struct seq_file *m, void *unused)
 			   dev_priv->rps.pm_intrmsk_mbz);
 		seq_printf(m, "GT_PERF_STATUS: 0x%08x\n", gt_perf_status);
 		seq_printf(m, "Render p-state ratio: %d\n",
-			   (gt_perf_status & (IS_GEN9(dev_priv) ? 0x1ff00 : 0xff00)) >> 8);
+			   (gt_perf_status & (INTEL_GEN(dev_priv) >= 9 ? 0x1ff00 : 0xff00)) >> 8);
 		seq_printf(m, "Render p-state VID: %d\n",
 			   gt_perf_status & 0xff);
 		seq_printf(m, "Render p-state limit: %d\n",
@@ -1237,18 +1237,21 @@ static int i915_frequency_info(struct seq_file *m, void *unused)
 
 		max_freq = (IS_GEN9_LP(dev_priv) ? rp_state_cap >> 0 :
 			    rp_state_cap >> 16) & 0xff;
-		max_freq *= (IS_GEN9_BC(dev_priv) ? GEN9_FREQ_SCALER : 1);
+		max_freq *= (IS_GEN9_BC(dev_priv) ||
+			     IS_CANNONLAKE(dev_priv) ? GEN9_FREQ_SCALER : 1);
 		seq_printf(m, "Lowest (RPN) frequency: %dMHz\n",
 			   intel_gpu_freq(dev_priv, max_freq));
 
 		max_freq = (rp_state_cap & 0xff00) >> 8;
-		max_freq *= (IS_GEN9_BC(dev_priv) ? GEN9_FREQ_SCALER : 1);
+		max_freq *= (IS_GEN9_BC(dev_priv) ||
+			     IS_CANNONLAKE(dev_priv) ? GEN9_FREQ_SCALER : 1);
 		seq_printf(m, "Nominal (RP1) frequency: %dMHz\n",
 			   intel_gpu_freq(dev_priv, max_freq));
 
 		max_freq = (IS_GEN9_LP(dev_priv) ? rp_state_cap >> 16 :
 			    rp_state_cap >> 0) & 0xff;
-		max_freq *= (IS_GEN9_BC(dev_priv) ? GEN9_FREQ_SCALER : 1);
+		max_freq *= (IS_GEN9_BC(dev_priv) ||
+			     IS_CANNONLAKE(dev_priv) ? GEN9_FREQ_SCALER : 1);
 		seq_printf(m, "Max non-overclocked (RP0) frequency: %dMHz\n",
 			   intel_gpu_freq(dev_priv, max_freq));
 		seq_printf(m, "Max overclocked frequency: %dMHz\n",
@@ -1824,7 +1827,7 @@ static int i915_ring_freq_table(struct seq_file *m, void *unused)
 	if (ret)
 		goto out;
 
-	if (IS_GEN9_BC(dev_priv)) {
+	if (IS_GEN9_BC(dev_priv) || IS_CANNONLAKE(dev_priv)) {
 		/* Convert GT frequency to 50 HZ units */
 		min_gpu_freq =
 			dev_priv->rps.min_freq_softlimit / GEN9_FREQ_SCALER;
@@ -1844,7 +1847,8 @@ static int i915_ring_freq_table(struct seq_file *m, void *unused)
 				       &ia_freq);
 		seq_printf(m, "%d\t\t%d\t\t\t\t%d\n",
 			   intel_gpu_freq(dev_priv, (gpu_freq *
-						     (IS_GEN9_BC(dev_priv) ?
+						     (IS_GEN9_BC(dev_priv) ||
+						      IS_CANNONLAKE(dev_priv) ?
 						      GEN9_FREQ_SCALER : 1))),
 			   ((ia_freq >> 0) & 0xff) * 100,
 			   ((ia_freq >> 8) & 0xff) * 100);
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 98e89e6..657036d 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -3311,7 +3311,7 @@ enum skl_disp_power_wells {
 #define INTERVAL_1_28_US(us)	roundup(((us) * 100) >> 7, 25)
 #define INTERVAL_1_33_US(us)	(((us) * 3)   >> 2)
 #define INTERVAL_0_833_US(us)	(((us) * 6) / 5)
-#define GT_INTERVAL_FROM_US(dev_priv, us) (IS_GEN9(dev_priv) ? \
+#define GT_INTERVAL_FROM_US(dev_priv, us) (INTEL_GEN(dev_priv) >= 9 ? \
 				(IS_GEN9_LP(dev_priv) ? \
 				INTERVAL_0_833_US(us) : \
 				INTERVAL_1_33_US(us)) : \
@@ -3320,7 +3320,7 @@ enum skl_disp_power_wells {
 #define INTERVAL_1_28_TO_US(interval)  (((interval) << 7) / 100)
 #define INTERVAL_1_33_TO_US(interval)  (((interval) << 2) / 3)
 #define INTERVAL_0_833_TO_US(interval) (((interval) * 5)  / 6)
-#define GT_PM_INTERVAL_TO_US(dev_priv, interval) (IS_GEN9(dev_priv) ? \
+#define GT_PM_INTERVAL_TO_US(dev_priv, interval) (INTEL_GEN(dev_priv) >= 9 ? \
                            (IS_GEN9_LP(dev_priv) ? \
                            INTERVAL_0_833_TO_US(interval) : \
                            INTERVAL_1_33_TO_US(interval)) : \
diff --git a/drivers/gpu/drm/i915/i915_sysfs.c b/drivers/gpu/drm/i915/i915_sysfs.c
index f3fdfda..a87a3fd 100644
--- a/drivers/gpu/drm/i915/i915_sysfs.c
+++ b/drivers/gpu/drm/i915/i915_sysfs.c
@@ -255,7 +255,7 @@ static ssize_t gt_act_freq_mhz_show(struct device *kdev,
 		ret = intel_gpu_freq(dev_priv, (freq >> 8) & 0xff);
 	} else {
 		u32 rpstat = I915_READ(GEN6_RPSTAT1);
-		if (IS_GEN9(dev_priv))
+		if (INTEL_GEN(dev_priv) >= 9)
 			ret = (rpstat & GEN9_CAGF_MASK) >> GEN9_CAGF_SHIFT;
 		else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
 			ret = (rpstat & HSW_CAGF_MASK) >> HSW_CAGF_SHIFT;
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 798e55f..4c07b91 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -5088,7 +5088,7 @@ static u32 intel_rps_limits(struct drm_i915_private *dev_priv, u8 val)
 	 * the hw runs at the minimal clock before selecting the desired
 	 * frequency, if the down threshold expires in that window we will not
 	 * receive a down interrupt. */
-	if (IS_GEN9(dev_priv)) {
+	if (INTEL_GEN(dev_priv) >= 9) {
 		limits = (dev_priv->rps.max_freq_softlimit) << 23;
 		if (val <= dev_priv->rps.min_freq_softlimit)
 			limits |= (dev_priv->rps.min_freq_softlimit) << 14;
@@ -5230,7 +5230,7 @@ static int gen6_set_rps(struct drm_i915_private *dev_priv, u8 val)
 	if (val != dev_priv->rps.cur_freq) {
 		gen6_set_rps_thresholds(dev_priv, val);
 
-		if (IS_GEN9(dev_priv))
+		if (INTEL_GEN(dev_priv) >= 9)
 			I915_WRITE(GEN6_RPNSWREQ,
 				   GEN9_FREQUENCY(val));
 		else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
@@ -5612,7 +5612,7 @@ static void gen6_init_rps_frequencies(struct drm_i915_private *dev_priv)
 
 	dev_priv->rps.efficient_freq = dev_priv->rps.rp1_freq;
 	if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv) ||
-	    IS_GEN9_BC(dev_priv)) {
+	    IS_GEN9_BC(dev_priv) || IS_CANNONLAKE(dev_priv)) {
 		u32 ddcc_status = 0;
 
 		if (sandybridge_pcode_read(dev_priv,
@@ -5625,7 +5625,7 @@ static void gen6_init_rps_frequencies(struct drm_i915_private *dev_priv)
 					dev_priv->rps.max_freq);
 	}
 
-	if (IS_GEN9_BC(dev_priv)) {
+	if (IS_GEN9_BC(dev_priv) || IS_CANNONLAKE(dev_priv)) {
 		/* Store the frequency values in 16.66 MHZ units, which is
 		 * the natural hardware unit for SKL
 		 */
@@ -5931,7 +5931,7 @@ static void gen6_update_ring_freq(struct drm_i915_private *dev_priv)
 	/* convert DDR frequency from units of 266.6MHz to bandwidth */
 	min_ring_freq = mult_frac(min_ring_freq, 8, 3);
 
-	if (IS_GEN9_BC(dev_priv)) {
+	if (IS_GEN9_BC(dev_priv) || IS_CANNONLAKE(dev_priv)) {
 		/* Convert GT frequency to 50 HZ units */
 		min_gpu_freq = dev_priv->rps.min_freq / GEN9_FREQ_SCALER;
 		max_gpu_freq = dev_priv->rps.max_freq / GEN9_FREQ_SCALER;
@@ -5949,7 +5949,7 @@ static void gen6_update_ring_freq(struct drm_i915_private *dev_priv)
 		int diff = max_gpu_freq - gpu_freq;
 		unsigned int ia_freq = 0, ring_freq = 0;
 
-		if (IS_GEN9_BC(dev_priv)) {
+		if (IS_GEN9_BC(dev_priv) || IS_CANNONLAKE(dev_priv)) {
 			/*
 			 * ring_freq = 2 * GT. ring_freq is in 100MHz units
 			 * No floor required for ring frequency on SKL.
@@ -7080,7 +7080,7 @@ void intel_enable_gt_powersave(struct drm_i915_private *dev_priv)
 	} else if (INTEL_GEN(dev_priv) >= 9) {
 		gen9_enable_rc6(dev_priv);
 		gen9_enable_rps(dev_priv);
-		if (IS_GEN9_BC(dev_priv))
+		if (IS_GEN9_BC(dev_priv) || IS_CANNONLAKE(dev_priv))
 			gen6_update_ring_freq(dev_priv);
 	} else if (IS_BROADWELL(dev_priv)) {
 		gen8_enable_rps(dev_priv);
@@ -8345,7 +8345,7 @@ static int chv_freq_opcode(struct drm_i915_private *dev_priv, int val)
 
 int intel_gpu_freq(struct drm_i915_private *dev_priv, int val)
 {
-	if (IS_GEN9(dev_priv))
+	if (INTEL_GEN(dev_priv) >= 9)
 		return DIV_ROUND_CLOSEST(val * GT_FREQUENCY_MULTIPLIER,
 					 GEN9_FREQ_SCALER);
 	else if (IS_CHERRYVIEW(dev_priv))
@@ -8358,7 +8358,7 @@ int intel_gpu_freq(struct drm_i915_private *dev_priv, int val)
 
 int intel_freq_opcode(struct drm_i915_private *dev_priv, int val)
 {
-	if (IS_GEN9(dev_priv))
+	if (INTEL_GEN(dev_priv) >= 9)
 		return DIV_ROUND_CLOSEST(val * GEN9_FREQ_SCALER,
 					 GT_FREQUENCY_MULTIPLIER);
 	else if (IS_CHERRYVIEW(dev_priv))
-- 
1.9.1

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[PATCH 26/67] drm/i915/cnl: Add power wells for CNL

[Rodrigo Vivi]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

CNL power wells are very similar to SKL, with the exception that the
misc IO well has been split into separate AUX IO wells.

Not sure if DMC is supposed to manage the AUX wells for us or not.
Let's assume so for now.

v2: DDI A power well wants DDI A domains, not DDI B domains
v3: s/BIT/BIT_ULL and add proper Aux IO domains. (Rodrigo)
v4: Remove PW_DDI_E. Not supported on Current CNL SKUs. (Rodrigo).

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h         |   5 ++
 drivers/gpu/drm/i915/intel_runtime_pm.c | 138 +++++++++++++++++++++++++++++++-
 2 files changed, 139 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 657036d..ac8a223 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -1057,6 +1057,7 @@ enum skl_disp_power_wells {
 	SKL_DISP_PW_MISC_IO,
 	SKL_DISP_PW_DDI_A_E,
 	GLK_DISP_PW_DDI_A = SKL_DISP_PW_DDI_A_E,
+	CNL_DISP_PW_DDI_A = SKL_DISP_PW_DDI_A_E,
 	SKL_DISP_PW_DDI_B,
 	SKL_DISP_PW_DDI_C,
 	SKL_DISP_PW_DDI_D,
@@ -1064,6 +1065,10 @@ enum skl_disp_power_wells {
 	GLK_DISP_PW_AUX_A = 8,
 	GLK_DISP_PW_AUX_B,
 	GLK_DISP_PW_AUX_C,
+	CNL_DISP_PW_AUX_A = GLK_DISP_PW_AUX_A,
+	CNL_DISP_PW_AUX_B = GLK_DISP_PW_AUX_B,
+	CNL_DISP_PW_AUX_C = GLK_DISP_PW_AUX_C,
+	CNL_DISP_PW_AUX_D,
 
 	SKL_DISP_PW_1 = 14,
 	SKL_DISP_PW_2,
diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c b/drivers/gpu/drm/i915/intel_runtime_pm.c
index f8a375f..c67eb89 100644
--- a/drivers/gpu/drm/i915/intel_runtime_pm.c
+++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
@@ -494,6 +494,57 @@ static void hsw_set_power_well(struct drm_i915_private *dev_priv,
 	BIT_ULL(POWER_DOMAIN_AUX_A) |			\
 	BIT_ULL(POWER_DOMAIN_INIT))
 
+#define CNL_DISPLAY_POWERWELL_2_POWER_DOMAINS (		\
+	BIT_ULL(POWER_DOMAIN_TRANSCODER_A) |		\
+	BIT_ULL(POWER_DOMAIN_PIPE_B) |			\
+	BIT_ULL(POWER_DOMAIN_TRANSCODER_B) |		\
+	BIT_ULL(POWER_DOMAIN_PIPE_C) |			\
+	BIT_ULL(POWER_DOMAIN_TRANSCODER_C) |		\
+	BIT_ULL(POWER_DOMAIN_PIPE_B_PANEL_FITTER) |		\
+	BIT_ULL(POWER_DOMAIN_PIPE_C_PANEL_FITTER) |		\
+	BIT_ULL(POWER_DOMAIN_PORT_DDI_B_LANES) |		\
+	BIT_ULL(POWER_DOMAIN_PORT_DDI_C_LANES) |		\
+	BIT_ULL(POWER_DOMAIN_PORT_DDI_D_LANES) |		\
+	BIT_ULL(POWER_DOMAIN_PORT_DDI_E_LANES) |		\
+	BIT_ULL(POWER_DOMAIN_AUX_B) |                       \
+	BIT_ULL(POWER_DOMAIN_AUX_C) |			\
+	BIT_ULL(POWER_DOMAIN_AUX_D) |			\
+	BIT_ULL(POWER_DOMAIN_AUDIO) |			\
+	BIT_ULL(POWER_DOMAIN_VGA) |				\
+	BIT_ULL(POWER_DOMAIN_INIT))
+#define CNL_DISPLAY_DDI_A_IO_POWER_DOMAINS (		\
+	BIT_ULL(POWER_DOMAIN_PORT_DDI_A_IO) |		\
+	BIT_ULL(POWER_DOMAIN_INIT))
+#define CNL_DISPLAY_DDI_B_IO_POWER_DOMAINS (		\
+	BIT_ULL(POWER_DOMAIN_PORT_DDI_B_IO) |		\
+	BIT_ULL(POWER_DOMAIN_INIT))
+#define CNL_DISPLAY_DDI_C_IO_POWER_DOMAINS (		\
+	BIT_ULL(POWER_DOMAIN_PORT_DDI_C_IO) |		\
+	BIT_ULL(POWER_DOMAIN_INIT))
+#define CNL_DISPLAY_DDI_D_IO_POWER_DOMAINS (		\
+	BIT_ULL(POWER_DOMAIN_PORT_DDI_D_IO) |		\
+	BIT_ULL(POWER_DOMAIN_INIT))
+#define CNL_DISPLAY_DDI_E_IO_POWER_DOMAINS (		\
+	BIT_ULL(POWER_DOMAIN_PORT_DDI_E_IO) |		\
+	BIT_ULL(POWER_DOMAIN_INIT))
+#define CNL_DISPLAY_AUX_A_POWER_DOMAINS (		\
+	BIT_ULL(POWER_DOMAIN_AUX_A) |			\
+	BIT_ULL(POWER_DOMAIN_INIT))
+#define CNL_DISPLAY_AUX_B_POWER_DOMAINS (		\
+	BIT_ULL(POWER_DOMAIN_AUX_B) |			\
+	BIT_ULL(POWER_DOMAIN_INIT))
+#define CNL_DISPLAY_AUX_C_POWER_DOMAINS (		\
+	BIT_ULL(POWER_DOMAIN_AUX_C) |			\
+	BIT_ULL(POWER_DOMAIN_INIT))
+#define CNL_DISPLAY_AUX_D_POWER_DOMAINS (		\
+	BIT_ULL(POWER_DOMAIN_AUX_D) |			\
+	BIT_ULL(POWER_DOMAIN_INIT))
+#define CNL_DISPLAY_DC_OFF_POWER_DOMAINS (		\
+	CNL_DISPLAY_POWERWELL_2_POWER_DOMAINS |		\
+	BIT_ULL(POWER_DOMAIN_MODESET) |			\
+	BIT_ULL(POWER_DOMAIN_AUX_A) |			\
+	BIT_ULL(POWER_DOMAIN_INIT))
+
 static void assert_can_enable_dc9(struct drm_i915_private *dev_priv)
 {
 	WARN_ONCE((I915_READ(DC_STATE_EN) & DC_STATE_EN_DC9),
@@ -762,13 +813,14 @@ static void skl_set_power_well(struct drm_i915_private *dev_priv,
 		}
 		break;
 	case SKL_DISP_PW_MISC_IO:
-	case SKL_DISP_PW_DDI_A_E: /* GLK_DISP_PW_DDI_A */
+	case SKL_DISP_PW_DDI_A_E: /* GLK_DISP_PW_DDI_A, CNL_DISP_PW_DDI_A */
 	case SKL_DISP_PW_DDI_B:
 	case SKL_DISP_PW_DDI_C:
 	case SKL_DISP_PW_DDI_D:
-	case GLK_DISP_PW_AUX_A:
-	case GLK_DISP_PW_AUX_B:
-	case GLK_DISP_PW_AUX_C:
+	case GLK_DISP_PW_AUX_A: /* CNL_DISP_PW_AUX_A */
+	case GLK_DISP_PW_AUX_B: /* CNL_DISP_PW_AUX_B */
+	case GLK_DISP_PW_AUX_C: /* CNL_DISP_PW_AUX_C */
+	case CNL_DISP_PW_AUX_D:
 		break;
 	default:
 		WARN(1, "Unknown power well %lu\n", power_well->id);
@@ -2275,6 +2327,82 @@ bool intel_display_power_well_is_enabled(struct drm_i915_private *dev_priv,
 	},
 };
 
+static struct i915_power_well cnl_power_wells[] = {
+	{
+		.name = "always-on",
+		.always_on = 1,
+		.domains = POWER_DOMAIN_MASK,
+		.ops = &i9xx_always_on_power_well_ops,
+	},
+	{
+		.name = "power well 1",
+		/* Handled by the DMC firmware */
+		.domains = 0,
+		.ops = &skl_power_well_ops,
+		.id = SKL_DISP_PW_1,
+	},
+	{
+		.name = "AUX A",
+		.domains = CNL_DISPLAY_AUX_A_POWER_DOMAINS,
+		.ops = &skl_power_well_ops,
+		.id = CNL_DISP_PW_AUX_A,
+	},
+	{
+		.name = "AUX B",
+		.domains = CNL_DISPLAY_AUX_B_POWER_DOMAINS,
+		.ops = &skl_power_well_ops,
+		.id = CNL_DISP_PW_AUX_B,
+	},
+	{
+		.name = "AUX C",
+		.domains = CNL_DISPLAY_AUX_C_POWER_DOMAINS,
+		.ops = &skl_power_well_ops,
+		.id = CNL_DISP_PW_AUX_C,
+	},
+	{
+		.name = "AUX D",
+		.domains = CNL_DISPLAY_AUX_D_POWER_DOMAINS,
+		.ops = &skl_power_well_ops,
+		.id = CNL_DISP_PW_AUX_D,
+	},
+	{
+		.name = "DC off",
+		.domains = CNL_DISPLAY_DC_OFF_POWER_DOMAINS,
+		.ops = &gen9_dc_off_power_well_ops,
+		.id = SKL_DISP_PW_DC_OFF,
+	},
+	{
+		.name = "power well 2",
+		.domains = CNL_DISPLAY_POWERWELL_2_POWER_DOMAINS,
+		.ops = &skl_power_well_ops,
+		.id = SKL_DISP_PW_2,
+	},
+	{
+		.name = "DDI A IO power well",
+		.domains = CNL_DISPLAY_DDI_A_IO_POWER_DOMAINS,
+		.ops = &skl_power_well_ops,
+		.id = CNL_DISP_PW_DDI_A,
+	},
+	{
+		.name = "DDI B IO power well",
+		.domains = CNL_DISPLAY_DDI_B_IO_POWER_DOMAINS,
+		.ops = &skl_power_well_ops,
+		.id = SKL_DISP_PW_DDI_B,
+	},
+	{
+		.name = "DDI C IO power well",
+		.domains = CNL_DISPLAY_DDI_C_IO_POWER_DOMAINS,
+		.ops = &skl_power_well_ops,
+		.id = SKL_DISP_PW_DDI_C,
+	},
+	{
+		.name = "DDI D IO power well",
+		.domains = CNL_DISPLAY_DDI_D_IO_POWER_DOMAINS,
+		.ops = &skl_power_well_ops,
+		.id = SKL_DISP_PW_DDI_D,
+	},
+};
+
 static int
 sanitize_disable_power_well_option(const struct drm_i915_private *dev_priv,
 				   int disable_power_well)
@@ -2369,6 +2497,8 @@ int intel_power_domains_init(struct drm_i915_private *dev_priv)
 		set_power_wells(power_domains, bdw_power_wells);
 	} else if (IS_GEN9_BC(dev_priv)) {
 		set_power_wells(power_domains, skl_power_wells);
+	} else if (IS_CANNONLAKE(dev_priv)) {
+		set_power_wells(power_domains, cnl_power_wells);
 	} else if (IS_BROXTON(dev_priv)) {
 		set_power_wells(power_domains, bxt_power_wells);
 	} else if (IS_GEMINILAKE(dev_priv)) {
-- 
1.9.1

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Re: [PATCH 26/67] drm/i915/cnl: Add power wells for CNL

[Imre Deak]

On Thu, Apr 06, 2017 at 12:15:22PM -0700, Rodrigo Vivi wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> CNL power wells are very similar to SKL, with the exception that the
> misc IO well has been split into separate AUX IO wells.
> 
> Not sure if DMC is supposed to manage the AUX wells for us or not.
> Let's assume so for now.
> 
> v2: DDI A power well wants DDI A domains, not DDI B domains
> v3: s/BIT/BIT_ULL and add proper Aux IO domains. (Rodrigo)
> v4: Remove PW_DDI_E. Not supported on Current CNL SKUs. (Rodrigo).
> 
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
> ---
>  drivers/gpu/drm/i915/i915_reg.h         |   5 ++
>  drivers/gpu/drm/i915/intel_runtime_pm.c | 138 +++++++++++++++++++++++++++++++-
>  2 files changed, 139 insertions(+), 4 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 657036d..ac8a223 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -1057,6 +1057,7 @@ enum skl_disp_power_wells {
>  	SKL_DISP_PW_MISC_IO,
>  	SKL_DISP_PW_DDI_A_E,
>  	GLK_DISP_PW_DDI_A = SKL_DISP_PW_DDI_A_E,
> +	CNL_DISP_PW_DDI_A = SKL_DISP_PW_DDI_A_E,
>  	SKL_DISP_PW_DDI_B,
>  	SKL_DISP_PW_DDI_C,
>  	SKL_DISP_PW_DDI_D,
> @@ -1064,6 +1065,10 @@ enum skl_disp_power_wells {
>  	GLK_DISP_PW_AUX_A = 8,
>  	GLK_DISP_PW_AUX_B,
>  	GLK_DISP_PW_AUX_C,
> +	CNL_DISP_PW_AUX_A = GLK_DISP_PW_AUX_A,
> +	CNL_DISP_PW_AUX_B = GLK_DISP_PW_AUX_B,
> +	CNL_DISP_PW_AUX_C = GLK_DISP_PW_AUX_C,
> +	CNL_DISP_PW_AUX_D,
>  
>  	SKL_DISP_PW_1 = 14,
>  	SKL_DISP_PW_2,
> diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c b/drivers/gpu/drm/i915/intel_runtime_pm.c
> index f8a375f..c67eb89 100644
> --- a/drivers/gpu/drm/i915/intel_runtime_pm.c
> +++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
> @@ -494,6 +494,57 @@ static void hsw_set_power_well(struct drm_i915_private *dev_priv,
>  	BIT_ULL(POWER_DOMAIN_AUX_A) |			\
>  	BIT_ULL(POWER_DOMAIN_INIT))
>  
> +#define CNL_DISPLAY_POWERWELL_2_POWER_DOMAINS (		\
> +	BIT_ULL(POWER_DOMAIN_TRANSCODER_A) |		\
> +	BIT_ULL(POWER_DOMAIN_PIPE_B) |			\
> +	BIT_ULL(POWER_DOMAIN_TRANSCODER_B) |		\
> +	BIT_ULL(POWER_DOMAIN_PIPE_C) |			\
> +	BIT_ULL(POWER_DOMAIN_TRANSCODER_C) |		\
> +	BIT_ULL(POWER_DOMAIN_PIPE_B_PANEL_FITTER) |		\
> +	BIT_ULL(POWER_DOMAIN_PIPE_C_PANEL_FITTER) |		\
> +	BIT_ULL(POWER_DOMAIN_PORT_DDI_B_LANES) |		\
> +	BIT_ULL(POWER_DOMAIN_PORT_DDI_C_LANES) |		\
> +	BIT_ULL(POWER_DOMAIN_PORT_DDI_D_LANES) |		\
> +	BIT_ULL(POWER_DOMAIN_PORT_DDI_E_LANES) |		\

If port E isn't supported the above and
CNL_DISPLAY_DDI_E_IO_POWER_DOMAINS could be also removed, unless you
wanted to keep them for reference. Either way, looks ok:

Reviewed-by: Imre Deak <imre.deak@intel.com>

> +	BIT_ULL(POWER_DOMAIN_AUX_B) |                       \
> +	BIT_ULL(POWER_DOMAIN_AUX_C) |			\
> +	BIT_ULL(POWER_DOMAIN_AUX_D) |			\
> +	BIT_ULL(POWER_DOMAIN_AUDIO) |			\
> +	BIT_ULL(POWER_DOMAIN_VGA) |				\
> +	BIT_ULL(POWER_DOMAIN_INIT))
> +#define CNL_DISPLAY_DDI_A_IO_POWER_DOMAINS (		\
> +	BIT_ULL(POWER_DOMAIN_PORT_DDI_A_IO) |		\
> +	BIT_ULL(POWER_DOMAIN_INIT))
> +#define CNL_DISPLAY_DDI_B_IO_POWER_DOMAINS (		\
> +	BIT_ULL(POWER_DOMAIN_PORT_DDI_B_IO) |		\
> +	BIT_ULL(POWER_DOMAIN_INIT))
> +#define CNL_DISPLAY_DDI_C_IO_POWER_DOMAINS (		\
> +	BIT_ULL(POWER_DOMAIN_PORT_DDI_C_IO) |		\
> +	BIT_ULL(POWER_DOMAIN_INIT))
> +#define CNL_DISPLAY_DDI_D_IO_POWER_DOMAINS (		\
> +	BIT_ULL(POWER_DOMAIN_PORT_DDI_D_IO) |		\
> +	BIT_ULL(POWER_DOMAIN_INIT))
> +#define CNL_DISPLAY_DDI_E_IO_POWER_DOMAINS (		\
> +	BIT_ULL(POWER_DOMAIN_PORT_DDI_E_IO) |		\
> +	BIT_ULL(POWER_DOMAIN_INIT))
> +#define CNL_DISPLAY_AUX_A_POWER_DOMAINS (		\
> +	BIT_ULL(POWER_DOMAIN_AUX_A) |			\
> +	BIT_ULL(POWER_DOMAIN_INIT))
> +#define CNL_DISPLAY_AUX_B_POWER_DOMAINS (		\
> +	BIT_ULL(POWER_DOMAIN_AUX_B) |			\
> +	BIT_ULL(POWER_DOMAIN_INIT))
> +#define CNL_DISPLAY_AUX_C_POWER_DOMAINS (		\
> +	BIT_ULL(POWER_DOMAIN_AUX_C) |			\
> +	BIT_ULL(POWER_DOMAIN_INIT))
> +#define CNL_DISPLAY_AUX_D_POWER_DOMAINS (		\
> +	BIT_ULL(POWER_DOMAIN_AUX_D) |			\
> +	BIT_ULL(POWER_DOMAIN_INIT))
> +#define CNL_DISPLAY_DC_OFF_POWER_DOMAINS (		\
> +	CNL_DISPLAY_POWERWELL_2_POWER_DOMAINS |		\
> +	BIT_ULL(POWER_DOMAIN_MODESET) |			\
> +	BIT_ULL(POWER_DOMAIN_AUX_A) |			\
> +	BIT_ULL(POWER_DOMAIN_INIT))
> +
>  static void assert_can_enable_dc9(struct drm_i915_private *dev_priv)
>  {
>  	WARN_ONCE((I915_READ(DC_STATE_EN) & DC_STATE_EN_DC9),
> @@ -762,13 +813,14 @@ static void skl_set_power_well(struct drm_i915_private *dev_priv,
>  		}
>  		break;
>  	case SKL_DISP_PW_MISC_IO:
> -	case SKL_DISP_PW_DDI_A_E: /* GLK_DISP_PW_DDI_A */
> +	case SKL_DISP_PW_DDI_A_E: /* GLK_DISP_PW_DDI_A, CNL_DISP_PW_DDI_A */
>  	case SKL_DISP_PW_DDI_B:
>  	case SKL_DISP_PW_DDI_C:
>  	case SKL_DISP_PW_DDI_D:
> -	case GLK_DISP_PW_AUX_A:
> -	case GLK_DISP_PW_AUX_B:
> -	case GLK_DISP_PW_AUX_C:
> +	case GLK_DISP_PW_AUX_A: /* CNL_DISP_PW_AUX_A */
> +	case GLK_DISP_PW_AUX_B: /* CNL_DISP_PW_AUX_B */
> +	case GLK_DISP_PW_AUX_C: /* CNL_DISP_PW_AUX_C */
> +	case CNL_DISP_PW_AUX_D:
>  		break;
>  	default:
>  		WARN(1, "Unknown power well %lu\n", power_well->id);
> @@ -2275,6 +2327,82 @@ bool intel_display_power_well_is_enabled(struct drm_i915_private *dev_priv,
>  	},
>  };
>  
> +static struct i915_power_well cnl_power_wells[] = {
> +	{
> +		.name = "always-on",
> +		.always_on = 1,
> +		.domains = POWER_DOMAIN_MASK,
> +		.ops = &i9xx_always_on_power_well_ops,
> +	},
> +	{
> +		.name = "power well 1",
> +		/* Handled by the DMC firmware */
> +		.domains = 0,
> +		.ops = &skl_power_well_ops,
> +		.id = SKL_DISP_PW_1,
> +	},
> +	{
> +		.name = "AUX A",
> +		.domains = CNL_DISPLAY_AUX_A_POWER_DOMAINS,
> +		.ops = &skl_power_well_ops,
> +		.id = CNL_DISP_PW_AUX_A,
> +	},
> +	{
> +		.name = "AUX B",
> +		.domains = CNL_DISPLAY_AUX_B_POWER_DOMAINS,
> +		.ops = &skl_power_well_ops,
> +		.id = CNL_DISP_PW_AUX_B,
> +	},
> +	{
> +		.name = "AUX C",
> +		.domains = CNL_DISPLAY_AUX_C_POWER_DOMAINS,
> +		.ops = &skl_power_well_ops,
> +		.id = CNL_DISP_PW_AUX_C,
> +	},
> +	{
> +		.name = "AUX D",
> +		.domains = CNL_DISPLAY_AUX_D_POWER_DOMAINS,
> +		.ops = &skl_power_well_ops,
> +		.id = CNL_DISP_PW_AUX_D,
> +	},
> +	{
> +		.name = "DC off",
> +		.domains = CNL_DISPLAY_DC_OFF_POWER_DOMAINS,
> +		.ops = &gen9_dc_off_power_well_ops,
> +		.id = SKL_DISP_PW_DC_OFF,
> +	},
> +	{
> +		.name = "power well 2",
> +		.domains = CNL_DISPLAY_POWERWELL_2_POWER_DOMAINS,
> +		.ops = &skl_power_well_ops,
> +		.id = SKL_DISP_PW_2,
> +	},
> +	{
> +		.name = "DDI A IO power well",
> +		.domains = CNL_DISPLAY_DDI_A_IO_POWER_DOMAINS,
> +		.ops = &skl_power_well_ops,
> +		.id = CNL_DISP_PW_DDI_A,
> +	},
> +	{
> +		.name = "DDI B IO power well",
> +		.domains = CNL_DISPLAY_DDI_B_IO_POWER_DOMAINS,
> +		.ops = &skl_power_well_ops,
> +		.id = SKL_DISP_PW_DDI_B,
> +	},
> +	{
> +		.name = "DDI C IO power well",
> +		.domains = CNL_DISPLAY_DDI_C_IO_POWER_DOMAINS,
> +		.ops = &skl_power_well_ops,
> +		.id = SKL_DISP_PW_DDI_C,
> +	},
> +	{
> +		.name = "DDI D IO power well",
> +		.domains = CNL_DISPLAY_DDI_D_IO_POWER_DOMAINS,
> +		.ops = &skl_power_well_ops,
> +		.id = SKL_DISP_PW_DDI_D,
> +	},
> +};
> +
>  static int
>  sanitize_disable_power_well_option(const struct drm_i915_private *dev_priv,
>  				   int disable_power_well)
> @@ -2369,6 +2497,8 @@ int intel_power_domains_init(struct drm_i915_private *dev_priv)
>  		set_power_wells(power_domains, bdw_power_wells);
>  	} else if (IS_GEN9_BC(dev_priv)) {
>  		set_power_wells(power_domains, skl_power_wells);
> +	} else if (IS_CANNONLAKE(dev_priv)) {
> +		set_power_wells(power_domains, cnl_power_wells);
>  	} else if (IS_BROXTON(dev_priv)) {
>  		set_power_wells(power_domains, bxt_power_wells);
>  	} else if (IS_GEMINILAKE(dev_priv)) {
> -- 
> 1.9.1
> 
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Re: [PATCH 26/67] drm/i915/cnl: Add power wells for CNL

[Vivi, Rodrigo]

On Mon, 2017-06-05 at 18:55 +0300, Imre Deak wrote:
> On Thu, Apr 06, 2017 at 12:15:22PM -0700, Rodrigo Vivi wrote:
> > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > 
> > CNL power wells are very similar to SKL, with the exception that the
> > misc IO well has been split into separate AUX IO wells.
> > 
> > Not sure if DMC is supposed to manage the AUX wells for us or not.
> > Let's assume so for now.
> > 
> > v2: DDI A power well wants DDI A domains, not DDI B domains
> > v3: s/BIT/BIT_ULL and add proper Aux IO domains. (Rodrigo)
> > v4: Remove PW_DDI_E. Not supported on Current CNL SKUs. (Rodrigo).
> > 
> > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
> > ---
> >  drivers/gpu/drm/i915/i915_reg.h         |   5 ++
> >  drivers/gpu/drm/i915/intel_runtime_pm.c | 138 +++++++++++++++++++++++++++++++-
> >  2 files changed, 139 insertions(+), 4 deletions(-)
> > 
> > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> > index 657036d..ac8a223 100644
> > --- a/drivers/gpu/drm/i915/i915_reg.h
> > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > @@ -1057,6 +1057,7 @@ enum skl_disp_power_wells {
> >  	SKL_DISP_PW_MISC_IO,
> >  	SKL_DISP_PW_DDI_A_E,
> >  	GLK_DISP_PW_DDI_A = SKL_DISP_PW_DDI_A_E,
> > +	CNL_DISP_PW_DDI_A = SKL_DISP_PW_DDI_A_E,
> >  	SKL_DISP_PW_DDI_B,
> >  	SKL_DISP_PW_DDI_C,
> >  	SKL_DISP_PW_DDI_D,
> > @@ -1064,6 +1065,10 @@ enum skl_disp_power_wells {
> >  	GLK_DISP_PW_AUX_A = 8,
> >  	GLK_DISP_PW_AUX_B,
> >  	GLK_DISP_PW_AUX_C,
> > +	CNL_DISP_PW_AUX_A = GLK_DISP_PW_AUX_A,
> > +	CNL_DISP_PW_AUX_B = GLK_DISP_PW_AUX_B,
> > +	CNL_DISP_PW_AUX_C = GLK_DISP_PW_AUX_C,
> > +	CNL_DISP_PW_AUX_D,
> >  
> >  	SKL_DISP_PW_1 = 14,
> >  	SKL_DISP_PW_2,
> > diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c b/drivers/gpu/drm/i915/intel_runtime_pm.c
> > index f8a375f..c67eb89 100644
> > --- a/drivers/gpu/drm/i915/intel_runtime_pm.c
> > +++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
> > @@ -494,6 +494,57 @@ static void hsw_set_power_well(struct drm_i915_private *dev_priv,
> >  	BIT_ULL(POWER_DOMAIN_AUX_A) |			\
> >  	BIT_ULL(POWER_DOMAIN_INIT))
> >  
> > +#define CNL_DISPLAY_POWERWELL_2_POWER_DOMAINS (		\
> > +	BIT_ULL(POWER_DOMAIN_TRANSCODER_A) |		\
> > +	BIT_ULL(POWER_DOMAIN_PIPE_B) |			\
> > +	BIT_ULL(POWER_DOMAIN_TRANSCODER_B) |		\
> > +	BIT_ULL(POWER_DOMAIN_PIPE_C) |			\
> > +	BIT_ULL(POWER_DOMAIN_TRANSCODER_C) |		\
> > +	BIT_ULL(POWER_DOMAIN_PIPE_B_PANEL_FITTER) |		\
> > +	BIT_ULL(POWER_DOMAIN_PIPE_C_PANEL_FITTER) |		\
> > +	BIT_ULL(POWER_DOMAIN_PORT_DDI_B_LANES) |		\
> > +	BIT_ULL(POWER_DOMAIN_PORT_DDI_C_LANES) |		\
> > +	BIT_ULL(POWER_DOMAIN_PORT_DDI_D_LANES) |		\
> > +	BIT_ULL(POWER_DOMAIN_PORT_DDI_E_LANES) |		\
> 
> If port E isn't supported the above and
> CNL_DISPLAY_DDI_E_IO_POWER_DOMAINS could be also removed, unless you
> wanted to keep them for reference. Either way, looks ok:

I agree. I will remove on the next rebase.

> 
> Reviewed-by: Imre Deak <imre.deak@intel.com>

Thanks.

> 
> > +	BIT_ULL(POWER_DOMAIN_AUX_B) |                       \
> > +	BIT_ULL(POWER_DOMAIN_AUX_C) |			\
> > +	BIT_ULL(POWER_DOMAIN_AUX_D) |			\
> > +	BIT_ULL(POWER_DOMAIN_AUDIO) |			\
> > +	BIT_ULL(POWER_DOMAIN_VGA) |				\
> > +	BIT_ULL(POWER_DOMAIN_INIT))
> > +#define CNL_DISPLAY_DDI_A_IO_POWER_DOMAINS (		\
> > +	BIT_ULL(POWER_DOMAIN_PORT_DDI_A_IO) |		\
> > +	BIT_ULL(POWER_DOMAIN_INIT))
> > +#define CNL_DISPLAY_DDI_B_IO_POWER_DOMAINS (		\
> > +	BIT_ULL(POWER_DOMAIN_PORT_DDI_B_IO) |		\
> > +	BIT_ULL(POWER_DOMAIN_INIT))
> > +#define CNL_DISPLAY_DDI_C_IO_POWER_DOMAINS (		\
> > +	BIT_ULL(POWER_DOMAIN_PORT_DDI_C_IO) |		\
> > +	BIT_ULL(POWER_DOMAIN_INIT))
> > +#define CNL_DISPLAY_DDI_D_IO_POWER_DOMAINS (		\
> > +	BIT_ULL(POWER_DOMAIN_PORT_DDI_D_IO) |		\
> > +	BIT_ULL(POWER_DOMAIN_INIT))
> > +#define CNL_DISPLAY_DDI_E_IO_POWER_DOMAINS (		\
> > +	BIT_ULL(POWER_DOMAIN_PORT_DDI_E_IO) |		\
> > +	BIT_ULL(POWER_DOMAIN_INIT))
> > +#define CNL_DISPLAY_AUX_A_POWER_DOMAINS (		\
> > +	BIT_ULL(POWER_DOMAIN_AUX_A) |			\
> > +	BIT_ULL(POWER_DOMAIN_INIT))
> > +#define CNL_DISPLAY_AUX_B_POWER_DOMAINS (		\
> > +	BIT_ULL(POWER_DOMAIN_AUX_B) |			\
> > +	BIT_ULL(POWER_DOMAIN_INIT))
> > +#define CNL_DISPLAY_AUX_C_POWER_DOMAINS (		\
> > +	BIT_ULL(POWER_DOMAIN_AUX_C) |			\
> > +	BIT_ULL(POWER_DOMAIN_INIT))
> > +#define CNL_DISPLAY_AUX_D_POWER_DOMAINS (		\
> > +	BIT_ULL(POWER_DOMAIN_AUX_D) |			\
> > +	BIT_ULL(POWER_DOMAIN_INIT))
> > +#define CNL_DISPLAY_DC_OFF_POWER_DOMAINS (		\
> > +	CNL_DISPLAY_POWERWELL_2_POWER_DOMAINS |		\
> > +	BIT_ULL(POWER_DOMAIN_MODESET) |			\
> > +	BIT_ULL(POWER_DOMAIN_AUX_A) |			\
> > +	BIT_ULL(POWER_DOMAIN_INIT))
> > +
> >  static void assert_can_enable_dc9(struct drm_i915_private *dev_priv)
> >  {
> >  	WARN_ONCE((I915_READ(DC_STATE_EN) & DC_STATE_EN_DC9),
> > @@ -762,13 +813,14 @@ static void skl_set_power_well(struct drm_i915_private *dev_priv,
> >  		}
> >  		break;
> >  	case SKL_DISP_PW_MISC_IO:
> > -	case SKL_DISP_PW_DDI_A_E: /* GLK_DISP_PW_DDI_A */
> > +	case SKL_DISP_PW_DDI_A_E: /* GLK_DISP_PW_DDI_A, CNL_DISP_PW_DDI_A */
> >  	case SKL_DISP_PW_DDI_B:
> >  	case SKL_DISP_PW_DDI_C:
> >  	case SKL_DISP_PW_DDI_D:
> > -	case GLK_DISP_PW_AUX_A:
> > -	case GLK_DISP_PW_AUX_B:
> > -	case GLK_DISP_PW_AUX_C:
> > +	case GLK_DISP_PW_AUX_A: /* CNL_DISP_PW_AUX_A */
> > +	case GLK_DISP_PW_AUX_B: /* CNL_DISP_PW_AUX_B */
> > +	case GLK_DISP_PW_AUX_C: /* CNL_DISP_PW_AUX_C */
> > +	case CNL_DISP_PW_AUX_D:
> >  		break;
> >  	default:
> >  		WARN(1, "Unknown power well %lu\n", power_well->id);
> > @@ -2275,6 +2327,82 @@ bool intel_display_power_well_is_enabled(struct drm_i915_private *dev_priv,
> >  	},
> >  };
> >  
> > +static struct i915_power_well cnl_power_wells[] = {
> > +	{
> > +		.name = "always-on",
> > +		.always_on = 1,
> > +		.domains = POWER_DOMAIN_MASK,
> > +		.ops = &i9xx_always_on_power_well_ops,
> > +	},
> > +	{
> > +		.name = "power well 1",
> > +		/* Handled by the DMC firmware */
> > +		.domains = 0,
> > +		.ops = &skl_power_well_ops,
> > +		.id = SKL_DISP_PW_1,
> > +	},
> > +	{
> > +		.name = "AUX A",
> > +		.domains = CNL_DISPLAY_AUX_A_POWER_DOMAINS,
> > +		.ops = &skl_power_well_ops,
> > +		.id = CNL_DISP_PW_AUX_A,
> > +	},
> > +	{
> > +		.name = "AUX B",
> > +		.domains = CNL_DISPLAY_AUX_B_POWER_DOMAINS,
> > +		.ops = &skl_power_well_ops,
> > +		.id = CNL_DISP_PW_AUX_B,
> > +	},
> > +	{
> > +		.name = "AUX C",
> > +		.domains = CNL_DISPLAY_AUX_C_POWER_DOMAINS,
> > +		.ops = &skl_power_well_ops,
> > +		.id = CNL_DISP_PW_AUX_C,
> > +	},
> > +	{
> > +		.name = "AUX D",
> > +		.domains = CNL_DISPLAY_AUX_D_POWER_DOMAINS,
> > +		.ops = &skl_power_well_ops,
> > +		.id = CNL_DISP_PW_AUX_D,
> > +	},
> > +	{
> > +		.name = "DC off",
> > +		.domains = CNL_DISPLAY_DC_OFF_POWER_DOMAINS,
> > +		.ops = &gen9_dc_off_power_well_ops,
> > +		.id = SKL_DISP_PW_DC_OFF,
> > +	},
> > +	{
> > +		.name = "power well 2",
> > +		.domains = CNL_DISPLAY_POWERWELL_2_POWER_DOMAINS,
> > +		.ops = &skl_power_well_ops,
> > +		.id = SKL_DISP_PW_2,
> > +	},
> > +	{
> > +		.name = "DDI A IO power well",
> > +		.domains = CNL_DISPLAY_DDI_A_IO_POWER_DOMAINS,
> > +		.ops = &skl_power_well_ops,
> > +		.id = CNL_DISP_PW_DDI_A,
> > +	},
> > +	{
> > +		.name = "DDI B IO power well",
> > +		.domains = CNL_DISPLAY_DDI_B_IO_POWER_DOMAINS,
> > +		.ops = &skl_power_well_ops,
> > +		.id = SKL_DISP_PW_DDI_B,
> > +	},
> > +	{
> > +		.name = "DDI C IO power well",
> > +		.domains = CNL_DISPLAY_DDI_C_IO_POWER_DOMAINS,
> > +		.ops = &skl_power_well_ops,
> > +		.id = SKL_DISP_PW_DDI_C,
> > +	},
> > +	{
> > +		.name = "DDI D IO power well",
> > +		.domains = CNL_DISPLAY_DDI_D_IO_POWER_DOMAINS,
> > +		.ops = &skl_power_well_ops,
> > +		.id = SKL_DISP_PW_DDI_D,
> > +	},
> > +};
> > +
> >  static int
> >  sanitize_disable_power_well_option(const struct drm_i915_private *dev_priv,
> >  				   int disable_power_well)
> > @@ -2369,6 +2497,8 @@ int intel_power_domains_init(struct drm_i915_private *dev_priv)
> >  		set_power_wells(power_domains, bdw_power_wells);
> >  	} else if (IS_GEN9_BC(dev_priv)) {
> >  		set_power_wells(power_domains, skl_power_wells);
> > +	} else if (IS_CANNONLAKE(dev_priv)) {
> > +		set_power_wells(power_domains, cnl_power_wells);
> >  	} else if (IS_BROXTON(dev_priv)) {
> >  		set_power_wells(power_domains, bxt_power_wells);
> >  	} else if (IS_GEMINILAKE(dev_priv)) {
> > -- 
> > 1.9.1
> > 
> > _______________________________________________
> > Intel-gfx mailing list
> > Intel-gfx@lists.freedesktop.org
> > https://lists.freedesktop.org/mailman/listinfo/intel-gfx

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[PATCH 27/67] drm/i915/cnl: Also need power well sanitize.

[Rodrigo Vivi]

The workaround added in
commit c6782b76d31a ("drm/i915/gen9: Reset secondary power well
equests left on by DMC/KVMR")
needs to be applied on Cannonlake as well.

So let's assume any platform using this power well setup
will also need and let's just go ahead and remove if condition.

Cc: Imre Deak <imre.deak@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
---
 drivers/gpu/drm/i915/intel_runtime_pm.c | 3 +--
 1 file changed, 1 insertion(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c b/drivers/gpu/drm/i915/intel_runtime_pm.c
index c67eb89..1797c91 100644
--- a/drivers/gpu/drm/i915/intel_runtime_pm.c
+++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
@@ -855,8 +855,7 @@ static void skl_set_power_well(struct drm_i915_private *dev_priv,
 			DRM_DEBUG_KMS("Disabling %s\n", power_well->name);
 		}
 
-		if (IS_GEN9(dev_priv))
-			gen9_sanitize_power_well_requests(dev_priv, power_well);
+		gen9_sanitize_power_well_requests(dev_priv, power_well);
 	}
 
 	if (wait_for(!!(I915_READ(HSW_PWR_WELL_DRIVER) & state_mask) == enable,
-- 
1.9.1

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Re: [PATCH 27/67] drm/i915/cnl: Also need power well sanitize.

[Imre Deak]

On Thu, Apr 06, 2017 at 12:15:23PM -0700, Rodrigo Vivi wrote:
> The workaround added in
> commit c6782b76d31a ("drm/i915/gen9: Reset secondary power well
> equests left on by DMC/KVMR")
> needs to be applied on Cannonlake as well.
> 
> So let's assume any platform using this power well setup
> will also need and let's just go ahead and remove if condition.
> 
> Cc: Imre Deak <imre.deak@intel.com>
> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>

Do you know if this is really needed on CNL, that is the
HSW_PWR_WELL_DEBUG reg has request bits that the WA clears? If so,
I'd feel easier if we could get BSpec updated with the expected
programming for this.

--Imre

> ---
>  drivers/gpu/drm/i915/intel_runtime_pm.c | 3 +--
>  1 file changed, 1 insertion(+), 2 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c b/drivers/gpu/drm/i915/intel_runtime_pm.c
> index c67eb89..1797c91 100644
> --- a/drivers/gpu/drm/i915/intel_runtime_pm.c
> +++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
> @@ -855,8 +855,7 @@ static void skl_set_power_well(struct drm_i915_private *dev_priv,
>  			DRM_DEBUG_KMS("Disabling %s\n", power_well->name);
>  		}
>  
> -		if (IS_GEN9(dev_priv))
> -			gen9_sanitize_power_well_requests(dev_priv, power_well);
> +		gen9_sanitize_power_well_requests(dev_priv, power_well);
>  	}
>  
>  	if (wait_for(!!(I915_READ(HSW_PWR_WELL_DRIVER) & state_mask) == enable,
> -- 
> 1.9.1
> 
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Re: [PATCH 27/67] drm/i915/cnl: Also need power well sanitize.

[Vivi, Rodrigo]

On Thu, 2017-04-13 at 17:44 +0300, Imre Deak wrote:
> On Thu, Apr 06, 2017 at 12:15:23PM -0700, Rodrigo Vivi wrote:
> > The workaround added in
> > commit c6782b76d31a ("drm/i915/gen9: Reset secondary power well
> > equests left on by DMC/KVMR")
> > needs to be applied on Cannonlake as well.
> > 
> > So let's assume any platform using this power well setup
> > will also need and let's just go ahead and remove if condition.
> > 
> > Cc: Imre Deak <imre.deak@intel.com>
> > Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
> 
> Do you know if this is really needed on CNL, that is the
> HSW_PWR_WELL_DEBUG reg has request bits that the WA clears? If so,
> I'd feel easier if we could get BSpec updated with the expected
> programming for this.

Yes, we do need. Without this some power well times out.

> 
> --Imre
> 
> > ---
> >  drivers/gpu/drm/i915/intel_runtime_pm.c | 3 +--
> >  1 file changed, 1 insertion(+), 2 deletions(-)
> > 
> > diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c b/drivers/gpu/drm/i915/intel_runtime_pm.c
> > index c67eb89..1797c91 100644
> > --- a/drivers/gpu/drm/i915/intel_runtime_pm.c
> > +++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
> > @@ -855,8 +855,7 @@ static void skl_set_power_well(struct drm_i915_private *dev_priv,
> >  			DRM_DEBUG_KMS("Disabling %s\n", power_well->name);
> >  		}
> >  
> > -		if (IS_GEN9(dev_priv))
> > -			gen9_sanitize_power_well_requests(dev_priv, power_well);
> > +		gen9_sanitize_power_well_requests(dev_priv, power_well);
> >  	}
> >  
> >  	if (wait_for(!!(I915_READ(HSW_PWR_WELL_DRIVER) & state_mask) == enable,
> > -- 
> > 1.9.1
> > 

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Re: [PATCH 27/67] drm/i915/cnl: Also need power well sanitize.

[Imre Deak]

On Thu, Apr 06, 2017 at 12:15:23PM -0700, Rodrigo Vivi wrote:
> The workaround added in
> commit c6782b76d31a ("drm/i915/gen9: Reset secondary power well
> equests left on by DMC/KVMR")
> needs to be applied on Cannonlake as well.
> 
> So let's assume any platform using this power well setup
> will also need and let's just go ahead and remove if condition.
> 
> Cc: Imre Deak <imre.deak@intel.com>
> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>

Reviewed-by: Imre Deak <imre.deak@intel.com>

> ---
>  drivers/gpu/drm/i915/intel_runtime_pm.c | 3 +--
>  1 file changed, 1 insertion(+), 2 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c b/drivers/gpu/drm/i915/intel_runtime_pm.c
> index c67eb89..1797c91 100644
> --- a/drivers/gpu/drm/i915/intel_runtime_pm.c
> +++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
> @@ -855,8 +855,7 @@ static void skl_set_power_well(struct drm_i915_private *dev_priv,
>  			DRM_DEBUG_KMS("Disabling %s\n", power_well->name);
>  		}
>  
> -		if (IS_GEN9(dev_priv))
> -			gen9_sanitize_power_well_requests(dev_priv, power_well);
> +		gen9_sanitize_power_well_requests(dev_priv, power_well);
>  	}
>  
>  	if (wait_for(!!(I915_READ(HSW_PWR_WELL_DRIVER) & state_mask) == enable,
> -- 
> 1.9.1
> 
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[PATCH 28/67] drm/i915/cnl: Implement .get_display_clock_speed() for CNL

[Rodrigo Vivi]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Add support for reading out the cdclk frequency from the hardware on
CNL. Very similar to BXT, with a few new twists and turns:
* the PLL is now called CDCLK PLL, not DE PLL
* reference clock can be 24 MHz in addition to the 19.2 MHz BXT had
* the ratio now lives in the PLL enable register
* Only 1x and 2x CD2X dividers are supported

v2: Deal with PLL lock bit the same way as BXT/SKL do now
v3: DSSM refclk indicator is bit 31 not 24 (Ander)
v4: Rebased by Rodrigo after Ville's cdclk rework.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h    |  5 ++++
 drivers/gpu/drm/i915/intel_cdclk.c | 54 +++++++++++++++++++++++++++++++++++++-
 2 files changed, 58 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index ac8a223..8353892 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -6557,6 +6557,9 @@ enum {
 #define SKL_DFSM_PIPE_B_DISABLE		(1 << 21)
 #define SKL_DFSM_PIPE_C_DISABLE		(1 << 28)
 
+#define SKL_DSSM			_MMIO(0x51004)
+#define CNL_DSSM_CDCLK_PLL_REFCLK_24MHz	(1 << 31)
+
 #define GEN7_FF_SLICE_CS_CHICKEN1	_MMIO(0x20e0)
 #define   GEN9_FFSC_PERCTX_PREEMPT_CTRL	(1<<14)
 
@@ -8130,6 +8133,8 @@ enum {
 #define BXT_DE_PLL_ENABLE		_MMIO(0x46070)
 #define   BXT_DE_PLL_PLL_ENABLE		(1 << 31)
 #define   BXT_DE_PLL_LOCK		(1 << 30)
+#define   CNL_CDCLK_PLL_RATIO(x)	(x)	/* {28,44} * 19.2 or 24MHz */
+#define   CNL_CDCLK_PLL_RATIO_MASK	0xff
 
 /* GEN9 DC */
 #define DC_STATE_EN			_MMIO(0x45504)
diff --git a/drivers/gpu/drm/i915/intel_cdclk.c b/drivers/gpu/drm/i915/intel_cdclk.c
index 4745596..a4e2bd5 100644
--- a/drivers/gpu/drm/i915/intel_cdclk.c
+++ b/drivers/gpu/drm/i915/intel_cdclk.c
@@ -1400,6 +1400,56 @@ void bxt_uninit_cdclk(struct drm_i915_private *dev_priv)
 	bxt_set_cdclk(dev_priv, &cdclk_state);
 }
 
+static void cnl_cdclk_pll_update(struct drm_i915_private *dev_priv,
+				 struct intel_cdclk_state *cdclk_state)
+{
+	u32 val;
+
+	if (I915_READ(SKL_DSSM) & CNL_DSSM_CDCLK_PLL_REFCLK_24MHz)
+		cdclk_state->ref = 24000;
+	else
+		cdclk_state->ref = 19200;
+
+	cdclk_state->vco = 0;
+
+	val = I915_READ(BXT_DE_PLL_ENABLE);
+	if ((val & BXT_DE_PLL_PLL_ENABLE) == 0)
+		return;
+
+	if (WARN_ON((val & BXT_DE_PLL_LOCK) == 0))
+		return;
+
+	cdclk_state->vco = (val & CNL_CDCLK_PLL_RATIO_MASK) * cdclk_state->ref;
+}
+
+static void cnl_get_cdclk(struct drm_i915_private *dev_priv,
+			 struct intel_cdclk_state *cdclk_state)
+{
+	u32 divider;
+	int div;
+
+	cnl_cdclk_pll_update(dev_priv, cdclk_state);
+
+	if (cdclk_state->vco == 0)
+		return;
+
+	divider = I915_READ(CDCLK_CTL) & BXT_CDCLK_CD2X_DIV_SEL_MASK;
+
+	switch (divider) {
+	case BXT_CDCLK_CD2X_DIV_SEL_1:
+		div = 2;
+		break;
+	case BXT_CDCLK_CD2X_DIV_SEL_2:
+		div = 4;
+		break;
+	default:
+		MISSING_CASE(divider);
+		return;
+	}
+
+	cdclk_state->cdclk = DIV_ROUND_CLOSEST(cdclk_state->vco, div);
+}
+
 /**
  * intel_cdclk_state_compare - Determine if two CDCLK states differ
  * @a: first CDCLK state
@@ -1897,7 +1947,9 @@ void intel_init_cdclk_hooks(struct drm_i915_private *dev_priv)
 			skl_modeset_calc_cdclk;
 	}
 
-	if (IS_GEN9_BC(dev_priv))
+	if (IS_CANNONLAKE(dev_priv))
+		dev_priv->display.get_cdclk = cnl_get_cdclk;
+	else if (IS_GEN9_BC(dev_priv))
 		dev_priv->display.get_cdclk = skl_get_cdclk;
 	else if (IS_GEN9_LP(dev_priv))
 		dev_priv->display.get_cdclk = bxt_get_cdclk;
-- 
1.9.1

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Re: [PATCH 28/67] drm/i915/cnl: Implement .get_display_clock_speed() for CNL

[Imre Deak]

On Thu, Apr 06, 2017 at 12:15:24PM -0700, Rodrigo Vivi wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> Add support for reading out the cdclk frequency from the hardware on
> CNL. Very similar to BXT, with a few new twists and turns:
> * the PLL is now called CDCLK PLL, not DE PLL
> * reference clock can be 24 MHz in addition to the 19.2 MHz BXT had
> * the ratio now lives in the PLL enable register
> * Only 1x and 2x CD2X dividers are supported
> 
> v2: Deal with PLL lock bit the same way as BXT/SKL do now
> v3: DSSM refclk indicator is bit 31 not 24 (Ander)
> v4: Rebased by Rodrigo after Ville's cdclk rework.
> 
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
> ---
>  drivers/gpu/drm/i915/i915_reg.h    |  5 ++++
>  drivers/gpu/drm/i915/intel_cdclk.c | 54 +++++++++++++++++++++++++++++++++++++-
>  2 files changed, 58 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index ac8a223..8353892 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -6557,6 +6557,9 @@ enum {
>  #define SKL_DFSM_PIPE_B_DISABLE		(1 << 21)
>  #define SKL_DFSM_PIPE_C_DISABLE		(1 << 28)
>  
> +#define SKL_DSSM			_MMIO(0x51004)
> +#define CNL_DSSM_CDCLK_PLL_REFCLK_24MHz	(1 << 31)
> +
>  #define GEN7_FF_SLICE_CS_CHICKEN1	_MMIO(0x20e0)
>  #define   GEN9_FFSC_PERCTX_PREEMPT_CTRL	(1<<14)
>  
> @@ -8130,6 +8133,8 @@ enum {
>  #define BXT_DE_PLL_ENABLE		_MMIO(0x46070)
>  #define   BXT_DE_PLL_PLL_ENABLE		(1 << 31)
>  #define   BXT_DE_PLL_LOCK		(1 << 30)
> +#define   CNL_CDCLK_PLL_RATIO(x)	(x)	/* {28,44} * 19.2 or 24MHz */

Nit: 35,55 are also valid for 19.2MHz.

> +#define   CNL_CDCLK_PLL_RATIO_MASK	0xff
>  
>  /* GEN9 DC */
>  #define DC_STATE_EN			_MMIO(0x45504)
> diff --git a/drivers/gpu/drm/i915/intel_cdclk.c b/drivers/gpu/drm/i915/intel_cdclk.c
> index 4745596..a4e2bd5 100644
> --- a/drivers/gpu/drm/i915/intel_cdclk.c
> +++ b/drivers/gpu/drm/i915/intel_cdclk.c
> @@ -1400,6 +1400,56 @@ void bxt_uninit_cdclk(struct drm_i915_private *dev_priv)
>  	bxt_set_cdclk(dev_priv, &cdclk_state);
>  }
>  
> +static void cnl_cdclk_pll_update(struct drm_i915_private *dev_priv,
> +				 struct intel_cdclk_state *cdclk_state)
> +{
> +	u32 val;
> +
> +	if (I915_READ(SKL_DSSM) & CNL_DSSM_CDCLK_PLL_REFCLK_24MHz)
> +		cdclk_state->ref = 24000;
> +	else
> +		cdclk_state->ref = 19200;
> +
> +	cdclk_state->vco = 0;
> +
> +	val = I915_READ(BXT_DE_PLL_ENABLE);
> +	if ((val & BXT_DE_PLL_PLL_ENABLE) == 0)
> +		return;
> +
> +	if (WARN_ON((val & BXT_DE_PLL_LOCK) == 0))
> +		return;
> +
> +	cdclk_state->vco = (val & CNL_CDCLK_PLL_RATIO_MASK) * cdclk_state->ref;
> +}
> +
> +static void cnl_get_cdclk(struct drm_i915_private *dev_priv,
> +			 struct intel_cdclk_state *cdclk_state)
> +{
> +	u32 divider;
> +	int div;
> +
> +	cnl_cdclk_pll_update(dev_priv, cdclk_state);

The other platforms set cdclk to the ref clock here, not sure
if it's ok to leave it uninited. With that change it looks ok:

Reviewed-by: Imre Deak <imre.deak@intel.com>

> +
> +	if (cdclk_state->vco == 0)
> +		return;
> +
> +	divider = I915_READ(CDCLK_CTL) & BXT_CDCLK_CD2X_DIV_SEL_MASK;
> +
> +	switch (divider) {
> +	case BXT_CDCLK_CD2X_DIV_SEL_1:
> +		div = 2;
> +		break;
> +	case BXT_CDCLK_CD2X_DIV_SEL_2:
> +		div = 4;
> +		break;
> +	default:
> +		MISSING_CASE(divider);
> +		return;
> +	}
> +
> +	cdclk_state->cdclk = DIV_ROUND_CLOSEST(cdclk_state->vco, div);
> +}
> +
>  /**
>   * intel_cdclk_state_compare - Determine if two CDCLK states differ
>   * @a: first CDCLK state
> @@ -1897,7 +1947,9 @@ void intel_init_cdclk_hooks(struct drm_i915_private *dev_priv)
>  			skl_modeset_calc_cdclk;
>  	}
>  
> -	if (IS_GEN9_BC(dev_priv))
> +	if (IS_CANNONLAKE(dev_priv))
> +		dev_priv->display.get_cdclk = cnl_get_cdclk;
> +	else if (IS_GEN9_BC(dev_priv))
>  		dev_priv->display.get_cdclk = skl_get_cdclk;
>  	else if (IS_GEN9_LP(dev_priv))
>  		dev_priv->display.get_cdclk = bxt_get_cdclk;
> -- 
> 1.9.1
> 
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Re: [PATCH 28/67] drm/i915/cnl: Implement .get_display_clock_speed() for CNL

[Vivi, Rodrigo]

On Fri, 2017-06-02 at 21:06 +0300, Imre Deak wrote:
> On Thu, Apr 06, 2017 at 12:15:24PM -0700, Rodrigo Vivi wrote:
> > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > 
> > Add support for reading out the cdclk frequency from the hardware on
> > CNL. Very similar to BXT, with a few new twists and turns:
> > * the PLL is now called CDCLK PLL, not DE PLL
> > * reference clock can be 24 MHz in addition to the 19.2 MHz BXT had
> > * the ratio now lives in the PLL enable register
> > * Only 1x and 2x CD2X dividers are supported
> > 
> > v2: Deal with PLL lock bit the same way as BXT/SKL do now
> > v3: DSSM refclk indicator is bit 31 not 24 (Ander)
> > v4: Rebased by Rodrigo after Ville's cdclk rework.
> > 
> > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
> > ---
> >  drivers/gpu/drm/i915/i915_reg.h    |  5 ++++
> >  drivers/gpu/drm/i915/intel_cdclk.c | 54 +++++++++++++++++++++++++++++++++++++-
> >  2 files changed, 58 insertions(+), 1 deletion(-)
> > 
> > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> > index ac8a223..8353892 100644
> > --- a/drivers/gpu/drm/i915/i915_reg.h
> > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > @@ -6557,6 +6557,9 @@ enum {
> >  #define SKL_DFSM_PIPE_B_DISABLE		(1 << 21)
> >  #define SKL_DFSM_PIPE_C_DISABLE		(1 << 28)
> >  
> > +#define SKL_DSSM			_MMIO(0x51004)
> > +#define CNL_DSSM_CDCLK_PLL_REFCLK_24MHz	(1 << 31)
> > +
> >  #define GEN7_FF_SLICE_CS_CHICKEN1	_MMIO(0x20e0)
> >  #define   GEN9_FFSC_PERCTX_PREEMPT_CTRL	(1<<14)
> >  
> > @@ -8130,6 +8133,8 @@ enum {
> >  #define BXT_DE_PLL_ENABLE		_MMIO(0x46070)
> >  #define   BXT_DE_PLL_PLL_ENABLE		(1 << 31)
> >  #define   BXT_DE_PLL_LOCK		(1 << 30)
> > +#define   CNL_CDCLK_PLL_RATIO(x)	(x)	/* {28,44} * 19.2 or 24MHz */

> 
> Nit: 35,55 are also valid for 19.2MHz.

hm... should I just remove the comments then?!


> > +#define   CNL_CDCLK_PLL_RATIO_MASK	0xff
> >  
> >  /* GEN9 DC */
> >  #define DC_STATE_EN			_MMIO(0x45504)
> > diff --git a/drivers/gpu/drm/i915/intel_cdclk.c b/drivers/gpu/drm/i915/intel_cdclk.c
> > index 4745596..a4e2bd5 100644
> > --- a/drivers/gpu/drm/i915/intel_cdclk.c
> > +++ b/drivers/gpu/drm/i915/intel_cdclk.c
> > @@ -1400,6 +1400,56 @@ void bxt_uninit_cdclk(struct drm_i915_private *dev_priv)
> >  	bxt_set_cdclk(dev_priv, &cdclk_state);
> >  }
> >  
> > +static void cnl_cdclk_pll_update(struct drm_i915_private *dev_priv,
> > +				 struct intel_cdclk_state *cdclk_state)
> > +{
> > +	u32 val;
> > +
> > +	if (I915_READ(SKL_DSSM) & CNL_DSSM_CDCLK_PLL_REFCLK_24MHz)
> > +		cdclk_state->ref = 24000;
> > +	else
> > +		cdclk_state->ref = 19200;
> > +
> > +	cdclk_state->vco = 0;
> > +
> > +	val = I915_READ(BXT_DE_PLL_ENABLE);
> > +	if ((val & BXT_DE_PLL_PLL_ENABLE) == 0)
> > +		return;
> > +
> > +	if (WARN_ON((val & BXT_DE_PLL_LOCK) == 0))
> > +		return;
> > +
> > +	cdclk_state->vco = (val & CNL_CDCLK_PLL_RATIO_MASK) * cdclk_state->ref;
> > +}
> > +
> > +static void cnl_get_cdclk(struct drm_i915_private *dev_priv,
> > +			 struct intel_cdclk_state *cdclk_state)
> > +{
> > +	u32 divider;
> > +	int div;
> > +
> > +	cnl_cdclk_pll_update(dev_priv, cdclk_state);
> 
> The other platforms set cdclk to the ref clock here, not sure
> if it's ok to leave it uninited. With that change it looks ok:

Not sure how to address this here...
I see bxt and skl using the cdclk_state here...

> 
> Reviewed-by: Imre Deak <imre.deak@intel.com>
> 
> > +
> > +	if (cdclk_state->vco == 0)
> > +		return;
> > +
> > +	divider = I915_READ(CDCLK_CTL) & BXT_CDCLK_CD2X_DIV_SEL_MASK;
> > +
> > +	switch (divider) {
> > +	case BXT_CDCLK_CD2X_DIV_SEL_1:
> > +		div = 2;
> > +		break;
> > +	case BXT_CDCLK_CD2X_DIV_SEL_2:
> > +		div = 4;
> > +		break;
> > +	default:
> > +		MISSING_CASE(divider);
> > +		return;
> > +	}
> > +
> > +	cdclk_state->cdclk = DIV_ROUND_CLOSEST(cdclk_state->vco, div);
> > +}
> > +
> >  /**
> >   * intel_cdclk_state_compare - Determine if two CDCLK states differ
> >   * @a: first CDCLK state
> > @@ -1897,7 +1947,9 @@ void intel_init_cdclk_hooks(struct drm_i915_private *dev_priv)
> >  			skl_modeset_calc_cdclk;
> >  	}
> >  
> > -	if (IS_GEN9_BC(dev_priv))
> > +	if (IS_CANNONLAKE(dev_priv))
> > +		dev_priv->display.get_cdclk = cnl_get_cdclk;
> > +	else if (IS_GEN9_BC(dev_priv))
> >  		dev_priv->display.get_cdclk = skl_get_cdclk;
> >  	else if (IS_GEN9_LP(dev_priv))
> >  		dev_priv->display.get_cdclk = bxt_get_cdclk;
> > -- 
> > 1.9.1
> > 
> > _______________________________________________
> > Intel-gfx mailing list
> > Intel-gfx@lists.freedesktop.org
> > https://lists.freedesktop.org/mailman/listinfo/intel-gfx

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Re: [PATCH 28/67] drm/i915/cnl: Implement .get_display_clock_speed() for CNL

[Ville Syrjälä]

On Mon, Jun 05, 2017 at 05:59:02PM +0000, Vivi, Rodrigo wrote:
> On Fri, 2017-06-02 at 21:06 +0300, Imre Deak wrote:
> > On Thu, Apr 06, 2017 at 12:15:24PM -0700, Rodrigo Vivi wrote:
> > > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > > 
> > > Add support for reading out the cdclk frequency from the hardware on
> > > CNL. Very similar to BXT, with a few new twists and turns:
> > > * the PLL is now called CDCLK PLL, not DE PLL
> > > * reference clock can be 24 MHz in addition to the 19.2 MHz BXT had
> > > * the ratio now lives in the PLL enable register
> > > * Only 1x and 2x CD2X dividers are supported
> > > 
> > > v2: Deal with PLL lock bit the same way as BXT/SKL do now
> > > v3: DSSM refclk indicator is bit 31 not 24 (Ander)
> > > v4: Rebased by Rodrigo after Ville's cdclk rework.
> > > 
> > > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > > Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
> > > ---
> > >  drivers/gpu/drm/i915/i915_reg.h    |  5 ++++
> > >  drivers/gpu/drm/i915/intel_cdclk.c | 54 +++++++++++++++++++++++++++++++++++++-
> > >  2 files changed, 58 insertions(+), 1 deletion(-)
> > > 
> > > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> > > index ac8a223..8353892 100644
> > > --- a/drivers/gpu/drm/i915/i915_reg.h
> > > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > > @@ -6557,6 +6557,9 @@ enum {
> > >  #define SKL_DFSM_PIPE_B_DISABLE		(1 << 21)
> > >  #define SKL_DFSM_PIPE_C_DISABLE		(1 << 28)
> > >  
> > > +#define SKL_DSSM			_MMIO(0x51004)
> > > +#define CNL_DSSM_CDCLK_PLL_REFCLK_24MHz	(1 << 31)
> > > +
> > >  #define GEN7_FF_SLICE_CS_CHICKEN1	_MMIO(0x20e0)
> > >  #define   GEN9_FFSC_PERCTX_PREEMPT_CTRL	(1<<14)
> > >  
> > > @@ -8130,6 +8133,8 @@ enum {
> > >  #define BXT_DE_PLL_ENABLE		_MMIO(0x46070)
> > >  #define   BXT_DE_PLL_PLL_ENABLE		(1 << 31)
> > >  #define   BXT_DE_PLL_LOCK		(1 << 30)
> > > +#define   CNL_CDCLK_PLL_RATIO(x)	(x)	/* {28,44} * 19.2 or 24MHz */
> 
> > 
> > Nit: 35,55 are also valid for 19.2MHz.
> 
> hm... should I just remove the comments then?!
> 
> 
> > > +#define   CNL_CDCLK_PLL_RATIO_MASK	0xff
> > >  
> > >  /* GEN9 DC */
> > >  #define DC_STATE_EN			_MMIO(0x45504)
> > > diff --git a/drivers/gpu/drm/i915/intel_cdclk.c b/drivers/gpu/drm/i915/intel_cdclk.c
> > > index 4745596..a4e2bd5 100644
> > > --- a/drivers/gpu/drm/i915/intel_cdclk.c
> > > +++ b/drivers/gpu/drm/i915/intel_cdclk.c
> > > @@ -1400,6 +1400,56 @@ void bxt_uninit_cdclk(struct drm_i915_private *dev_priv)
> > >  	bxt_set_cdclk(dev_priv, &cdclk_state);
> > >  }
> > >  
> > > +static void cnl_cdclk_pll_update(struct drm_i915_private *dev_priv,
> > > +				 struct intel_cdclk_state *cdclk_state)
> > > +{
> > > +	u32 val;
> > > +
> > > +	if (I915_READ(SKL_DSSM) & CNL_DSSM_CDCLK_PLL_REFCLK_24MHz)
> > > +		cdclk_state->ref = 24000;
> > > +	else
> > > +		cdclk_state->ref = 19200;
> > > +
> > > +	cdclk_state->vco = 0;
> > > +
> > > +	val = I915_READ(BXT_DE_PLL_ENABLE);
> > > +	if ((val & BXT_DE_PLL_PLL_ENABLE) == 0)
> > > +		return;
> > > +
> > > +	if (WARN_ON((val & BXT_DE_PLL_LOCK) == 0))
> > > +		return;
> > > +
> > > +	cdclk_state->vco = (val & CNL_CDCLK_PLL_RATIO_MASK) * cdclk_state->ref;
> > > +}
> > > +
> > > +static void cnl_get_cdclk(struct drm_i915_private *dev_priv,
> > > +			 struct intel_cdclk_state *cdclk_state)
> > > +{
> > > +	u32 divider;
> > > +	int div;
> > > +
> > > +	cnl_cdclk_pll_update(dev_priv, cdclk_state);
> > 
> > The other platforms set cdclk to the ref clock here, not sure
> > if it's ok to leave it uninited. With that change it looks ok:
> 
> Not sure how to address this here...
> I see bxt and skl using the cdclk_state here...

Assuming refclk is the bypass clock then just doing what the earlier
platforms do would be correct. IIRC there was some platform where
the bypass clock wasn't the refclk, but that was perhaps some
future thing. Either way, whatever the bypass clock is we will want
the readout to correctly reflect it when the PLL is off.

> 
> > 
> > Reviewed-by: Imre Deak <imre.deak@intel.com>
> > 
> > > +
> > > +	if (cdclk_state->vco == 0)
> > > +		return;
> > > +
> > > +	divider = I915_READ(CDCLK_CTL) & BXT_CDCLK_CD2X_DIV_SEL_MASK;
> > > +
> > > +	switch (divider) {
> > > +	case BXT_CDCLK_CD2X_DIV_SEL_1:
> > > +		div = 2;
> > > +		break;
> > > +	case BXT_CDCLK_CD2X_DIV_SEL_2:
> > > +		div = 4;
> > > +		break;
> > > +	default:
> > > +		MISSING_CASE(divider);
> > > +		return;
> > > +	}
> > > +
> > > +	cdclk_state->cdclk = DIV_ROUND_CLOSEST(cdclk_state->vco, div);
> > > +}
> > > +
> > >  /**
> > >   * intel_cdclk_state_compare - Determine if two CDCLK states differ
> > >   * @a: first CDCLK state
> > > @@ -1897,7 +1947,9 @@ void intel_init_cdclk_hooks(struct drm_i915_private *dev_priv)
> > >  			skl_modeset_calc_cdclk;
> > >  	}
> > >  
> > > -	if (IS_GEN9_BC(dev_priv))
> > > +	if (IS_CANNONLAKE(dev_priv))
> > > +		dev_priv->display.get_cdclk = cnl_get_cdclk;
> > > +	else if (IS_GEN9_BC(dev_priv))
> > >  		dev_priv->display.get_cdclk = skl_get_cdclk;
> > >  	else if (IS_GEN9_LP(dev_priv))
> > >  		dev_priv->display.get_cdclk = bxt_get_cdclk;
> > > -- 
> > > 1.9.1
> > > 
> > > _______________________________________________
> > > Intel-gfx mailing list
> > > Intel-gfx@lists.freedesktop.org
> > > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
> 

-- 
Ville Syrjälä
Intel OTC
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Re: [PATCH 28/67] drm/i915/cnl: Implement .get_display_clock_speed() for CNL

[Imre Deak]

On Mon, Jun 05, 2017 at 09:04:26PM +0300, Ville Syrjälä wrote:
> On Mon, Jun 05, 2017 at 05:59:02PM +0000, Vivi, Rodrigo wrote:
> > On Fri, 2017-06-02 at 21:06 +0300, Imre Deak wrote:
> > > > [...]
> > > > +static void cnl_cdclk_pll_update(struct drm_i915_private *dev_priv,
> > > > +				 struct intel_cdclk_state *cdclk_state)
> > > > +{
> > > > +	u32 val;
> > > > +
> > > > +	if (I915_READ(SKL_DSSM) & CNL_DSSM_CDCLK_PLL_REFCLK_24MHz)
> > > > +		cdclk_state->ref = 24000;
> > > > +	else
> > > > +		cdclk_state->ref = 19200;
> > > > +
> > > > +	cdclk_state->vco = 0;
> > > > +
> > > > +	val = I915_READ(BXT_DE_PLL_ENABLE);
> > > > +	if ((val & BXT_DE_PLL_PLL_ENABLE) == 0)
> > > > +		return;
> > > > +
> > > > +	if (WARN_ON((val & BXT_DE_PLL_LOCK) == 0))
> > > > +		return;
> > > > +
> > > > +	cdclk_state->vco = (val & CNL_CDCLK_PLL_RATIO_MASK) * cdclk_state->ref;
> > > > +}
> > > > +
> > > > +static void cnl_get_cdclk(struct drm_i915_private *dev_priv,
> > > > +			 struct intel_cdclk_state *cdclk_state)
> > > > +{
> > > > +	u32 divider;
> > > > +	int div;
> > > > +
> > > > +	cnl_cdclk_pll_update(dev_priv, cdclk_state);
> > > 
> > > The other platforms set cdclk to the ref clock here, not sure
> > > if it's ok to leave it uninited. With that change it looks ok:
> > 
> > Not sure how to address this here...
> > I see bxt and skl using the cdclk_state here...
> 
> Assuming refclk is the bypass clock then just doing what the earlier
> platforms do would be correct.

Yes, according to Bspec the CDCLK freq is the refclock freq when the PLL
is disabled.

> IIRC there was some platform where the bypass clock wasn't the refclk,
> but that was perhaps some future thing. Either way, whatever the
> bypass clock is we will want the readout to correctly reflect it when
> the PLL is off.
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Re: [PATCH 28/67] drm/i915/cnl: Implement .get_display_clock_speed() for CNL

[Vivi, Rodrigo]

On Mon, 2017-06-05 at 21:21 +0300, Imre Deak wrote:
> On Mon, Jun 05, 2017 at 09:04:26PM +0300, Ville Syrjälä wrote:
> > On Mon, Jun 05, 2017 at 05:59:02PM +0000, Vivi, Rodrigo wrote:
> > > On Fri, 2017-06-02 at 21:06 +0300, Imre Deak wrote:
> > > > > [...]
> > > > > +static void cnl_cdclk_pll_update(struct drm_i915_private *dev_priv,
> > > > > +				 struct intel_cdclk_state *cdclk_state)
> > > > > +{
> > > > > +	u32 val;
> > > > > +
> > > > > +	if (I915_READ(SKL_DSSM) & CNL_DSSM_CDCLK_PLL_REFCLK_24MHz)
> > > > > +		cdclk_state->ref = 24000;
> > > > > +	else
> > > > > +		cdclk_state->ref = 19200;
> > > > > +
> > > > > +	cdclk_state->vco = 0;
> > > > > +
> > > > > +	val = I915_READ(BXT_DE_PLL_ENABLE);
> > > > > +	if ((val & BXT_DE_PLL_PLL_ENABLE) == 0)
> > > > > +		return;
> > > > > +
> > > > > +	if (WARN_ON((val & BXT_DE_PLL_LOCK) == 0))
> > > > > +		return;
> > > > > +
> > > > > +	cdclk_state->vco = (val & CNL_CDCLK_PLL_RATIO_MASK) * cdclk_state->ref;
> > > > > +}
> > > > > +
> > > > > +static void cnl_get_cdclk(struct drm_i915_private *dev_priv,
> > > > > +			 struct intel_cdclk_state *cdclk_state)
> > > > > +{
> > > > > +	u32 divider;
> > > > > +	int div;
> > > > > +
> > > > > +	cnl_cdclk_pll_update(dev_priv, cdclk_state);
> > > > 
> > > > The other platforms set cdclk to the ref clock here, not sure
> > > > if it's ok to leave it uninited. With that change it looks ok:
> > > 
> > > Not sure how to address this here...
> > > I see bxt and skl using the cdclk_state here...
> > 
> > Assuming refclk is the bypass clock then just doing what the earlier
> > platforms do would be correct.
> 
> Yes, according to Bspec the CDCLK freq is the refclock freq when the PLL
> is disabled.

So, do I need to change anything?

> 
> > IIRC there was some platform where the bypass clock wasn't the refclk,
> > but that was perhaps some future thing. Either way, whatever the
> > bypass clock is we will want the readout to correctly reflect it when
> > the PLL is off.

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Re: [PATCH 28/67] drm/i915/cnl: Implement .get_display_clock_speed() for CNL

[Imre Deak]

On Mon, Jun 05, 2017 at 09:28:52PM +0300, Vivi, Rodrigo wrote:
> On Mon, 2017-06-05 at 21:21 +0300, Imre Deak wrote:
> > On Mon, Jun 05, 2017 at 09:04:26PM +0300, Ville Syrjälä wrote:
> > > On Mon, Jun 05, 2017 at 05:59:02PM +0000, Vivi, Rodrigo wrote:
> > > > On Fri, 2017-06-02 at 21:06 +0300, Imre Deak wrote:
> > > > > > [...]
> > > > > > +static void cnl_cdclk_pll_update(struct drm_i915_private *dev_priv,
> > > > > > +				 struct intel_cdclk_state *cdclk_state)
> > > > > > +{
> > > > > > +	u32 val;
> > > > > > +
> > > > > > +	if (I915_READ(SKL_DSSM) & CNL_DSSM_CDCLK_PLL_REFCLK_24MHz)
> > > > > > +		cdclk_state->ref = 24000;
> > > > > > +	else
> > > > > > +		cdclk_state->ref = 19200;
> > > > > > +
> > > > > > +	cdclk_state->vco = 0;
> > > > > > +
> > > > > > +	val = I915_READ(BXT_DE_PLL_ENABLE);
> > > > > > +	if ((val & BXT_DE_PLL_PLL_ENABLE) == 0)
> > > > > > +		return;
> > > > > > +
> > > > > > +	if (WARN_ON((val & BXT_DE_PLL_LOCK) == 0))
> > > > > > +		return;
> > > > > > +
> > > > > > +	cdclk_state->vco = (val & CNL_CDCLK_PLL_RATIO_MASK) * cdclk_state->ref;
> > > > > > +}
> > > > > > +
> > > > > > +static void cnl_get_cdclk(struct drm_i915_private *dev_priv,
> > > > > > +			 struct intel_cdclk_state *cdclk_state)
> > > > > > +{
> > > > > > +	u32 divider;
> > > > > > +	int div;
> > > > > > +
> > > > > > +	cnl_cdclk_pll_update(dev_priv, cdclk_state);
> > > > > 
> > > > > The other platforms set cdclk to the ref clock here, not sure
> > > > > if it's ok to leave it uninited. With that change it looks ok:
> > > > 
> > > > Not sure how to address this here...
> > > > I see bxt and skl using the cdclk_state here...
> > > 
> > > Assuming refclk is the bypass clock then just doing what the earlier
> > > platforms do would be correct.
> > 
> > Yes, according to Bspec the CDCLK freq is the refclock freq when the PLL
> > is disabled.
> 
> So, do I need to change anything?

Yes, add the following after cnl_cdclk_pll_update() as done on other
gen9+ platforms:

cdclk_state->cdclk = cdclk_state->ref;

--Imre

> 
> > 
> > > IIRC there was some platform where the bypass clock wasn't the refclk,
> > > but that was perhaps some future thing. Either way, whatever the
> > > bypass clock is we will want the readout to correctly reflect it when
> > > the PLL is off.
> 
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Re: [PATCH 28/67] drm/i915/cnl: Implement .get_display_clock_speed() for CNL

[Rodrigo Vivi]

When addressing Imre's comments I noticed:

error: ‘cnl_set_cdclk’ defined but not used [-Werror=unused-function]
static void cnl_set_cdclk(struct drm_i915_private *dev_priv,
             ^
cc1: all warnings being treated as errors

Ville, since the original is yours I'd like your advise on how to proceed.
1. squash both
2. swap the patches and create a temporary emply cnl_set_cdclk
3. ?

Thanks,
Rodrigo.

On Mon, Jun 5, 2017 at 1:07 PM, Imre Deak <imre.deak@intel.com> wrote:
> On Mon, Jun 05, 2017 at 09:28:52PM +0300, Vivi, Rodrigo wrote:
>> On Mon, 2017-06-05 at 21:21 +0300, Imre Deak wrote:
>> > On Mon, Jun 05, 2017 at 09:04:26PM +0300, Ville Syrjälä wrote:
>> > > On Mon, Jun 05, 2017 at 05:59:02PM +0000, Vivi, Rodrigo wrote:
>> > > > On Fri, 2017-06-02 at 21:06 +0300, Imre Deak wrote:
>> > > > > > [...]
>> > > > > > +static void cnl_cdclk_pll_update(struct drm_i915_private *dev_priv,
>> > > > > > +                            struct intel_cdclk_state *cdclk_state)
>> > > > > > +{
>> > > > > > +   u32 val;
>> > > > > > +
>> > > > > > +   if (I915_READ(SKL_DSSM) & CNL_DSSM_CDCLK_PLL_REFCLK_24MHz)
>> > > > > > +           cdclk_state->ref = 24000;
>> > > > > > +   else
>> > > > > > +           cdclk_state->ref = 19200;
>> > > > > > +
>> > > > > > +   cdclk_state->vco = 0;
>> > > > > > +
>> > > > > > +   val = I915_READ(BXT_DE_PLL_ENABLE);
>> > > > > > +   if ((val & BXT_DE_PLL_PLL_ENABLE) == 0)
>> > > > > > +           return;
>> > > > > > +
>> > > > > > +   if (WARN_ON((val & BXT_DE_PLL_LOCK) == 0))
>> > > > > > +           return;
>> > > > > > +
>> > > > > > +   cdclk_state->vco = (val & CNL_CDCLK_PLL_RATIO_MASK) * cdclk_state->ref;
>> > > > > > +}
>> > > > > > +
>> > > > > > +static void cnl_get_cdclk(struct drm_i915_private *dev_priv,
>> > > > > > +                    struct intel_cdclk_state *cdclk_state)
>> > > > > > +{
>> > > > > > +   u32 divider;
>> > > > > > +   int div;
>> > > > > > +
>> > > > > > +   cnl_cdclk_pll_update(dev_priv, cdclk_state);
>> > > > >
>> > > > > The other platforms set cdclk to the ref clock here, not sure
>> > > > > if it's ok to leave it uninited. With that change it looks ok:
>> > > >
>> > > > Not sure how to address this here...
>> > > > I see bxt and skl using the cdclk_state here...
>> > >
>> > > Assuming refclk is the bypass clock then just doing what the earlier
>> > > platforms do would be correct.
>> >
>> > Yes, according to Bspec the CDCLK freq is the refclock freq when the PLL
>> > is disabled.
>>
>> So, do I need to change anything?
>
> Yes, add the following after cnl_cdclk_pll_update() as done on other
> gen9+ platforms:
>
> cdclk_state->cdclk = cdclk_state->ref;
>
> --Imre
>
>>
>> >
>> > > IIRC there was some platform where the bypass clock wasn't the refclk,
>> > > but that was perhaps some future thing. Either way, whatever the
>> > > bypass clock is we will want the readout to correctly reflect it when
>> > > the PLL is off.
>>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx



-- 
Rodrigo Vivi
Blog: http://blog.vivi.eng.br
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Re: [PATCH 28/67] drm/i915/cnl: Implement .get_display_clock_speed() for CNL

[Ville Syrjälä]

On Tue, Jun 06, 2017 at 02:56:23PM -0700, Rodrigo Vivi wrote:
> When addressing Imre's comments I noticed:
> 
> error: ‘cnl_set_cdclk’ defined but not used [-Werror=unused-function]
> static void cnl_set_cdclk(struct drm_i915_private *dev_priv,
>              ^
> cc1: all warnings being treated as errors
> 
> Ville, since the original is yours I'd like your advise on how to proceed.
> 1. squash both
> 2. swap the patches and create a temporary emply cnl_set_cdclk
> 3. ?

I would just ignore that since it gets fixed in the following patches.
I know adding unused stuff isn't really looked upon favorably but 
squashing it with the display init patch would make that patch less
focused and quite large. I guess you could squash it with the
dynamic cdclk change patch, but then you'd have to reorder the display
init patch to be after that and that order doesn't make as much sense
since you would then be adding optional extra functionality before the
basic functionality in in place.

> 
> Thanks,
> Rodrigo.
> 
> On Mon, Jun 5, 2017 at 1:07 PM, Imre Deak <imre.deak@intel.com> wrote:
> > On Mon, Jun 05, 2017 at 09:28:52PM +0300, Vivi, Rodrigo wrote:
> >> On Mon, 2017-06-05 at 21:21 +0300, Imre Deak wrote:
> >> > On Mon, Jun 05, 2017 at 09:04:26PM +0300, Ville Syrjälä wrote:
> >> > > On Mon, Jun 05, 2017 at 05:59:02PM +0000, Vivi, Rodrigo wrote:
> >> > > > On Fri, 2017-06-02 at 21:06 +0300, Imre Deak wrote:
> >> > > > > > [...]
> >> > > > > > +static void cnl_cdclk_pll_update(struct drm_i915_private *dev_priv,
> >> > > > > > +                            struct intel_cdclk_state *cdclk_state)
> >> > > > > > +{
> >> > > > > > +   u32 val;
> >> > > > > > +
> >> > > > > > +   if (I915_READ(SKL_DSSM) & CNL_DSSM_CDCLK_PLL_REFCLK_24MHz)
> >> > > > > > +           cdclk_state->ref = 24000;
> >> > > > > > +   else
> >> > > > > > +           cdclk_state->ref = 19200;
> >> > > > > > +
> >> > > > > > +   cdclk_state->vco = 0;
> >> > > > > > +
> >> > > > > > +   val = I915_READ(BXT_DE_PLL_ENABLE);
> >> > > > > > +   if ((val & BXT_DE_PLL_PLL_ENABLE) == 0)
> >> > > > > > +           return;
> >> > > > > > +
> >> > > > > > +   if (WARN_ON((val & BXT_DE_PLL_LOCK) == 0))
> >> > > > > > +           return;
> >> > > > > > +
> >> > > > > > +   cdclk_state->vco = (val & CNL_CDCLK_PLL_RATIO_MASK) * cdclk_state->ref;
> >> > > > > > +}
> >> > > > > > +
> >> > > > > > +static void cnl_get_cdclk(struct drm_i915_private *dev_priv,
> >> > > > > > +                    struct intel_cdclk_state *cdclk_state)
> >> > > > > > +{
> >> > > > > > +   u32 divider;
> >> > > > > > +   int div;
> >> > > > > > +
> >> > > > > > +   cnl_cdclk_pll_update(dev_priv, cdclk_state);
> >> > > > >
> >> > > > > The other platforms set cdclk to the ref clock here, not sure
> >> > > > > if it's ok to leave it uninited. With that change it looks ok:
> >> > > >
> >> > > > Not sure how to address this here...
> >> > > > I see bxt and skl using the cdclk_state here...
> >> > >
> >> > > Assuming refclk is the bypass clock then just doing what the earlier
> >> > > platforms do would be correct.
> >> >
> >> > Yes, according to Bspec the CDCLK freq is the refclock freq when the PLL
> >> > is disabled.
> >>
> >> So, do I need to change anything?
> >
> > Yes, add the following after cnl_cdclk_pll_update() as done on other
> > gen9+ platforms:
> >
> > cdclk_state->cdclk = cdclk_state->ref;
> >
> > --Imre
> >
> >>
> >> >
> >> > > IIRC there was some platform where the bypass clock wasn't the refclk,
> >> > > but that was perhaps some future thing. Either way, whatever the
> >> > > bypass clock is we will want the readout to correctly reflect it when
> >> > > the PLL is off.
> >>
> > _______________________________________________
> > Intel-gfx mailing list
> > Intel-gfx@lists.freedesktop.org
> > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
> 
> 
> 
> -- 
> Rodrigo Vivi
> Blog: http://blog.vivi.eng.br
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
Ville Syrjälä
Intel OTC
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Re: [PATCH 28/67] drm/i915/cnl: Implement .get_display_clock_speed() for CNL

[Ville Syrjälä]

On Wed, Jun 07, 2017 at 01:59:05PM +0300, Ville Syrjälä wrote:
> On Tue, Jun 06, 2017 at 02:56:23PM -0700, Rodrigo Vivi wrote:
> > When addressing Imre's comments I noticed:
> > 
> > error: ‘cnl_set_cdclk’ defined but not used [-Werror=unused-function]
> > static void cnl_set_cdclk(struct drm_i915_private *dev_priv,
> >              ^
> > cc1: all warnings being treated as errors
> > 
> > Ville, since the original is yours I'd like your advise on how to proceed.
> > 1. squash both
> > 2. swap the patches and create a temporary emply cnl_set_cdclk
> > 3. ?
> 
> I would just ignore that since it gets fixed in the following patches.
> I know adding unused stuff isn't really looked upon favorably but 
> squashing it with the display init patch would make that patch less
> focused and quite large. I guess you could squash it with the
> dynamic cdclk change patch, but then you'd have to reorder the display
> init patch to be after that and that order doesn't make as much sense
> since you would then be adding optional extra functionality before the
> basic functionality in in place.

If you really want to avoid the warning then I guess adding
__attribute__((unused)) and subsequently removing it would do the trick.

> 
> > 
> > Thanks,
> > Rodrigo.
> > 
> > On Mon, Jun 5, 2017 at 1:07 PM, Imre Deak <imre.deak@intel.com> wrote:
> > > On Mon, Jun 05, 2017 at 09:28:52PM +0300, Vivi, Rodrigo wrote:
> > >> On Mon, 2017-06-05 at 21:21 +0300, Imre Deak wrote:
> > >> > On Mon, Jun 05, 2017 at 09:04:26PM +0300, Ville Syrjälä wrote:
> > >> > > On Mon, Jun 05, 2017 at 05:59:02PM +0000, Vivi, Rodrigo wrote:
> > >> > > > On Fri, 2017-06-02 at 21:06 +0300, Imre Deak wrote:
> > >> > > > > > [...]
> > >> > > > > > +static void cnl_cdclk_pll_update(struct drm_i915_private *dev_priv,
> > >> > > > > > +                            struct intel_cdclk_state *cdclk_state)
> > >> > > > > > +{
> > >> > > > > > +   u32 val;
> > >> > > > > > +
> > >> > > > > > +   if (I915_READ(SKL_DSSM) & CNL_DSSM_CDCLK_PLL_REFCLK_24MHz)
> > >> > > > > > +           cdclk_state->ref = 24000;
> > >> > > > > > +   else
> > >> > > > > > +           cdclk_state->ref = 19200;
> > >> > > > > > +
> > >> > > > > > +   cdclk_state->vco = 0;
> > >> > > > > > +
> > >> > > > > > +   val = I915_READ(BXT_DE_PLL_ENABLE);
> > >> > > > > > +   if ((val & BXT_DE_PLL_PLL_ENABLE) == 0)
> > >> > > > > > +           return;
> > >> > > > > > +
> > >> > > > > > +   if (WARN_ON((val & BXT_DE_PLL_LOCK) == 0))
> > >> > > > > > +           return;
> > >> > > > > > +
> > >> > > > > > +   cdclk_state->vco = (val & CNL_CDCLK_PLL_RATIO_MASK) * cdclk_state->ref;
> > >> > > > > > +}
> > >> > > > > > +
> > >> > > > > > +static void cnl_get_cdclk(struct drm_i915_private *dev_priv,
> > >> > > > > > +                    struct intel_cdclk_state *cdclk_state)
> > >> > > > > > +{
> > >> > > > > > +   u32 divider;
> > >> > > > > > +   int div;
> > >> > > > > > +
> > >> > > > > > +   cnl_cdclk_pll_update(dev_priv, cdclk_state);
> > >> > > > >
> > >> > > > > The other platforms set cdclk to the ref clock here, not sure
> > >> > > > > if it's ok to leave it uninited. With that change it looks ok:
> > >> > > >
> > >> > > > Not sure how to address this here...
> > >> > > > I see bxt and skl using the cdclk_state here...
> > >> > >
> > >> > > Assuming refclk is the bypass clock then just doing what the earlier
> > >> > > platforms do would be correct.
> > >> >
> > >> > Yes, according to Bspec the CDCLK freq is the refclock freq when the PLL
> > >> > is disabled.
> > >>
> > >> So, do I need to change anything?
> > >
> > > Yes, add the following after cnl_cdclk_pll_update() as done on other
> > > gen9+ platforms:
> > >
> > > cdclk_state->cdclk = cdclk_state->ref;
> > >
> > > --Imre
> > >
> > >>
> > >> >
> > >> > > IIRC there was some platform where the bypass clock wasn't the refclk,
> > >> > > but that was perhaps some future thing. Either way, whatever the
> > >> > > bypass clock is we will want the readout to correctly reflect it when
> > >> > > the PLL is off.
> > >>
> > > _______________________________________________
> > > Intel-gfx mailing list
> > > Intel-gfx@lists.freedesktop.org
> > > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
> > 
> > 
> > 
> > -- 
> > Rodrigo Vivi
> > Blog: http://blog.vivi.eng.br
> > _______________________________________________
> > Intel-gfx mailing list
> > Intel-gfx@lists.freedesktop.org
> > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
> 
> -- 
> Ville Syrjälä
> Intel OTC
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
Ville Syrjälä
Intel OTC
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Re: [PATCH 28/67] drm/i915/cnl: Implement .get_display_clock_speed() for CNL

[Rodrigo Vivi]

On Wed, Jun 7, 2017 at 4:09 AM, Ville Syrjälä
<ville.syrjala@linux.intel.com> wrote:
> On Wed, Jun 07, 2017 at 01:59:05PM +0300, Ville Syrjälä wrote:
>> On Tue, Jun 06, 2017 at 02:56:23PM -0700, Rodrigo Vivi wrote:
>> > When addressing Imre's comments I noticed:
>> >
>> > error: ‘cnl_set_cdclk’ defined but not used [-Werror=unused-function]
>> > static void cnl_set_cdclk(struct drm_i915_private *dev_priv,
>> >              ^
>> > cc1: all warnings being treated as errors
>> >
>> > Ville, since the original is yours I'd like your advise on how to proceed.
>> > 1. squash both
>> > 2. swap the patches and create a temporary emply cnl_set_cdclk
>> > 3. ?
>>
>> I would just ignore that since it gets fixed in the following patches.
>> I know adding unused stuff isn't really looked upon favorably but
>> squashing it with the display init patch would make that patch less
>> focused and quite large. I guess you could squash it with the
>> dynamic cdclk change patch, but then you'd have to reorder the display
>> init patch to be after that and that order doesn't make as much sense
>> since you would then be adding optional extra functionality before the
>> basic functionality in in place.
>
> If you really want to avoid the warning then I guess adding
> __attribute__((unused)) and subsequently removing it would do the trick.

cool! I liked that trick.
So whenever someone is bisecting and end up on that patch the
compilation is not broken with the Werror enabled. ;)
>
>>
>> >
>> > Thanks,
>> > Rodrigo.
>> >
>> > On Mon, Jun 5, 2017 at 1:07 PM, Imre Deak <imre.deak@intel.com> wrote:
>> > > On Mon, Jun 05, 2017 at 09:28:52PM +0300, Vivi, Rodrigo wrote:
>> > >> On Mon, 2017-06-05 at 21:21 +0300, Imre Deak wrote:
>> > >> > On Mon, Jun 05, 2017 at 09:04:26PM +0300, Ville Syrjälä wrote:
>> > >> > > On Mon, Jun 05, 2017 at 05:59:02PM +0000, Vivi, Rodrigo wrote:
>> > >> > > > On Fri, 2017-06-02 at 21:06 +0300, Imre Deak wrote:
>> > >> > > > > > [...]
>> > >> > > > > > +static void cnl_cdclk_pll_update(struct drm_i915_private *dev_priv,
>> > >> > > > > > +                            struct intel_cdclk_state *cdclk_state)
>> > >> > > > > > +{
>> > >> > > > > > +   u32 val;
>> > >> > > > > > +
>> > >> > > > > > +   if (I915_READ(SKL_DSSM) & CNL_DSSM_CDCLK_PLL_REFCLK_24MHz)
>> > >> > > > > > +           cdclk_state->ref = 24000;
>> > >> > > > > > +   else
>> > >> > > > > > +           cdclk_state->ref = 19200;
>> > >> > > > > > +
>> > >> > > > > > +   cdclk_state->vco = 0;
>> > >> > > > > > +
>> > >> > > > > > +   val = I915_READ(BXT_DE_PLL_ENABLE);
>> > >> > > > > > +   if ((val & BXT_DE_PLL_PLL_ENABLE) == 0)
>> > >> > > > > > +           return;
>> > >> > > > > > +
>> > >> > > > > > +   if (WARN_ON((val & BXT_DE_PLL_LOCK) == 0))
>> > >> > > > > > +           return;
>> > >> > > > > > +
>> > >> > > > > > +   cdclk_state->vco = (val & CNL_CDCLK_PLL_RATIO_MASK) * cdclk_state->ref;
>> > >> > > > > > +}
>> > >> > > > > > +
>> > >> > > > > > +static void cnl_get_cdclk(struct drm_i915_private *dev_priv,
>> > >> > > > > > +                    struct intel_cdclk_state *cdclk_state)
>> > >> > > > > > +{
>> > >> > > > > > +   u32 divider;
>> > >> > > > > > +   int div;
>> > >> > > > > > +
>> > >> > > > > > +   cnl_cdclk_pll_update(dev_priv, cdclk_state);
>> > >> > > > >
>> > >> > > > > The other platforms set cdclk to the ref clock here, not sure
>> > >> > > > > if it's ok to leave it uninited. With that change it looks ok:
>> > >> > > >
>> > >> > > > Not sure how to address this here...
>> > >> > > > I see bxt and skl using the cdclk_state here...
>> > >> > >
>> > >> > > Assuming refclk is the bypass clock then just doing what the earlier
>> > >> > > platforms do would be correct.
>> > >> >
>> > >> > Yes, according to Bspec the CDCLK freq is the refclock freq when the PLL
>> > >> > is disabled.
>> > >>
>> > >> So, do I need to change anything?
>> > >
>> > > Yes, add the following after cnl_cdclk_pll_update() as done on other
>> > > gen9+ platforms:
>> > >
>> > > cdclk_state->cdclk = cdclk_state->ref;
>> > >
>> > > --Imre
>> > >
>> > >>
>> > >> >
>> > >> > > IIRC there was some platform where the bypass clock wasn't the refclk,
>> > >> > > but that was perhaps some future thing. Either way, whatever the
>> > >> > > bypass clock is we will want the readout to correctly reflect it when
>> > >> > > the PLL is off.
>> > >>
>> > > _______________________________________________
>> > > Intel-gfx mailing list
>> > > Intel-gfx@lists.freedesktop.org
>> > > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
>> >
>> >
>> >
>> > --
>> > Rodrigo Vivi
>> > Blog: http://blog.vivi.eng.br
>> > _______________________________________________
>> > Intel-gfx mailing list
>> > Intel-gfx@lists.freedesktop.org
>> > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
>>
>> --
>> Ville Syrjälä
>> Intel OTC
>> _______________________________________________
>> Intel-gfx mailing list
>> Intel-gfx@lists.freedesktop.org
>> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
>
> --
> Ville Syrjälä
> Intel OTC



-- 
Rodrigo Vivi
Blog: http://blog.vivi.eng.br
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[PATCH 29/67] drm/i915/cnl: Implement .set_cdclk() for CNL

[Rodrigo Vivi]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Add support for changing the cdclk frequency on CNL. Again, quite
similar to BXT, but there are some annoying differences which means
trying to share more code might not be feasible:
* PLL ratio now lives in the PLL enable register
* pcode came from SKL, not from BXT

We support three cdclk frequencies: 168,336,528 Mhz. The first two
use the same PLL frequency, the last one uses a different one meaning
we once again may need to toggle the PLL off and on when changing
cdclk.

v2: Rebased by Rodrigo on top of Ville's cdclk rework.
v3: Respect order of set_ bellow get_ (Ville)

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
---
 drivers/gpu/drm/i915/intel_cdclk.c | 105 +++++++++++++++++++++++++++++++++++++
 1 file changed, 105 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_cdclk.c b/drivers/gpu/drm/i915/intel_cdclk.c
index a4e2bd5..bee4394 100644
--- a/drivers/gpu/drm/i915/intel_cdclk.c
+++ b/drivers/gpu/drm/i915/intel_cdclk.c
@@ -1450,6 +1450,111 @@ static void cnl_get_cdclk(struct drm_i915_private *dev_priv,
 	cdclk_state->cdclk = DIV_ROUND_CLOSEST(cdclk_state->vco, div);
 }
 
+static void cnl_cdclk_pll_disable(struct drm_i915_private *dev_priv)
+{
+	u32 val;
+
+	val = I915_READ(BXT_DE_PLL_ENABLE);
+	val &= ~BXT_DE_PLL_PLL_ENABLE;
+	I915_WRITE(BXT_DE_PLL_ENABLE, val);
+
+	/* Timeout 200us */
+	if (wait_for((I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_LOCK) == 0, 1))
+		DRM_ERROR("timout waiting for CDCLK PLL unlock\n");
+
+	dev_priv->cdclk.hw.vco = 0;
+}
+
+static void cnl_cdclk_pll_enable(struct drm_i915_private *dev_priv, int vco)
+{
+	int ratio = DIV_ROUND_CLOSEST(vco, dev_priv->cdclk.hw.ref);
+	u32 val;
+
+	val = CNL_CDCLK_PLL_RATIO(ratio);
+	I915_WRITE(BXT_DE_PLL_ENABLE, val);
+
+	val |= BXT_DE_PLL_PLL_ENABLE;
+	I915_WRITE(BXT_DE_PLL_ENABLE, val);
+
+	/* Timeout 200us */
+	if (wait_for((I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_LOCK) != 0, 1))
+		DRM_ERROR("timout waiting for CDCLK PLL lock\n");
+
+	dev_priv->cdclk.hw.vco = vco;
+}
+
+static void cnl_set_cdclk(struct drm_i915_private *dev_priv,
+			  const struct intel_cdclk_state *cdclk_state)
+{
+	int cdclk = cdclk_state->cdclk;
+	int vco = cdclk_state->vco;
+	u32 val, divider, pcu_ack;
+	int ret;
+
+	mutex_lock(&dev_priv->rps.hw_lock);
+	ret = skl_pcode_request(dev_priv, SKL_PCODE_CDCLK_CONTROL,
+				SKL_CDCLK_PREPARE_FOR_CHANGE,
+				SKL_CDCLK_READY_FOR_CHANGE,
+				SKL_CDCLK_READY_FOR_CHANGE, 3);
+	mutex_unlock(&dev_priv->rps.hw_lock);
+	if (ret) {
+		DRM_ERROR("Failed to inform PCU about cdclk change (%d)\n",
+			  ret);
+		return;
+	}
+
+	/* cdclk = vco / 2 / div{1,2} */
+	switch (DIV_ROUND_CLOSEST(vco, cdclk)) {
+	case 4:
+		divider = BXT_CDCLK_CD2X_DIV_SEL_2;
+		break;
+	case 2:
+		divider = BXT_CDCLK_CD2X_DIV_SEL_1;
+		break;
+	default:
+		WARN_ON(cdclk != dev_priv->cdclk.hw.ref);
+		WARN_ON(vco != 0);
+
+		divider = BXT_CDCLK_CD2X_DIV_SEL_1;
+		break;
+	}
+
+	switch (cdclk) {
+	case 528000:
+		pcu_ack = 2;
+		break;
+	case 336000:
+		pcu_ack = 1;
+		break;
+	case 168000:
+	default:
+		pcu_ack = 0;
+		break;
+	}
+
+	if (dev_priv->cdclk.hw.vco != 0 &&
+	    dev_priv->cdclk.hw.vco != vco)
+		cnl_cdclk_pll_disable(dev_priv);
+
+	if (dev_priv->cdclk.hw.vco != vco)
+		cnl_cdclk_pll_enable(dev_priv, vco);
+
+	val = divider | skl_cdclk_decimal(cdclk);
+	/*
+	 * FIXME if only the cd2x divider needs changing, it could be done
+	 * without shutting off the pipe (if only one pipe is active).
+	 */
+	val |= BXT_CDCLK_CD2X_PIPE_NONE;
+	I915_WRITE(CDCLK_CTL, val);
+
+	/* inform PCU of the change */
+	mutex_lock(&dev_priv->rps.hw_lock);
+	sandybridge_pcode_write(dev_priv, SKL_PCODE_CDCLK_CONTROL, pcu_ack);
+	mutex_unlock(&dev_priv->rps.hw_lock);
+
+	intel_update_cdclk(dev_priv);
+}
+
 /**
  * intel_cdclk_state_compare - Determine if two CDCLK states differ
  * @a: first CDCLK state
-- 
1.9.1

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Re: [PATCH 29/67] drm/i915/cnl: Implement .set_cdclk() for CNL

[Imre Deak]

On Thu, Apr 06, 2017 at 12:15:25PM -0700, Rodrigo Vivi wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> Add support for changing the cdclk frequency on CNL. Again, quite
> similar to BXT, but there are some annoying differences which means
> trying to share more code might not be feasible:
> * PLL ratio now lives in the PLL enable register
> * pcode came from SKL, not from BXT
> 
> We support three cdclk frequencies: 168,336,528 Mhz. The first two
> use the same PLL frequency, the last one uses a different one meaning
> we once again may need to toggle the PLL off and on when changing
> cdclk.
> 
> v2: Rebased by Rodrigo on top of Ville's cdclk rework.
> v3: Respect order of set_ bellow get_ (Ville)
> 
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>

Reviewed-by: Imre Deak <imre.deak@intel.com>

> ---
>  drivers/gpu/drm/i915/intel_cdclk.c | 105 +++++++++++++++++++++++++++++++++++++
>  1 file changed, 105 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/intel_cdclk.c b/drivers/gpu/drm/i915/intel_cdclk.c
> index a4e2bd5..bee4394 100644
> --- a/drivers/gpu/drm/i915/intel_cdclk.c
> +++ b/drivers/gpu/drm/i915/intel_cdclk.c
> @@ -1450,6 +1450,111 @@ static void cnl_get_cdclk(struct drm_i915_private *dev_priv,
>  	cdclk_state->cdclk = DIV_ROUND_CLOSEST(cdclk_state->vco, div);
>  }
>  
> +static void cnl_cdclk_pll_disable(struct drm_i915_private *dev_priv)
> +{
> +	u32 val;
> +
> +	val = I915_READ(BXT_DE_PLL_ENABLE);
> +	val &= ~BXT_DE_PLL_PLL_ENABLE;
> +	I915_WRITE(BXT_DE_PLL_ENABLE, val);
> +
> +	/* Timeout 200us */
> +	if (wait_for((I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_LOCK) == 0, 1))
> +		DRM_ERROR("timout waiting for CDCLK PLL unlock\n");
> +
> +	dev_priv->cdclk.hw.vco = 0;
> +}
> +
> +static void cnl_cdclk_pll_enable(struct drm_i915_private *dev_priv, int vco)
> +{
> +	int ratio = DIV_ROUND_CLOSEST(vco, dev_priv->cdclk.hw.ref);
> +	u32 val;
> +
> +	val = CNL_CDCLK_PLL_RATIO(ratio);
> +	I915_WRITE(BXT_DE_PLL_ENABLE, val);
> +
> +	val |= BXT_DE_PLL_PLL_ENABLE;
> +	I915_WRITE(BXT_DE_PLL_ENABLE, val);
> +
> +	/* Timeout 200us */
> +	if (wait_for((I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_LOCK) != 0, 1))
> +		DRM_ERROR("timout waiting for CDCLK PLL lock\n");
> +
> +	dev_priv->cdclk.hw.vco = vco;
> +}
> +
> +static void cnl_set_cdclk(struct drm_i915_private *dev_priv,
> +			  const struct intel_cdclk_state *cdclk_state)
> +{
> +	int cdclk = cdclk_state->cdclk;
> +	int vco = cdclk_state->vco;
> +	u32 val, divider, pcu_ack;
> +	int ret;
> +
> +	mutex_lock(&dev_priv->rps.hw_lock);
> +	ret = skl_pcode_request(dev_priv, SKL_PCODE_CDCLK_CONTROL,
> +				SKL_CDCLK_PREPARE_FOR_CHANGE,
> +				SKL_CDCLK_READY_FOR_CHANGE,
> +				SKL_CDCLK_READY_FOR_CHANGE, 3);
> +	mutex_unlock(&dev_priv->rps.hw_lock);
> +	if (ret) {
> +		DRM_ERROR("Failed to inform PCU about cdclk change (%d)\n",
> +			  ret);
> +		return;
> +	}
> +
> +	/* cdclk = vco / 2 / div{1,2} */
> +	switch (DIV_ROUND_CLOSEST(vco, cdclk)) {
> +	case 4:
> +		divider = BXT_CDCLK_CD2X_DIV_SEL_2;
> +		break;
> +	case 2:
> +		divider = BXT_CDCLK_CD2X_DIV_SEL_1;
> +		break;
> +	default:
> +		WARN_ON(cdclk != dev_priv->cdclk.hw.ref);
> +		WARN_ON(vco != 0);
> +
> +		divider = BXT_CDCLK_CD2X_DIV_SEL_1;
> +		break;
> +	}
> +
> +	switch (cdclk) {
> +	case 528000:
> +		pcu_ack = 2;
> +		break;
> +	case 336000:
> +		pcu_ack = 1;
> +		break;
> +	case 168000:
> +	default:
> +		pcu_ack = 0;
> +		break;
> +	}
> +
> +	if (dev_priv->cdclk.hw.vco != 0 &&
> +	    dev_priv->cdclk.hw.vco != vco)
> +		cnl_cdclk_pll_disable(dev_priv);
> +
> +	if (dev_priv->cdclk.hw.vco != vco)
> +		cnl_cdclk_pll_enable(dev_priv, vco);
> +
> +	val = divider | skl_cdclk_decimal(cdclk);
> +	/*
> +	 * FIXME if only the cd2x divider needs changing, it could be done
> +	 * without shutting off the pipe (if only one pipe is active).
> +	 */
> +	val |= BXT_CDCLK_CD2X_PIPE_NONE;
> +	I915_WRITE(CDCLK_CTL, val);
> +
> +	/* inform PCU of the change */
> +	mutex_lock(&dev_priv->rps.hw_lock);
> +	sandybridge_pcode_write(dev_priv, SKL_PCODE_CDCLK_CONTROL, pcu_ack);
> +	mutex_unlock(&dev_priv->rps.hw_lock);
> +
> +	intel_update_cdclk(dev_priv);
> +}
> +
>  /**
>   * intel_cdclk_state_compare - Determine if two CDCLK states differ
>   * @a: first CDCLK state
> -- 
> 1.9.1
> 
> _______________________________________________
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> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
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[PATCH 30/67] drm/i915/cnl: Implement CNL display init/unit sequence

[Rodrigo Vivi]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Implement the CNL display init/uninit sequence as outlined in Bspec.

Quite similar to SKL/BXT. The main complicaiton is probably the extra
procmon setup we must do based on the process/voltage information we
can read out from some register.

For now we assume DMC will handle the AUX wells, and we'll just enable
all of them during the init sequence. Even if DMC will handle them, we
should perhaps trim the set of enabled wells based on which DDI ports
are actually present.

v2: s/skl_dbuf/gen9_dbuf/ to follow upstream
    bxt needed a cdclk sanitize step, so let's add it for cnl too
v3: s/CHICKEN_MISC_1/CHICKEN_MISC_2/ (Ander)
v4: Rebased by Rodrigo after Ville's cdclk rework
v5: Removed unecessary Aux IO forced enable/disable, Fix DW10 setup
    Fix procpon Mask. (Credits-to Paulo and Clint)
    Remove A0 workaround.
v6: Rebased on top of recent code (Rodrigo).
v7: Respect the order of sanitize_ after set_
    (Done by Rodrigo, Requested by Ville)

Cc: Paulo Zanoni <paulo.r.zanoni@intel.com>
Cc: Clint Taylor <clinton.a.taylor@intel.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h         |  25 +++++++
 drivers/gpu/drm/i915/intel_cdclk.c      | 108 ++++++++++++++++++++++++++++++
 drivers/gpu/drm/i915/intel_drv.h        |   2 +
 drivers/gpu/drm/i915/intel_runtime_pm.c | 113 +++++++++++++++++++++++++++++++-
 4 files changed, 246 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 8353892..3cfc65f 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -1655,6 +1655,9 @@ enum skl_disp_power_wells {
 #define   PHY_RESERVED			(1 << 7)
 #define BXT_PORT_CL1CM_DW0(phy)		_BXT_PHY((phy), _PORT_CL1CM_DW0_BC)
 
+#define CNL_PORT_CL1CM_DW5		_MMIO(0x162014)
+#define   CL_POWER_DOWN_ENABLE		(1 << 4)
+
 #define _PORT_CL1CM_DW9_A		0x162024
 #define _PORT_CL1CM_DW9_BC		0x6C024
 #define   IREF0RC_OFFSET_SHIFT		8
@@ -1687,6 +1690,25 @@ enum skl_disp_power_wells {
 #define BXT_PORT_CL2CM_DW6(phy)		_BXT_PHY((phy), _PORT_CL2CM_DW6_BC)
 #define   DW6_OLDO_DYN_PWR_DOWN_EN	(1 << 28)
 
+#define CNL_PORT_COMP_DW0		_MMIO(0x162100)
+#define   COMP_INIT			(1 << 31)
+#define CNL_PORT_COMP_DW1		_MMIO(0x162104)
+#define CNL_PORT_COMP_DW3		_MMIO(0x16210c)
+#define   PROCESS_INFO_DOT_0		(0 << 26)
+#define   PROCESS_INFO_DOT_1		(1 << 26)
+#define   PROCESS_INFO_DOT_4		(2 << 26)
+#define   PROCESS_INFO_MASK		(7 << 26)
+#define   PROCESS_INFO_SHIFT		26
+#define   VOLTAGE_INFO_0_85V		(0 << 24)
+#define   VOLTAGE_INFO_0_95V		(1 << 24)
+#define   VOLTAGE_INFO_1_05V		(2 << 24)
+#define   VOLTAGE_INFO_MASK		(3 << 24)
+#define   VOLTAGE_INFO_SHIFT		24
+#define CNL_PORT_COMP_DW8		_MMIO(0x162120)
+#define   PRDIC_ICOMP_DIS		(1 << 14)
+#define CNL_PORT_COMP_DW9		_MMIO(0x162124)
+#define CNL_PORT_COMP_DW10		_MMIO(0x162128)
+
 /* BXT PHY Ref registers */
 #define _PORT_REF_DW3_A			0x16218C
 #define _PORT_REF_DW3_BC		0x6C18C
@@ -6517,6 +6539,9 @@ enum {
 #define  GLK_CL1_PWR_DOWN	(1 << 11)
 #define  GLK_CL2_PWR_DOWN	(1 << 12)
 
+#define CHICKEN_MISC_2		_MMIO(0x42084)
+#define  COMP_PWR_DOWN		(1 << 23)
+
 #define _CHICKEN_PIPESL_1_A	0x420b0
 #define _CHICKEN_PIPESL_1_B	0x420b4
 #define  HSW_FBCQ_DIS			(1 << 22)
diff --git a/drivers/gpu/drm/i915/intel_cdclk.c b/drivers/gpu/drm/i915/intel_cdclk.c
index bee4394..f9ba1e7 100644
--- a/drivers/gpu/drm/i915/intel_cdclk.c
+++ b/drivers/gpu/drm/i915/intel_cdclk.c
@@ -1555,6 +1555,114 @@ static void cnl_set_cdclk(struct drm_i915_private *dev_priv,
 	intel_update_cdclk(dev_priv);
 }
 
+static int cnl_cdclk_pll_vco(struct drm_i915_private *dev_priv, int cdclk)
+{
+	int ratio;
+
+	if (cdclk == dev_priv->cdclk.hw.ref)
+		return 0;
+
+	switch (cdclk) {
+	default:
+		MISSING_CASE(cdclk);
+	case 168000:
+	case 336000:
+		ratio = dev_priv->cdclk.hw.ref == 19200 ? 35 : 28;
+		break;
+	case 528000:
+		ratio = dev_priv->cdclk.hw.ref == 19200 ? 55 : 44;
+		break;
+	}
+
+	return dev_priv->cdclk.hw.ref * ratio;
+}
+
+static void cnl_sanitize_cdclk(struct drm_i915_private *dev_priv)
+{
+	u32 cdctl, expected;
+
+	intel_update_cdclk(dev_priv);
+
+	if (dev_priv->cdclk.hw.vco == 0 ||
+	    dev_priv->cdclk.hw.cdclk == dev_priv->cdclk.hw.ref)
+		goto sanitize;
+
+	/* DPLL okay; verify the cdclock
+	 *
+	 * Some BIOS versions leave an incorrect decimal frequency value and
+	 * set reserved MBZ bits in CDCLK_CTL at least during exiting from S4,
+	 * so sanitize this register.
+	 */
+	cdctl = I915_READ(CDCLK_CTL);
+	/*
+	 * Let's ignore the pipe field, since BIOS could have configured the
+	 * dividers both synching to an active pipe, or asynchronously
+	 * (PIPE_NONE).
+	 */
+	cdctl &= ~BXT_CDCLK_CD2X_PIPE_NONE;
+
+	expected = (cdctl & BXT_CDCLK_CD2X_DIV_SEL_MASK) |
+		   skl_cdclk_decimal(dev_priv->cdclk.hw.cdclk);
+
+	if (cdctl == expected)
+		/* All well; nothing to sanitize */
+		return;
+
+sanitize:
+	DRM_DEBUG_KMS("Sanitizing cdclk programmed by pre-os\n");
+
+	/* force cdclk programming */
+	dev_priv->cdclk.hw.cdclk = 0;
+
+	/* force full PLL disable + enable */
+	dev_priv->cdclk.hw.vco = -1;
+}
+
+/**
+ * cnl_init_cdclk - Initialize CDCLK on CNL
+ * @dev_priv: i915 device
+ *
+ * Initialize CDCLK for CNL. This is generally
+ * done only during the display core initialization sequence,
+ * after which the DMC will take care of turning CDCLK off/on
+ * as needed.
+ */
+
+void cnl_init_cdclk(struct drm_i915_private *dev_priv)
+{
+	struct intel_cdclk_state cdclk_state;
+
+	cnl_sanitize_cdclk(dev_priv);
+
+	if (dev_priv->cdclk.hw.cdclk != 0 &&
+	    dev_priv->cdclk.hw.vco != 0)
+		return;
+
+	cdclk_state = dev_priv->cdclk.hw;
+
+	cdclk_state.cdclk = 168000;
+	cdclk_state.vco = cnl_cdclk_pll_vco(dev_priv, cdclk_state.cdclk);
+
+	cnl_set_cdclk(dev_priv, &cdclk_state);
+}
+
+/**
+ * cnl_uninit_cdclk - Uninitialize CDCLK on CNL
+ * @dev_priv: i915 device
+ *
+ * Uninitialize CDCLK for CNL. This is done only
+ * during the display core uninitialization sequence.
+ */
+void cnl_uninit_cdclk(struct drm_i915_private *dev_priv)
+{
+	struct intel_cdclk_state cdclk_state = dev_priv->cdclk.hw;
+
+	cdclk_state.cdclk = cdclk_state.ref;
+	cdclk_state.vco = 0;
+
+	cnl_set_cdclk(dev_priv, &cdclk_state);
+}
+
 /**
  * intel_cdclk_state_compare - Determine if two CDCLK states differ
  * @a: first CDCLK state
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 7bc0c25..a526e6e 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -1280,6 +1280,8 @@ void intel_audio_codec_enable(struct intel_encoder *encoder,
 /* intel_cdclk.c */
 void skl_init_cdclk(struct drm_i915_private *dev_priv);
 void skl_uninit_cdclk(struct drm_i915_private *dev_priv);
+void cnl_init_cdclk(struct drm_i915_private *dev_priv);
+void cnl_uninit_cdclk(struct drm_i915_private *dev_priv);
 void bxt_init_cdclk(struct drm_i915_private *dev_priv);
 void bxt_uninit_cdclk(struct drm_i915_private *dev_priv);
 void intel_init_cdclk_hooks(struct drm_i915_private *dev_priv);
diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c b/drivers/gpu/drm/i915/intel_runtime_pm.c
index 1797c91..5c3c6ec 100644
--- a/drivers/gpu/drm/i915/intel_runtime_pm.c
+++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
@@ -2698,6 +2698,111 @@ void bxt_display_core_uninit(struct drm_i915_private *dev_priv)
 	mutex_unlock(&power_domains->lock);
 }
 
+#define CNL_PROCMON_IDX(val) \
+	(((val) & (PROCESS_INFO_MASK | VOLTAGE_INFO_MASK)) >> VOLTAGE_INFO_SHIFT)
+#define NUM_CNL_PROCMON \
+	(CNL_PROCMON_IDX(VOLTAGE_INFO_MASK | PROCESS_INFO_MASK) + 1)
+
+static const struct cnl_procmon {
+	u32 dw1, dw9, dw10;
+} cnl_procmon_values[NUM_CNL_PROCMON] = {
+	[CNL_PROCMON_IDX(VOLTAGE_INFO_0_85V | PROCESS_INFO_DOT_0)] =
+		{ .dw1 = 0x00 << 16, .dw9 = 0x62AB67BB, .dw10 = 0x51914F96, },
+	[CNL_PROCMON_IDX(VOLTAGE_INFO_0_95V | PROCESS_INFO_DOT_0)] =
+		{ .dw1 = 0x00 << 16, .dw9 = 0x86E172C7, .dw10 = 0x77CA5EAB, },
+	[CNL_PROCMON_IDX(VOLTAGE_INFO_0_95V | PROCESS_INFO_DOT_1)] =
+		{ .dw1 = 0x00 << 16, .dw9 = 0x93F87FE1, .dw10 = 0x8AE871C5, },
+	[CNL_PROCMON_IDX(VOLTAGE_INFO_1_05V | PROCESS_INFO_DOT_0)] =
+		{ .dw1 = 0x00 << 16, .dw9 = 0x98FA82DD, .dw10 = 0x89E46DC1, },
+	[CNL_PROCMON_IDX(VOLTAGE_INFO_1_05V | PROCESS_INFO_DOT_1)] =
+		{ .dw1 = 0x44 << 16, .dw9 = 0x9A00AB25, .dw10 = 0x8AE38FF1, },
+};
+
+static void cnl_display_core_init(struct drm_i915_private *dev_priv, bool resume)
+{
+	struct i915_power_domains *power_domains = &dev_priv->power_domains;
+	const struct cnl_procmon *procmon;
+	struct i915_power_well *well;
+	u32 val;
+
+	gen9_set_dc_state(dev_priv, DC_STATE_DISABLE);
+
+	/* 1. Enable PCH Reset Handshake */
+	val = I915_READ(HSW_NDE_RSTWRN_OPT);
+	val |= RESET_PCH_HANDSHAKE_ENABLE;
+	I915_WRITE(HSW_NDE_RSTWRN_OPT, val);
+
+	/* 2. Enable Comp */
+	val = I915_READ(CHICKEN_MISC_2);
+	val &= ~COMP_PWR_DOWN;
+	I915_WRITE(CHICKEN_MISC_2, val);
+
+	val = I915_READ(CNL_PORT_COMP_DW3);
+	procmon = &cnl_procmon_values[CNL_PROCMON_IDX(val)];
+
+	WARN_ON(procmon->dw10 == 0);
+
+	val = I915_READ(CNL_PORT_COMP_DW1);
+	val &= ~((0xff << 16) | 0xff);
+	val |= procmon->dw1;
+	I915_WRITE(CNL_PORT_COMP_DW1, val);
+
+	I915_WRITE(CNL_PORT_COMP_DW9, procmon->dw9);
+	I915_WRITE(CNL_PORT_COMP_DW10, procmon->dw10);
+
+	val = I915_READ(CNL_PORT_COMP_DW0);
+	val |= COMP_INIT;
+	I915_WRITE(CNL_PORT_COMP_DW0, val);
+
+	/* 3. */
+	val = I915_READ(CNL_PORT_CL1CM_DW5);
+	val |= CL_POWER_DOWN_ENABLE;
+	I915_WRITE(CNL_PORT_CL1CM_DW5, val);
+
+	/* 4. Enable Power Well 1 (PG1) and Aux IO Power */
+	mutex_lock(&power_domains->lock);
+	well = lookup_power_well(dev_priv, SKL_DISP_PW_1);
+	intel_power_well_enable(dev_priv, well);
+	mutex_unlock(&power_domains->lock);
+
+	/* 5. Enable CD clock */
+	cnl_init_cdclk(dev_priv);
+
+	/* 6. Enable DBUF */
+	gen9_dbuf_enable(dev_priv);
+}
+
+#undef CNL_PROCMON_IDX
+#undef NUM_CNL_PROCMON
+
+static void cnl_display_core_uninit(struct drm_i915_private *dev_priv)
+{
+	struct i915_power_domains *power_domains = &dev_priv->power_domains;
+	struct i915_power_well *well;
+	u32 val;
+
+	gen9_set_dc_state(dev_priv, DC_STATE_DISABLE);
+
+	/* 1. Disable all display engine functions -> aready done */
+
+	/* 2. Disable DBUF */
+	gen9_dbuf_disable(dev_priv);
+
+	/* 3. Disable CD clock */
+	cnl_uninit_cdclk(dev_priv);
+
+	/* 4. Disable Power Well 1 (PG1) and Aux IO Power */
+	mutex_lock(&power_domains->lock);
+	well = lookup_power_well(dev_priv, SKL_DISP_PW_1);
+	intel_power_well_disable(dev_priv, well);
+	mutex_unlock(&power_domains->lock);
+
+	/* 5. Disable Comp */
+	val = I915_READ(CHICKEN_MISC_2);
+	val |= COMP_PWR_DOWN;
+	I915_WRITE(CHICKEN_MISC_2, val);
+}
+
 static void chv_phy_control_init(struct drm_i915_private *dev_priv)
 {
 	struct i915_power_well *cmn_bc =
@@ -2830,7 +2935,9 @@ void intel_power_domains_init_hw(struct drm_i915_private *dev_priv, bool resume)
 
 	power_domains->initializing = true;
 
-	if (IS_GEN9_BC(dev_priv)) {
+	if (IS_CANNONLAKE(dev_priv)) {
+		cnl_display_core_init(dev_priv, resume);
+	} else if (IS_GEN9_BC(dev_priv)) {
 		skl_display_core_init(dev_priv, resume);
 	} else if (IS_GEN9_LP(dev_priv)) {
 		bxt_display_core_init(dev_priv, resume);
@@ -2869,7 +2976,9 @@ void intel_power_domains_suspend(struct drm_i915_private *dev_priv)
 	if (!i915.disable_power_well)
 		intel_display_power_put(dev_priv, POWER_DOMAIN_INIT);
 
-	if (IS_GEN9_BC(dev_priv))
+	if (IS_CANNONLAKE(dev_priv))
+		cnl_display_core_uninit(dev_priv);
+	else if (IS_GEN9_BC(dev_priv))
 		skl_display_core_uninit(dev_priv);
 	else if (IS_GEN9_LP(dev_priv))
 		bxt_display_core_uninit(dev_priv);
-- 
1.9.1

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[PATCH] drm/i915/cnl: Implement CNL display init/unit sequence

[Rodrigo Vivi]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Implement the CNL display init/uninit sequence as outlined in Bspec.

Quite similar to SKL/BXT. The main complicaiton is probably the extra
procmon setup we must do based on the process/voltage information we
can read out from some register.

For now we assume DMC will handle the AUX wells, and we'll just enable
all of them during the init sequence. Even if DMC will handle them, we
should perhaps trim the set of enabled wells based on which DDI ports
are actually present.

v2: s/skl_dbuf/gen9_dbuf/ to follow upstream
    bxt needed a cdclk sanitize step, so let's add it for cnl too
v3: s/CHICKEN_MISC_1/CHICKEN_MISC_2/ (Ander)
v4: Rebased by Rodrigo after Ville's cdclk rework
v5: Removed unecessary Aux IO forced enable/disable, Fix DW10 setup
    Fix procpon Mask. (Credits-to Paulo and Clint)
    Remove A0 workaround.
v6: Rebased on top of recent code (Rodrigo).
v7: Respect the order of sanitize_ after set_
    (Done by Rodrigo, Requested by Ville)
v8: (Rodrigo) Remove CHICKEN_MISC_2 double definition.

Cc: Paulo Zanoni <paulo.r.zanoni@intel.com>
Cc: Clint Taylor <clinton.a.taylor@intel.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h         |  23 +++++++
 drivers/gpu/drm/i915/intel_cdclk.c      | 108 ++++++++++++++++++++++++++++++
 drivers/gpu/drm/i915/intel_drv.h        |   2 +
 drivers/gpu/drm/i915/intel_runtime_pm.c | 113 +++++++++++++++++++++++++++++++-
 4 files changed, 244 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 8353892..9b2d8c0 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -1655,6 +1655,9 @@ enum skl_disp_power_wells {
 #define   PHY_RESERVED			(1 << 7)
 #define BXT_PORT_CL1CM_DW0(phy)		_BXT_PHY((phy), _PORT_CL1CM_DW0_BC)
 
+#define CNL_PORT_CL1CM_DW5		_MMIO(0x162014)
+#define   CL_POWER_DOWN_ENABLE		(1 << 4)
+
 #define _PORT_CL1CM_DW9_A		0x162024
 #define _PORT_CL1CM_DW9_BC		0x6C024
 #define   IREF0RC_OFFSET_SHIFT		8
@@ -1687,6 +1690,25 @@ enum skl_disp_power_wells {
 #define BXT_PORT_CL2CM_DW6(phy)		_BXT_PHY((phy), _PORT_CL2CM_DW6_BC)
 #define   DW6_OLDO_DYN_PWR_DOWN_EN	(1 << 28)
 
+#define CNL_PORT_COMP_DW0		_MMIO(0x162100)
+#define   COMP_INIT			(1 << 31)
+#define CNL_PORT_COMP_DW1		_MMIO(0x162104)
+#define CNL_PORT_COMP_DW3		_MMIO(0x16210c)
+#define   PROCESS_INFO_DOT_0		(0 << 26)
+#define   PROCESS_INFO_DOT_1		(1 << 26)
+#define   PROCESS_INFO_DOT_4		(2 << 26)
+#define   PROCESS_INFO_MASK		(7 << 26)
+#define   PROCESS_INFO_SHIFT		26
+#define   VOLTAGE_INFO_0_85V		(0 << 24)
+#define   VOLTAGE_INFO_0_95V		(1 << 24)
+#define   VOLTAGE_INFO_1_05V		(2 << 24)
+#define   VOLTAGE_INFO_MASK		(3 << 24)
+#define   VOLTAGE_INFO_SHIFT		24
+#define CNL_PORT_COMP_DW8		_MMIO(0x162120)
+#define   PRDIC_ICOMP_DIS		(1 << 14)
+#define CNL_PORT_COMP_DW9		_MMIO(0x162124)
+#define CNL_PORT_COMP_DW10		_MMIO(0x162128)
+
 /* BXT PHY Ref registers */
 #define _PORT_REF_DW3_A			0x16218C
 #define _PORT_REF_DW3_BC		0x6C18C
@@ -6513,6 +6535,7 @@ enum {
 #define  KVM_CONFIG_CHANGE_NOTIFICATION_SELECT	(1 << 14)
 
 #define CHICKEN_MISC_2		_MMIO(0x42084)
+#define  COMP_PWR_DOWN		(1 << 23)
 #define  GLK_CL0_PWR_DOWN	(1 << 10)
 #define  GLK_CL1_PWR_DOWN	(1 << 11)
 #define  GLK_CL2_PWR_DOWN	(1 << 12)
diff --git a/drivers/gpu/drm/i915/intel_cdclk.c b/drivers/gpu/drm/i915/intel_cdclk.c
index bee4394..f9ba1e7 100644
--- a/drivers/gpu/drm/i915/intel_cdclk.c
+++ b/drivers/gpu/drm/i915/intel_cdclk.c
@@ -1555,6 +1555,114 @@ static void cnl_set_cdclk(struct drm_i915_private *dev_priv,
 	intel_update_cdclk(dev_priv);
 }
 
+static int cnl_cdclk_pll_vco(struct drm_i915_private *dev_priv, int cdclk)
+{
+	int ratio;
+
+	if (cdclk == dev_priv->cdclk.hw.ref)
+		return 0;
+
+	switch (cdclk) {
+	default:
+		MISSING_CASE(cdclk);
+	case 168000:
+	case 336000:
+		ratio = dev_priv->cdclk.hw.ref == 19200 ? 35 : 28;
+		break;
+	case 528000:
+		ratio = dev_priv->cdclk.hw.ref == 19200 ? 55 : 44;
+		break;
+	}
+
+	return dev_priv->cdclk.hw.ref * ratio;
+}
+
+static void cnl_sanitize_cdclk(struct drm_i915_private *dev_priv)
+{
+	u32 cdctl, expected;
+
+	intel_update_cdclk(dev_priv);
+
+	if (dev_priv->cdclk.hw.vco == 0 ||
+	    dev_priv->cdclk.hw.cdclk == dev_priv->cdclk.hw.ref)
+		goto sanitize;
+
+	/* DPLL okay; verify the cdclock
+	 *
+	 * Some BIOS versions leave an incorrect decimal frequency value and
+	 * set reserved MBZ bits in CDCLK_CTL at least during exiting from S4,
+	 * so sanitize this register.
+	 */
+	cdctl = I915_READ(CDCLK_CTL);
+	/*
+	 * Let's ignore the pipe field, since BIOS could have configured the
+	 * dividers both synching to an active pipe, or asynchronously
+	 * (PIPE_NONE).
+	 */
+	cdctl &= ~BXT_CDCLK_CD2X_PIPE_NONE;
+
+	expected = (cdctl & BXT_CDCLK_CD2X_DIV_SEL_MASK) |
+		   skl_cdclk_decimal(dev_priv->cdclk.hw.cdclk);
+
+	if (cdctl == expected)
+		/* All well; nothing to sanitize */
+		return;
+
+sanitize:
+	DRM_DEBUG_KMS("Sanitizing cdclk programmed by pre-os\n");
+
+	/* force cdclk programming */
+	dev_priv->cdclk.hw.cdclk = 0;
+
+	/* force full PLL disable + enable */
+	dev_priv->cdclk.hw.vco = -1;
+}
+
+/**
+ * cnl_init_cdclk - Initialize CDCLK on CNL
+ * @dev_priv: i915 device
+ *
+ * Initialize CDCLK for CNL. This is generally
+ * done only during the display core initialization sequence,
+ * after which the DMC will take care of turning CDCLK off/on
+ * as needed.
+ */
+
+void cnl_init_cdclk(struct drm_i915_private *dev_priv)
+{
+	struct intel_cdclk_state cdclk_state;
+
+	cnl_sanitize_cdclk(dev_priv);
+
+	if (dev_priv->cdclk.hw.cdclk != 0 &&
+	    dev_priv->cdclk.hw.vco != 0)
+		return;
+
+	cdclk_state = dev_priv->cdclk.hw;
+
+	cdclk_state.cdclk = 168000;
+	cdclk_state.vco = cnl_cdclk_pll_vco(dev_priv, cdclk_state.cdclk);
+
+	cnl_set_cdclk(dev_priv, &cdclk_state);
+}
+
+/**
+ * cnl_uninit_cdclk - Uninitialize CDCLK on CNL
+ * @dev_priv: i915 device
+ *
+ * Uninitialize CDCLK for CNL. This is done only
+ * during the display core uninitialization sequence.
+ */
+void cnl_uninit_cdclk(struct drm_i915_private *dev_priv)
+{
+	struct intel_cdclk_state cdclk_state = dev_priv->cdclk.hw;
+
+	cdclk_state.cdclk = cdclk_state.ref;
+	cdclk_state.vco = 0;
+
+	cnl_set_cdclk(dev_priv, &cdclk_state);
+}
+
 /**
  * intel_cdclk_state_compare - Determine if two CDCLK states differ
  * @a: first CDCLK state
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 7bc0c25..a526e6e 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -1280,6 +1280,8 @@ void intel_audio_codec_enable(struct intel_encoder *encoder,
 /* intel_cdclk.c */
 void skl_init_cdclk(struct drm_i915_private *dev_priv);
 void skl_uninit_cdclk(struct drm_i915_private *dev_priv);
+void cnl_init_cdclk(struct drm_i915_private *dev_priv);
+void cnl_uninit_cdclk(struct drm_i915_private *dev_priv);
 void bxt_init_cdclk(struct drm_i915_private *dev_priv);
 void bxt_uninit_cdclk(struct drm_i915_private *dev_priv);
 void intel_init_cdclk_hooks(struct drm_i915_private *dev_priv);
diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c b/drivers/gpu/drm/i915/intel_runtime_pm.c
index 1797c91..5c3c6ec 100644
--- a/drivers/gpu/drm/i915/intel_runtime_pm.c
+++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
@@ -2698,6 +2698,111 @@ void bxt_display_core_uninit(struct drm_i915_private *dev_priv)
 	mutex_unlock(&power_domains->lock);
 }
 
+#define CNL_PROCMON_IDX(val) \
+	(((val) & (PROCESS_INFO_MASK | VOLTAGE_INFO_MASK)) >> VOLTAGE_INFO_SHIFT)
+#define NUM_CNL_PROCMON \
+	(CNL_PROCMON_IDX(VOLTAGE_INFO_MASK | PROCESS_INFO_MASK) + 1)
+
+static const struct cnl_procmon {
+	u32 dw1, dw9, dw10;
+} cnl_procmon_values[NUM_CNL_PROCMON] = {
+	[CNL_PROCMON_IDX(VOLTAGE_INFO_0_85V | PROCESS_INFO_DOT_0)] =
+		{ .dw1 = 0x00 << 16, .dw9 = 0x62AB67BB, .dw10 = 0x51914F96, },
+	[CNL_PROCMON_IDX(VOLTAGE_INFO_0_95V | PROCESS_INFO_DOT_0)] =
+		{ .dw1 = 0x00 << 16, .dw9 = 0x86E172C7, .dw10 = 0x77CA5EAB, },
+	[CNL_PROCMON_IDX(VOLTAGE_INFO_0_95V | PROCESS_INFO_DOT_1)] =
+		{ .dw1 = 0x00 << 16, .dw9 = 0x93F87FE1, .dw10 = 0x8AE871C5, },
+	[CNL_PROCMON_IDX(VOLTAGE_INFO_1_05V | PROCESS_INFO_DOT_0)] =
+		{ .dw1 = 0x00 << 16, .dw9 = 0x98FA82DD, .dw10 = 0x89E46DC1, },
+	[CNL_PROCMON_IDX(VOLTAGE_INFO_1_05V | PROCESS_INFO_DOT_1)] =
+		{ .dw1 = 0x44 << 16, .dw9 = 0x9A00AB25, .dw10 = 0x8AE38FF1, },
+};
+
+static void cnl_display_core_init(struct drm_i915_private *dev_priv, bool resume)
+{
+	struct i915_power_domains *power_domains = &dev_priv->power_domains;
+	const struct cnl_procmon *procmon;
+	struct i915_power_well *well;
+	u32 val;
+
+	gen9_set_dc_state(dev_priv, DC_STATE_DISABLE);
+
+	/* 1. Enable PCH Reset Handshake */
+	val = I915_READ(HSW_NDE_RSTWRN_OPT);
+	val |= RESET_PCH_HANDSHAKE_ENABLE;
+	I915_WRITE(HSW_NDE_RSTWRN_OPT, val);
+
+	/* 2. Enable Comp */
+	val = I915_READ(CHICKEN_MISC_2);
+	val &= ~COMP_PWR_DOWN;
+	I915_WRITE(CHICKEN_MISC_2, val);
+
+	val = I915_READ(CNL_PORT_COMP_DW3);
+	procmon = &cnl_procmon_values[CNL_PROCMON_IDX(val)];
+
+	WARN_ON(procmon->dw10 == 0);
+
+	val = I915_READ(CNL_PORT_COMP_DW1);
+	val &= ~((0xff << 16) | 0xff);
+	val |= procmon->dw1;
+	I915_WRITE(CNL_PORT_COMP_DW1, val);
+
+	I915_WRITE(CNL_PORT_COMP_DW9, procmon->dw9);
+	I915_WRITE(CNL_PORT_COMP_DW10, procmon->dw10);
+
+	val = I915_READ(CNL_PORT_COMP_DW0);
+	val |= COMP_INIT;
+	I915_WRITE(CNL_PORT_COMP_DW0, val);
+
+	/* 3. */
+	val = I915_READ(CNL_PORT_CL1CM_DW5);
+	val |= CL_POWER_DOWN_ENABLE;
+	I915_WRITE(CNL_PORT_CL1CM_DW5, val);
+
+	/* 4. Enable Power Well 1 (PG1) and Aux IO Power */
+	mutex_lock(&power_domains->lock);
+	well = lookup_power_well(dev_priv, SKL_DISP_PW_1);
+	intel_power_well_enable(dev_priv, well);
+	mutex_unlock(&power_domains->lock);
+
+	/* 5. Enable CD clock */
+	cnl_init_cdclk(dev_priv);
+
+	/* 6. Enable DBUF */
+	gen9_dbuf_enable(dev_priv);
+}
+
+#undef CNL_PROCMON_IDX
+#undef NUM_CNL_PROCMON
+
+static void cnl_display_core_uninit(struct drm_i915_private *dev_priv)
+{
+	struct i915_power_domains *power_domains = &dev_priv->power_domains;
+	struct i915_power_well *well;
+	u32 val;
+
+	gen9_set_dc_state(dev_priv, DC_STATE_DISABLE);
+
+	/* 1. Disable all display engine functions -> aready done */
+
+	/* 2. Disable DBUF */
+	gen9_dbuf_disable(dev_priv);
+
+	/* 3. Disable CD clock */
+	cnl_uninit_cdclk(dev_priv);
+
+	/* 4. Disable Power Well 1 (PG1) and Aux IO Power */
+	mutex_lock(&power_domains->lock);
+	well = lookup_power_well(dev_priv, SKL_DISP_PW_1);
+	intel_power_well_disable(dev_priv, well);
+	mutex_unlock(&power_domains->lock);
+
+	/* 5. Disable Comp */
+	val = I915_READ(CHICKEN_MISC_2);
+	val |= COMP_PWR_DOWN;
+	I915_WRITE(CHICKEN_MISC_2, val);
+}
+
 static void chv_phy_control_init(struct drm_i915_private *dev_priv)
 {
 	struct i915_power_well *cmn_bc =
@@ -2830,7 +2935,9 @@ void intel_power_domains_init_hw(struct drm_i915_private *dev_priv, bool resume)
 
 	power_domains->initializing = true;
 
-	if (IS_GEN9_BC(dev_priv)) {
+	if (IS_CANNONLAKE(dev_priv)) {
+		cnl_display_core_init(dev_priv, resume);
+	} else if (IS_GEN9_BC(dev_priv)) {
 		skl_display_core_init(dev_priv, resume);
 	} else if (IS_GEN9_LP(dev_priv)) {
 		bxt_display_core_init(dev_priv, resume);
@@ -2869,7 +2976,9 @@ void intel_power_domains_suspend(struct drm_i915_private *dev_priv)
 	if (!i915.disable_power_well)
 		intel_display_power_put(dev_priv, POWER_DOMAIN_INIT);
 
-	if (IS_GEN9_BC(dev_priv))
+	if (IS_CANNONLAKE(dev_priv))
+		cnl_display_core_uninit(dev_priv);
+	else if (IS_GEN9_BC(dev_priv))
 		skl_display_core_uninit(dev_priv);
 	else if (IS_GEN9_LP(dev_priv))
 		bxt_display_core_uninit(dev_priv);
-- 
1.9.1

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Intel-gfx@lists.freedesktop.org
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Re: [PATCH] drm/i915/cnl: Implement CNL display init/unit sequence

[Imre Deak]

On Thu, Apr 13, 2017 at 09:13:02AM -0700, Rodrigo Vivi wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> Implement the CNL display init/uninit sequence as outlined in Bspec.
> 
> Quite similar to SKL/BXT. The main complicaiton is probably the extra
> procmon setup we must do based on the process/voltage information we
> can read out from some register.
> 
> For now we assume DMC will handle the AUX wells, and we'll just enable
> all of them during the init sequence. Even if DMC will handle them, we
> should perhaps trim the set of enabled wells based on which DDI ports
> are actually present.

The above needs to be aligned with the current version of the code.

Yes, looks like DMC saves/restores the state of both AUX and DDI power
wells. The spec says to enable the AUX wells during init, but I think
it's ok to do this on-demand. 

> 
> v2: s/skl_dbuf/gen9_dbuf/ to follow upstream
>     bxt needed a cdclk sanitize step, so let's add it for cnl too
> v3: s/CHICKEN_MISC_1/CHICKEN_MISC_2/ (Ander)
> v4: Rebased by Rodrigo after Ville's cdclk rework
> v5: Removed unecessary Aux IO forced enable/disable, Fix DW10 setup
>     Fix procpon Mask. (Credits-to Paulo and Clint)
>     Remove A0 workaround.
> v6: Rebased on top of recent code (Rodrigo).
> v7: Respect the order of sanitize_ after set_
>     (Done by Rodrigo, Requested by Ville)
> v8: (Rodrigo) Remove CHICKEN_MISC_2 double definition.
> 
> Cc: Paulo Zanoni <paulo.r.zanoni@intel.com>
> Cc: Clint Taylor <clinton.a.taylor@intel.com>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
> ---
>  drivers/gpu/drm/i915/i915_reg.h         |  23 +++++++
>  drivers/gpu/drm/i915/intel_cdclk.c      | 108 ++++++++++++++++++++++++++++++
>  drivers/gpu/drm/i915/intel_drv.h        |   2 +
>  drivers/gpu/drm/i915/intel_runtime_pm.c | 113 +++++++++++++++++++++++++++++++-
>  4 files changed, 244 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 8353892..9b2d8c0 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -1655,6 +1655,9 @@ enum skl_disp_power_wells {
>  #define   PHY_RESERVED			(1 << 7)
>  #define BXT_PORT_CL1CM_DW0(phy)		_BXT_PHY((phy), _PORT_CL1CM_DW0_BC)
>  
> +#define CNL_PORT_CL1CM_DW5		_MMIO(0x162014)
> +#define   CL_POWER_DOWN_ENABLE		(1 << 4)
> +
>  #define _PORT_CL1CM_DW9_A		0x162024
>  #define _PORT_CL1CM_DW9_BC		0x6C024
>  #define   IREF0RC_OFFSET_SHIFT		8
> @@ -1687,6 +1690,25 @@ enum skl_disp_power_wells {
>  #define BXT_PORT_CL2CM_DW6(phy)		_BXT_PHY((phy), _PORT_CL2CM_DW6_BC)
>  #define   DW6_OLDO_DYN_PWR_DOWN_EN	(1 << 28)
>  
> +#define CNL_PORT_COMP_DW0		_MMIO(0x162100)
> +#define   COMP_INIT			(1 << 31)
> +#define CNL_PORT_COMP_DW1		_MMIO(0x162104)
> +#define CNL_PORT_COMP_DW3		_MMIO(0x16210c)
> +#define   PROCESS_INFO_DOT_0		(0 << 26)
> +#define   PROCESS_INFO_DOT_1		(1 << 26)
> +#define   PROCESS_INFO_DOT_4		(2 << 26)
> +#define   PROCESS_INFO_MASK		(7 << 26)
> +#define   PROCESS_INFO_SHIFT		26
> +#define   VOLTAGE_INFO_0_85V		(0 << 24)
> +#define   VOLTAGE_INFO_0_95V		(1 << 24)
> +#define   VOLTAGE_INFO_1_05V		(2 << 24)
> +#define   VOLTAGE_INFO_MASK		(3 << 24)
> +#define   VOLTAGE_INFO_SHIFT		24
> +#define CNL_PORT_COMP_DW8		_MMIO(0x162120)
> +#define   PRDIC_ICOMP_DIS		(1 << 14)

DW8 looks to be unused.

> +#define CNL_PORT_COMP_DW9		_MMIO(0x162124)
> +#define CNL_PORT_COMP_DW10		_MMIO(0x162128)
> +
>  /* BXT PHY Ref registers */
>  #define _PORT_REF_DW3_A			0x16218C
>  #define _PORT_REF_DW3_BC		0x6C18C
> @@ -6513,6 +6535,7 @@ enum {
>  #define  KVM_CONFIG_CHANGE_NOTIFICATION_SELECT	(1 << 14)
>  
>  #define CHICKEN_MISC_2		_MMIO(0x42084)
> +#define  COMP_PWR_DOWN		(1 << 23)
>  #define  GLK_CL0_PWR_DOWN	(1 << 10)
>  #define  GLK_CL1_PWR_DOWN	(1 << 11)
>  #define  GLK_CL2_PWR_DOWN	(1 << 12)
> diff --git a/drivers/gpu/drm/i915/intel_cdclk.c b/drivers/gpu/drm/i915/intel_cdclk.c
> index bee4394..f9ba1e7 100644
> --- a/drivers/gpu/drm/i915/intel_cdclk.c
> +++ b/drivers/gpu/drm/i915/intel_cdclk.c
> @@ -1555,6 +1555,114 @@ static void cnl_set_cdclk(struct drm_i915_private *dev_priv,
>  	intel_update_cdclk(dev_priv);
>  }
>  
> +static int cnl_cdclk_pll_vco(struct drm_i915_private *dev_priv, int cdclk)
> +{
> +	int ratio;
> +
> +	if (cdclk == dev_priv->cdclk.hw.ref)
> +		return 0;
> +
> +	switch (cdclk) {
> +	default:
> +		MISSING_CASE(cdclk);
> +	case 168000:
> +	case 336000:
> +		ratio = dev_priv->cdclk.hw.ref == 19200 ? 35 : 28;
> +		break;
> +	case 528000:
> +		ratio = dev_priv->cdclk.hw.ref == 19200 ? 55 : 44;
> +		break;
> +	}
> +
> +	return dev_priv->cdclk.hw.ref * ratio;
> +}
> +
> +static void cnl_sanitize_cdclk(struct drm_i915_private *dev_priv)
> +{
> +	u32 cdctl, expected;
> +
> +	intel_update_cdclk(dev_priv);
> +
> +	if (dev_priv->cdclk.hw.vco == 0 ||
> +	    dev_priv->cdclk.hw.cdclk == dev_priv->cdclk.hw.ref)
> +		goto sanitize;
> +
> +	/* DPLL okay; verify the cdclock
> +	 *
> +	 * Some BIOS versions leave an incorrect decimal frequency value and
> +	 * set reserved MBZ bits in CDCLK_CTL at least during exiting from S4,
> +	 * so sanitize this register.
> +	 */
> +	cdctl = I915_READ(CDCLK_CTL);
> +	/*
> +	 * Let's ignore the pipe field, since BIOS could have configured the
> +	 * dividers both synching to an active pipe, or asynchronously
> +	 * (PIPE_NONE).
> +	 */
> +	cdctl &= ~BXT_CDCLK_CD2X_PIPE_NONE;
> +
> +	expected = (cdctl & BXT_CDCLK_CD2X_DIV_SEL_MASK) |
> +		   skl_cdclk_decimal(dev_priv->cdclk.hw.cdclk);
> +
> +	if (cdctl == expected)
> +		/* All well; nothing to sanitize */
> +		return;
> +
> +sanitize:
> +	DRM_DEBUG_KMS("Sanitizing cdclk programmed by pre-os\n");
> +
> +	/* force cdclk programming */
> +	dev_priv->cdclk.hw.cdclk = 0;
> +
> +	/* force full PLL disable + enable */
> +	dev_priv->cdclk.hw.vco = -1;
> +}
> +
> +/**
> + * cnl_init_cdclk - Initialize CDCLK on CNL
> + * @dev_priv: i915 device
> + *
> + * Initialize CDCLK for CNL. This is generally
> + * done only during the display core initialization sequence,
> + * after which the DMC will take care of turning CDCLK off/on
> + * as needed.
> + */
> +

Extra w/s.

Looks ok:
Reviewed-by: Imre Deak <imre.deak@intel.com>

> +void cnl_init_cdclk(struct drm_i915_private *dev_priv)
> +{
> +	struct intel_cdclk_state cdclk_state;
> +
> +	cnl_sanitize_cdclk(dev_priv);
> +
> +	if (dev_priv->cdclk.hw.cdclk != 0 &&
> +	    dev_priv->cdclk.hw.vco != 0)
> +		return;
> +
> +	cdclk_state = dev_priv->cdclk.hw;
> +
> +	cdclk_state.cdclk = 168000;
> +	cdclk_state.vco = cnl_cdclk_pll_vco(dev_priv, cdclk_state.cdclk);
> +
> +	cnl_set_cdclk(dev_priv, &cdclk_state);
> +}
> +
> +/**
> + * cnl_uninit_cdclk - Uninitialize CDCLK on CNL
> + * @dev_priv: i915 device
> + *
> + * Uninitialize CDCLK for CNL. This is done only
> + * during the display core uninitialization sequence.
> + */
> +void cnl_uninit_cdclk(struct drm_i915_private *dev_priv)
> +{
> +	struct intel_cdclk_state cdclk_state = dev_priv->cdclk.hw;
> +
> +	cdclk_state.cdclk = cdclk_state.ref;
> +	cdclk_state.vco = 0;
> +
> +	cnl_set_cdclk(dev_priv, &cdclk_state);
> +}
> +
>  /**
>   * intel_cdclk_state_compare - Determine if two CDCLK states differ
>   * @a: first CDCLK state
> diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
> index 7bc0c25..a526e6e 100644
> --- a/drivers/gpu/drm/i915/intel_drv.h
> +++ b/drivers/gpu/drm/i915/intel_drv.h
> @@ -1280,6 +1280,8 @@ void intel_audio_codec_enable(struct intel_encoder *encoder,
>  /* intel_cdclk.c */
>  void skl_init_cdclk(struct drm_i915_private *dev_priv);
>  void skl_uninit_cdclk(struct drm_i915_private *dev_priv);
> +void cnl_init_cdclk(struct drm_i915_private *dev_priv);
> +void cnl_uninit_cdclk(struct drm_i915_private *dev_priv);
>  void bxt_init_cdclk(struct drm_i915_private *dev_priv);
>  void bxt_uninit_cdclk(struct drm_i915_private *dev_priv);
>  void intel_init_cdclk_hooks(struct drm_i915_private *dev_priv);
> diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c b/drivers/gpu/drm/i915/intel_runtime_pm.c
> index 1797c91..5c3c6ec 100644
> --- a/drivers/gpu/drm/i915/intel_runtime_pm.c
> +++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
> @@ -2698,6 +2698,111 @@ void bxt_display_core_uninit(struct drm_i915_private *dev_priv)
>  	mutex_unlock(&power_domains->lock);
>  }
>  
> +#define CNL_PROCMON_IDX(val) \
> +	(((val) & (PROCESS_INFO_MASK | VOLTAGE_INFO_MASK)) >> VOLTAGE_INFO_SHIFT)
> +#define NUM_CNL_PROCMON \
> +	(CNL_PROCMON_IDX(VOLTAGE_INFO_MASK | PROCESS_INFO_MASK) + 1)
> +
> +static const struct cnl_procmon {
> +	u32 dw1, dw9, dw10;
> +} cnl_procmon_values[NUM_CNL_PROCMON] = {
> +	[CNL_PROCMON_IDX(VOLTAGE_INFO_0_85V | PROCESS_INFO_DOT_0)] =
> +		{ .dw1 = 0x00 << 16, .dw9 = 0x62AB67BB, .dw10 = 0x51914F96, },
> +	[CNL_PROCMON_IDX(VOLTAGE_INFO_0_95V | PROCESS_INFO_DOT_0)] =
> +		{ .dw1 = 0x00 << 16, .dw9 = 0x86E172C7, .dw10 = 0x77CA5EAB, },
> +	[CNL_PROCMON_IDX(VOLTAGE_INFO_0_95V | PROCESS_INFO_DOT_1)] =
> +		{ .dw1 = 0x00 << 16, .dw9 = 0x93F87FE1, .dw10 = 0x8AE871C5, },
> +	[CNL_PROCMON_IDX(VOLTAGE_INFO_1_05V | PROCESS_INFO_DOT_0)] =
> +		{ .dw1 = 0x00 << 16, .dw9 = 0x98FA82DD, .dw10 = 0x89E46DC1, },
> +	[CNL_PROCMON_IDX(VOLTAGE_INFO_1_05V | PROCESS_INFO_DOT_1)] =
> +		{ .dw1 = 0x44 << 16, .dw9 = 0x9A00AB25, .dw10 = 0x8AE38FF1, },
> +};
> +
> +static void cnl_display_core_init(struct drm_i915_private *dev_priv, bool resume)
> +{
> +	struct i915_power_domains *power_domains = &dev_priv->power_domains;
> +	const struct cnl_procmon *procmon;
> +	struct i915_power_well *well;
> +	u32 val;
> +
> +	gen9_set_dc_state(dev_priv, DC_STATE_DISABLE);
> +
> +	/* 1. Enable PCH Reset Handshake */
> +	val = I915_READ(HSW_NDE_RSTWRN_OPT);
> +	val |= RESET_PCH_HANDSHAKE_ENABLE;
> +	I915_WRITE(HSW_NDE_RSTWRN_OPT, val);
> +
> +	/* 2. Enable Comp */
> +	val = I915_READ(CHICKEN_MISC_2);
> +	val &= ~COMP_PWR_DOWN;
> +	I915_WRITE(CHICKEN_MISC_2, val);
> +
> +	val = I915_READ(CNL_PORT_COMP_DW3);
> +	procmon = &cnl_procmon_values[CNL_PROCMON_IDX(val)];
> +
> +	WARN_ON(procmon->dw10 == 0);
> +
> +	val = I915_READ(CNL_PORT_COMP_DW1);
> +	val &= ~((0xff << 16) | 0xff);
> +	val |= procmon->dw1;
> +	I915_WRITE(CNL_PORT_COMP_DW1, val);
> +
> +	I915_WRITE(CNL_PORT_COMP_DW9, procmon->dw9);
> +	I915_WRITE(CNL_PORT_COMP_DW10, procmon->dw10);
> +
> +	val = I915_READ(CNL_PORT_COMP_DW0);
> +	val |= COMP_INIT;
> +	I915_WRITE(CNL_PORT_COMP_DW0, val);
> +
> +	/* 3. */
> +	val = I915_READ(CNL_PORT_CL1CM_DW5);
> +	val |= CL_POWER_DOWN_ENABLE;
> +	I915_WRITE(CNL_PORT_CL1CM_DW5, val);
> +
> +	/* 4. Enable Power Well 1 (PG1) and Aux IO Power */
> +	mutex_lock(&power_domains->lock);
> +	well = lookup_power_well(dev_priv, SKL_DISP_PW_1);
> +	intel_power_well_enable(dev_priv, well);
> +	mutex_unlock(&power_domains->lock);
> +
> +	/* 5. Enable CD clock */
> +	cnl_init_cdclk(dev_priv);
> +
> +	/* 6. Enable DBUF */
> +	gen9_dbuf_enable(dev_priv);
> +}
> +
> +#undef CNL_PROCMON_IDX
> +#undef NUM_CNL_PROCMON
> +
> +static void cnl_display_core_uninit(struct drm_i915_private *dev_priv)
> +{
> +	struct i915_power_domains *power_domains = &dev_priv->power_domains;
> +	struct i915_power_well *well;
> +	u32 val;
> +
> +	gen9_set_dc_state(dev_priv, DC_STATE_DISABLE);
> +
> +	/* 1. Disable all display engine functions -> aready done */
> +
> +	/* 2. Disable DBUF */
> +	gen9_dbuf_disable(dev_priv);
> +
> +	/* 3. Disable CD clock */
> +	cnl_uninit_cdclk(dev_priv);
> +
> +	/* 4. Disable Power Well 1 (PG1) and Aux IO Power */
> +	mutex_lock(&power_domains->lock);
> +	well = lookup_power_well(dev_priv, SKL_DISP_PW_1);
> +	intel_power_well_disable(dev_priv, well);
> +	mutex_unlock(&power_domains->lock);
> +
> +	/* 5. Disable Comp */
> +	val = I915_READ(CHICKEN_MISC_2);
> +	val |= COMP_PWR_DOWN;
> +	I915_WRITE(CHICKEN_MISC_2, val);
> +}
> +
>  static void chv_phy_control_init(struct drm_i915_private *dev_priv)
>  {
>  	struct i915_power_well *cmn_bc =
> @@ -2830,7 +2935,9 @@ void intel_power_domains_init_hw(struct drm_i915_private *dev_priv, bool resume)
>  
>  	power_domains->initializing = true;
>  
> -	if (IS_GEN9_BC(dev_priv)) {
> +	if (IS_CANNONLAKE(dev_priv)) {
> +		cnl_display_core_init(dev_priv, resume);
> +	} else if (IS_GEN9_BC(dev_priv)) {
>  		skl_display_core_init(dev_priv, resume);
>  	} else if (IS_GEN9_LP(dev_priv)) {
>  		bxt_display_core_init(dev_priv, resume);
> @@ -2869,7 +2976,9 @@ void intel_power_domains_suspend(struct drm_i915_private *dev_priv)
>  	if (!i915.disable_power_well)
>  		intel_display_power_put(dev_priv, POWER_DOMAIN_INIT);
>  
> -	if (IS_GEN9_BC(dev_priv))
> +	if (IS_CANNONLAKE(dev_priv))
> +		cnl_display_core_uninit(dev_priv);
> +	else if (IS_GEN9_BC(dev_priv))
>  		skl_display_core_uninit(dev_priv);
>  	else if (IS_GEN9_LP(dev_priv))
>  		bxt_display_core_uninit(dev_priv);
> -- 
> 1.9.1
> 
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> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
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Re: [PATCH] drm/i915/cnl: Implement CNL display init/unit sequence

[Vivi, Rodrigo]

On Mon, 2017-06-05 at 18:07 +0300, Imre Deak wrote:
> On Thu, Apr 13, 2017 at 09:13:02AM -0700, Rodrigo Vivi wrote:
> > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > 
> > Implement the CNL display init/uninit sequence as outlined in Bspec.
> > 
> > Quite similar to SKL/BXT. The main complicaiton is probably the extra
> > procmon setup we must do based on the process/voltage information we
> > can read out from some register.
> > 
> > For now we assume DMC will handle the AUX wells, and we'll just enable
> > all of them during the init sequence. Even if DMC will handle them, we
> > should perhaps trim the set of enabled wells based on which DDI ports
> > are actually present.
> 
> The above needs to be aligned with the current version of the code.
> 
> Yes, looks like DMC saves/restores the state of both AUX and DDI power
> wells. The spec says to enable the AUX wells during init, but I think
> it's ok to do this on-demand. 

Indeed. I updated the code during some rebase but forgot to update the
commit message. I will remove this chuck on next rebase.

> 
> > 
> > v2: s/skl_dbuf/gen9_dbuf/ to follow upstream
> >     bxt needed a cdclk sanitize step, so let's add it for cnl too
> > v3: s/CHICKEN_MISC_1/CHICKEN_MISC_2/ (Ander)
> > v4: Rebased by Rodrigo after Ville's cdclk rework
> > v5: Removed unecessary Aux IO forced enable/disable, Fix DW10 setup
> >     Fix procpon Mask. (Credits-to Paulo and Clint)
> >     Remove A0 workaround.
> > v6: Rebased on top of recent code (Rodrigo).
> > v7: Respect the order of sanitize_ after set_
> >     (Done by Rodrigo, Requested by Ville)
> > v8: (Rodrigo) Remove CHICKEN_MISC_2 double definition.
> > 
> > Cc: Paulo Zanoni <paulo.r.zanoni@intel.com>
> > Cc: Clint Taylor <clinton.a.taylor@intel.com>
> > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
> > ---
> >  drivers/gpu/drm/i915/i915_reg.h         |  23 +++++++
> >  drivers/gpu/drm/i915/intel_cdclk.c      | 108 ++++++++++++++++++++++++++++++
> >  drivers/gpu/drm/i915/intel_drv.h        |   2 +
> >  drivers/gpu/drm/i915/intel_runtime_pm.c | 113 +++++++++++++++++++++++++++++++-
> >  4 files changed, 244 insertions(+), 2 deletions(-)
> > 
> > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> > index 8353892..9b2d8c0 100644
> > --- a/drivers/gpu/drm/i915/i915_reg.h
> > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > @@ -1655,6 +1655,9 @@ enum skl_disp_power_wells {
> >  #define   PHY_RESERVED			(1 << 7)
> >  #define BXT_PORT_CL1CM_DW0(phy)		_BXT_PHY((phy), _PORT_CL1CM_DW0_BC)
> >  
> > +#define CNL_PORT_CL1CM_DW5		_MMIO(0x162014)
> > +#define   CL_POWER_DOWN_ENABLE		(1 << 4)
> > +
> >  #define _PORT_CL1CM_DW9_A		0x162024
> >  #define _PORT_CL1CM_DW9_BC		0x6C024
> >  #define   IREF0RC_OFFSET_SHIFT		8
> > @@ -1687,6 +1690,25 @@ enum skl_disp_power_wells {
> >  #define BXT_PORT_CL2CM_DW6(phy)		_BXT_PHY((phy), _PORT_CL2CM_DW6_BC)
> >  #define   DW6_OLDO_DYN_PWR_DOWN_EN	(1 << 28)
> >  
> > +#define CNL_PORT_COMP_DW0		_MMIO(0x162100)
> > +#define   COMP_INIT			(1 << 31)
> > +#define CNL_PORT_COMP_DW1		_MMIO(0x162104)
> > +#define CNL_PORT_COMP_DW3		_MMIO(0x16210c)
> > +#define   PROCESS_INFO_DOT_0		(0 << 26)
> > +#define   PROCESS_INFO_DOT_1		(1 << 26)
> > +#define   PROCESS_INFO_DOT_4		(2 << 26)
> > +#define   PROCESS_INFO_MASK		(7 << 26)
> > +#define   PROCESS_INFO_SHIFT		26
> > +#define   VOLTAGE_INFO_0_85V		(0 << 24)
> > +#define   VOLTAGE_INFO_0_95V		(1 << 24)
> > +#define   VOLTAGE_INFO_1_05V		(2 << 24)
> > +#define   VOLTAGE_INFO_MASK		(3 << 24)
> > +#define   VOLTAGE_INFO_SHIFT		24
> > +#define CNL_PORT_COMP_DW8		_MMIO(0x162120)
> > +#define   PRDIC_ICOMP_DIS		(1 << 14)
> 
> DW8 looks to be unused.

I believe an early w/a for A0 was using that, but that got remove.

I will also remove this.

> 
> > +#define CNL_PORT_COMP_DW9		_MMIO(0x162124)
> > +#define CNL_PORT_COMP_DW10		_MMIO(0x162128)
> > +
> >  /* BXT PHY Ref registers */
> >  #define _PORT_REF_DW3_A			0x16218C
> >  #define _PORT_REF_DW3_BC		0x6C18C
> > @@ -6513,6 +6535,7 @@ enum {
> >  #define  KVM_CONFIG_CHANGE_NOTIFICATION_SELECT	(1 << 14)
> >  
> >  #define CHICKEN_MISC_2		_MMIO(0x42084)
> > +#define  COMP_PWR_DOWN		(1 << 23)
> >  #define  GLK_CL0_PWR_DOWN	(1 << 10)
> >  #define  GLK_CL1_PWR_DOWN	(1 << 11)
> >  #define  GLK_CL2_PWR_DOWN	(1 << 12)
> > diff --git a/drivers/gpu/drm/i915/intel_cdclk.c b/drivers/gpu/drm/i915/intel_cdclk.c
> > index bee4394..f9ba1e7 100644
> > --- a/drivers/gpu/drm/i915/intel_cdclk.c
> > +++ b/drivers/gpu/drm/i915/intel_cdclk.c
> > @@ -1555,6 +1555,114 @@ static void cnl_set_cdclk(struct drm_i915_private *dev_priv,
> >  	intel_update_cdclk(dev_priv);
> >  }
> >  
> > +static int cnl_cdclk_pll_vco(struct drm_i915_private *dev_priv, int cdclk)
> > +{
> > +	int ratio;
> > +
> > +	if (cdclk == dev_priv->cdclk.hw.ref)
> > +		return 0;
> > +
> > +	switch (cdclk) {
> > +	default:
> > +		MISSING_CASE(cdclk);
> > +	case 168000:
> > +	case 336000:
> > +		ratio = dev_priv->cdclk.hw.ref == 19200 ? 35 : 28;
> > +		break;
> > +	case 528000:
> > +		ratio = dev_priv->cdclk.hw.ref == 19200 ? 55 : 44;
> > +		break;
> > +	}
> > +
> > +	return dev_priv->cdclk.hw.ref * ratio;
> > +}
> > +
> > +static void cnl_sanitize_cdclk(struct drm_i915_private *dev_priv)
> > +{
> > +	u32 cdctl, expected;
> > +
> > +	intel_update_cdclk(dev_priv);
> > +
> > +	if (dev_priv->cdclk.hw.vco == 0 ||
> > +	    dev_priv->cdclk.hw.cdclk == dev_priv->cdclk.hw.ref)
> > +		goto sanitize;
> > +
> > +	/* DPLL okay; verify the cdclock
> > +	 *
> > +	 * Some BIOS versions leave an incorrect decimal frequency value and
> > +	 * set reserved MBZ bits in CDCLK_CTL at least during exiting from S4,
> > +	 * so sanitize this register.
> > +	 */
> > +	cdctl = I915_READ(CDCLK_CTL);
> > +	/*
> > +	 * Let's ignore the pipe field, since BIOS could have configured the
> > +	 * dividers both synching to an active pipe, or asynchronously
> > +	 * (PIPE_NONE).
> > +	 */
> > +	cdctl &= ~BXT_CDCLK_CD2X_PIPE_NONE;
> > +
> > +	expected = (cdctl & BXT_CDCLK_CD2X_DIV_SEL_MASK) |
> > +		   skl_cdclk_decimal(dev_priv->cdclk.hw.cdclk);
> > +
> > +	if (cdctl == expected)
> > +		/* All well; nothing to sanitize */
> > +		return;
> > +
> > +sanitize:
> > +	DRM_DEBUG_KMS("Sanitizing cdclk programmed by pre-os\n");
> > +
> > +	/* force cdclk programming */
> > +	dev_priv->cdclk.hw.cdclk = 0;
> > +
> > +	/* force full PLL disable + enable */
> > +	dev_priv->cdclk.hw.vco = -1;
> > +}
> > +
> > +/**
> > + * cnl_init_cdclk - Initialize CDCLK on CNL
> > + * @dev_priv: i915 device
> > + *
> > + * Initialize CDCLK for CNL. This is generally
> > + * done only during the display core initialization sequence,
> > + * after which the DMC will take care of turning CDCLK off/on
> > + * as needed.
> > + */
> > +
> 
> Extra w/s.

what do you mean here?

> 
> Looks ok:
> Reviewed-by: Imre Deak <imre.deak@intel.com>

thanks

> 
> > +void cnl_init_cdclk(struct drm_i915_private *dev_priv)
> > +{
> > +	struct intel_cdclk_state cdclk_state;
> > +
> > +	cnl_sanitize_cdclk(dev_priv);
> > +
> > +	if (dev_priv->cdclk.hw.cdclk != 0 &&
> > +	    dev_priv->cdclk.hw.vco != 0)
> > +		return;
> > +
> > +	cdclk_state = dev_priv->cdclk.hw;
> > +
> > +	cdclk_state.cdclk = 168000;
> > +	cdclk_state.vco = cnl_cdclk_pll_vco(dev_priv, cdclk_state.cdclk);
> > +
> > +	cnl_set_cdclk(dev_priv, &cdclk_state);
> > +}
> > +
> > +/**
> > + * cnl_uninit_cdclk - Uninitialize CDCLK on CNL
> > + * @dev_priv: i915 device
> > + *
> > + * Uninitialize CDCLK for CNL. This is done only
> > + * during the display core uninitialization sequence.
> > + */
> > +void cnl_uninit_cdclk(struct drm_i915_private *dev_priv)
> > +{
> > +	struct intel_cdclk_state cdclk_state = dev_priv->cdclk.hw;
> > +
> > +	cdclk_state.cdclk = cdclk_state.ref;
> > +	cdclk_state.vco = 0;
> > +
> > +	cnl_set_cdclk(dev_priv, &cdclk_state);
> > +}
> > +
> >  /**
> >   * intel_cdclk_state_compare - Determine if two CDCLK states differ
> >   * @a: first CDCLK state
> > diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
> > index 7bc0c25..a526e6e 100644
> > --- a/drivers/gpu/drm/i915/intel_drv.h
> > +++ b/drivers/gpu/drm/i915/intel_drv.h
> > @@ -1280,6 +1280,8 @@ void intel_audio_codec_enable(struct intel_encoder *encoder,
> >  /* intel_cdclk.c */
> >  void skl_init_cdclk(struct drm_i915_private *dev_priv);
> >  void skl_uninit_cdclk(struct drm_i915_private *dev_priv);
> > +void cnl_init_cdclk(struct drm_i915_private *dev_priv);
> > +void cnl_uninit_cdclk(struct drm_i915_private *dev_priv);
> >  void bxt_init_cdclk(struct drm_i915_private *dev_priv);
> >  void bxt_uninit_cdclk(struct drm_i915_private *dev_priv);
> >  void intel_init_cdclk_hooks(struct drm_i915_private *dev_priv);
> > diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c b/drivers/gpu/drm/i915/intel_runtime_pm.c
> > index 1797c91..5c3c6ec 100644
> > --- a/drivers/gpu/drm/i915/intel_runtime_pm.c
> > +++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
> > @@ -2698,6 +2698,111 @@ void bxt_display_core_uninit(struct drm_i915_private *dev_priv)
> >  	mutex_unlock(&power_domains->lock);
> >  }
> >  
> > +#define CNL_PROCMON_IDX(val) \
> > +	(((val) & (PROCESS_INFO_MASK | VOLTAGE_INFO_MASK)) >> VOLTAGE_INFO_SHIFT)
> > +#define NUM_CNL_PROCMON \
> > +	(CNL_PROCMON_IDX(VOLTAGE_INFO_MASK | PROCESS_INFO_MASK) + 1)
> > +
> > +static const struct cnl_procmon {
> > +	u32 dw1, dw9, dw10;
> > +} cnl_procmon_values[NUM_CNL_PROCMON] = {
> > +	[CNL_PROCMON_IDX(VOLTAGE_INFO_0_85V | PROCESS_INFO_DOT_0)] =
> > +		{ .dw1 = 0x00 << 16, .dw9 = 0x62AB67BB, .dw10 = 0x51914F96, },
> > +	[CNL_PROCMON_IDX(VOLTAGE_INFO_0_95V | PROCESS_INFO_DOT_0)] =
> > +		{ .dw1 = 0x00 << 16, .dw9 = 0x86E172C7, .dw10 = 0x77CA5EAB, },
> > +	[CNL_PROCMON_IDX(VOLTAGE_INFO_0_95V | PROCESS_INFO_DOT_1)] =
> > +		{ .dw1 = 0x00 << 16, .dw9 = 0x93F87FE1, .dw10 = 0x8AE871C5, },
> > +	[CNL_PROCMON_IDX(VOLTAGE_INFO_1_05V | PROCESS_INFO_DOT_0)] =
> > +		{ .dw1 = 0x00 << 16, .dw9 = 0x98FA82DD, .dw10 = 0x89E46DC1, },
> > +	[CNL_PROCMON_IDX(VOLTAGE_INFO_1_05V | PROCESS_INFO_DOT_1)] =
> > +		{ .dw1 = 0x44 << 16, .dw9 = 0x9A00AB25, .dw10 = 0x8AE38FF1, },
> > +};
> > +
> > +static void cnl_display_core_init(struct drm_i915_private *dev_priv, bool resume)
> > +{
> > +	struct i915_power_domains *power_domains = &dev_priv->power_domains;
> > +	const struct cnl_procmon *procmon;
> > +	struct i915_power_well *well;
> > +	u32 val;
> > +
> > +	gen9_set_dc_state(dev_priv, DC_STATE_DISABLE);
> > +
> > +	/* 1. Enable PCH Reset Handshake */
> > +	val = I915_READ(HSW_NDE_RSTWRN_OPT);
> > +	val |= RESET_PCH_HANDSHAKE_ENABLE;
> > +	I915_WRITE(HSW_NDE_RSTWRN_OPT, val);
> > +
> > +	/* 2. Enable Comp */
> > +	val = I915_READ(CHICKEN_MISC_2);
> > +	val &= ~COMP_PWR_DOWN;
> > +	I915_WRITE(CHICKEN_MISC_2, val);
> > +
> > +	val = I915_READ(CNL_PORT_COMP_DW3);
> > +	procmon = &cnl_procmon_values[CNL_PROCMON_IDX(val)];
> > +
> > +	WARN_ON(procmon->dw10 == 0);
> > +
> > +	val = I915_READ(CNL_PORT_COMP_DW1);
> > +	val &= ~((0xff << 16) | 0xff);
> > +	val |= procmon->dw1;
> > +	I915_WRITE(CNL_PORT_COMP_DW1, val);
> > +
> > +	I915_WRITE(CNL_PORT_COMP_DW9, procmon->dw9);
> > +	I915_WRITE(CNL_PORT_COMP_DW10, procmon->dw10);
> > +
> > +	val = I915_READ(CNL_PORT_COMP_DW0);
> > +	val |= COMP_INIT;
> > +	I915_WRITE(CNL_PORT_COMP_DW0, val);
> > +
> > +	/* 3. */
> > +	val = I915_READ(CNL_PORT_CL1CM_DW5);
> > +	val |= CL_POWER_DOWN_ENABLE;
> > +	I915_WRITE(CNL_PORT_CL1CM_DW5, val);
> > +
> > +	/* 4. Enable Power Well 1 (PG1) and Aux IO Power */
> > +	mutex_lock(&power_domains->lock);
> > +	well = lookup_power_well(dev_priv, SKL_DISP_PW_1);
> > +	intel_power_well_enable(dev_priv, well);
> > +	mutex_unlock(&power_domains->lock);
> > +
> > +	/* 5. Enable CD clock */
> > +	cnl_init_cdclk(dev_priv);
> > +
> > +	/* 6. Enable DBUF */
> > +	gen9_dbuf_enable(dev_priv);
> > +}
> > +
> > +#undef CNL_PROCMON_IDX
> > +#undef NUM_CNL_PROCMON
> > +
> > +static void cnl_display_core_uninit(struct drm_i915_private *dev_priv)
> > +{
> > +	struct i915_power_domains *power_domains = &dev_priv->power_domains;
> > +	struct i915_power_well *well;
> > +	u32 val;
> > +
> > +	gen9_set_dc_state(dev_priv, DC_STATE_DISABLE);
> > +
> > +	/* 1. Disable all display engine functions -> aready done */
> > +
> > +	/* 2. Disable DBUF */
> > +	gen9_dbuf_disable(dev_priv);
> > +
> > +	/* 3. Disable CD clock */
> > +	cnl_uninit_cdclk(dev_priv);
> > +
> > +	/* 4. Disable Power Well 1 (PG1) and Aux IO Power */
> > +	mutex_lock(&power_domains->lock);
> > +	well = lookup_power_well(dev_priv, SKL_DISP_PW_1);
> > +	intel_power_well_disable(dev_priv, well);
> > +	mutex_unlock(&power_domains->lock);
> > +
> > +	/* 5. Disable Comp */
> > +	val = I915_READ(CHICKEN_MISC_2);
> > +	val |= COMP_PWR_DOWN;
> > +	I915_WRITE(CHICKEN_MISC_2, val);
> > +}
> > +
> >  static void chv_phy_control_init(struct drm_i915_private *dev_priv)
> >  {
> >  	struct i915_power_well *cmn_bc =
> > @@ -2830,7 +2935,9 @@ void intel_power_domains_init_hw(struct drm_i915_private *dev_priv, bool resume)
> >  
> >  	power_domains->initializing = true;
> >  
> > -	if (IS_GEN9_BC(dev_priv)) {
> > +	if (IS_CANNONLAKE(dev_priv)) {
> > +		cnl_display_core_init(dev_priv, resume);
> > +	} else if (IS_GEN9_BC(dev_priv)) {
> >  		skl_display_core_init(dev_priv, resume);
> >  	} else if (IS_GEN9_LP(dev_priv)) {
> >  		bxt_display_core_init(dev_priv, resume);
> > @@ -2869,7 +2976,9 @@ void intel_power_domains_suspend(struct drm_i915_private *dev_priv)
> >  	if (!i915.disable_power_well)
> >  		intel_display_power_put(dev_priv, POWER_DOMAIN_INIT);
> >  
> > -	if (IS_GEN9_BC(dev_priv))
> > +	if (IS_CANNONLAKE(dev_priv))
> > +		cnl_display_core_uninit(dev_priv);
> > +	else if (IS_GEN9_BC(dev_priv))
> >  		skl_display_core_uninit(dev_priv);
> >  	else if (IS_GEN9_LP(dev_priv))
> >  		bxt_display_core_uninit(dev_priv);
> > -- 
> > 1.9.1
> > 
> > _______________________________________________
> > Intel-gfx mailing list
> > Intel-gfx@lists.freedesktop.org
> > https://lists.freedesktop.org/mailman/listinfo/intel-gfx

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Re: [PATCH] drm/i915/cnl: Implement CNL display init/unit sequence

[Imre Deak]

On Mon, Jun 05, 2017 at 07:38:45PM +0300, Vivi, Rodrigo wrote:
> On Mon, 2017-06-05 at 18:07 +0300, Imre Deak wrote:
> > On Thu, Apr 13, 2017 at 09:13:02AM -0700, Rodrigo Vivi wrote:
> > > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > > 
> > > Implement the CNL display init/uninit sequence as outlined in Bspec.
> > > 
> > > Quite similar to SKL/BXT. The main complicaiton is probably the extra
> > > procmon setup we must do based on the process/voltage information we
> > > can read out from some register.
> > > 
> > > For now we assume DMC will handle the AUX wells, and we'll just enable
> > > all of them during the init sequence. Even if DMC will handle them, we
> > > should perhaps trim the set of enabled wells based on which DDI ports
> > > are actually present.
> > 
> > The above needs to be aligned with the current version of the code.
> > 
> > Yes, looks like DMC saves/restores the state of both AUX and DDI power
> > wells. The spec says to enable the AUX wells during init, but I think
> > it's ok to do this on-demand. 
> 
> Indeed. I updated the code during some rebase but forgot to update the
> commit message. I will remove this chuck on next rebase.
> 
> > 
> > > 
> > > v2: s/skl_dbuf/gen9_dbuf/ to follow upstream
> > >     bxt needed a cdclk sanitize step, so let's add it for cnl too
> > > v3: s/CHICKEN_MISC_1/CHICKEN_MISC_2/ (Ander)
> > > v4: Rebased by Rodrigo after Ville's cdclk rework
> > > v5: Removed unecessary Aux IO forced enable/disable, Fix DW10 setup
> > >     Fix procpon Mask. (Credits-to Paulo and Clint)
> > >     Remove A0 workaround.
> > > v6: Rebased on top of recent code (Rodrigo).
> > > v7: Respect the order of sanitize_ after set_
> > >     (Done by Rodrigo, Requested by Ville)
> > > v8: (Rodrigo) Remove CHICKEN_MISC_2 double definition.
> > > 
> > > Cc: Paulo Zanoni <paulo.r.zanoni@intel.com>
> > > Cc: Clint Taylor <clinton.a.taylor@intel.com>
> > > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > > Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
> > > ---
> > >  drivers/gpu/drm/i915/i915_reg.h         |  23 +++++++
> > >  drivers/gpu/drm/i915/intel_cdclk.c      | 108 ++++++++++++++++++++++++++++++
> > >  drivers/gpu/drm/i915/intel_drv.h        |   2 +
> > >  drivers/gpu/drm/i915/intel_runtime_pm.c | 113 +++++++++++++++++++++++++++++++-
> > >  4 files changed, 244 insertions(+), 2 deletions(-)
> > > 
> > > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> > > index 8353892..9b2d8c0 100644
> > > --- a/drivers/gpu/drm/i915/i915_reg.h
> > > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > > @@ -1655,6 +1655,9 @@ enum skl_disp_power_wells {
> > >  #define   PHY_RESERVED			(1 << 7)
> > >  #define BXT_PORT_CL1CM_DW0(phy)		_BXT_PHY((phy), _PORT_CL1CM_DW0_BC)
> > >  
> > > +#define CNL_PORT_CL1CM_DW5		_MMIO(0x162014)
> > > +#define   CL_POWER_DOWN_ENABLE		(1 << 4)
> > > +
> > >  #define _PORT_CL1CM_DW9_A		0x162024
> > >  #define _PORT_CL1CM_DW9_BC		0x6C024
> > >  #define   IREF0RC_OFFSET_SHIFT		8
> > > @@ -1687,6 +1690,25 @@ enum skl_disp_power_wells {
> > >  #define BXT_PORT_CL2CM_DW6(phy)		_BXT_PHY((phy), _PORT_CL2CM_DW6_BC)
> > >  #define   DW6_OLDO_DYN_PWR_DOWN_EN	(1 << 28)
> > >  
> > > +#define CNL_PORT_COMP_DW0		_MMIO(0x162100)
> > > +#define   COMP_INIT			(1 << 31)
> > > +#define CNL_PORT_COMP_DW1		_MMIO(0x162104)
> > > +#define CNL_PORT_COMP_DW3		_MMIO(0x16210c)
> > > +#define   PROCESS_INFO_DOT_0		(0 << 26)
> > > +#define   PROCESS_INFO_DOT_1		(1 << 26)
> > > +#define   PROCESS_INFO_DOT_4		(2 << 26)
> > > +#define   PROCESS_INFO_MASK		(7 << 26)
> > > +#define   PROCESS_INFO_SHIFT		26
> > > +#define   VOLTAGE_INFO_0_85V		(0 << 24)
> > > +#define   VOLTAGE_INFO_0_95V		(1 << 24)
> > > +#define   VOLTAGE_INFO_1_05V		(2 << 24)
> > > +#define   VOLTAGE_INFO_MASK		(3 << 24)
> > > +#define   VOLTAGE_INFO_SHIFT		24
> > > +#define CNL_PORT_COMP_DW8		_MMIO(0x162120)
> > > +#define   PRDIC_ICOMP_DIS		(1 << 14)
> > 
> > DW8 looks to be unused.
> 
> I believe an early w/a for A0 was using that, but that got remove.
> 
> I will also remove this.
> 
> > 
> > > +#define CNL_PORT_COMP_DW9		_MMIO(0x162124)
> > > +#define CNL_PORT_COMP_DW10		_MMIO(0x162128)
> > > +
> > >  /* BXT PHY Ref registers */
> > >  #define _PORT_REF_DW3_A			0x16218C
> > >  #define _PORT_REF_DW3_BC		0x6C18C
> > > @@ -6513,6 +6535,7 @@ enum {
> > >  #define  KVM_CONFIG_CHANGE_NOTIFICATION_SELECT	(1 << 14)
> > >  
> > >  #define CHICKEN_MISC_2		_MMIO(0x42084)
> > > +#define  COMP_PWR_DOWN		(1 << 23)
> > >  #define  GLK_CL0_PWR_DOWN	(1 << 10)
> > >  #define  GLK_CL1_PWR_DOWN	(1 << 11)
> > >  #define  GLK_CL2_PWR_DOWN	(1 << 12)
> > > diff --git a/drivers/gpu/drm/i915/intel_cdclk.c b/drivers/gpu/drm/i915/intel_cdclk.c
> > > index bee4394..f9ba1e7 100644
> > > --- a/drivers/gpu/drm/i915/intel_cdclk.c
> > > +++ b/drivers/gpu/drm/i915/intel_cdclk.c
> > > @@ -1555,6 +1555,114 @@ static void cnl_set_cdclk(struct drm_i915_private *dev_priv,
> > >  	intel_update_cdclk(dev_priv);
> > >  }
> > >  
> > > +static int cnl_cdclk_pll_vco(struct drm_i915_private *dev_priv, int cdclk)
> > > +{
> > > +	int ratio;
> > > +
> > > +	if (cdclk == dev_priv->cdclk.hw.ref)
> > > +		return 0;
> > > +
> > > +	switch (cdclk) {
> > > +	default:
> > > +		MISSING_CASE(cdclk);
> > > +	case 168000:
> > > +	case 336000:
> > > +		ratio = dev_priv->cdclk.hw.ref == 19200 ? 35 : 28;
> > > +		break;
> > > +	case 528000:
> > > +		ratio = dev_priv->cdclk.hw.ref == 19200 ? 55 : 44;
> > > +		break;
> > > +	}
> > > +
> > > +	return dev_priv->cdclk.hw.ref * ratio;
> > > +}
> > > +
> > > +static void cnl_sanitize_cdclk(struct drm_i915_private *dev_priv)
> > > +{
> > > +	u32 cdctl, expected;
> > > +
> > > +	intel_update_cdclk(dev_priv);
> > > +
> > > +	if (dev_priv->cdclk.hw.vco == 0 ||
> > > +	    dev_priv->cdclk.hw.cdclk == dev_priv->cdclk.hw.ref)
> > > +		goto sanitize;
> > > +
> > > +	/* DPLL okay; verify the cdclock
> > > +	 *
> > > +	 * Some BIOS versions leave an incorrect decimal frequency value and
> > > +	 * set reserved MBZ bits in CDCLK_CTL at least during exiting from S4,
> > > +	 * so sanitize this register.
> > > +	 */
> > > +	cdctl = I915_READ(CDCLK_CTL);
> > > +	/*
> > > +	 * Let's ignore the pipe field, since BIOS could have configured the
> > > +	 * dividers both synching to an active pipe, or asynchronously
> > > +	 * (PIPE_NONE).
> > > +	 */
> > > +	cdctl &= ~BXT_CDCLK_CD2X_PIPE_NONE;
> > > +
> > > +	expected = (cdctl & BXT_CDCLK_CD2X_DIV_SEL_MASK) |
> > > +		   skl_cdclk_decimal(dev_priv->cdclk.hw.cdclk);
> > > +
> > > +	if (cdctl == expected)
> > > +		/* All well; nothing to sanitize */
> > > +		return;
> > > +
> > > +sanitize:
> > > +	DRM_DEBUG_KMS("Sanitizing cdclk programmed by pre-os\n");
> > > +
> > > +	/* force cdclk programming */
> > > +	dev_priv->cdclk.hw.cdclk = 0;
> > > +
> > > +	/* force full PLL disable + enable */
> > > +	dev_priv->cdclk.hw.vco = -1;
> > > +}
> > > +
> > > +/**
> > > + * cnl_init_cdclk - Initialize CDCLK on CNL
> > > + * @dev_priv: i915 device
> > > + *
> > > + * Initialize CDCLK for CNL. This is generally
> > > + * done only during the display core initialization sequence,
> > > + * after which the DMC will take care of turning CDCLK off/on
> > > + * as needed.
> > > + */
> > > +
> > 
> > Extra w/s.
> 
> what do you mean here?

The blank line between the docbook part and function definition.

> 
> > 
> > Looks ok:
> > Reviewed-by: Imre Deak <imre.deak@intel.com>
> 
> thanks
> 
> > 
> > > +void cnl_init_cdclk(struct drm_i915_private *dev_priv)
> > > +{
> > > +	struct intel_cdclk_state cdclk_state;
> > > +
> > > +	cnl_sanitize_cdclk(dev_priv);
> > > +
> > > +	if (dev_priv->cdclk.hw.cdclk != 0 &&
> > > +	    dev_priv->cdclk.hw.vco != 0)
> > > +		return;
> > > +
> > > +	cdclk_state = dev_priv->cdclk.hw;
> > > +
> > > +	cdclk_state.cdclk = 168000;
> > > +	cdclk_state.vco = cnl_cdclk_pll_vco(dev_priv, cdclk_state.cdclk);
> > > +
> > > +	cnl_set_cdclk(dev_priv, &cdclk_state);
> > > +}
> > > +
> > > +/**
> > > + * cnl_uninit_cdclk - Uninitialize CDCLK on CNL
> > > + * @dev_priv: i915 device
> > > + *
> > > + * Uninitialize CDCLK for CNL. This is done only
> > > + * during the display core uninitialization sequence.
> > > + */
> > > +void cnl_uninit_cdclk(struct drm_i915_private *dev_priv)
> > > +{
> > > +	struct intel_cdclk_state cdclk_state = dev_priv->cdclk.hw;
> > > +
> > > +	cdclk_state.cdclk = cdclk_state.ref;
> > > +	cdclk_state.vco = 0;
> > > +
> > > +	cnl_set_cdclk(dev_priv, &cdclk_state);
> > > +}
> > > +
> > >  /**
> > >   * intel_cdclk_state_compare - Determine if two CDCLK states differ
> > >   * @a: first CDCLK state
> > > diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
> > > index 7bc0c25..a526e6e 100644
> > > --- a/drivers/gpu/drm/i915/intel_drv.h
> > > +++ b/drivers/gpu/drm/i915/intel_drv.h
> > > @@ -1280,6 +1280,8 @@ void intel_audio_codec_enable(struct intel_encoder *encoder,
> > >  /* intel_cdclk.c */
> > >  void skl_init_cdclk(struct drm_i915_private *dev_priv);
> > >  void skl_uninit_cdclk(struct drm_i915_private *dev_priv);
> > > +void cnl_init_cdclk(struct drm_i915_private *dev_priv);
> > > +void cnl_uninit_cdclk(struct drm_i915_private *dev_priv);
> > >  void bxt_init_cdclk(struct drm_i915_private *dev_priv);
> > >  void bxt_uninit_cdclk(struct drm_i915_private *dev_priv);
> > >  void intel_init_cdclk_hooks(struct drm_i915_private *dev_priv);
> > > diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c b/drivers/gpu/drm/i915/intel_runtime_pm.c
> > > index 1797c91..5c3c6ec 100644
> > > --- a/drivers/gpu/drm/i915/intel_runtime_pm.c
> > > +++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
> > > @@ -2698,6 +2698,111 @@ void bxt_display_core_uninit(struct drm_i915_private *dev_priv)
> > >  	mutex_unlock(&power_domains->lock);
> > >  }
> > >  
> > > +#define CNL_PROCMON_IDX(val) \
> > > +	(((val) & (PROCESS_INFO_MASK | VOLTAGE_INFO_MASK)) >> VOLTAGE_INFO_SHIFT)
> > > +#define NUM_CNL_PROCMON \
> > > +	(CNL_PROCMON_IDX(VOLTAGE_INFO_MASK | PROCESS_INFO_MASK) + 1)
> > > +
> > > +static const struct cnl_procmon {
> > > +	u32 dw1, dw9, dw10;
> > > +} cnl_procmon_values[NUM_CNL_PROCMON] = {
> > > +	[CNL_PROCMON_IDX(VOLTAGE_INFO_0_85V | PROCESS_INFO_DOT_0)] =
> > > +		{ .dw1 = 0x00 << 16, .dw9 = 0x62AB67BB, .dw10 = 0x51914F96, },
> > > +	[CNL_PROCMON_IDX(VOLTAGE_INFO_0_95V | PROCESS_INFO_DOT_0)] =
> > > +		{ .dw1 = 0x00 << 16, .dw9 = 0x86E172C7, .dw10 = 0x77CA5EAB, },
> > > +	[CNL_PROCMON_IDX(VOLTAGE_INFO_0_95V | PROCESS_INFO_DOT_1)] =
> > > +		{ .dw1 = 0x00 << 16, .dw9 = 0x93F87FE1, .dw10 = 0x8AE871C5, },
> > > +	[CNL_PROCMON_IDX(VOLTAGE_INFO_1_05V | PROCESS_INFO_DOT_0)] =
> > > +		{ .dw1 = 0x00 << 16, .dw9 = 0x98FA82DD, .dw10 = 0x89E46DC1, },
> > > +	[CNL_PROCMON_IDX(VOLTAGE_INFO_1_05V | PROCESS_INFO_DOT_1)] =
> > > +		{ .dw1 = 0x44 << 16, .dw9 = 0x9A00AB25, .dw10 = 0x8AE38FF1, },
> > > +};
> > > +
> > > +static void cnl_display_core_init(struct drm_i915_private *dev_priv, bool resume)
> > > +{
> > > +	struct i915_power_domains *power_domains = &dev_priv->power_domains;
> > > +	const struct cnl_procmon *procmon;
> > > +	struct i915_power_well *well;
> > > +	u32 val;
> > > +
> > > +	gen9_set_dc_state(dev_priv, DC_STATE_DISABLE);
> > > +
> > > +	/* 1. Enable PCH Reset Handshake */
> > > +	val = I915_READ(HSW_NDE_RSTWRN_OPT);
> > > +	val |= RESET_PCH_HANDSHAKE_ENABLE;
> > > +	I915_WRITE(HSW_NDE_RSTWRN_OPT, val);
> > > +
> > > +	/* 2. Enable Comp */
> > > +	val = I915_READ(CHICKEN_MISC_2);
> > > +	val &= ~COMP_PWR_DOWN;
> > > +	I915_WRITE(CHICKEN_MISC_2, val);
> > > +
> > > +	val = I915_READ(CNL_PORT_COMP_DW3);
> > > +	procmon = &cnl_procmon_values[CNL_PROCMON_IDX(val)];
> > > +
> > > +	WARN_ON(procmon->dw10 == 0);
> > > +
> > > +	val = I915_READ(CNL_PORT_COMP_DW1);
> > > +	val &= ~((0xff << 16) | 0xff);
> > > +	val |= procmon->dw1;
> > > +	I915_WRITE(CNL_PORT_COMP_DW1, val);
> > > +
> > > +	I915_WRITE(CNL_PORT_COMP_DW9, procmon->dw9);
> > > +	I915_WRITE(CNL_PORT_COMP_DW10, procmon->dw10);
> > > +
> > > +	val = I915_READ(CNL_PORT_COMP_DW0);
> > > +	val |= COMP_INIT;
> > > +	I915_WRITE(CNL_PORT_COMP_DW0, val);
> > > +
> > > +	/* 3. */
> > > +	val = I915_READ(CNL_PORT_CL1CM_DW5);
> > > +	val |= CL_POWER_DOWN_ENABLE;
> > > +	I915_WRITE(CNL_PORT_CL1CM_DW5, val);
> > > +
> > > +	/* 4. Enable Power Well 1 (PG1) and Aux IO Power */
> > > +	mutex_lock(&power_domains->lock);
> > > +	well = lookup_power_well(dev_priv, SKL_DISP_PW_1);
> > > +	intel_power_well_enable(dev_priv, well);
> > > +	mutex_unlock(&power_domains->lock);
> > > +
> > > +	/* 5. Enable CD clock */
> > > +	cnl_init_cdclk(dev_priv);
> > > +
> > > +	/* 6. Enable DBUF */
> > > +	gen9_dbuf_enable(dev_priv);
> > > +}
> > > +
> > > +#undef CNL_PROCMON_IDX
> > > +#undef NUM_CNL_PROCMON
> > > +
> > > +static void cnl_display_core_uninit(struct drm_i915_private *dev_priv)
> > > +{
> > > +	struct i915_power_domains *power_domains = &dev_priv->power_domains;
> > > +	struct i915_power_well *well;
> > > +	u32 val;
> > > +
> > > +	gen9_set_dc_state(dev_priv, DC_STATE_DISABLE);
> > > +
> > > +	/* 1. Disable all display engine functions -> aready done */
> > > +
> > > +	/* 2. Disable DBUF */
> > > +	gen9_dbuf_disable(dev_priv);
> > > +
> > > +	/* 3. Disable CD clock */
> > > +	cnl_uninit_cdclk(dev_priv);
> > > +
> > > +	/* 4. Disable Power Well 1 (PG1) and Aux IO Power */
> > > +	mutex_lock(&power_domains->lock);
> > > +	well = lookup_power_well(dev_priv, SKL_DISP_PW_1);
> > > +	intel_power_well_disable(dev_priv, well);
> > > +	mutex_unlock(&power_domains->lock);
> > > +
> > > +	/* 5. Disable Comp */
> > > +	val = I915_READ(CHICKEN_MISC_2);
> > > +	val |= COMP_PWR_DOWN;
> > > +	I915_WRITE(CHICKEN_MISC_2, val);
> > > +}
> > > +
> > >  static void chv_phy_control_init(struct drm_i915_private *dev_priv)
> > >  {
> > >  	struct i915_power_well *cmn_bc =
> > > @@ -2830,7 +2935,9 @@ void intel_power_domains_init_hw(struct drm_i915_private *dev_priv, bool resume)
> > >  
> > >  	power_domains->initializing = true;
> > >  
> > > -	if (IS_GEN9_BC(dev_priv)) {
> > > +	if (IS_CANNONLAKE(dev_priv)) {
> > > +		cnl_display_core_init(dev_priv, resume);
> > > +	} else if (IS_GEN9_BC(dev_priv)) {
> > >  		skl_display_core_init(dev_priv, resume);
> > >  	} else if (IS_GEN9_LP(dev_priv)) {
> > >  		bxt_display_core_init(dev_priv, resume);
> > > @@ -2869,7 +2976,9 @@ void intel_power_domains_suspend(struct drm_i915_private *dev_priv)
> > >  	if (!i915.disable_power_well)
> > >  		intel_display_power_put(dev_priv, POWER_DOMAIN_INIT);
> > >  
> > > -	if (IS_GEN9_BC(dev_priv))
> > > +	if (IS_CANNONLAKE(dev_priv))
> > > +		cnl_display_core_uninit(dev_priv);
> > > +	else if (IS_GEN9_BC(dev_priv))
> > >  		skl_display_core_uninit(dev_priv);
> > >  	else if (IS_GEN9_LP(dev_priv))
> > >  		bxt_display_core_uninit(dev_priv);
> > > -- 
> > > 1.9.1
> > > 
> > > _______________________________________________
> > > Intel-gfx mailing list
> > > Intel-gfx@lists.freedesktop.org
> > > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
> 
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Intel-gfx@lists.freedesktop.org
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[PATCH 31/67] drm/i915/cnl: Allow dynamic cdclk changes on CNL

[Rodrigo Vivi]

All the low level cdclk bits are present, so let's add the required
hooks to reconfigure cdclk on the fly.

v2: Rebase due to cnl_sanitize_cdclk()
v3: Rebased by Rodrigo on top of Ville's cdclk rework.
v4: Rebase moving cnl_calc_cdclk up to follow same order
    as previous platforms.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
---
 drivers/gpu/drm/i915/intel_cdclk.c | 54 ++++++++++++++++++++++++++++++++++++--
 1 file changed, 52 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_cdclk.c b/drivers/gpu/drm/i915/intel_cdclk.c
index f9ba1e7..a8c254b 100644
--- a/drivers/gpu/drm/i915/intel_cdclk.c
+++ b/drivers/gpu/drm/i915/intel_cdclk.c
@@ -1400,6 +1400,16 @@ void bxt_uninit_cdclk(struct drm_i915_private *dev_priv)
 	bxt_set_cdclk(dev_priv, &cdclk_state);
 }
 
+static int cnl_calc_cdclk(int max_pixclk)
+{
+	if (max_pixclk > 336000)
+		return 528000;
+	else if (max_pixclk > 168000)
+		return 336000;
+	else
+		return 168000;
+}
+
 static void cnl_cdclk_pll_update(struct drm_i915_private *dev_priv,
 				 struct intel_cdclk_state *cdclk_state)
 {
@@ -1640,7 +1650,7 @@ void cnl_init_cdclk(struct drm_i915_private *dev_priv)
 
 	cdclk_state = dev_priv->cdclk.hw;
 
-	cdclk_state.cdclk = 168000;
+	cdclk_state.cdclk = cnl_calc_cdclk(0);
 	cdclk_state.vco = cnl_cdclk_pll_vco(dev_priv, cdclk_state.cdclk);
 
 	cnl_set_cdclk(dev_priv, &cdclk_state);
@@ -1928,6 +1938,40 @@ static int bxt_modeset_calc_cdclk(struct drm_atomic_state *state)
 	return 0;
 }
 
+static int cnl_modeset_calc_cdclk(struct drm_atomic_state *state)
+{
+	struct drm_i915_private *dev_priv = to_i915(state->dev);
+	struct intel_atomic_state *intel_state =
+		to_intel_atomic_state(state);
+	int max_pixclk = intel_max_pixel_rate(state);
+	int cdclk, vco;
+
+	cdclk = cnl_calc_cdclk(max_pixclk);
+	vco = cnl_cdclk_pll_vco(dev_priv, cdclk);
+
+	if (cdclk > dev_priv->max_cdclk_freq) {
+		DRM_DEBUG_KMS("requested cdclk (%d kHz) exceeds max (%d kHz)\n",
+			      cdclk, dev_priv->max_cdclk_freq);
+		return -EINVAL;
+	}
+
+	intel_state->cdclk.logical.vco = vco;
+	intel_state->cdclk.logical.cdclk = cdclk;
+
+	if (!intel_state->active_crtcs) {
+		cdclk = cnl_calc_cdclk(0);
+		vco = cnl_cdclk_pll_vco(dev_priv, cdclk);
+
+		intel_state->cdclk.actual.vco = vco;
+		intel_state->cdclk.actual.cdclk = cdclk;
+	} else {
+		intel_state->cdclk.actual =
+			intel_state->cdclk.logical;
+	}
+
+	return 0;
+}
+
 static int intel_compute_max_dotclk(struct drm_i915_private *dev_priv)
 {
 	int max_cdclk_freq = dev_priv->max_cdclk_freq;
@@ -1959,7 +2003,9 @@ static int intel_compute_max_dotclk(struct drm_i915_private *dev_priv)
  */
 void intel_update_max_cdclk(struct drm_i915_private *dev_priv)
 {
-	if (IS_GEN9_BC(dev_priv)) {
+	if (IS_CANNONLAKE(dev_priv)) {
+		dev_priv->max_cdclk_freq = 528000;
+	} else if (IS_GEN9_BC(dev_priv)) {
 		u32 limit = I915_READ(SKL_DFSM) & SKL_DFSM_CDCLK_LIMIT_MASK;
 		int max_cdclk, vco;
 
@@ -2158,6 +2204,10 @@ void intel_init_cdclk_hooks(struct drm_i915_private *dev_priv)
 		dev_priv->display.set_cdclk = skl_set_cdclk;
 		dev_priv->display.modeset_calc_cdclk =
 			skl_modeset_calc_cdclk;
+	} else if (IS_CANNONLAKE(dev_priv)) {
+		dev_priv->display.set_cdclk = cnl_set_cdclk;
+		dev_priv->display.modeset_calc_cdclk =
+			cnl_modeset_calc_cdclk;
 	}
 
 	if (IS_CANNONLAKE(dev_priv))
-- 
1.9.1

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Re: [PATCH 31/67] drm/i915/cnl: Allow dynamic cdclk changes on CNL

[Imre Deak]

On Thu, Apr 06, 2017 at 12:15:27PM -0700, Rodrigo Vivi wrote:
> All the low level cdclk bits are present, so let's add the required
> hooks to reconfigure cdclk on the fly.
> 
> v2: Rebase due to cnl_sanitize_cdclk()
> v3: Rebased by Rodrigo on top of Ville's cdclk rework.
> v4: Rebase moving cnl_calc_cdclk up to follow same order
>     as previous platforms.
> 
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
> ---
>  drivers/gpu/drm/i915/intel_cdclk.c | 54 ++++++++++++++++++++++++++++++++++++--
>  1 file changed, 52 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_cdclk.c b/drivers/gpu/drm/i915/intel_cdclk.c
> index f9ba1e7..a8c254b 100644
> --- a/drivers/gpu/drm/i915/intel_cdclk.c
> +++ b/drivers/gpu/drm/i915/intel_cdclk.c
> @@ -1400,6 +1400,16 @@ void bxt_uninit_cdclk(struct drm_i915_private *dev_priv)
>  	bxt_set_cdclk(dev_priv, &cdclk_state);
>  }
>  
> +static int cnl_calc_cdclk(int max_pixclk)
> +{
> +	if (max_pixclk > 336000)
> +		return 528000;
> +	else if (max_pixclk > 168000)
> +		return 336000;
> +	else
> +		return 168000;
> +}
> +
>  static void cnl_cdclk_pll_update(struct drm_i915_private *dev_priv,
>  				 struct intel_cdclk_state *cdclk_state)
>  {
> @@ -1640,7 +1650,7 @@ void cnl_init_cdclk(struct drm_i915_private *dev_priv)
>  
>  	cdclk_state = dev_priv->cdclk.hw;
>  
> -	cdclk_state.cdclk = 168000;
> +	cdclk_state.cdclk = cnl_calc_cdclk(0);
>  	cdclk_state.vco = cnl_cdclk_pll_vco(dev_priv, cdclk_state.cdclk);
>  
>  	cnl_set_cdclk(dev_priv, &cdclk_state);
> @@ -1928,6 +1938,40 @@ static int bxt_modeset_calc_cdclk(struct drm_atomic_state *state)
>  	return 0;
>  }
>  
> +static int cnl_modeset_calc_cdclk(struct drm_atomic_state *state)
> +{
> +	struct drm_i915_private *dev_priv = to_i915(state->dev);
> +	struct intel_atomic_state *intel_state =
> +		to_intel_atomic_state(state);
> +	int max_pixclk = intel_max_pixel_rate(state);
> +	int cdclk, vco;
> +
> +	cdclk = cnl_calc_cdclk(max_pixclk);
> +	vco = cnl_cdclk_pll_vco(dev_priv, cdclk);

The spec says not to set CDCLK to 168MHz if audio is used with 96MHz
BCLK, what's the plan to add that constraint? At least there could be a
TODO: here.

> +
> +	if (cdclk > dev_priv->max_cdclk_freq) {
> +		DRM_DEBUG_KMS("requested cdclk (%d kHz) exceeds max (%d kHz)\n",
> +			      cdclk, dev_priv->max_cdclk_freq);
> +		return -EINVAL;
> +	}
> +
> +	intel_state->cdclk.logical.vco = vco;
> +	intel_state->cdclk.logical.cdclk = cdclk;
> +
> +	if (!intel_state->active_crtcs) {
> +		cdclk = cnl_calc_cdclk(0);
> +		vco = cnl_cdclk_pll_vco(dev_priv, cdclk);
> +
> +		intel_state->cdclk.actual.vco = vco;
> +		intel_state->cdclk.actual.cdclk = cdclk;
> +	} else {
> +		intel_state->cdclk.actual =
> +			intel_state->cdclk.logical;
> +	}
> +
> +	return 0;
> +}
> +
>  static int intel_compute_max_dotclk(struct drm_i915_private *dev_priv)
>  {
>  	int max_cdclk_freq = dev_priv->max_cdclk_freq;
> @@ -1959,7 +2003,9 @@ static int intel_compute_max_dotclk(struct drm_i915_private *dev_priv)
>   */
>  void intel_update_max_cdclk(struct drm_i915_private *dev_priv)
>  {
> -	if (IS_GEN9_BC(dev_priv)) {
> +	if (IS_CANNONLAKE(dev_priv)) {
> +		dev_priv->max_cdclk_freq = 528000;
> +	} else if (IS_GEN9_BC(dev_priv)) {
>  		u32 limit = I915_READ(SKL_DFSM) & SKL_DFSM_CDCLK_LIMIT_MASK;
>  		int max_cdclk, vco;
>  
> @@ -2158,6 +2204,10 @@ void intel_init_cdclk_hooks(struct drm_i915_private *dev_priv)
>  		dev_priv->display.set_cdclk = skl_set_cdclk;
>  		dev_priv->display.modeset_calc_cdclk =
>  			skl_modeset_calc_cdclk;
> +	} else if (IS_CANNONLAKE(dev_priv)) {
> +		dev_priv->display.set_cdclk = cnl_set_cdclk;
> +		dev_priv->display.modeset_calc_cdclk =
> +			cnl_modeset_calc_cdclk;
>  	}
>  
>  	if (IS_CANNONLAKE(dev_priv))
> -- 
> 1.9.1
> 
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
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Re: [PATCH 31/67] drm/i915/cnl: Allow dynamic cdclk changes on CNL

[Vivi, Rodrigo]

On Mon, 2017-06-05 at 18:22 +0300, Imre Deak wrote:
> On Thu, Apr 06, 2017 at 12:15:27PM -0700, Rodrigo Vivi wrote:
> > All the low level cdclk bits are present, so let's add the required
> > hooks to reconfigure cdclk on the fly.
> > 
> > v2: Rebase due to cnl_sanitize_cdclk()
> > v3: Rebased by Rodrigo on top of Ville's cdclk rework.
> > v4: Rebase moving cnl_calc_cdclk up to follow same order
> >     as previous platforms.
> > 
> > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
> > ---
> >  drivers/gpu/drm/i915/intel_cdclk.c | 54 ++++++++++++++++++++++++++++++++++++--
> >  1 file changed, 52 insertions(+), 2 deletions(-)
> > 
> > diff --git a/drivers/gpu/drm/i915/intel_cdclk.c b/drivers/gpu/drm/i915/intel_cdclk.c
> > index f9ba1e7..a8c254b 100644
> > --- a/drivers/gpu/drm/i915/intel_cdclk.c
> > +++ b/drivers/gpu/drm/i915/intel_cdclk.c
> > @@ -1400,6 +1400,16 @@ void bxt_uninit_cdclk(struct drm_i915_private *dev_priv)
> >  	bxt_set_cdclk(dev_priv, &cdclk_state);
> >  }
> >  
> > +static int cnl_calc_cdclk(int max_pixclk)
> > +{
> > +	if (max_pixclk > 336000)
> > +		return 528000;
> > +	else if (max_pixclk > 168000)
> > +		return 336000;
> > +	else
> > +		return 168000;
> > +}
> > +
> >  static void cnl_cdclk_pll_update(struct drm_i915_private *dev_priv,
> >  				 struct intel_cdclk_state *cdclk_state)
> >  {
> > @@ -1640,7 +1650,7 @@ void cnl_init_cdclk(struct drm_i915_private *dev_priv)
> >  
> >  	cdclk_state = dev_priv->cdclk.hw;
> >  
> > -	cdclk_state.cdclk = 168000;
> > +	cdclk_state.cdclk = cnl_calc_cdclk(0);
> >  	cdclk_state.vco = cnl_cdclk_pll_vco(dev_priv, cdclk_state.cdclk);
> >  
> >  	cnl_set_cdclk(dev_priv, &cdclk_state);
> > @@ -1928,6 +1938,40 @@ static int bxt_modeset_calc_cdclk(struct drm_atomic_state *state)
> >  	return 0;
> >  }
> >  
> > +static int cnl_modeset_calc_cdclk(struct drm_atomic_state *state)
> > +{
> > +	struct drm_i915_private *dev_priv = to_i915(state->dev);
> > +	struct intel_atomic_state *intel_state =
> > +		to_intel_atomic_state(state);
> > +	int max_pixclk = intel_max_pixel_rate(state);
> > +	int cdclk, vco;
> > +
> > +	cdclk = cnl_calc_cdclk(max_pixclk);
> > +	vco = cnl_cdclk_pll_vco(dev_priv, cdclk);
> 
> The spec says not to set CDCLK to 168MHz if audio is used with 96MHz
> BCLK, what's the plan to add that constraint? At least there could be a
> TODO: here.

That's a good question.
Do we have ways to know the audio freq?
Or we need to add few extra hooks?
And agree, at least a TODO or FIXME here is needed while we dont have a
clear path.

> 
> > +
> > +	if (cdclk > dev_priv->max_cdclk_freq) {
> > +		DRM_DEBUG_KMS("requested cdclk (%d kHz) exceeds max (%d kHz)\n",
> > +			      cdclk, dev_priv->max_cdclk_freq);
> > +		return -EINVAL;
> > +	}
> > +
> > +	intel_state->cdclk.logical.vco = vco;
> > +	intel_state->cdclk.logical.cdclk = cdclk;
> > +
> > +	if (!intel_state->active_crtcs) {
> > +		cdclk = cnl_calc_cdclk(0);
> > +		vco = cnl_cdclk_pll_vco(dev_priv, cdclk);
> > +
> > +		intel_state->cdclk.actual.vco = vco;
> > +		intel_state->cdclk.actual.cdclk = cdclk;
> > +	} else {
> > +		intel_state->cdclk.actual =
> > +			intel_state->cdclk.logical;
> > +	}
> > +
> > +	return 0;
> > +}
> > +
> >  static int intel_compute_max_dotclk(struct drm_i915_private *dev_priv)
> >  {
> >  	int max_cdclk_freq = dev_priv->max_cdclk_freq;
> > @@ -1959,7 +2003,9 @@ static int intel_compute_max_dotclk(struct drm_i915_private *dev_priv)
> >   */
> >  void intel_update_max_cdclk(struct drm_i915_private *dev_priv)
> >  {
> > -	if (IS_GEN9_BC(dev_priv)) {
> > +	if (IS_CANNONLAKE(dev_priv)) {
> > +		dev_priv->max_cdclk_freq = 528000;
> > +	} else if (IS_GEN9_BC(dev_priv)) {
> >  		u32 limit = I915_READ(SKL_DFSM) & SKL_DFSM_CDCLK_LIMIT_MASK;
> >  		int max_cdclk, vco;
> >  
> > @@ -2158,6 +2204,10 @@ void intel_init_cdclk_hooks(struct drm_i915_private *dev_priv)
> >  		dev_priv->display.set_cdclk = skl_set_cdclk;
> >  		dev_priv->display.modeset_calc_cdclk =
> >  			skl_modeset_calc_cdclk;
> > +	} else if (IS_CANNONLAKE(dev_priv)) {
> > +		dev_priv->display.set_cdclk = cnl_set_cdclk;
> > +		dev_priv->display.modeset_calc_cdclk =
> > +			cnl_modeset_calc_cdclk;
> >  	}
> >  
> >  	if (IS_CANNONLAKE(dev_priv))
> > -- 
> > 1.9.1
> > 
> > _______________________________________________
> > Intel-gfx mailing list
> > Intel-gfx@lists.freedesktop.org
> > https://lists.freedesktop.org/mailman/listinfo/intel-gfx

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Re: [PATCH 31/67] drm/i915/cnl: Allow dynamic cdclk changes on CNL

[Ville Syrjälä]

On Mon, Jun 05, 2017 at 04:41:07PM +0000, Vivi, Rodrigo wrote:
> On Mon, 2017-06-05 at 18:22 +0300, Imre Deak wrote:
> > On Thu, Apr 06, 2017 at 12:15:27PM -0700, Rodrigo Vivi wrote:
> > > All the low level cdclk bits are present, so let's add the required
> > > hooks to reconfigure cdclk on the fly.
> > > 
> > > v2: Rebase due to cnl_sanitize_cdclk()
> > > v3: Rebased by Rodrigo on top of Ville's cdclk rework.
> > > v4: Rebase moving cnl_calc_cdclk up to follow same order
> > >     as previous platforms.
> > > 
> > > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > > Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
> > > ---
> > >  drivers/gpu/drm/i915/intel_cdclk.c | 54 ++++++++++++++++++++++++++++++++++++--
> > >  1 file changed, 52 insertions(+), 2 deletions(-)
> > > 
> > > diff --git a/drivers/gpu/drm/i915/intel_cdclk.c b/drivers/gpu/drm/i915/intel_cdclk.c
> > > index f9ba1e7..a8c254b 100644
> > > --- a/drivers/gpu/drm/i915/intel_cdclk.c
> > > +++ b/drivers/gpu/drm/i915/intel_cdclk.c
> > > @@ -1400,6 +1400,16 @@ void bxt_uninit_cdclk(struct drm_i915_private *dev_priv)
> > >  	bxt_set_cdclk(dev_priv, &cdclk_state);
> > >  }
> > >  
> > > +static int cnl_calc_cdclk(int max_pixclk)
> > > +{
> > > +	if (max_pixclk > 336000)
> > > +		return 528000;
> > > +	else if (max_pixclk > 168000)
> > > +		return 336000;
> > > +	else
> > > +		return 168000;
> > > +}
> > > +
> > >  static void cnl_cdclk_pll_update(struct drm_i915_private *dev_priv,
> > >  				 struct intel_cdclk_state *cdclk_state)
> > >  {
> > > @@ -1640,7 +1650,7 @@ void cnl_init_cdclk(struct drm_i915_private *dev_priv)
> > >  
> > >  	cdclk_state = dev_priv->cdclk.hw;
> > >  
> > > -	cdclk_state.cdclk = 168000;
> > > +	cdclk_state.cdclk = cnl_calc_cdclk(0);
> > >  	cdclk_state.vco = cnl_cdclk_pll_vco(dev_priv, cdclk_state.cdclk);
> > >  
> > >  	cnl_set_cdclk(dev_priv, &cdclk_state);
> > > @@ -1928,6 +1938,40 @@ static int bxt_modeset_calc_cdclk(struct drm_atomic_state *state)
> > >  	return 0;
> > >  }
> > >  
> > > +static int cnl_modeset_calc_cdclk(struct drm_atomic_state *state)
> > > +{
> > > +	struct drm_i915_private *dev_priv = to_i915(state->dev);
> > > +	struct intel_atomic_state *intel_state =
> > > +		to_intel_atomic_state(state);
> > > +	int max_pixclk = intel_max_pixel_rate(state);
> > > +	int cdclk, vco;
> > > +
> > > +	cdclk = cnl_calc_cdclk(max_pixclk);
> > > +	vco = cnl_cdclk_pll_vco(dev_priv, cdclk);
> > 
> > The spec says not to set CDCLK to 168MHz if audio is used with 96MHz
> > BCLK, what's the plan to add that constraint? At least there could be a
> > TODO: here.
> 
> That's a good question.
> Do we have ways to know the audio freq?
> Or we need to add few extra hooks?
> And agree, at least a TODO or FIXME here is needed while we dont have a
> clear path.

bdw_adjust_min_pipe_pixel_rate() just assumes 96MHz. There was some
discussion on the topic, and I found some register that possibly could
tell us something. But the best solution would probably involve querying
it from the audio driver.

> 
> > 
> > > +
> > > +	if (cdclk > dev_priv->max_cdclk_freq) {
> > > +		DRM_DEBUG_KMS("requested cdclk (%d kHz) exceeds max (%d kHz)\n",
> > > +			      cdclk, dev_priv->max_cdclk_freq);
> > > +		return -EINVAL;
> > > +	}
> > > +
> > > +	intel_state->cdclk.logical.vco = vco;
> > > +	intel_state->cdclk.logical.cdclk = cdclk;
> > > +
> > > +	if (!intel_state->active_crtcs) {
> > > +		cdclk = cnl_calc_cdclk(0);
> > > +		vco = cnl_cdclk_pll_vco(dev_priv, cdclk);
> > > +
> > > +		intel_state->cdclk.actual.vco = vco;
> > > +		intel_state->cdclk.actual.cdclk = cdclk;
> > > +	} else {
> > > +		intel_state->cdclk.actual =
> > > +			intel_state->cdclk.logical;
> > > +	}
> > > +
> > > +	return 0;
> > > +}
> > > +
> > >  static int intel_compute_max_dotclk(struct drm_i915_private *dev_priv)
> > >  {
> > >  	int max_cdclk_freq = dev_priv->max_cdclk_freq;
> > > @@ -1959,7 +2003,9 @@ static int intel_compute_max_dotclk(struct drm_i915_private *dev_priv)
> > >   */
> > >  void intel_update_max_cdclk(struct drm_i915_private *dev_priv)
> > >  {
> > > -	if (IS_GEN9_BC(dev_priv)) {
> > > +	if (IS_CANNONLAKE(dev_priv)) {
> > > +		dev_priv->max_cdclk_freq = 528000;
> > > +	} else if (IS_GEN9_BC(dev_priv)) {
> > >  		u32 limit = I915_READ(SKL_DFSM) & SKL_DFSM_CDCLK_LIMIT_MASK;
> > >  		int max_cdclk, vco;
> > >  
> > > @@ -2158,6 +2204,10 @@ void intel_init_cdclk_hooks(struct drm_i915_private *dev_priv)
> > >  		dev_priv->display.set_cdclk = skl_set_cdclk;
> > >  		dev_priv->display.modeset_calc_cdclk =
> > >  			skl_modeset_calc_cdclk;
> > > +	} else if (IS_CANNONLAKE(dev_priv)) {
> > > +		dev_priv->display.set_cdclk = cnl_set_cdclk;
> > > +		dev_priv->display.modeset_calc_cdclk =
> > > +			cnl_modeset_calc_cdclk;
> > >  	}
> > >  
> > >  	if (IS_CANNONLAKE(dev_priv))
> > > -- 
> > > 1.9.1
> > > 
> > > _______________________________________________
> > > Intel-gfx mailing list
> > > Intel-gfx@lists.freedesktop.org
> > > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
> 

-- 
Ville Syrjälä
Intel OTC
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Re: [PATCH 31/67] drm/i915/cnl: Allow dynamic cdclk changes on CNL

[Pandiyan, Dhinakaran]

On Mon, 2017-06-05 at 19:55 +0300, Ville Syrjälä wrote:
> On Mon, Jun 05, 2017 at 04:41:07PM +0000, Vivi, Rodrigo wrote:
> > On Mon, 2017-06-05 at 18:22 +0300, Imre Deak wrote:
> > > On Thu, Apr 06, 2017 at 12:15:27PM -0700, Rodrigo Vivi wrote:
> > > > All the low level cdclk bits are present, so let's add the required
> > > > hooks to reconfigure cdclk on the fly.
> > > > 
> > > > v2: Rebase due to cnl_sanitize_cdclk()
> > > > v3: Rebased by Rodrigo on top of Ville's cdclk rework.
> > > > v4: Rebase moving cnl_calc_cdclk up to follow same order
> > > >     as previous platforms.
> > > > 
> > > > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > > > Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
> > > > ---
> > > >  drivers/gpu/drm/i915/intel_cdclk.c | 54 ++++++++++++++++++++++++++++++++++++--
> > > >  1 file changed, 52 insertions(+), 2 deletions(-)
> > > > 
> > > > diff --git a/drivers/gpu/drm/i915/intel_cdclk.c b/drivers/gpu/drm/i915/intel_cdclk.c
> > > > index f9ba1e7..a8c254b 100644
> > > > --- a/drivers/gpu/drm/i915/intel_cdclk.c
> > > > +++ b/drivers/gpu/drm/i915/intel_cdclk.c
> > > > @@ -1400,6 +1400,16 @@ void bxt_uninit_cdclk(struct drm_i915_private *dev_priv)
> > > >  	bxt_set_cdclk(dev_priv, &cdclk_state);
> > > >  }
> > > >  
> > > > +static int cnl_calc_cdclk(int max_pixclk)
> > > > +{
> > > > +	if (max_pixclk > 336000)
> > > > +		return 528000;
> > > > +	else if (max_pixclk > 168000)
> > > > +		return 336000;
> > > > +	else
> > > > +		return 168000;
> > > > +}
> > > > +
> > > >  static void cnl_cdclk_pll_update(struct drm_i915_private *dev_priv,
> > > >  				 struct intel_cdclk_state *cdclk_state)
> > > >  {
> > > > @@ -1640,7 +1650,7 @@ void cnl_init_cdclk(struct drm_i915_private *dev_priv)
> > > >  
> > > >  	cdclk_state = dev_priv->cdclk.hw;
> > > >  
> > > > -	cdclk_state.cdclk = 168000;
> > > > +	cdclk_state.cdclk = cnl_calc_cdclk(0);
> > > >  	cdclk_state.vco = cnl_cdclk_pll_vco(dev_priv, cdclk_state.cdclk);
> > > >  
> > > >  	cnl_set_cdclk(dev_priv, &cdclk_state);
> > > > @@ -1928,6 +1938,40 @@ static int bxt_modeset_calc_cdclk(struct drm_atomic_state *state)
> > > >  	return 0;
> > > >  }
> > > >  
> > > > +static int cnl_modeset_calc_cdclk(struct drm_atomic_state *state)
> > > > +{
> > > > +	struct drm_i915_private *dev_priv = to_i915(state->dev);
> > > > +	struct intel_atomic_state *intel_state =
> > > > +		to_intel_atomic_state(state);
> > > > +	int max_pixclk = intel_max_pixel_rate(state);
> > > > +	int cdclk, vco;
> > > > +
> > > > +	cdclk = cnl_calc_cdclk(max_pixclk);
> > > > +	vco = cnl_cdclk_pll_vco(dev_priv, cdclk);
> > > 
> > > The spec says not to set CDCLK to 168MHz if audio is used with 96MHz
> > > BCLK, what's the plan to add that constraint? At least there could be a
> > > TODO: here.
> > 
> > That's a good question.
> > Do we have ways to know the audio freq?
> > Or we need to add few extra hooks?
> > And agree, at least a TODO or FIXME here is needed while we dont have a
> > clear path.
> 
> bdw_adjust_min_pipe_pixel_rate() just assumes 96MHz. There was some
> discussion on the topic, and I found some register that possibly could
> tell us something. But the best solution would probably involve querying
> it from the audio driver.
> 

The last time I checked with the audio folks, the driver does not change
the BCLK freq. and the default is 96 MHz. 


> > 
> > > 
> > > > +
> > > > +	if (cdclk > dev_priv->max_cdclk_freq) {
> > > > +		DRM_DEBUG_KMS("requested cdclk (%d kHz) exceeds max (%d kHz)\n",
> > > > +			      cdclk, dev_priv->max_cdclk_freq);
> > > > +		return -EINVAL;
> > > > +	}
> > > > +
> > > > +	intel_state->cdclk.logical.vco = vco;
> > > > +	intel_state->cdclk.logical.cdclk = cdclk;
> > > > +
> > > > +	if (!intel_state->active_crtcs) {
> > > > +		cdclk = cnl_calc_cdclk(0);
> > > > +		vco = cnl_cdclk_pll_vco(dev_priv, cdclk);
> > > > +
> > > > +		intel_state->cdclk.actual.vco = vco;
> > > > +		intel_state->cdclk.actual.cdclk = cdclk;
> > > > +	} else {
> > > > +		intel_state->cdclk.actual =
> > > > +			intel_state->cdclk.logical;
> > > > +	}
> > > > +
> > > > +	return 0;
> > > > +}
> > > > +
> > > >  static int intel_compute_max_dotclk(struct drm_i915_private *dev_priv)
> > > >  {
> > > >  	int max_cdclk_freq = dev_priv->max_cdclk_freq;
> > > > @@ -1959,7 +2003,9 @@ static int intel_compute_max_dotclk(struct drm_i915_private *dev_priv)
> > > >   */
> > > >  void intel_update_max_cdclk(struct drm_i915_private *dev_priv)
> > > >  {
> > > > -	if (IS_GEN9_BC(dev_priv)) {
> > > > +	if (IS_CANNONLAKE(dev_priv)) {
> > > > +		dev_priv->max_cdclk_freq = 528000;
> > > > +	} else if (IS_GEN9_BC(dev_priv)) {
> > > >  		u32 limit = I915_READ(SKL_DFSM) & SKL_DFSM_CDCLK_LIMIT_MASK;
> > > >  		int max_cdclk, vco;
> > > >  
> > > > @@ -2158,6 +2204,10 @@ void intel_init_cdclk_hooks(struct drm_i915_private *dev_priv)
> > > >  		dev_priv->display.set_cdclk = skl_set_cdclk;
> > > >  		dev_priv->display.modeset_calc_cdclk =
> > > >  			skl_modeset_calc_cdclk;
> > > > +	} else if (IS_CANNONLAKE(dev_priv)) {
> > > > +		dev_priv->display.set_cdclk = cnl_set_cdclk;
> > > > +		dev_priv->display.modeset_calc_cdclk =
> > > > +			cnl_modeset_calc_cdclk;
> > > >  	}
> > > >  
> > > >  	if (IS_CANNONLAKE(dev_priv))
> > > > -- 
> > > > 1.9.1
> > > > 
> > > > _______________________________________________
> > > > Intel-gfx mailing list
> > > > Intel-gfx@lists.freedesktop.org
> > > > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
> > 
> 

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Re: [PATCH 31/67] drm/i915/cnl: Allow dynamic cdclk changes on CNL

[Rodrigo Vivi]

On Mon, Jun 5, 2017 at 10:04 AM, Pandiyan, Dhinakaran
<dhinakaran.pandiyan@intel.com> wrote:
> On Mon, 2017-06-05 at 19:55 +0300, Ville Syrjälä wrote:
>> On Mon, Jun 05, 2017 at 04:41:07PM +0000, Vivi, Rodrigo wrote:
>> > On Mon, 2017-06-05 at 18:22 +0300, Imre Deak wrote:
>> > > On Thu, Apr 06, 2017 at 12:15:27PM -0700, Rodrigo Vivi wrote:
>> > > > All the low level cdclk bits are present, so let's add the required
>> > > > hooks to reconfigure cdclk on the fly.
>> > > >
>> > > > v2: Rebase due to cnl_sanitize_cdclk()
>> > > > v3: Rebased by Rodrigo on top of Ville's cdclk rework.
>> > > > v4: Rebase moving cnl_calc_cdclk up to follow same order
>> > > >     as previous platforms.
>> > > >
>> > > > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
>> > > > Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
>> > > > ---
>> > > >  drivers/gpu/drm/i915/intel_cdclk.c | 54 ++++++++++++++++++++++++++++++++++++--
>> > > >  1 file changed, 52 insertions(+), 2 deletions(-)
>> > > >
>> > > > diff --git a/drivers/gpu/drm/i915/intel_cdclk.c b/drivers/gpu/drm/i915/intel_cdclk.c
>> > > > index f9ba1e7..a8c254b 100644
>> > > > --- a/drivers/gpu/drm/i915/intel_cdclk.c
>> > > > +++ b/drivers/gpu/drm/i915/intel_cdclk.c
>> > > > @@ -1400,6 +1400,16 @@ void bxt_uninit_cdclk(struct drm_i915_private *dev_priv)
>> > > >         bxt_set_cdclk(dev_priv, &cdclk_state);
>> > > >  }
>> > > >
>> > > > +static int cnl_calc_cdclk(int max_pixclk)
>> > > > +{
>> > > > +       if (max_pixclk > 336000)
>> > > > +               return 528000;
>> > > > +       else if (max_pixclk > 168000)
>> > > > +               return 336000;
>> > > > +       else
>> > > > +               return 168000;
>> > > > +}
>> > > > +
>> > > >  static void cnl_cdclk_pll_update(struct drm_i915_private *dev_priv,
>> > > >                                  struct intel_cdclk_state *cdclk_state)
>> > > >  {
>> > > > @@ -1640,7 +1650,7 @@ void cnl_init_cdclk(struct drm_i915_private *dev_priv)
>> > > >
>> > > >         cdclk_state = dev_priv->cdclk.hw;
>> > > >
>> > > > -       cdclk_state.cdclk = 168000;
>> > > > +       cdclk_state.cdclk = cnl_calc_cdclk(0);
>> > > >         cdclk_state.vco = cnl_cdclk_pll_vco(dev_priv, cdclk_state.cdclk);
>> > > >
>> > > >         cnl_set_cdclk(dev_priv, &cdclk_state);
>> > > > @@ -1928,6 +1938,40 @@ static int bxt_modeset_calc_cdclk(struct drm_atomic_state *state)
>> > > >         return 0;
>> > > >  }
>> > > >
>> > > > +static int cnl_modeset_calc_cdclk(struct drm_atomic_state *state)
>> > > > +{
>> > > > +       struct drm_i915_private *dev_priv = to_i915(state->dev);
>> > > > +       struct intel_atomic_state *intel_state =
>> > > > +               to_intel_atomic_state(state);
>> > > > +       int max_pixclk = intel_max_pixel_rate(state);
>> > > > +       int cdclk, vco;
>> > > > +
>> > > > +       cdclk = cnl_calc_cdclk(max_pixclk);
>> > > > +       vco = cnl_cdclk_pll_vco(dev_priv, cdclk);
>> > >
>> > > The spec says not to set CDCLK to 168MHz if audio is used with 96MHz
>> > > BCLK, what's the plan to add that constraint? At least there could be a
>> > > TODO: here.
>> >
>> > That's a good question.
>> > Do we have ways to know the audio freq?
>> > Or we need to add few extra hooks?
>> > And agree, at least a TODO or FIXME here is needed while we dont have a
>> > clear path.
>>
>> bdw_adjust_min_pipe_pixel_rate() just assumes 96MHz. There was some
>> discussion on the topic, and I found some register that possibly could
>> tell us something. But the best solution would probably involve querying
>> it from the audio driver.
>>
>
> The last time I checked with the audio folks, the driver does not change
> the BCLK freq. and the default is 96 MHz.

So, what should we do for now? Block 168? Remove 168?

>
>
>> >
>> > >
>> > > > +
>> > > > +       if (cdclk > dev_priv->max_cdclk_freq) {
>> > > > +               DRM_DEBUG_KMS("requested cdclk (%d kHz) exceeds max (%d kHz)\n",
>> > > > +                             cdclk, dev_priv->max_cdclk_freq);
>> > > > +               return -EINVAL;
>> > > > +       }
>> > > > +
>> > > > +       intel_state->cdclk.logical.vco = vco;
>> > > > +       intel_state->cdclk.logical.cdclk = cdclk;
>> > > > +
>> > > > +       if (!intel_state->active_crtcs) {
>> > > > +               cdclk = cnl_calc_cdclk(0);
>> > > > +               vco = cnl_cdclk_pll_vco(dev_priv, cdclk);
>> > > > +
>> > > > +               intel_state->cdclk.actual.vco = vco;
>> > > > +               intel_state->cdclk.actual.cdclk = cdclk;
>> > > > +       } else {
>> > > > +               intel_state->cdclk.actual =
>> > > > +                       intel_state->cdclk.logical;
>> > > > +       }
>> > > > +
>> > > > +       return 0;
>> > > > +}
>> > > > +
>> > > >  static int intel_compute_max_dotclk(struct drm_i915_private *dev_priv)
>> > > >  {
>> > > >         int max_cdclk_freq = dev_priv->max_cdclk_freq;
>> > > > @@ -1959,7 +2003,9 @@ static int intel_compute_max_dotclk(struct drm_i915_private *dev_priv)
>> > > >   */
>> > > >  void intel_update_max_cdclk(struct drm_i915_private *dev_priv)
>> > > >  {
>> > > > -       if (IS_GEN9_BC(dev_priv)) {
>> > > > +       if (IS_CANNONLAKE(dev_priv)) {
>> > > > +               dev_priv->max_cdclk_freq = 528000;
>> > > > +       } else if (IS_GEN9_BC(dev_priv)) {
>> > > >                 u32 limit = I915_READ(SKL_DFSM) & SKL_DFSM_CDCLK_LIMIT_MASK;
>> > > >                 int max_cdclk, vco;
>> > > >
>> > > > @@ -2158,6 +2204,10 @@ void intel_init_cdclk_hooks(struct drm_i915_private *dev_priv)
>> > > >                 dev_priv->display.set_cdclk = skl_set_cdclk;
>> > > >                 dev_priv->display.modeset_calc_cdclk =
>> > > >                         skl_modeset_calc_cdclk;
>> > > > +       } else if (IS_CANNONLAKE(dev_priv)) {
>> > > > +               dev_priv->display.set_cdclk = cnl_set_cdclk;
>> > > > +               dev_priv->display.modeset_calc_cdclk =
>> > > > +                       cnl_modeset_calc_cdclk;
>> > > >         }
>> > > >
>> > > >         if (IS_CANNONLAKE(dev_priv))
>> > > > --
>> > > > 1.9.1
>> > > >
>> > > > _______________________________________________
>> > > > Intel-gfx mailing list
>> > > > Intel-gfx@lists.freedesktop.org
>> > > > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
>> >
>>
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx



-- 
Rodrigo Vivi
Blog: http://blog.vivi.eng.br
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Re: [PATCH 31/67] drm/i915/cnl: Allow dynamic cdclk changes on CNL

[Pandiyan, Dhinakaran]

On Tue, 2017-06-06 at 08:24 -0700, Rodrigo Vivi wrote:
> On Mon, Jun 5, 2017 at 10:04 AM, Pandiyan, Dhinakaran
> <dhinakaran.pandiyan@intel.com> wrote:
> > On Mon, 2017-06-05 at 19:55 +0300, Ville Syrjälä wrote:
> >> On Mon, Jun 05, 2017 at 04:41:07PM +0000, Vivi, Rodrigo wrote:
> >> > On Mon, 2017-06-05 at 18:22 +0300, Imre Deak wrote:
> >> > > On Thu, Apr 06, 2017 at 12:15:27PM -0700, Rodrigo Vivi wrote:
> >> > > > All the low level cdclk bits are present, so let's add the required
> >> > > > hooks to reconfigure cdclk on the fly.
> >> > > >
> >> > > > v2: Rebase due to cnl_sanitize_cdclk()
> >> > > > v3: Rebased by Rodrigo on top of Ville's cdclk rework.
> >> > > > v4: Rebase moving cnl_calc_cdclk up to follow same order
> >> > > >     as previous platforms.
> >> > > >
> >> > > > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> >> > > > Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
> >> > > > ---
> >> > > >  drivers/gpu/drm/i915/intel_cdclk.c | 54 ++++++++++++++++++++++++++++++++++++--
> >> > > >  1 file changed, 52 insertions(+), 2 deletions(-)
> >> > > >
> >> > > > diff --git a/drivers/gpu/drm/i915/intel_cdclk.c b/drivers/gpu/drm/i915/intel_cdclk.c
> >> > > > index f9ba1e7..a8c254b 100644
> >> > > > --- a/drivers/gpu/drm/i915/intel_cdclk.c
> >> > > > +++ b/drivers/gpu/drm/i915/intel_cdclk.c
> >> > > > @@ -1400,6 +1400,16 @@ void bxt_uninit_cdclk(struct drm_i915_private *dev_priv)
> >> > > >         bxt_set_cdclk(dev_priv, &cdclk_state);
> >> > > >  }
> >> > > >
> >> > > > +static int cnl_calc_cdclk(int max_pixclk)
> >> > > > +{
> >> > > > +       if (max_pixclk > 336000)
> >> > > > +               return 528000;
> >> > > > +       else if (max_pixclk > 168000)
> >> > > > +               return 336000;
> >> > > > +       else
> >> > > > +               return 168000;
> >> > > > +}
> >> > > > +
> >> > > >  static void cnl_cdclk_pll_update(struct drm_i915_private *dev_priv,
> >> > > >                                  struct intel_cdclk_state *cdclk_state)
> >> > > >  {
> >> > > > @@ -1640,7 +1650,7 @@ void cnl_init_cdclk(struct drm_i915_private *dev_priv)
> >> > > >
> >> > > >         cdclk_state = dev_priv->cdclk.hw;
> >> > > >
> >> > > > -       cdclk_state.cdclk = 168000;
> >> > > > +       cdclk_state.cdclk = cnl_calc_cdclk(0);
> >> > > >         cdclk_state.vco = cnl_cdclk_pll_vco(dev_priv, cdclk_state.cdclk);
> >> > > >
> >> > > >         cnl_set_cdclk(dev_priv, &cdclk_state);
> >> > > > @@ -1928,6 +1938,40 @@ static int bxt_modeset_calc_cdclk(struct drm_atomic_state *state)
> >> > > >         return 0;
> >> > > >  }
> >> > > >
> >> > > > +static int cnl_modeset_calc_cdclk(struct drm_atomic_state *state)
> >> > > > +{
> >> > > > +       struct drm_i915_private *dev_priv = to_i915(state->dev);
> >> > > > +       struct intel_atomic_state *intel_state =
> >> > > > +               to_intel_atomic_state(state);
> >> > > > +       int max_pixclk = intel_max_pixel_rate(state);
> >> > > > +       int cdclk, vco;
> >> > > > +
> >> > > > +       cdclk = cnl_calc_cdclk(max_pixclk);
> >> > > > +       vco = cnl_cdclk_pll_vco(dev_priv, cdclk);
> >> > >
> >> > > The spec says not to set CDCLK to 168MHz if audio is used with 96MHz
> >> > > BCLK, what's the plan to add that constraint? At least there could be a
> >> > > TODO: here.
> >> >
> >> > That's a good question.
> >> > Do we have ways to know the audio freq?
> >> > Or we need to add few extra hooks?
> >> > And agree, at least a TODO or FIXME here is needed while we dont have a
> >> > clear path.
> >>
> >> bdw_adjust_min_pipe_pixel_rate() just assumes 96MHz. There was some
> >> discussion on the topic, and I found some register that possibly could
> >> tell us something. But the best solution would probably involve querying
> >> it from the audio driver.
> >>
> >
> > The last time I checked with the audio folks, the driver does not change
> > the BCLK freq. and the default is 96 MHz.
> 
> So, what should we do for now? Block 168? Remove 168?

As Ville wrote, bdw_adjust_min_pipe_pixel_rate() already does that. You
just have to modify intel_max_pixel_rate() to include CNL too.

-DK

> 
> >
> >
> >> >
> >> > >
> >> > > > +
> >> > > > +       if (cdclk > dev_priv->max_cdclk_freq) {
> >> > > > +               DRM_DEBUG_KMS("requested cdclk (%d kHz) exceeds max (%d kHz)\n",
> >> > > > +                             cdclk, dev_priv->max_cdclk_freq);
> >> > > > +               return -EINVAL;
> >> > > > +       }
> >> > > > +
> >> > > > +       intel_state->cdclk.logical.vco = vco;
> >> > > > +       intel_state->cdclk.logical.cdclk = cdclk;
> >> > > > +
> >> > > > +       if (!intel_state->active_crtcs) {
> >> > > > +               cdclk = cnl_calc_cdclk(0);
> >> > > > +               vco = cnl_cdclk_pll_vco(dev_priv, cdclk);
> >> > > > +
> >> > > > +               intel_state->cdclk.actual.vco = vco;
> >> > > > +               intel_state->cdclk.actual.cdclk = cdclk;
> >> > > > +       } else {
> >> > > > +               intel_state->cdclk.actual =
> >> > > > +                       intel_state->cdclk.logical;
> >> > > > +       }
> >> > > > +
> >> > > > +       return 0;
> >> > > > +}
> >> > > > +
> >> > > >  static int intel_compute_max_dotclk(struct drm_i915_private *dev_priv)
> >> > > >  {
> >> > > >         int max_cdclk_freq = dev_priv->max_cdclk_freq;
> >> > > > @@ -1959,7 +2003,9 @@ static int intel_compute_max_dotclk(struct drm_i915_private *dev_priv)
> >> > > >   */
> >> > > >  void intel_update_max_cdclk(struct drm_i915_private *dev_priv)
> >> > > >  {
> >> > > > -       if (IS_GEN9_BC(dev_priv)) {
> >> > > > +       if (IS_CANNONLAKE(dev_priv)) {
> >> > > > +               dev_priv->max_cdclk_freq = 528000;
> >> > > > +       } else if (IS_GEN9_BC(dev_priv)) {
> >> > > >                 u32 limit = I915_READ(SKL_DFSM) & SKL_DFSM_CDCLK_LIMIT_MASK;
> >> > > >                 int max_cdclk, vco;
> >> > > >
> >> > > > @@ -2158,6 +2204,10 @@ void intel_init_cdclk_hooks(struct drm_i915_private *dev_priv)
> >> > > >                 dev_priv->display.set_cdclk = skl_set_cdclk;
> >> > > >                 dev_priv->display.modeset_calc_cdclk =
> >> > > >                         skl_modeset_calc_cdclk;
> >> > > > +       } else if (IS_CANNONLAKE(dev_priv)) {
> >> > > > +               dev_priv->display.set_cdclk = cnl_set_cdclk;
> >> > > > +               dev_priv->display.modeset_calc_cdclk =
> >> > > > +                       cnl_modeset_calc_cdclk;
> >> > > >         }
> >> > > >
> >> > > >         if (IS_CANNONLAKE(dev_priv))
> >> > > > --
> >> > > > 1.9.1
> >> > > >
> >> > > > _______________________________________________
> >> > > > Intel-gfx mailing list
> >> > > > Intel-gfx@lists.freedesktop.org
> >> > > > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
> >> >
> >>
> >
> > _______________________________________________
> > Intel-gfx mailing list
> > Intel-gfx@lists.freedesktop.org
> > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
> 
> 
> 

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Re: [PATCH 31/67] drm/i915/cnl: Allow dynamic cdclk changes on CNL

[Rodrigo Vivi]

On Tue, Jun 6, 2017 at 10:39 AM, Pandiyan, Dhinakaran
<dhinakaran.pandiyan@intel.com> wrote:
> On Tue, 2017-06-06 at 08:24 -0700, Rodrigo Vivi wrote:
>> On Mon, Jun 5, 2017 at 10:04 AM, Pandiyan, Dhinakaran
>> <dhinakaran.pandiyan@intel.com> wrote:
>> > On Mon, 2017-06-05 at 19:55 +0300, Ville Syrjälä wrote:
>> >> On Mon, Jun 05, 2017 at 04:41:07PM +0000, Vivi, Rodrigo wrote:
>> >> > On Mon, 2017-06-05 at 18:22 +0300, Imre Deak wrote:
>> >> > > On Thu, Apr 06, 2017 at 12:15:27PM -0700, Rodrigo Vivi wrote:
>> >> > > > All the low level cdclk bits are present, so let's add the required
>> >> > > > hooks to reconfigure cdclk on the fly.
>> >> > > >
>> >> > > > v2: Rebase due to cnl_sanitize_cdclk()
>> >> > > > v3: Rebased by Rodrigo on top of Ville's cdclk rework.
>> >> > > > v4: Rebase moving cnl_calc_cdclk up to follow same order
>> >> > > >     as previous platforms.
>> >> > > >
>> >> > > > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
>> >> > > > Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
>> >> > > > ---
>> >> > > >  drivers/gpu/drm/i915/intel_cdclk.c | 54 ++++++++++++++++++++++++++++++++++++--
>> >> > > >  1 file changed, 52 insertions(+), 2 deletions(-)
>> >> > > >
>> >> > > > diff --git a/drivers/gpu/drm/i915/intel_cdclk.c b/drivers/gpu/drm/i915/intel_cdclk.c
>> >> > > > index f9ba1e7..a8c254b 100644
>> >> > > > --- a/drivers/gpu/drm/i915/intel_cdclk.c
>> >> > > > +++ b/drivers/gpu/drm/i915/intel_cdclk.c
>> >> > > > @@ -1400,6 +1400,16 @@ void bxt_uninit_cdclk(struct drm_i915_private *dev_priv)
>> >> > > >         bxt_set_cdclk(dev_priv, &cdclk_state);
>> >> > > >  }
>> >> > > >
>> >> > > > +static int cnl_calc_cdclk(int max_pixclk)
>> >> > > > +{
>> >> > > > +       if (max_pixclk > 336000)
>> >> > > > +               return 528000;
>> >> > > > +       else if (max_pixclk > 168000)
>> >> > > > +               return 336000;
>> >> > > > +       else
>> >> > > > +               return 168000;
>> >> > > > +}
>> >> > > > +
>> >> > > >  static void cnl_cdclk_pll_update(struct drm_i915_private *dev_priv,
>> >> > > >                                  struct intel_cdclk_state *cdclk_state)
>> >> > > >  {
>> >> > > > @@ -1640,7 +1650,7 @@ void cnl_init_cdclk(struct drm_i915_private *dev_priv)
>> >> > > >
>> >> > > >         cdclk_state = dev_priv->cdclk.hw;
>> >> > > >
>> >> > > > -       cdclk_state.cdclk = 168000;
>> >> > > > +       cdclk_state.cdclk = cnl_calc_cdclk(0);
>> >> > > >         cdclk_state.vco = cnl_cdclk_pll_vco(dev_priv, cdclk_state.cdclk);
>> >> > > >
>> >> > > >         cnl_set_cdclk(dev_priv, &cdclk_state);
>> >> > > > @@ -1928,6 +1938,40 @@ static int bxt_modeset_calc_cdclk(struct drm_atomic_state *state)
>> >> > > >         return 0;
>> >> > > >  }
>> >> > > >
>> >> > > > +static int cnl_modeset_calc_cdclk(struct drm_atomic_state *state)
>> >> > > > +{
>> >> > > > +       struct drm_i915_private *dev_priv = to_i915(state->dev);
>> >> > > > +       struct intel_atomic_state *intel_state =
>> >> > > > +               to_intel_atomic_state(state);
>> >> > > > +       int max_pixclk = intel_max_pixel_rate(state);
>> >> > > > +       int cdclk, vco;
>> >> > > > +
>> >> > > > +       cdclk = cnl_calc_cdclk(max_pixclk);
>> >> > > > +       vco = cnl_cdclk_pll_vco(dev_priv, cdclk);
>> >> > >
>> >> > > The spec says not to set CDCLK to 168MHz if audio is used with 96MHz
>> >> > > BCLK, what's the plan to add that constraint? At least there could be a
>> >> > > TODO: here.
>> >> >
>> >> > That's a good question.
>> >> > Do we have ways to know the audio freq?
>> >> > Or we need to add few extra hooks?
>> >> > And agree, at least a TODO or FIXME here is needed while we dont have a
>> >> > clear path.
>> >>
>> >> bdw_adjust_min_pipe_pixel_rate() just assumes 96MHz. There was some
>> >> discussion on the topic, and I found some register that possibly could
>> >> tell us something. But the best solution would probably involve querying
>> >> it from the audio driver.
>> >>
>> >
>> > The last time I checked with the audio folks, the driver does not change
>> > the BCLK freq. and the default is 96 MHz.
>>
>> So, what should we do for now? Block 168? Remove 168?
>
> As Ville wrote, bdw_adjust_min_pipe_pixel_rate() already does that. You
> just have to modify intel_max_pixel_rate() to include CNL too.

ah! cool, thanks!

>
> -DK
>
>>
>> >
>> >
>> >> >
>> >> > >
>> >> > > > +
>> >> > > > +       if (cdclk > dev_priv->max_cdclk_freq) {
>> >> > > > +               DRM_DEBUG_KMS("requested cdclk (%d kHz) exceeds max (%d kHz)\n",
>> >> > > > +                             cdclk, dev_priv->max_cdclk_freq);
>> >> > > > +               return -EINVAL;
>> >> > > > +       }
>> >> > > > +
>> >> > > > +       intel_state->cdclk.logical.vco = vco;
>> >> > > > +       intel_state->cdclk.logical.cdclk = cdclk;
>> >> > > > +
>> >> > > > +       if (!intel_state->active_crtcs) {
>> >> > > > +               cdclk = cnl_calc_cdclk(0);
>> >> > > > +               vco = cnl_cdclk_pll_vco(dev_priv, cdclk);
>> >> > > > +
>> >> > > > +               intel_state->cdclk.actual.vco = vco;
>> >> > > > +               intel_state->cdclk.actual.cdclk = cdclk;
>> >> > > > +       } else {
>> >> > > > +               intel_state->cdclk.actual =
>> >> > > > +                       intel_state->cdclk.logical;
>> >> > > > +       }
>> >> > > > +
>> >> > > > +       return 0;
>> >> > > > +}
>> >> > > > +
>> >> > > >  static int intel_compute_max_dotclk(struct drm_i915_private *dev_priv)
>> >> > > >  {
>> >> > > >         int max_cdclk_freq = dev_priv->max_cdclk_freq;
>> >> > > > @@ -1959,7 +2003,9 @@ static int intel_compute_max_dotclk(struct drm_i915_private *dev_priv)
>> >> > > >   */
>> >> > > >  void intel_update_max_cdclk(struct drm_i915_private *dev_priv)
>> >> > > >  {
>> >> > > > -       if (IS_GEN9_BC(dev_priv)) {
>> >> > > > +       if (IS_CANNONLAKE(dev_priv)) {
>> >> > > > +               dev_priv->max_cdclk_freq = 528000;
>> >> > > > +       } else if (IS_GEN9_BC(dev_priv)) {
>> >> > > >                 u32 limit = I915_READ(SKL_DFSM) & SKL_DFSM_CDCLK_LIMIT_MASK;
>> >> > > >                 int max_cdclk, vco;
>> >> > > >
>> >> > > > @@ -2158,6 +2204,10 @@ void intel_init_cdclk_hooks(struct drm_i915_private *dev_priv)
>> >> > > >                 dev_priv->display.set_cdclk = skl_set_cdclk;
>> >> > > >                 dev_priv->display.modeset_calc_cdclk =
>> >> > > >                         skl_modeset_calc_cdclk;
>> >> > > > +       } else if (IS_CANNONLAKE(dev_priv)) {
>> >> > > > +               dev_priv->display.set_cdclk = cnl_set_cdclk;
>> >> > > > +               dev_priv->display.modeset_calc_cdclk =
>> >> > > > +                       cnl_modeset_calc_cdclk;
>> >> > > >         }
>> >> > > >
>> >> > > >         if (IS_CANNONLAKE(dev_priv))
>> >> > > > --
>> >> > > > 1.9.1
>> >> > > >
>> >> > > > _______________________________________________
>> >> > > > Intel-gfx mailing list
>> >> > > > Intel-gfx@lists.freedesktop.org
>> >> > > > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
>> >> >
>> >>
>> >
>> > _______________________________________________
>> > Intel-gfx mailing list
>> > Intel-gfx@lists.freedesktop.org
>> > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
>>
>>
>>
>



-- 
Rodrigo Vivi
Blog: http://blog.vivi.eng.br
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [PATCH 31/67] drm/i915/cnl: Allow dynamic cdclk changes on CNL

[Rodrigo Vivi]

On Tue, Jun 6, 2017 at 11:09 AM, Rodrigo Vivi <rodrigo.vivi@gmail.com> wrote:
> On Tue, Jun 6, 2017 at 10:39 AM, Pandiyan, Dhinakaran
> <dhinakaran.pandiyan@intel.com> wrote:
>> On Tue, 2017-06-06 at 08:24 -0700, Rodrigo Vivi wrote:
>>> On Mon, Jun 5, 2017 at 10:04 AM, Pandiyan, Dhinakaran
>>> <dhinakaran.pandiyan@intel.com> wrote:
>>> > On Mon, 2017-06-05 at 19:55 +0300, Ville Syrjälä wrote:
>>> >> On Mon, Jun 05, 2017 at 04:41:07PM +0000, Vivi, Rodrigo wrote:
>>> >> > On Mon, 2017-06-05 at 18:22 +0300, Imre Deak wrote:
>>> >> > > On Thu, Apr 06, 2017 at 12:15:27PM -0700, Rodrigo Vivi wrote:
>>> >> > > > All the low level cdclk bits are present, so let's add the required
>>> >> > > > hooks to reconfigure cdclk on the fly.
>>> >> > > >
>>> >> > > > v2: Rebase due to cnl_sanitize_cdclk()
>>> >> > > > v3: Rebased by Rodrigo on top of Ville's cdclk rework.
>>> >> > > > v4: Rebase moving cnl_calc_cdclk up to follow same order
>>> >> > > >     as previous platforms.
>>> >> > > >
>>> >> > > > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
>>> >> > > > Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
>>> >> > > > ---
>>> >> > > >  drivers/gpu/drm/i915/intel_cdclk.c | 54 ++++++++++++++++++++++++++++++++++++--
>>> >> > > >  1 file changed, 52 insertions(+), 2 deletions(-)
>>> >> > > >
>>> >> > > > diff --git a/drivers/gpu/drm/i915/intel_cdclk.c b/drivers/gpu/drm/i915/intel_cdclk.c
>>> >> > > > index f9ba1e7..a8c254b 100644
>>> >> > > > --- a/drivers/gpu/drm/i915/intel_cdclk.c
>>> >> > > > +++ b/drivers/gpu/drm/i915/intel_cdclk.c
>>> >> > > > @@ -1400,6 +1400,16 @@ void bxt_uninit_cdclk(struct drm_i915_private *dev_priv)
>>> >> > > >         bxt_set_cdclk(dev_priv, &cdclk_state);
>>> >> > > >  }
>>> >> > > >
>>> >> > > > +static int cnl_calc_cdclk(int max_pixclk)
>>> >> > > > +{
>>> >> > > > +       if (max_pixclk > 336000)
>>> >> > > > +               return 528000;
>>> >> > > > +       else if (max_pixclk > 168000)
>>> >> > > > +               return 336000;
>>> >> > > > +       else
>>> >> > > > +               return 168000;
>>> >> > > > +}
>>> >> > > > +
>>> >> > > >  static void cnl_cdclk_pll_update(struct drm_i915_private *dev_priv,
>>> >> > > >                                  struct intel_cdclk_state *cdclk_state)
>>> >> > > >  {
>>> >> > > > @@ -1640,7 +1650,7 @@ void cnl_init_cdclk(struct drm_i915_private *dev_priv)
>>> >> > > >
>>> >> > > >         cdclk_state = dev_priv->cdclk.hw;
>>> >> > > >
>>> >> > > > -       cdclk_state.cdclk = 168000;
>>> >> > > > +       cdclk_state.cdclk = cnl_calc_cdclk(0);
>>> >> > > >         cdclk_state.vco = cnl_cdclk_pll_vco(dev_priv, cdclk_state.cdclk);
>>> >> > > >
>>> >> > > >         cnl_set_cdclk(dev_priv, &cdclk_state);
>>> >> > > > @@ -1928,6 +1938,40 @@ static int bxt_modeset_calc_cdclk(struct drm_atomic_state *state)
>>> >> > > >         return 0;
>>> >> > > >  }
>>> >> > > >
>>> >> > > > +static int cnl_modeset_calc_cdclk(struct drm_atomic_state *state)
>>> >> > > > +{
>>> >> > > > +       struct drm_i915_private *dev_priv = to_i915(state->dev);
>>> >> > > > +       struct intel_atomic_state *intel_state =
>>> >> > > > +               to_intel_atomic_state(state);
>>> >> > > > +       int max_pixclk = intel_max_pixel_rate(state);
>>> >> > > > +       int cdclk, vco;
>>> >> > > > +
>>> >> > > > +       cdclk = cnl_calc_cdclk(max_pixclk);
>>> >> > > > +       vco = cnl_cdclk_pll_vco(dev_priv, cdclk);
>>> >> > >
>>> >> > > The spec says not to set CDCLK to 168MHz if audio is used with 96MHz
>>> >> > > BCLK, what's the plan to add that constraint? At least there could be a
>>> >> > > TODO: here.
>>> >> >
>>> >> > That's a good question.
>>> >> > Do we have ways to know the audio freq?
>>> >> > Or we need to add few extra hooks?
>>> >> > And agree, at least a TODO or FIXME here is needed while we dont have a
>>> >> > clear path.
>>> >>
>>> >> bdw_adjust_min_pipe_pixel_rate() just assumes 96MHz. There was some
>>> >> discussion on the topic, and I found some register that possibly could
>>> >> tell us something. But the best solution would probably involve querying
>>> >> it from the audio driver.
>>> >>
>>> >
>>> > The last time I checked with the audio folks, the driver does not change
>>> > the BCLK freq. and the default is 96 MHz.
>>>
>>> So, what should we do for now? Block 168? Remove 168?
>>
>> As Ville wrote, bdw_adjust_min_pipe_pixel_rate() already does that. You
>> just have to modify intel_max_pixel_rate() to include CNL too.
>

oh, so just squash [PATCH 67/67] drm/i915/cnl: Adjust min pixelrate.
here?

>
>>
>> -DK
>>
>>>
>>> >
>>> >
>>> >> >
>>> >> > >
>>> >> > > > +
>>> >> > > > +       if (cdclk > dev_priv->max_cdclk_freq) {
>>> >> > > > +               DRM_DEBUG_KMS("requested cdclk (%d kHz) exceeds max (%d kHz)\n",
>>> >> > > > +                             cdclk, dev_priv->max_cdclk_freq);
>>> >> > > > +               return -EINVAL;
>>> >> > > > +       }
>>> >> > > > +
>>> >> > > > +       intel_state->cdclk.logical.vco = vco;
>>> >> > > > +       intel_state->cdclk.logical.cdclk = cdclk;
>>> >> > > > +
>>> >> > > > +       if (!intel_state->active_crtcs) {
>>> >> > > > +               cdclk = cnl_calc_cdclk(0);
>>> >> > > > +               vco = cnl_cdclk_pll_vco(dev_priv, cdclk);
>>> >> > > > +
>>> >> > > > +               intel_state->cdclk.actual.vco = vco;
>>> >> > > > +               intel_state->cdclk.actual.cdclk = cdclk;
>>> >> > > > +       } else {
>>> >> > > > +               intel_state->cdclk.actual =
>>> >> > > > +                       intel_state->cdclk.logical;
>>> >> > > > +       }
>>> >> > > > +
>>> >> > > > +       return 0;
>>> >> > > > +}
>>> >> > > > +
>>> >> > > >  static int intel_compute_max_dotclk(struct drm_i915_private *dev_priv)
>>> >> > > >  {
>>> >> > > >         int max_cdclk_freq = dev_priv->max_cdclk_freq;
>>> >> > > > @@ -1959,7 +2003,9 @@ static int intel_compute_max_dotclk(struct drm_i915_private *dev_priv)
>>> >> > > >   */
>>> >> > > >  void intel_update_max_cdclk(struct drm_i915_private *dev_priv)
>>> >> > > >  {
>>> >> > > > -       if (IS_GEN9_BC(dev_priv)) {
>>> >> > > > +       if (IS_CANNONLAKE(dev_priv)) {
>>> >> > > > +               dev_priv->max_cdclk_freq = 528000;
>>> >> > > > +       } else if (IS_GEN9_BC(dev_priv)) {
>>> >> > > >                 u32 limit = I915_READ(SKL_DFSM) & SKL_DFSM_CDCLK_LIMIT_MASK;
>>> >> > > >                 int max_cdclk, vco;
>>> >> > > >
>>> >> > > > @@ -2158,6 +2204,10 @@ void intel_init_cdclk_hooks(struct drm_i915_private *dev_priv)
>>> >> > > >                 dev_priv->display.set_cdclk = skl_set_cdclk;
>>> >> > > >                 dev_priv->display.modeset_calc_cdclk =
>>> >> > > >                         skl_modeset_calc_cdclk;
>>> >> > > > +       } else if (IS_CANNONLAKE(dev_priv)) {
>>> >> > > > +               dev_priv->display.set_cdclk = cnl_set_cdclk;
>>> >> > > > +               dev_priv->display.modeset_calc_cdclk =
>>> >> > > > +                       cnl_modeset_calc_cdclk;
>>> >> > > >         }
>>> >> > > >
>>> >> > > >         if (IS_CANNONLAKE(dev_priv))
>>> >> > > > --
>>> >> > > > 1.9.1
>>> >> > > >
>>> >> > > > _______________________________________________
>>> >> > > > Intel-gfx mailing list
>>> >> > > > Intel-gfx@lists.freedesktop.org
>>> >> > > > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
>>> >> >
>>> >>
>>> >
>>> > _______________________________________________
>>> > Intel-gfx mailing list
>>> > Intel-gfx@lists.freedesktop.org
>>> > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
>>>
>>>
>>>
>>
>
>
>
> --
> Rodrigo Vivi
> Blog: http://blog.vivi.eng.br



-- 
Rodrigo Vivi
Blog: http://blog.vivi.eng.br
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [PATCH 31/67] drm/i915/cnl: Allow dynamic cdclk changes on CNL

[Pandiyan, Dhinakaran]

On Tue, 2017-06-06 at 11:12 -0700, Rodrigo Vivi wrote:
> On Tue, Jun 6, 2017 at 11:09 AM, Rodrigo Vivi <rodrigo.vivi@gmail.com> wrote:
> > On Tue, Jun 6, 2017 at 10:39 AM, Pandiyan, Dhinakaran
> > <dhinakaran.pandiyan@intel.com> wrote:
> >> On Tue, 2017-06-06 at 08:24 -0700, Rodrigo Vivi wrote:
> >>> On Mon, Jun 5, 2017 at 10:04 AM, Pandiyan, Dhinakaran
> >>> <dhinakaran.pandiyan@intel.com> wrote:
> >>> > On Mon, 2017-06-05 at 19:55 +0300, Ville Syrjälä wrote:
> >>> >> On Mon, Jun 05, 2017 at 04:41:07PM +0000, Vivi, Rodrigo wrote:
> >>> >> > On Mon, 2017-06-05 at 18:22 +0300, Imre Deak wrote:
> >>> >> > > On Thu, Apr 06, 2017 at 12:15:27PM -0700, Rodrigo Vivi wrote:
> >>> >> > > > All the low level cdclk bits are present, so let's add the required
> >>> >> > > > hooks to reconfigure cdclk on the fly.
> >>> >> > > >
> >>> >> > > > v2: Rebase due to cnl_sanitize_cdclk()
> >>> >> > > > v3: Rebased by Rodrigo on top of Ville's cdclk rework.
> >>> >> > > > v4: Rebase moving cnl_calc_cdclk up to follow same order
> >>> >> > > >     as previous platforms.
> >>> >> > > >
> >>> >> > > > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> >>> >> > > > Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
> >>> >> > > > ---
> >>> >> > > >  drivers/gpu/drm/i915/intel_cdclk.c | 54 ++++++++++++++++++++++++++++++++++++--
> >>> >> > > >  1 file changed, 52 insertions(+), 2 deletions(-)
> >>> >> > > >
> >>> >> > > > diff --git a/drivers/gpu/drm/i915/intel_cdclk.c b/drivers/gpu/drm/i915/intel_cdclk.c
> >>> >> > > > index f9ba1e7..a8c254b 100644
> >>> >> > > > --- a/drivers/gpu/drm/i915/intel_cdclk.c
> >>> >> > > > +++ b/drivers/gpu/drm/i915/intel_cdclk.c
> >>> >> > > > @@ -1400,6 +1400,16 @@ void bxt_uninit_cdclk(struct drm_i915_private *dev_priv)
> >>> >> > > >         bxt_set_cdclk(dev_priv, &cdclk_state);
> >>> >> > > >  }
> >>> >> > > >
> >>> >> > > > +static int cnl_calc_cdclk(int max_pixclk)
> >>> >> > > > +{
> >>> >> > > > +       if (max_pixclk > 336000)
> >>> >> > > > +               return 528000;
> >>> >> > > > +       else if (max_pixclk > 168000)
> >>> >> > > > +               return 336000;
> >>> >> > > > +       else
> >>> >> > > > +               return 168000;
> >>> >> > > > +}
> >>> >> > > > +
> >>> >> > > >  static void cnl_cdclk_pll_update(struct drm_i915_private *dev_priv,
> >>> >> > > >                                  struct intel_cdclk_state *cdclk_state)
> >>> >> > > >  {
> >>> >> > > > @@ -1640,7 +1650,7 @@ void cnl_init_cdclk(struct drm_i915_private *dev_priv)
> >>> >> > > >
> >>> >> > > >         cdclk_state = dev_priv->cdclk.hw;
> >>> >> > > >
> >>> >> > > > -       cdclk_state.cdclk = 168000;
> >>> >> > > > +       cdclk_state.cdclk = cnl_calc_cdclk(0);
> >>> >> > > >         cdclk_state.vco = cnl_cdclk_pll_vco(dev_priv, cdclk_state.cdclk);
> >>> >> > > >
> >>> >> > > >         cnl_set_cdclk(dev_priv, &cdclk_state);
> >>> >> > > > @@ -1928,6 +1938,40 @@ static int bxt_modeset_calc_cdclk(struct drm_atomic_state *state)
> >>> >> > > >         return 0;
> >>> >> > > >  }
> >>> >> > > >
> >>> >> > > > +static int cnl_modeset_calc_cdclk(struct drm_atomic_state *state)
> >>> >> > > > +{
> >>> >> > > > +       struct drm_i915_private *dev_priv = to_i915(state->dev);
> >>> >> > > > +       struct intel_atomic_state *intel_state =
> >>> >> > > > +               to_intel_atomic_state(state);
> >>> >> > > > +       int max_pixclk = intel_max_pixel_rate(state);
> >>> >> > > > +       int cdclk, vco;
> >>> >> > > > +
> >>> >> > > > +       cdclk = cnl_calc_cdclk(max_pixclk);
> >>> >> > > > +       vco = cnl_cdclk_pll_vco(dev_priv, cdclk);
> >>> >> > >
> >>> >> > > The spec says not to set CDCLK to 168MHz if audio is used with 96MHz
> >>> >> > > BCLK, what's the plan to add that constraint? At least there could be a
> >>> >> > > TODO: here.
> >>> >> >
> >>> >> > That's a good question.
> >>> >> > Do we have ways to know the audio freq?
> >>> >> > Or we need to add few extra hooks?
> >>> >> > And agree, at least a TODO or FIXME here is needed while we dont have a
> >>> >> > clear path.
> >>> >>
> >>> >> bdw_adjust_min_pipe_pixel_rate() just assumes 96MHz. There was some
> >>> >> discussion on the topic, and I found some register that possibly could
> >>> >> tell us something. But the best solution would probably involve querying
> >>> >> it from the audio driver.
> >>> >>
> >>> >
> >>> > The last time I checked with the audio folks, the driver does not change
> >>> > the BCLK freq. and the default is 96 MHz.
> >>>
> >>> So, what should we do for now? Block 168? Remove 168?
> >>
> >> As Ville wrote, bdw_adjust_min_pipe_pixel_rate() already does that. You
> >> just have to modify intel_max_pixel_rate() to include CNL too.
> >
> 
> oh, so just squash [PATCH 67/67] drm/i915/cnl: Adjust min pixelrate.
> here?
> 

I completely forgot about that patch, makes sense to squash that here.



> >
> >>
> >> -DK
> >>
> >>>
> >>> >
> >>> >
> >>> >> >
> >>> >> > >
> >>> >> > > > +
> >>> >> > > > +       if (cdclk > dev_priv->max_cdclk_freq) {
> >>> >> > > > +               DRM_DEBUG_KMS("requested cdclk (%d kHz) exceeds max (%d kHz)\n",
> >>> >> > > > +                             cdclk, dev_priv->max_cdclk_freq);
> >>> >> > > > +               return -EINVAL;
> >>> >> > > > +       }
> >>> >> > > > +
> >>> >> > > > +       intel_state->cdclk.logical.vco = vco;
> >>> >> > > > +       intel_state->cdclk.logical.cdclk = cdclk;
> >>> >> > > > +
> >>> >> > > > +       if (!intel_state->active_crtcs) {
> >>> >> > > > +               cdclk = cnl_calc_cdclk(0);
> >>> >> > > > +               vco = cnl_cdclk_pll_vco(dev_priv, cdclk);
> >>> >> > > > +
> >>> >> > > > +               intel_state->cdclk.actual.vco = vco;
> >>> >> > > > +               intel_state->cdclk.actual.cdclk = cdclk;
> >>> >> > > > +       } else {
> >>> >> > > > +               intel_state->cdclk.actual =
> >>> >> > > > +                       intel_state->cdclk.logical;
> >>> >> > > > +       }
> >>> >> > > > +
> >>> >> > > > +       return 0;
> >>> >> > > > +}
> >>> >> > > > +
> >>> >> > > >  static int intel_compute_max_dotclk(struct drm_i915_private *dev_priv)
> >>> >> > > >  {
> >>> >> > > >         int max_cdclk_freq = dev_priv->max_cdclk_freq;
> >>> >> > > > @@ -1959,7 +2003,9 @@ static int intel_compute_max_dotclk(struct drm_i915_private *dev_priv)
> >>> >> > > >   */
> >>> >> > > >  void intel_update_max_cdclk(struct drm_i915_private *dev_priv)
> >>> >> > > >  {
> >>> >> > > > -       if (IS_GEN9_BC(dev_priv)) {
> >>> >> > > > +       if (IS_CANNONLAKE(dev_priv)) {
> >>> >> > > > +               dev_priv->max_cdclk_freq = 528000;
> >>> >> > > > +       } else if (IS_GEN9_BC(dev_priv)) {
> >>> >> > > >                 u32 limit = I915_READ(SKL_DFSM) & SKL_DFSM_CDCLK_LIMIT_MASK;
> >>> >> > > >                 int max_cdclk, vco;
> >>> >> > > >
> >>> >> > > > @@ -2158,6 +2204,10 @@ void intel_init_cdclk_hooks(struct drm_i915_private *dev_priv)
> >>> >> > > >                 dev_priv->display.set_cdclk = skl_set_cdclk;
> >>> >> > > >                 dev_priv->display.modeset_calc_cdclk =
> >>> >> > > >                         skl_modeset_calc_cdclk;
> >>> >> > > > +       } else if (IS_CANNONLAKE(dev_priv)) {
> >>> >> > > > +               dev_priv->display.set_cdclk = cnl_set_cdclk;
> >>> >> > > > +               dev_priv->display.modeset_calc_cdclk =
> >>> >> > > > +                       cnl_modeset_calc_cdclk;
> >>> >> > > >         }
> >>> >> > > >
> >>> >> > > >         if (IS_CANNONLAKE(dev_priv))
> >>> >> > > > --
> >>> >> > > > 1.9.1
> >>> >> > > >
> >>> >> > > > _______________________________________________
> >>> >> > > > Intel-gfx mailing list
> >>> >> > > > Intel-gfx@lists.freedesktop.org
> >>> >> > > > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
> >>> >> >
> >>> >>
> >>> >
> >>> > _______________________________________________
> >>> > Intel-gfx mailing list
> >>> > Intel-gfx@lists.freedesktop.org
> >>> > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
> >>>
> >>>
> >>>
> >>
> >
> >
> >
> > --
> > Rodrigo Vivi
> > Blog: http://blog.vivi.eng.br
> 
> 
> 

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Re: [PATCH 31/67] drm/i915/cnl: Allow dynamic cdclk changes on CNL

[Rodrigo Vivi]

On Tue, Jun 6, 2017 at 2:48 PM, Pandiyan, Dhinakaran
<dhinakaran.pandiyan@intel.com> wrote:
> On Tue, 2017-06-06 at 11:12 -0700, Rodrigo Vivi wrote:
>> On Tue, Jun 6, 2017 at 11:09 AM, Rodrigo Vivi <rodrigo.vivi@gmail.com> wrote:
>> > On Tue, Jun 6, 2017 at 10:39 AM, Pandiyan, Dhinakaran
>> > <dhinakaran.pandiyan@intel.com> wrote:
>> >> On Tue, 2017-06-06 at 08:24 -0700, Rodrigo Vivi wrote:
>> >>> On Mon, Jun 5, 2017 at 10:04 AM, Pandiyan, Dhinakaran
>> >>> <dhinakaran.pandiyan@intel.com> wrote:
>> >>> > On Mon, 2017-06-05 at 19:55 +0300, Ville Syrjälä wrote:
>> >>> >> On Mon, Jun 05, 2017 at 04:41:07PM +0000, Vivi, Rodrigo wrote:
>> >>> >> > On Mon, 2017-06-05 at 18:22 +0300, Imre Deak wrote:
>> >>> >> > > On Thu, Apr 06, 2017 at 12:15:27PM -0700, Rodrigo Vivi wrote:
>> >>> >> > > > All the low level cdclk bits are present, so let's add the required
>> >>> >> > > > hooks to reconfigure cdclk on the fly.
>> >>> >> > > >
>> >>> >> > > > v2: Rebase due to cnl_sanitize_cdclk()
>> >>> >> > > > v3: Rebased by Rodrigo on top of Ville's cdclk rework.
>> >>> >> > > > v4: Rebase moving cnl_calc_cdclk up to follow same order
>> >>> >> > > >     as previous platforms.
>> >>> >> > > >
>> >>> >> > > > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
>> >>> >> > > > Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
>> >>> >> > > > ---
>> >>> >> > > >  drivers/gpu/drm/i915/intel_cdclk.c | 54 ++++++++++++++++++++++++++++++++++++--
>> >>> >> > > >  1 file changed, 52 insertions(+), 2 deletions(-)
>> >>> >> > > >
>> >>> >> > > > diff --git a/drivers/gpu/drm/i915/intel_cdclk.c b/drivers/gpu/drm/i915/intel_cdclk.c
>> >>> >> > > > index f9ba1e7..a8c254b 100644
>> >>> >> > > > --- a/drivers/gpu/drm/i915/intel_cdclk.c
>> >>> >> > > > +++ b/drivers/gpu/drm/i915/intel_cdclk.c
>> >>> >> > > > @@ -1400,6 +1400,16 @@ void bxt_uninit_cdclk(struct drm_i915_private *dev_priv)
>> >>> >> > > >         bxt_set_cdclk(dev_priv, &cdclk_state);
>> >>> >> > > >  }
>> >>> >> > > >
>> >>> >> > > > +static int cnl_calc_cdclk(int max_pixclk)
>> >>> >> > > > +{
>> >>> >> > > > +       if (max_pixclk > 336000)
>> >>> >> > > > +               return 528000;
>> >>> >> > > > +       else if (max_pixclk > 168000)
>> >>> >> > > > +               return 336000;
>> >>> >> > > > +       else
>> >>> >> > > > +               return 168000;
>> >>> >> > > > +}
>> >>> >> > > > +
>> >>> >> > > >  static void cnl_cdclk_pll_update(struct drm_i915_private *dev_priv,
>> >>> >> > > >                                  struct intel_cdclk_state *cdclk_state)
>> >>> >> > > >  {
>> >>> >> > > > @@ -1640,7 +1650,7 @@ void cnl_init_cdclk(struct drm_i915_private *dev_priv)
>> >>> >> > > >
>> >>> >> > > >         cdclk_state = dev_priv->cdclk.hw;
>> >>> >> > > >
>> >>> >> > > > -       cdclk_state.cdclk = 168000;
>> >>> >> > > > +       cdclk_state.cdclk = cnl_calc_cdclk(0);
>> >>> >> > > >         cdclk_state.vco = cnl_cdclk_pll_vco(dev_priv, cdclk_state.cdclk);
>> >>> >> > > >
>> >>> >> > > >         cnl_set_cdclk(dev_priv, &cdclk_state);
>> >>> >> > > > @@ -1928,6 +1938,40 @@ static int bxt_modeset_calc_cdclk(struct drm_atomic_state *state)
>> >>> >> > > >         return 0;
>> >>> >> > > >  }
>> >>> >> > > >
>> >>> >> > > > +static int cnl_modeset_calc_cdclk(struct drm_atomic_state *state)
>> >>> >> > > > +{
>> >>> >> > > > +       struct drm_i915_private *dev_priv = to_i915(state->dev);
>> >>> >> > > > +       struct intel_atomic_state *intel_state =
>> >>> >> > > > +               to_intel_atomic_state(state);
>> >>> >> > > > +       int max_pixclk = intel_max_pixel_rate(state);
>> >>> >> > > > +       int cdclk, vco;
>> >>> >> > > > +
>> >>> >> > > > +       cdclk = cnl_calc_cdclk(max_pixclk);
>> >>> >> > > > +       vco = cnl_cdclk_pll_vco(dev_priv, cdclk);
>> >>> >> > >
>> >>> >> > > The spec says not to set CDCLK to 168MHz if audio is used with 96MHz
>> >>> >> > > BCLK, what's the plan to add that constraint? At least there could be a
>> >>> >> > > TODO: here.
>> >>> >> >
>> >>> >> > That's a good question.
>> >>> >> > Do we have ways to know the audio freq?
>> >>> >> > Or we need to add few extra hooks?
>> >>> >> > And agree, at least a TODO or FIXME here is needed while we dont have a
>> >>> >> > clear path.
>> >>> >>
>> >>> >> bdw_adjust_min_pipe_pixel_rate() just assumes 96MHz. There was some
>> >>> >> discussion on the topic, and I found some register that possibly could
>> >>> >> tell us something. But the best solution would probably involve querying
>> >>> >> it from the audio driver.
>> >>> >>
>> >>> >
>> >>> > The last time I checked with the audio folks, the driver does not change
>> >>> > the BCLK freq. and the default is 96 MHz.
>> >>>
>> >>> So, what should we do for now? Block 168? Remove 168?
>> >>
>> >> As Ville wrote, bdw_adjust_min_pipe_pixel_rate() already does that. You
>> >> just have to modify intel_max_pixel_rate() to include CNL too.
>> >
>>
>> oh, so just squash [PATCH 67/67] drm/i915/cnl: Adjust min pixelrate.
>> here?
>>
>
> I completely forgot about that patch, makes sense to squash that here.

squashed locally here... I will send out on next chunck...

>
>
>
>> >
>> >>
>> >> -DK
>> >>
>> >>>
>> >>> >
>> >>> >
>> >>> >> >
>> >>> >> > >
>> >>> >> > > > +
>> >>> >> > > > +       if (cdclk > dev_priv->max_cdclk_freq) {
>> >>> >> > > > +               DRM_DEBUG_KMS("requested cdclk (%d kHz) exceeds max (%d kHz)\n",
>> >>> >> > > > +                             cdclk, dev_priv->max_cdclk_freq);
>> >>> >> > > > +               return -EINVAL;
>> >>> >> > > > +       }
>> >>> >> > > > +
>> >>> >> > > > +       intel_state->cdclk.logical.vco = vco;
>> >>> >> > > > +       intel_state->cdclk.logical.cdclk = cdclk;
>> >>> >> > > > +
>> >>> >> > > > +       if (!intel_state->active_crtcs) {
>> >>> >> > > > +               cdclk = cnl_calc_cdclk(0);
>> >>> >> > > > +               vco = cnl_cdclk_pll_vco(dev_priv, cdclk);
>> >>> >> > > > +
>> >>> >> > > > +               intel_state->cdclk.actual.vco = vco;
>> >>> >> > > > +               intel_state->cdclk.actual.cdclk = cdclk;
>> >>> >> > > > +       } else {
>> >>> >> > > > +               intel_state->cdclk.actual =
>> >>> >> > > > +                       intel_state->cdclk.logical;
>> >>> >> > > > +       }
>> >>> >> > > > +
>> >>> >> > > > +       return 0;
>> >>> >> > > > +}
>> >>> >> > > > +
>> >>> >> > > >  static int intel_compute_max_dotclk(struct drm_i915_private *dev_priv)
>> >>> >> > > >  {
>> >>> >> > > >         int max_cdclk_freq = dev_priv->max_cdclk_freq;
>> >>> >> > > > @@ -1959,7 +2003,9 @@ static int intel_compute_max_dotclk(struct drm_i915_private *dev_priv)
>> >>> >> > > >   */
>> >>> >> > > >  void intel_update_max_cdclk(struct drm_i915_private *dev_priv)
>> >>> >> > > >  {
>> >>> >> > > > -       if (IS_GEN9_BC(dev_priv)) {
>> >>> >> > > > +       if (IS_CANNONLAKE(dev_priv)) {
>> >>> >> > > > +               dev_priv->max_cdclk_freq = 528000;
>> >>> >> > > > +       } else if (IS_GEN9_BC(dev_priv)) {
>> >>> >> > > >                 u32 limit = I915_READ(SKL_DFSM) & SKL_DFSM_CDCLK_LIMIT_MASK;
>> >>> >> > > >                 int max_cdclk, vco;
>> >>> >> > > >
>> >>> >> > > > @@ -2158,6 +2204,10 @@ void intel_init_cdclk_hooks(struct drm_i915_private *dev_priv)
>> >>> >> > > >                 dev_priv->display.set_cdclk = skl_set_cdclk;
>> >>> >> > > >                 dev_priv->display.modeset_calc_cdclk =
>> >>> >> > > >                         skl_modeset_calc_cdclk;
>> >>> >> > > > +       } else if (IS_CANNONLAKE(dev_priv)) {
>> >>> >> > > > +               dev_priv->display.set_cdclk = cnl_set_cdclk;
>> >>> >> > > > +               dev_priv->display.modeset_calc_cdclk =
>> >>> >> > > > +                       cnl_modeset_calc_cdclk;
>> >>> >> > > >         }
>> >>> >> > > >
>> >>> >> > > >         if (IS_CANNONLAKE(dev_priv))
>> >>> >> > > > --
>> >>> >> > > > 1.9.1
>> >>> >> > > >
>> >>> >> > > > _______________________________________________
>> >>> >> > > > Intel-gfx mailing list
>> >>> >> > > > Intel-gfx@lists.freedesktop.org
>> >>> >> > > > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
>> >>> >> >
>> >>> >>
>> >>> >
>> >>> > _______________________________________________
>> >>> > Intel-gfx mailing list
>> >>> > Intel-gfx@lists.freedesktop.org
>> >>> > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
>> >>>
>> >>>
>> >>>
>> >>
>> >
>> >
>> >
>> > --
>> > Rodrigo Vivi
>> > Blog: http://blog.vivi.eng.br
>>
>>
>>
>



-- 
Rodrigo Vivi
Blog: http://blog.vivi.eng.br
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[PATCH 32/67] drm/i915/cnl: DDI - PLL mapping

[Rodrigo Vivi]

One of the steps for PLL (un)initialization is to (un)map
the correspondent DDI that is actually using that PLL.

So, let's do this step following the places already stablished
and used so far, although spec put this as part of PLL
initialization sequences.

v2: Use proper prefix on bits names as suggested by Ander.
v3: Add missed "~". Without that the logic was inverted
    so we were disabling interrupts.
    Credits-to: Clinton
    Credits-to: Art
v4: Spec is getting updated to do DDI -> PLL mapping
    and clock on in 2 separated reg writes. (Paulo)
    Also update bits definitions to use space
    (1 << 1) instead of (1<<1). (Paulo)

Cc: Paulo Zanoni <paulo.r.zanoni@intel.com>
Cc: Art Runyan <arthur.j.runyan@intel.com>
Cc: Clint Taylor <clinton.a.taylor@intel.com>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Cc: Kahola, Mika <mika.kahola@intel.com>
Cc: Ander Conselvan De Oliveira <ander.conselvan.de.oliveira@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Reviewed-by: Kahola, Mika <mika.kahola@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h  |  9 +++++++++
 drivers/gpu/drm/i915/intel_ddi.c | 23 ++++++++++++++++++++---
 2 files changed, 29 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 3cfc65f..dcb8e21 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -8150,6 +8150,15 @@ enum {
 #define DPLL_CFGCR1(id)	_MMIO_PIPE((id) - SKL_DPLL1, _DPLL1_CFGCR1, _DPLL2_CFGCR1)
 #define DPLL_CFGCR2(id)	_MMIO_PIPE((id) - SKL_DPLL1, _DPLL1_CFGCR2, _DPLL2_CFGCR2)
 
+/*
+ * CNL Clocks
+ */
+#define DPCLKA_CFGCR0				_MMIO(0x6C200)
+#define  DPCLKA_CFGCR0_DDI_CLK_OFF(port)	(1 << ((port)+10))
+#define  DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(port)	(3 << ((port)*2))
+#define  DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(port)	((port)*2)
+#define  DPCLKA_CFGCR0_DDI_CLK_SEL(pll, port)	((pll) << ((port)*2))
+
 /* BXT display engine PLL */
 #define BXT_DE_PLL_CTL			_MMIO(0x6d000)
 #define   BXT_DE_PLL_RATIO(x)		(x)	/* {60,65,100} * 19.2MHz */
diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
index 0914ad9..2a901bf 100644
--- a/drivers/gpu/drm/i915/intel_ddi.c
+++ b/drivers/gpu/drm/i915/intel_ddi.c
@@ -1621,13 +1621,27 @@ static void intel_ddi_clk_select(struct intel_encoder *encoder,
 {
 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 	enum port port = intel_ddi_get_encoder_port(encoder);
+	uint32_t val;
 
 	if (WARN_ON(!pll))
 		return;
 
-	if (IS_GEN9_BC(dev_priv)) {
-		uint32_t val;
+	if (IS_CANNONLAKE(dev_priv)) {
+		/* Configure DPCLKA_CFGCR0 to map the DPLL to the DDI. */
+		val = I915_READ(DPCLKA_CFGCR0);
+		val |= DPCLKA_CFGCR0_DDI_CLK_SEL(pll->id, port);
+		I915_WRITE(DPCLKA_CFGCR0, val);
 
+		/*
+		 * Configure DPCLKA_CFGCR0 to turn on the clock for the DDI.
+		 * This step and the step before must be done with separate
+		 * register writes.
+		 */
+		val = I915_READ(DPCLKA_CFGCR0);
+		val &= ~(DPCLKA_CFGCR0_DDI_CLK_OFF(port) |
+			 DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(port));
+		I915_WRITE(DPCLKA_CFGCR0, val);
+	} else if (IS_GEN9_BC(dev_priv)) {
 		/* DDI -> PLL mapping  */
 		val = I915_READ(DPLL_CTRL2);
 
@@ -1763,7 +1777,10 @@ static void intel_ddi_post_disable(struct intel_encoder *intel_encoder,
 	if (dig_port)
 		intel_display_power_put(dev_priv, dig_port->ddi_io_power_domain);
 
-	if (IS_GEN9_BC(dev_priv))
+	if (IS_CANNONLAKE(dev_priv))
+		I915_WRITE(DPCLKA_CFGCR0, I915_READ(DPCLKA_CFGCR0) |
+			   DPCLKA_CFGCR0_DDI_CLK_OFF(port));
+	else if (IS_GEN9_BC(dev_priv))
 		I915_WRITE(DPLL_CTRL2, (I915_READ(DPLL_CTRL2) |
 					DPLL_CTRL2_DDI_CLK_OFF(port)));
 	else if (INTEL_GEN(dev_priv) < 9)
-- 
1.9.1

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Re: [PATCH 32/67] drm/i915/cnl: DDI - PLL mapping

[Paulo Zanoni]

Em Qui, 2017-04-06 às 12:15 -0700, Rodrigo Vivi escreveu:
> One of the steps for PLL (un)initialization is to (un)map
> the correspondent DDI that is actually using that PLL.
> 
> So, let's do this step following the places already stablished
> and used so far, although spec put this as part of PLL
> initialization sequences.
> 
> v2: Use proper prefix on bits names as suggested by Ander.
> v3: Add missed "~". Without that the logic was inverted
>     so we were disabling interrupts.
>     Credits-to: Clinton
>     Credits-to: Art
> v4: Spec is getting updated to do DDI -> PLL mapping
>     and clock on in 2 separated reg writes. (Paulo)
>     Also update bits definitions to use space
>     (1 << 1) instead of (1<<1). (Paulo)
> 
> Cc: Paulo Zanoni <paulo.r.zanoni@intel.com>
> Cc: Art Runyan <arthur.j.runyan@intel.com>
> Cc: Clint Taylor <clinton.a.taylor@intel.com>
> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> Cc: Kahola, Mika <mika.kahola@intel.com>
> Cc: Ander Conselvan De Oliveira <ander.conselvan.de.oliveira@intel.co
> m>
> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
> Reviewed-by: Kahola, Mika <mika.kahola@intel.com>
> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
> ---
>  drivers/gpu/drm/i915/i915_reg.h  |  9 +++++++++
>  drivers/gpu/drm/i915/intel_ddi.c | 23 ++++++++++++++++++++---
>  2 files changed, 29 insertions(+), 3 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_reg.h
> b/drivers/gpu/drm/i915/i915_reg.h
> index 3cfc65f..dcb8e21 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -8150,6 +8150,15 @@ enum {
>  #define DPLL_CFGCR1(id)	_MMIO_PIPE((id) - SKL_DPLL1,
> _DPLL1_CFGCR1, _DPLL2_CFGCR1)
>  #define DPLL_CFGCR2(id)	_MMIO_PIPE((id) - SKL_DPLL1,
> _DPLL1_CFGCR2, _DPLL2_CFGCR2)
>  
> +/*
> + * CNL Clocks
> + */
> +#define DPCLKA_CFGCR0				_MMIO(0x6C200)
> +#define  DPCLKA_CFGCR0_DDI_CLK_OFF(port)	(1 << ((port)+10))
> +#define  DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(port)	(3 <<
> ((port)*2))
> +#define  DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(port)	((port)*2)
> +#define  DPCLKA_CFGCR0_DDI_CLK_SEL(pll, port)	((pll) <<
> ((port)*2))
> +
>  /* BXT display engine PLL */
>  #define BXT_DE_PLL_CTL			_MMIO(0x6d000)
>  #define   BXT_DE_PLL_RATIO(x)		(x)	/*
> {60,65,100} * 19.2MHz */
> diff --git a/drivers/gpu/drm/i915/intel_ddi.c
> b/drivers/gpu/drm/i915/intel_ddi.c
> index 0914ad9..2a901bf 100644
> --- a/drivers/gpu/drm/i915/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/intel_ddi.c
> @@ -1621,13 +1621,27 @@ static void intel_ddi_clk_select(struct
> intel_encoder *encoder,
>  {
>  	struct drm_i915_private *dev_priv = to_i915(encoder-
> >base.dev);
>  	enum port port = intel_ddi_get_encoder_port(encoder);
> +	uint32_t val;
>  
>  	if (WARN_ON(!pll))
>  		return;
>  
> -	if (IS_GEN9_BC(dev_priv)) {
> -		uint32_t val;
> +	if (IS_CANNONLAKE(dev_priv)) {
> +		/* Configure DPCLKA_CFGCR0 to map the DPLL to the
> DDI. */
> +		val = I915_READ(DPCLKA_CFGCR0);
> +		val |= DPCLKA_CFGCR0_DDI_CLK_SEL(pll->id, port);
> +		I915_WRITE(DPCLKA_CFGCR0, val);

A question to the Atomic Lords: don't we need some sort of locking
around this register since it's used by all ports/clocks? I suppose
dev_priv->dpll_lock would do...

Maybe the same would apply for gen9_bc.

>  
> +		/*
> +		 * Configure DPCLKA_CFGCR0 to turn on the clock for
> the DDI.
> +		 * This step and the step before must be done with
> separate
> +		 * register writes.
> +		 */
> +		val = I915_READ(DPCLKA_CFGCR0);
> +		val &= ~(DPCLKA_CFGCR0_DDI_CLK_OFF(port) |
> +			 DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(port));
> +		I915_WRITE(DPCLKA_CFGCR0, val);
> +	} else if (IS_GEN9_BC(dev_priv)) {
>  		/* DDI -> PLL mapping  */
>  		val = I915_READ(DPLL_CTRL2);
>  
> @@ -1763,7 +1777,10 @@ static void intel_ddi_post_disable(struct
> intel_encoder *intel_encoder,
>  	if (dig_port)
>  		intel_display_power_put(dev_priv, dig_port-
> >ddi_io_power_domain);
>  
> -	if (IS_GEN9_BC(dev_priv))
> +	if (IS_CANNONLAKE(dev_priv))
> +		I915_WRITE(DPCLKA_CFGCR0, I915_READ(DPCLKA_CFGCR0) |
> +			   DPCLKA_CFGCR0_DDI_CLK_OFF(port));
> +	else if (IS_GEN9_BC(dev_priv))
>  		I915_WRITE(DPLL_CTRL2, (I915_READ(DPLL_CTRL2) |
>  					DPLL_CTRL2_DDI_CLK_OFF(port)
> ));
>  	else if (INTEL_GEN(dev_priv) < 9)
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Re: [PATCH 32/67] drm/i915/cnl: DDI - PLL mapping

[Ander Conselvan De Oliveira]

On Fri, 2017-04-07 at 18:12 -0300, Paulo Zanoni wrote:
> Em Qui, 2017-04-06 às 12:15 -0700, Rodrigo Vivi escreveu:
> > One of the steps for PLL (un)initialization is to (un)map
> > the correspondent DDI that is actually using that PLL.
> > 
> > So, let's do this step following the places already stablished
> > and used so far, although spec put this as part of PLL
> > initialization sequences.
> > 
> > v2: Use proper prefix on bits names as suggested by Ander.
> > v3: Add missed "~". Without that the logic was inverted
> >     so we were disabling interrupts.
> >     Credits-to: Clinton
> >     Credits-to: Art
> > v4: Spec is getting updated to do DDI -> PLL mapping
> >     and clock on in 2 separated reg writes. (Paulo)
> >     Also update bits definitions to use space
> >     (1 << 1) instead of (1<<1). (Paulo)
> > 
> > Cc: Paulo Zanoni <paulo.r.zanoni@intel.com>
> > Cc: Art Runyan <arthur.j.runyan@intel.com>
> > Cc: Clint Taylor <clinton.a.taylor@intel.com>
> > Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > Cc: Kahola, Mika <mika.kahola@intel.com>
> > Cc: Ander Conselvan De Oliveira <ander.conselvan.de.oliveira@intel.co
> > m>
> > Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
> > Reviewed-by: Kahola, Mika <mika.kahola@intel.com>
> > Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
> > ---
> >  drivers/gpu/drm/i915/i915_reg.h  |  9 +++++++++
> >  drivers/gpu/drm/i915/intel_ddi.c | 23 ++++++++++++++++++++---
> >  2 files changed, 29 insertions(+), 3 deletions(-)
> > 
> > diff --git a/drivers/gpu/drm/i915/i915_reg.h
> > b/drivers/gpu/drm/i915/i915_reg.h
> > index 3cfc65f..dcb8e21 100644
> > --- a/drivers/gpu/drm/i915/i915_reg.h
> > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > @@ -8150,6 +8150,15 @@ enum {
> >  #define DPLL_CFGCR1(id)	_MMIO_PIPE((id) - SKL_DPLL1,
> > _DPLL1_CFGCR1, _DPLL2_CFGCR1)
> >  #define DPLL_CFGCR2(id)	_MMIO_PIPE((id) - SKL_DPLL1,
> > _DPLL1_CFGCR2, _DPLL2_CFGCR2)
> >  
> > +/*
> > + * CNL Clocks
> > + */
> > +#define DPCLKA_CFGCR0				_MMIO(0x6C200)
> > +#define  DPCLKA_CFGCR0_DDI_CLK_OFF(port)	(1 << ((port)+10))
> > +#define  DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(port)	(3 <<
> > ((port)*2))
> > +#define  DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(port)	((port)*2)
> > +#define  DPCLKA_CFGCR0_DDI_CLK_SEL(pll, port)	((pll) <<
> > ((port)*2))
> > +
> >  /* BXT display engine PLL */
> >  #define BXT_DE_PLL_CTL			_MMIO(0x6d000)
> >  #define   BXT_DE_PLL_RATIO(x)		(x)	/*
> > {60,65,100} * 19.2MHz */
> > diff --git a/drivers/gpu/drm/i915/intel_ddi.c
> > b/drivers/gpu/drm/i915/intel_ddi.c
> > index 0914ad9..2a901bf 100644
> > --- a/drivers/gpu/drm/i915/intel_ddi.c
> > +++ b/drivers/gpu/drm/i915/intel_ddi.c
> > @@ -1621,13 +1621,27 @@ static void intel_ddi_clk_select(struct
> > intel_encoder *encoder,
> >  {
> >  	struct drm_i915_private *dev_priv = to_i915(encoder-
> > > base.dev);
> > 
> >  	enum port port = intel_ddi_get_encoder_port(encoder);
> > +	uint32_t val;
> >  
> >  	if (WARN_ON(!pll))
> >  		return;
> >  
> > -	if (IS_GEN9_BC(dev_priv)) {
> > -		uint32_t val;
> > +	if (IS_CANNONLAKE(dev_priv)) {
> > +		/* Configure DPCLKA_CFGCR0 to map the DPLL to the
> > DDI. */
> > +		val = I915_READ(DPCLKA_CFGCR0);
> > +		val |= DPCLKA_CFGCR0_DDI_CLK_SEL(pll->id, port);
> > +		I915_WRITE(DPCLKA_CFGCR0, val);
> 
> A question to the Atomic Lords: don't we need some sort of locking
> around this register since it's used by all ports/clocks? I suppose
> dev_priv->dpll_lock would do...
> 
> Maybe the same would apply for gen9_bc.

If there are modesets happening in parallel for different crtcs, then some
locking is needed. dpll_lock seems like the right call, that's what's used to
avoid the same problem with the enable/disable hooks.

Btw, I think this patch shows why something like [1] might be a good idea.

[1] https://patchwork.freedesktop.org/patch/113598/
> 
> >  
> > +		/*
> > +		 * Configure DPCLKA_CFGCR0 to turn on the clock for
> > the DDI.
> > +		 * This step and the step before must be done with
> > separate
> > +		 * register writes.
> > +		 */
> > +		val = I915_READ(DPCLKA_CFGCR0);
> > +		val &= ~(DPCLKA_CFGCR0_DDI_CLK_OFF(port) |
> > +			 DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(port));
> > +		I915_WRITE(DPCLKA_CFGCR0, val);
> > +	} else if (IS_GEN9_BC(dev_priv)) {
> >  		/* DDI -> PLL mapping  */
> >  		val = I915_READ(DPLL_CTRL2);
> >  
> > @@ -1763,7 +1777,10 @@ static void intel_ddi_post_disable(struct
> > intel_encoder *intel_encoder,
> >  	if (dig_port)
> >  		intel_display_power_put(dev_priv, dig_port-
> > > ddi_io_power_domain);
> > 
> >  
> > -	if (IS_GEN9_BC(dev_priv))
> > +	if (IS_CANNONLAKE(dev_priv))
> > +		I915_WRITE(DPCLKA_CFGCR0, I915_READ(DPCLKA_CFGCR0) |
> > +			   DPCLKA_CFGCR0_DDI_CLK_OFF(port));
> > +	else if (IS_GEN9_BC(dev_priv))
> >  		I915_WRITE(DPLL_CTRL2, (I915_READ(DPLL_CTRL2) |
> >  					DPLL_CTRL2_DDI_CLK_OFF(port)
> > ));
> >  	else if (INTEL_GEN(dev_priv) < 9)
> 
> _______________________________________________
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> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
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Re: [PATCH 32/67] drm/i915/cnl: DDI - PLL mapping

[Ville Syrjälä]

On Thu, May 04, 2017 at 03:35:51PM +0300, Ander Conselvan De Oliveira wrote:
> On Fri, 2017-04-07 at 18:12 -0300, Paulo Zanoni wrote:
> > Em Qui, 2017-04-06 às 12:15 -0700, Rodrigo Vivi escreveu:
> > > One of the steps for PLL (un)initialization is to (un)map
> > > the correspondent DDI that is actually using that PLL.
> > > 
> > > So, let's do this step following the places already stablished
> > > and used so far, although spec put this as part of PLL
> > > initialization sequences.
> > > 
> > > v2: Use proper prefix on bits names as suggested by Ander.
> > > v3: Add missed "~". Without that the logic was inverted
> > >     so we were disabling interrupts.
> > >     Credits-to: Clinton
> > >     Credits-to: Art
> > > v4: Spec is getting updated to do DDI -> PLL mapping
> > >     and clock on in 2 separated reg writes. (Paulo)
> > >     Also update bits definitions to use space
> > >     (1 << 1) instead of (1<<1). (Paulo)
> > > 
> > > Cc: Paulo Zanoni <paulo.r.zanoni@intel.com>
> > > Cc: Art Runyan <arthur.j.runyan@intel.com>
> > > Cc: Clint Taylor <clinton.a.taylor@intel.com>
> > > Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > > Cc: Kahola, Mika <mika.kahola@intel.com>
> > > Cc: Ander Conselvan De Oliveira <ander.conselvan.de.oliveira@intel.co
> > > m>
> > > Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
> > > Reviewed-by: Kahola, Mika <mika.kahola@intel.com>
> > > Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
> > > ---
> > >  drivers/gpu/drm/i915/i915_reg.h  |  9 +++++++++
> > >  drivers/gpu/drm/i915/intel_ddi.c | 23 ++++++++++++++++++++---
> > >  2 files changed, 29 insertions(+), 3 deletions(-)
> > > 
> > > diff --git a/drivers/gpu/drm/i915/i915_reg.h
> > > b/drivers/gpu/drm/i915/i915_reg.h
> > > index 3cfc65f..dcb8e21 100644
> > > --- a/drivers/gpu/drm/i915/i915_reg.h
> > > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > > @@ -8150,6 +8150,15 @@ enum {
> > >  #define DPLL_CFGCR1(id)	_MMIO_PIPE((id) - SKL_DPLL1,
> > > _DPLL1_CFGCR1, _DPLL2_CFGCR1)
> > >  #define DPLL_CFGCR2(id)	_MMIO_PIPE((id) - SKL_DPLL1,
> > > _DPLL1_CFGCR2, _DPLL2_CFGCR2)
> > >  
> > > +/*
> > > + * CNL Clocks
> > > + */
> > > +#define DPCLKA_CFGCR0				_MMIO(0x6C200)
> > > +#define  DPCLKA_CFGCR0_DDI_CLK_OFF(port)	(1 << ((port)+10))
> > > +#define  DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(port)	(3 <<
> > > ((port)*2))
> > > +#define  DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(port)	((port)*2)
> > > +#define  DPCLKA_CFGCR0_DDI_CLK_SEL(pll, port)	((pll) <<
> > > ((port)*2))
> > > +
> > >  /* BXT display engine PLL */
> > >  #define BXT_DE_PLL_CTL			_MMIO(0x6d000)
> > >  #define   BXT_DE_PLL_RATIO(x)		(x)	/*
> > > {60,65,100} * 19.2MHz */
> > > diff --git a/drivers/gpu/drm/i915/intel_ddi.c
> > > b/drivers/gpu/drm/i915/intel_ddi.c
> > > index 0914ad9..2a901bf 100644
> > > --- a/drivers/gpu/drm/i915/intel_ddi.c
> > > +++ b/drivers/gpu/drm/i915/intel_ddi.c
> > > @@ -1621,13 +1621,27 @@ static void intel_ddi_clk_select(struct
> > > intel_encoder *encoder,
> > >  {
> > >  	struct drm_i915_private *dev_priv = to_i915(encoder-
> > > > base.dev);
> > > 
> > >  	enum port port = intel_ddi_get_encoder_port(encoder);
> > > +	uint32_t val;
> > >  
> > >  	if (WARN_ON(!pll))
> > >  		return;
> > >  
> > > -	if (IS_GEN9_BC(dev_priv)) {
> > > -		uint32_t val;
> > > +	if (IS_CANNONLAKE(dev_priv)) {
> > > +		/* Configure DPCLKA_CFGCR0 to map the DPLL to the
> > > DDI. */
> > > +		val = I915_READ(DPCLKA_CFGCR0);
> > > +		val |= DPCLKA_CFGCR0_DDI_CLK_SEL(pll->id, port);
> > > +		I915_WRITE(DPCLKA_CFGCR0, val);
> > 
> > A question to the Atomic Lords: don't we need some sort of locking
> > around this register since it's used by all ports/clocks? I suppose
> > dev_priv->dpll_lock would do...
> > 
> > Maybe the same would apply for gen9_bc.
> 
> If there are modesets happening in parallel for different crtcs, then some
> locking is needed. dpll_lock seems like the right call, that's what's used to
> avoid the same problem with the enable/disable hooks.

If something is allowing modesets to commit in parallel then probably
the whole world is on fire. Historically connection_mutex has been there
to protect us, but not sure how that goes with nonblocking commits. I
do hope there's still something there to prevents this...

> 
> Btw, I think this patch shows why something like [1] might be a good idea.
> 
> [1] https://patchwork.freedesktop.org/patch/113598/
> > 
> > >  
> > > +		/*
> > > +		 * Configure DPCLKA_CFGCR0 to turn on the clock for
> > > the DDI.
> > > +		 * This step and the step before must be done with
> > > separate
> > > +		 * register writes.
> > > +		 */
> > > +		val = I915_READ(DPCLKA_CFGCR0);
> > > +		val &= ~(DPCLKA_CFGCR0_DDI_CLK_OFF(port) |
> > > +			 DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(port));
> > > +		I915_WRITE(DPCLKA_CFGCR0, val);
> > > +	} else if (IS_GEN9_BC(dev_priv)) {
> > >  		/* DDI -> PLL mapping  */
> > >  		val = I915_READ(DPLL_CTRL2);
> > >  
> > > @@ -1763,7 +1777,10 @@ static void intel_ddi_post_disable(struct
> > > intel_encoder *intel_encoder,
> > >  	if (dig_port)
> > >  		intel_display_power_put(dev_priv, dig_port-
> > > > ddi_io_power_domain);
> > > 
> > >  
> > > -	if (IS_GEN9_BC(dev_priv))
> > > +	if (IS_CANNONLAKE(dev_priv))
> > > +		I915_WRITE(DPCLKA_CFGCR0, I915_READ(DPCLKA_CFGCR0) |
> > > +			   DPCLKA_CFGCR0_DDI_CLK_OFF(port));
> > > +	else if (IS_GEN9_BC(dev_priv))
> > >  		I915_WRITE(DPLL_CTRL2, (I915_READ(DPLL_CTRL2) |
> > >  					DPLL_CTRL2_DDI_CLK_OFF(port)
> > > ));
> > >  	else if (INTEL_GEN(dev_priv) < 9)
> > 
> > _______________________________________________
> > Intel-gfx mailing list
> > Intel-gfx@lists.freedesktop.org
> > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
> _______________________________________________
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> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
Ville Syrjälä
Intel OTC
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Re: [PATCH 32/67] drm/i915/cnl: DDI - PLL mapping

[Maarten Lankhorst]

Op 04-05-17 om 14:44 schreef Ville Syrjälä:
> On Thu, May 04, 2017 at 03:35:51PM +0300, Ander Conselvan De Oliveira wrote:
>> On Fri, 2017-04-07 at 18:12 -0300, Paulo Zanoni wrote:
>>> Em Qui, 2017-04-06 às 12:15 -0700, Rodrigo Vivi escreveu:
>>>> One of the steps for PLL (un)initialization is to (un)map
>>>> the correspondent DDI that is actually using that PLL.
>>>>
>>>> So, let's do this step following the places already stablished
>>>> and used so far, although spec put this as part of PLL
>>>> initialization sequences.
>>>>
>>>> v2: Use proper prefix on bits names as suggested by Ander.
>>>> v3: Add missed "~". Without that the logic was inverted
>>>>     so we were disabling interrupts.
>>>>     Credits-to: Clinton
>>>>     Credits-to: Art
>>>> v4: Spec is getting updated to do DDI -> PLL mapping
>>>>     and clock on in 2 separated reg writes. (Paulo)
>>>>     Also update bits definitions to use space
>>>>     (1 << 1) instead of (1<<1). (Paulo)
>>>>
>>>> Cc: Paulo Zanoni <paulo.r.zanoni@intel.com>
>>>> Cc: Art Runyan <arthur.j.runyan@intel.com>
>>>> Cc: Clint Taylor <clinton.a.taylor@intel.com>
>>>> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
>>>> Cc: Kahola, Mika <mika.kahola@intel.com>
>>>> Cc: Ander Conselvan De Oliveira <ander.conselvan.de.oliveira@intel.co
>>>> m>
>>>> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
>>>> Reviewed-by: Kahola, Mika <mika.kahola@intel.com>
>>>> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
>>>> ---
>>>>  drivers/gpu/drm/i915/i915_reg.h  |  9 +++++++++
>>>>  drivers/gpu/drm/i915/intel_ddi.c | 23 ++++++++++++++++++++---
>>>>  2 files changed, 29 insertions(+), 3 deletions(-)
>>>>
>>>> diff --git a/drivers/gpu/drm/i915/i915_reg.h
>>>> b/drivers/gpu/drm/i915/i915_reg.h
>>>> index 3cfc65f..dcb8e21 100644
>>>> --- a/drivers/gpu/drm/i915/i915_reg.h
>>>> +++ b/drivers/gpu/drm/i915/i915_reg.h
>>>> @@ -8150,6 +8150,15 @@ enum {
>>>>  #define DPLL_CFGCR1(id)	_MMIO_PIPE((id) - SKL_DPLL1,
>>>> _DPLL1_CFGCR1, _DPLL2_CFGCR1)
>>>>  #define DPLL_CFGCR2(id)	_MMIO_PIPE((id) - SKL_DPLL1,
>>>> _DPLL1_CFGCR2, _DPLL2_CFGCR2)
>>>>  
>>>> +/*
>>>> + * CNL Clocks
>>>> + */
>>>> +#define DPCLKA_CFGCR0				_MMIO(0x6C200)
>>>> +#define  DPCLKA_CFGCR0_DDI_CLK_OFF(port)	(1 << ((port)+10))
>>>> +#define  DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(port)	(3 <<
>>>> ((port)*2))
>>>> +#define  DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(port)	((port)*2)
>>>> +#define  DPCLKA_CFGCR0_DDI_CLK_SEL(pll, port)	((pll) <<
>>>> ((port)*2))
>>>> +
>>>>  /* BXT display engine PLL */
>>>>  #define BXT_DE_PLL_CTL			_MMIO(0x6d000)
>>>>  #define   BXT_DE_PLL_RATIO(x)		(x)	/*
>>>> {60,65,100} * 19.2MHz */
>>>> diff --git a/drivers/gpu/drm/i915/intel_ddi.c
>>>> b/drivers/gpu/drm/i915/intel_ddi.c
>>>> index 0914ad9..2a901bf 100644
>>>> --- a/drivers/gpu/drm/i915/intel_ddi.c
>>>> +++ b/drivers/gpu/drm/i915/intel_ddi.c
>>>> @@ -1621,13 +1621,27 @@ static void intel_ddi_clk_select(struct
>>>> intel_encoder *encoder,
>>>>  {
>>>>  	struct drm_i915_private *dev_priv = to_i915(encoder-
>>>>> base.dev);
>>>>  	enum port port = intel_ddi_get_encoder_port(encoder);
>>>> +	uint32_t val;
>>>>  
>>>>  	if (WARN_ON(!pll))
>>>>  		return;
>>>>  
>>>> -	if (IS_GEN9_BC(dev_priv)) {
>>>> -		uint32_t val;
>>>> +	if (IS_CANNONLAKE(dev_priv)) {
>>>> +		/* Configure DPCLKA_CFGCR0 to map the DPLL to the
>>>> DDI. */
>>>> +		val = I915_READ(DPCLKA_CFGCR0);
>>>> +		val |= DPCLKA_CFGCR0_DDI_CLK_SEL(pll->id, port);
>>>> +		I915_WRITE(DPCLKA_CFGCR0, val);
>>> A question to the Atomic Lords: don't we need some sort of locking
>>> around this register since it's used by all ports/clocks? I suppose
>>> dev_priv->dpll_lock would do...
>>>
>>> Maybe the same would apply for gen9_bc.
>> If there are modesets happening in parallel for different crtcs, then some
>> locking is needed. dpll_lock seems like the right call, that's what's used to
>> avoid the same problem with the enable/disable hooks.
> If something is allowing modesets to commit in parallel then probably
> the whole world is on fire. Historically connection_mutex has been there
> to protect us, but not sure how that goes with nonblocking commits. I
> do hope there's still something there to prevents this...

During nonblocking modesets we don't hold any locks. It's still possible
that we force serialization through some other means, for example grabbing
all crtc_states might force serialization previously. But I'm not sure this
is guaranteed to happen even for SKL. It might happen for when DDB
allocation or cdclk changes but there's no guarantee during modeset.

So quite likely you'll need locking here. :)

~Maarten

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Re: [PATCH 32/67] drm/i915/cnl: DDI - PLL mapping

[Ville Syrjälä]

On Thu, May 04, 2017 at 03:02:07PM +0200, Maarten Lankhorst wrote:
> Op 04-05-17 om 14:44 schreef Ville Syrjälä:
> > On Thu, May 04, 2017 at 03:35:51PM +0300, Ander Conselvan De Oliveira wrote:
> >> On Fri, 2017-04-07 at 18:12 -0300, Paulo Zanoni wrote:
> >>> Em Qui, 2017-04-06 às 12:15 -0700, Rodrigo Vivi escreveu:
> >>>> One of the steps for PLL (un)initialization is to (un)map
> >>>> the correspondent DDI that is actually using that PLL.
> >>>>
> >>>> So, let's do this step following the places already stablished
> >>>> and used so far, although spec put this as part of PLL
> >>>> initialization sequences.
> >>>>
> >>>> v2: Use proper prefix on bits names as suggested by Ander.
> >>>> v3: Add missed "~". Without that the logic was inverted
> >>>>     so we were disabling interrupts.
> >>>>     Credits-to: Clinton
> >>>>     Credits-to: Art
> >>>> v4: Spec is getting updated to do DDI -> PLL mapping
> >>>>     and clock on in 2 separated reg writes. (Paulo)
> >>>>     Also update bits definitions to use space
> >>>>     (1 << 1) instead of (1<<1). (Paulo)
> >>>>
> >>>> Cc: Paulo Zanoni <paulo.r.zanoni@intel.com>
> >>>> Cc: Art Runyan <arthur.j.runyan@intel.com>
> >>>> Cc: Clint Taylor <clinton.a.taylor@intel.com>
> >>>> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> >>>> Cc: Kahola, Mika <mika.kahola@intel.com>
> >>>> Cc: Ander Conselvan De Oliveira <ander.conselvan.de.oliveira@intel.co
> >>>> m>
> >>>> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
> >>>> Reviewed-by: Kahola, Mika <mika.kahola@intel.com>
> >>>> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
> >>>> ---
> >>>>  drivers/gpu/drm/i915/i915_reg.h  |  9 +++++++++
> >>>>  drivers/gpu/drm/i915/intel_ddi.c | 23 ++++++++++++++++++++---
> >>>>  2 files changed, 29 insertions(+), 3 deletions(-)
> >>>>
> >>>> diff --git a/drivers/gpu/drm/i915/i915_reg.h
> >>>> b/drivers/gpu/drm/i915/i915_reg.h
> >>>> index 3cfc65f..dcb8e21 100644
> >>>> --- a/drivers/gpu/drm/i915/i915_reg.h
> >>>> +++ b/drivers/gpu/drm/i915/i915_reg.h
> >>>> @@ -8150,6 +8150,15 @@ enum {
> >>>>  #define DPLL_CFGCR1(id)	_MMIO_PIPE((id) - SKL_DPLL1,
> >>>> _DPLL1_CFGCR1, _DPLL2_CFGCR1)
> >>>>  #define DPLL_CFGCR2(id)	_MMIO_PIPE((id) - SKL_DPLL1,
> >>>> _DPLL1_CFGCR2, _DPLL2_CFGCR2)
> >>>>  
> >>>> +/*
> >>>> + * CNL Clocks
> >>>> + */
> >>>> +#define DPCLKA_CFGCR0				_MMIO(0x6C200)
> >>>> +#define  DPCLKA_CFGCR0_DDI_CLK_OFF(port)	(1 << ((port)+10))
> >>>> +#define  DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(port)	(3 <<
> >>>> ((port)*2))
> >>>> +#define  DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(port)	((port)*2)
> >>>> +#define  DPCLKA_CFGCR0_DDI_CLK_SEL(pll, port)	((pll) <<
> >>>> ((port)*2))
> >>>> +
> >>>>  /* BXT display engine PLL */
> >>>>  #define BXT_DE_PLL_CTL			_MMIO(0x6d000)
> >>>>  #define   BXT_DE_PLL_RATIO(x)		(x)	/*
> >>>> {60,65,100} * 19.2MHz */
> >>>> diff --git a/drivers/gpu/drm/i915/intel_ddi.c
> >>>> b/drivers/gpu/drm/i915/intel_ddi.c
> >>>> index 0914ad9..2a901bf 100644
> >>>> --- a/drivers/gpu/drm/i915/intel_ddi.c
> >>>> +++ b/drivers/gpu/drm/i915/intel_ddi.c
> >>>> @@ -1621,13 +1621,27 @@ static void intel_ddi_clk_select(struct
> >>>> intel_encoder *encoder,
> >>>>  {
> >>>>  	struct drm_i915_private *dev_priv = to_i915(encoder-
> >>>>> base.dev);
> >>>>  	enum port port = intel_ddi_get_encoder_port(encoder);
> >>>> +	uint32_t val;
> >>>>  
> >>>>  	if (WARN_ON(!pll))
> >>>>  		return;
> >>>>  
> >>>> -	if (IS_GEN9_BC(dev_priv)) {
> >>>> -		uint32_t val;
> >>>> +	if (IS_CANNONLAKE(dev_priv)) {
> >>>> +		/* Configure DPCLKA_CFGCR0 to map the DPLL to the
> >>>> DDI. */
> >>>> +		val = I915_READ(DPCLKA_CFGCR0);
> >>>> +		val |= DPCLKA_CFGCR0_DDI_CLK_SEL(pll->id, port);
> >>>> +		I915_WRITE(DPCLKA_CFGCR0, val);
> >>> A question to the Atomic Lords: don't we need some sort of locking
> >>> around this register since it's used by all ports/clocks? I suppose
> >>> dev_priv->dpll_lock would do...
> >>>
> >>> Maybe the same would apply for gen9_bc.
> >> If there are modesets happening in parallel for different crtcs, then some
> >> locking is needed. dpll_lock seems like the right call, that's what's used to
> >> avoid the same problem with the enable/disable hooks.
> > If something is allowing modesets to commit in parallel then probably
> > the whole world is on fire. Historically connection_mutex has been there
> > to protect us, but not sure how that goes with nonblocking commits. I
> > do hope there's still something there to prevents this...
> 
> During nonblocking modesets we don't hold any locks. It's still possible
> that we force serialization through some other means, for example grabbing
> all crtc_states might force serialization previously. But I'm not sure this
> is guaranteed to happen even for SKL. It might happen for when DDB
> allocation or cdclk changes but there's no guarantee during modeset.
> 
> So quite likely you'll need locking here. :)

Someone just need to fix things so that modesets are always serialized.
I don't think anyone has actually reviewd the entire driver sufficiently
to allow parallel modesets.

-- 
Ville Syrjälä
Intel OTC
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Re: [PATCH 32/67] drm/i915/cnl: DDI - PLL mapping

[Vivi, Rodrigo]

On Thu, 2017-05-04 at 16:11 +0300, Ville Syrjälä wrote:
> On Thu, May 04, 2017 at 03:02:07PM +0200, Maarten Lankhorst wrote:
> > Op 04-05-17 om 14:44 schreef Ville Syrjälä:
> > > On Thu, May 04, 2017 at 03:35:51PM +0300, Ander Conselvan De Oliveira wrote:
> > >> On Fri, 2017-04-07 at 18:12 -0300, Paulo Zanoni wrote:
> > >>> Em Qui, 2017-04-06 às 12:15 -0700, Rodrigo Vivi escreveu:
> > >>>> One of the steps for PLL (un)initialization is to (un)map
> > >>>> the correspondent DDI that is actually using that PLL.
> > >>>>
> > >>>> So, let's do this step following the places already stablished
> > >>>> and used so far, although spec put this as part of PLL
> > >>>> initialization sequences.
> > >>>>
> > >>>> v2: Use proper prefix on bits names as suggested by Ander.
> > >>>> v3: Add missed "~". Without that the logic was inverted
> > >>>>     so we were disabling interrupts.
> > >>>>     Credits-to: Clinton
> > >>>>     Credits-to: Art
> > >>>> v4: Spec is getting updated to do DDI -> PLL mapping
> > >>>>     and clock on in 2 separated reg writes. (Paulo)
> > >>>>     Also update bits definitions to use space
> > >>>>     (1 << 1) instead of (1<<1). (Paulo)
> > >>>>
> > >>>> Cc: Paulo Zanoni <paulo.r.zanoni@intel.com>
> > >>>> Cc: Art Runyan <arthur.j.runyan@intel.com>
> > >>>> Cc: Clint Taylor <clinton.a.taylor@intel.com>
> > >>>> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > >>>> Cc: Kahola, Mika <mika.kahola@intel.com>
> > >>>> Cc: Ander Conselvan De Oliveira <ander.conselvan.de.oliveira@intel.co
> > >>>> m>
> > >>>> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
> > >>>> Reviewed-by: Kahola, Mika <mika.kahola@intel.com>
> > >>>> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
> > >>>> ---
> > >>>>  drivers/gpu/drm/i915/i915_reg.h  |  9 +++++++++
> > >>>>  drivers/gpu/drm/i915/intel_ddi.c | 23 ++++++++++++++++++++---
> > >>>>  2 files changed, 29 insertions(+), 3 deletions(-)
> > >>>>
> > >>>> diff --git a/drivers/gpu/drm/i915/i915_reg.h
> > >>>> b/drivers/gpu/drm/i915/i915_reg.h
> > >>>> index 3cfc65f..dcb8e21 100644
> > >>>> --- a/drivers/gpu/drm/i915/i915_reg.h
> > >>>> +++ b/drivers/gpu/drm/i915/i915_reg.h
> > >>>> @@ -8150,6 +8150,15 @@ enum {
> > >>>>  #define DPLL_CFGCR1(id)	_MMIO_PIPE((id) - SKL_DPLL1,
> > >>>> _DPLL1_CFGCR1, _DPLL2_CFGCR1)
> > >>>>  #define DPLL_CFGCR2(id)	_MMIO_PIPE((id) - SKL_DPLL1,
> > >>>> _DPLL1_CFGCR2, _DPLL2_CFGCR2)
> > >>>>  
> > >>>> +/*
> > >>>> + * CNL Clocks
> > >>>> + */
> > >>>> +#define DPCLKA_CFGCR0				_MMIO(0x6C200)
> > >>>> +#define  DPCLKA_CFGCR0_DDI_CLK_OFF(port)	(1 << ((port)+10))
> > >>>> +#define  DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(port)	(3 <<
> > >>>> ((port)*2))
> > >>>> +#define  DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(port)	((port)*2)
> > >>>> +#define  DPCLKA_CFGCR0_DDI_CLK_SEL(pll, port)	((pll) <<
> > >>>> ((port)*2))
> > >>>> +
> > >>>>  /* BXT display engine PLL */
> > >>>>  #define BXT_DE_PLL_CTL			_MMIO(0x6d000)
> > >>>>  #define   BXT_DE_PLL_RATIO(x)		(x)	/*
> > >>>> {60,65,100} * 19.2MHz */
> > >>>> diff --git a/drivers/gpu/drm/i915/intel_ddi.c
> > >>>> b/drivers/gpu/drm/i915/intel_ddi.c
> > >>>> index 0914ad9..2a901bf 100644
> > >>>> --- a/drivers/gpu/drm/i915/intel_ddi.c
> > >>>> +++ b/drivers/gpu/drm/i915/intel_ddi.c
> > >>>> @@ -1621,13 +1621,27 @@ static void intel_ddi_clk_select(struct
> > >>>> intel_encoder *encoder,
> > >>>>  {
> > >>>>  	struct drm_i915_private *dev_priv = to_i915(encoder-
> > >>>>> base.dev);
> > >>>>  	enum port port = intel_ddi_get_encoder_port(encoder);
> > >>>> +	uint32_t val;
> > >>>>  
> > >>>>  	if (WARN_ON(!pll))
> > >>>>  		return;
> > >>>>  
> > >>>> -	if (IS_GEN9_BC(dev_priv)) {
> > >>>> -		uint32_t val;
> > >>>> +	if (IS_CANNONLAKE(dev_priv)) {
> > >>>> +		/* Configure DPCLKA_CFGCR0 to map the DPLL to the
> > >>>> DDI. */
> > >>>> +		val = I915_READ(DPCLKA_CFGCR0);
> > >>>> +		val |= DPCLKA_CFGCR0_DDI_CLK_SEL(pll->id, port);
> > >>>> +		I915_WRITE(DPCLKA_CFGCR0, val);
> > >>> A question to the Atomic Lords: don't we need some sort of locking
> > >>> around this register since it's used by all ports/clocks? I suppose
> > >>> dev_priv->dpll_lock would do...
> > >>>
> > >>> Maybe the same would apply for gen9_bc.
> > >> If there are modesets happening in parallel for different crtcs, then some
> > >> locking is needed. dpll_lock seems like the right call, that's what's used to
> > >> avoid the same problem with the enable/disable hooks.
> > > If something is allowing modesets to commit in parallel then probably
> > > the whole world is on fire. Historically connection_mutex has been there
> > > to protect us, but not sure how that goes with nonblocking commits. I
> > > do hope there's still something there to prevents this...
> > 
> > During nonblocking modesets we don't hold any locks. It's still possible
> > that we force serialization through some other means, for example grabbing
> > all crtc_states might force serialization previously. But I'm not sure this
> > is guaranteed to happen even for SKL. It might happen for when DDB
> > allocation or cdclk changes but there's no guarantee during modeset.
> > 
> > So quite likely you'll need locking here. :)
> 
> Someone just need to fix things so that modesets are always serialized.
> I don't think anyone has actually reviewd the entire driver sufficiently
> to allow parallel modesets.

Besides, the structure itself just follows previous platforms. If there
is something wrong it would affect all current platforms I'm afraid. 


> 

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Re: [PATCH 32/67] drm/i915/cnl: DDI - PLL mapping

[Ander Conselvan De Oliveira]

On Thu, 2017-04-06 at 12:15 -0700, Rodrigo Vivi wrote:
> One of the steps for PLL (un)initialization is to (un)map
> the correspondent DDI that is actually using that PLL.
> 
> So, let's do this step following the places already stablished
> and used so far, although spec put this as part of PLL
> initialization sequences.
> 
> v2: Use proper prefix on bits names as suggested by Ander.
> v3: Add missed "~". Without that the logic was inverted
>     so we were disabling interrupts.
>     Credits-to: Clinton
>     Credits-to: Art
> v4: Spec is getting updated to do DDI -> PLL mapping
>     and clock on in 2 separated reg writes. (Paulo)
>     Also update bits definitions to use space
>     (1 << 1) instead of (1<<1). (Paulo)
> 
> Cc: Paulo Zanoni <paulo.r.zanoni@intel.com>
> Cc: Art Runyan <arthur.j.runyan@intel.com>
> Cc: Clint Taylor <clinton.a.taylor@intel.com>
> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> Cc: Kahola, Mika <mika.kahola@intel.com>
> Cc: Ander Conselvan De Oliveira <ander.conselvan.de.oliveira@intel.com>
> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
> Reviewed-by: Kahola, Mika <mika.kahola@intel.com>
> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
> ---
>  drivers/gpu/drm/i915/i915_reg.h  |  9 +++++++++
>  drivers/gpu/drm/i915/intel_ddi.c | 23 ++++++++++++++++++++---
>  2 files changed, 29 insertions(+), 3 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 3cfc65f..dcb8e21 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -8150,6 +8150,15 @@ enum {
>  #define DPLL_CFGCR1(id)	_MMIO_PIPE((id) - SKL_DPLL1, _DPLL1_CFGCR1, _DPLL2_CFGCR1)
>  #define DPLL_CFGCR2(id)	_MMIO_PIPE((id) - SKL_DPLL1, _DPLL1_CFGCR2, _DPLL2_CFGCR2)
>  
> +/*
> + * CNL Clocks
> + */
> +#define DPCLKA_CFGCR0				_MMIO(0x6C200)
> +#define  DPCLKA_CFGCR0_DDI_CLK_OFF(port)	(1 << ((port)+10))
> +#define  DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(port)	(3 << ((port)*2))
> +#define  DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(port)	((port)*2)
> +#define  DPCLKA_CFGCR0_DDI_CLK_SEL(pll, port)	((pll) << ((port)*2))
> +
>  /* BXT display engine PLL */
>  #define BXT_DE_PLL_CTL			_MMIO(0x6d000)
>  #define   BXT_DE_PLL_RATIO(x)		(x)	/* {60,65,100} * 19.2MHz */
> diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
> index 0914ad9..2a901bf 100644
> --- a/drivers/gpu/drm/i915/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/intel_ddi.c
> @@ -1621,13 +1621,27 @@ static void intel_ddi_clk_select(struct intel_encoder *encoder,
>  {
>  	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
>  	enum port port = intel_ddi_get_encoder_port(encoder);
> +	uint32_t val;
>  
>  	if (WARN_ON(!pll))
>  		return;
>  
> -	if (IS_GEN9_BC(dev_priv)) {
> -		uint32_t val;
> +	if (IS_CANNONLAKE(dev_priv)) {
> +		/* Configure DPCLKA_CFGCR0 to map the DPLL to the DDI. */
> +		val = I915_READ(DPCLKA_CFGCR0);
> +		val |= DPCLKA_CFGCR0_DDI_CLK_SEL(pll->id, port);
> +		I915_WRITE(DPCLKA_CFGCR0, val);
>  
> +		/*
> +		 * Configure DPCLKA_CFGCR0 to turn on the clock for the DDI.
> +		 * This step and the step before must be done with separate
> +		 * register writes.
> +		 */
> +		val = I915_READ(DPCLKA_CFGCR0);
> +		val &= ~(DPCLKA_CFGCR0_DDI_CLK_OFF(port) |
> +			 DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(port));

		val |= DPCLKA_CFGCR0_DDI_CLK_SEL(pll->id, port); ?

Or clearing the clock select to zero has no effect here?

Ander

> +		I915_WRITE(DPCLKA_CFGCR0, val);
> +	} else if (IS_GEN9_BC(dev_priv)) {
>  		/* DDI -> PLL mapping  */
>  		val = I915_READ(DPLL_CTRL2);
>  
> @@ -1763,7 +1777,10 @@ static void intel_ddi_post_disable(struct intel_encoder *intel_encoder,
>  	if (dig_port)
>  		intel_display_power_put(dev_priv, dig_port->ddi_io_power_domain);
>  
> -	if (IS_GEN9_BC(dev_priv))
> +	if (IS_CANNONLAKE(dev_priv))
> +		I915_WRITE(DPCLKA_CFGCR0, I915_READ(DPCLKA_CFGCR0) |
> +			   DPCLKA_CFGCR0_DDI_CLK_OFF(port));
> +	else if (IS_GEN9_BC(dev_priv))
>  		I915_WRITE(DPLL_CTRL2, (I915_READ(DPLL_CTRL2) |
>  					DPLL_CTRL2_DDI_CLK_OFF(port)));
>  	else if (INTEL_GEN(dev_priv) < 9)
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[PATCH 33/67] drm/i915: Configure DPLL's for Cannonlake

[Rodrigo Vivi]

From: "Kahola, Mika" <mika.kahola@intel.com>

DPLL's are defined in DPCLKA_CFGCR0 register (0x6C200). Let's use these
definitions when computing dpll's for ddi ports.

v2: (Rodrigo) Remove register that was defined in another patch with
    fixed name and more bits.

Signed-off-by: Kahola, Mika <mika.kahola@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
---
 drivers/gpu/drm/i915/intel_display.c | 20 +++++++++++++++++++-
 1 file changed, 19 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 87d2822..4d0ae98 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -8850,6 +8850,22 @@ static int haswell_crtc_compute_clock(struct intel_crtc *crtc,
 	return 0;
 }
 
+static void cannonlake_get_ddi_pll(struct drm_i915_private *dev_priv,
+				   enum port port,
+				   struct intel_crtc_state *pipe_config)
+{
+	enum intel_dpll_id id;
+	u32 temp;
+
+	temp = I915_READ(DPCLKA_CFGCR0) & DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(port);
+	id = temp >> (port * 2);
+
+	if (WARN_ON(id < SKL_DPLL0 || id > SKL_DPLL2))
+		return;
+
+	pipe_config->shared_dpll = intel_get_shared_dpll_by_id(dev_priv, id);
+}
+
 static void bxt_get_ddi_pll(struct drm_i915_private *dev_priv,
 				enum port port,
 				struct intel_crtc_state *pipe_config)
@@ -9037,7 +9053,9 @@ static void haswell_get_ddi_port_state(struct intel_crtc *crtc,
 
 	port = (tmp & TRANS_DDI_PORT_MASK) >> TRANS_DDI_PORT_SHIFT;
 
-	if (IS_GEN9_BC(dev_priv))
+	if (IS_CANNONLAKE(dev_priv))
+		cannonlake_get_ddi_pll(dev_priv, port, pipe_config);
+	else if (IS_GEN9_BC(dev_priv))
 		skylake_get_ddi_pll(dev_priv, port, pipe_config);
 	else if (IS_GEN9_LP(dev_priv))
 		bxt_get_ddi_pll(dev_priv, port, pipe_config);
-- 
1.9.1

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Re: [PATCH 33/67] drm/i915: Configure DPLL's for Cannonlake

[Ander Conselvan De Oliveira]

On Thu, 2017-04-06 at 12:15 -0700, Rodrigo Vivi wrote:
> From: "Kahola, Mika" <mika.kahola@intel.com>
> 
> DPLL's are defined in DPCLKA_CFGCR0 register (0x6C200). Let's use these
> definitions when computing dpll's for ddi ports.
> 
> v2: (Rodrigo) Remove register that was defined in another patch with
>     fixed name and more bits.
> 
> Signed-off-by: Kahola, Mika <mika.kahola@intel.com>
> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
> ---
>  drivers/gpu/drm/i915/intel_display.c | 20 +++++++++++++++++++-
>  1 file changed, 19 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index 87d2822..4d0ae98 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -8850,6 +8850,22 @@ static int haswell_crtc_compute_clock(struct intel_crtc *crtc,
>  	return 0;
>  }
>  
> +static void cannonlake_get_ddi_pll(struct drm_i915_private *dev_priv,
> +				   enum port port,
> +				   struct intel_crtc_state *pipe_config)
> +{
> +	enum intel_dpll_id id;
> +	u32 temp;
> +
> +	temp = I915_READ(DPCLKA_CFGCR0) & DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(port);
> +	id = temp >> (port * 2);

Maybe use DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT which was defined in the previous
patch?

Also, might make sense to squash this with the next patch, but anyway,

Reviewed-by: Ander Conselvan de Oliveira <conselvan2@gmail.com>


> +
> +	if (WARN_ON(id < SKL_DPLL0 || id > SKL_DPLL2))
> +		return;
> +
> +	pipe_config->shared_dpll = intel_get_shared_dpll_by_id(dev_priv, id);
> +}
> +
>  static void bxt_get_ddi_pll(struct drm_i915_private *dev_priv,
>  				enum port port,
>  				struct intel_crtc_state *pipe_config)
> @@ -9037,7 +9053,9 @@ static void haswell_get_ddi_port_state(struct intel_crtc *crtc,
>  
>  	port = (tmp & TRANS_DDI_PORT_MASK) >> TRANS_DDI_PORT_SHIFT;
>  
> -	if (IS_GEN9_BC(dev_priv))
> +	if (IS_CANNONLAKE(dev_priv))
> +		cannonlake_get_ddi_pll(dev_priv, port, pipe_config);
> +	else if (IS_GEN9_BC(dev_priv))
>  		skylake_get_ddi_pll(dev_priv, port, pipe_config);
>  	else if (IS_GEN9_LP(dev_priv))
>  		bxt_get_ddi_pll(dev_priv, port, pipe_config);
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[PATCH 34/67] drm/i915/cnl: Initialize PLLs

[Rodrigo Vivi]

Although CNL follows PLL initialization more like Skylake
than Broxton we have a completely different initialization
sequence and registers used.

One big difference from SKL is that CDCLK PLL is now
exclusive (ADPLL) and for DDIs and MIPI we need to use
DFGPLLs 0, 1 or 2.

v2: Accept all Ander's suggestions and fixes:
    - Registers and bits names prefix
    - Group pll functions
    - bits masks fixes
    - remove read and modify on cfgcr1
    - fix cfgcr0 setup
v3: Set SSC_ENABLE for DP.
    Fix HDMI_MODE cfgcr0.
    Avoid touch cfgcr0 on DP.
    Add missed else on dpll_mgr definition so we use cnl one, not hsw.
v3: Centra freq should be always set to default and change bits
    definitions to (1 << 1) instead of (1<<1). (by Paulo)

Cc: Paulo Zanoni <paulo.r.zanoni@intel.com>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Cc: Kahola, Mika <mika.kahola@intel.com>
Reviewed-by: Ander Conselvan De Oliveira <ander.conselvan.de.oliveira@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h       |  48 ++++++
 drivers/gpu/drm/i915/intel_dpll_mgr.c | 300 +++++++++++++++++++++++++++++++++-
 drivers/gpu/drm/i915/intel_dpll_mgr.h |   4 +
 3 files changed, 350 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index dcb8e21..c38c1fd 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -58,6 +58,8 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
 #define _MMIO_TRANS(tran, a, b) _MMIO(_TRANS(tran, a, b))
 #define _PORT(port, a, b) ((a) + (port)*((b)-(a)))
 #define _MMIO_PORT(port, a, b) _MMIO(_PORT(port, a, b))
+#define _PLL(pll, a, b) ((a) + (pll)*((b)-(a)))
+#define _MMIO_PLL(pll, a, b) _MMIO(_PLL(pll, a, b))
 #define _PIPE3(pipe, ...) _PICK(pipe, __VA_ARGS__)
 #define _MMIO_PIPE3(pipe, a, b, c) _MMIO(_PIPE3(pipe, a, b, c))
 #define _PORT3(port, ...) _PICK(port, __VA_ARGS__)
@@ -8159,6 +8161,52 @@ enum {
 #define  DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(port)	((port)*2)
 #define  DPCLKA_CFGCR0_DDI_CLK_SEL(pll, port)	((pll) << ((port)*2))
 
+/* CNL PLL */
+#define DPLL0_ENABLE		0x46010
+#define DPLL1_ENABLE		0x46014
+#define  PLL_ENABLE		(1 << 31)
+#define  PLL_LOCK		(1 << 30)
+#define  PLL_POWER_ENABLE	(1 << 27)
+#define  PLL_POWER_STATE	(1 << 26)
+#define CNL_DPLL_ENABLE(pll)	_MMIO_PLL(pll, DPLL0_ENABLE, DPLL1_ENABLE)
+
+#define _CNL_DPLL0_CFGCR0		0x6C000
+#define _CNL_DPLL1_CFGCR0		0x6C080
+#define  DPLL_CFGCR0_HDMI_MODE		(1 << 30)
+#define  DPLL_CFGCR0_SSC_ENABLE		(1 << 29)
+#define  DPLL_CFGCR0_LINK_RATE_MASK	(0xf << 25)
+#define  DPLL_CFGCR0_LINK_RATE_2700	(0 << 25)
+#define  DPLL_CFGCR0_LINK_RATE_1350	(1 << 25)
+#define  DPLL_CFGCR0_LINK_RATE_810	(2 << 25)
+#define  DPLL_CFGCR0_LINK_RATE_1620	(3 << 25)
+#define  DPLL_CFGCR0_LINK_RATE_1080	(4 << 25)
+#define  DPLL_CFGCR0_LINK_RATE_2160	(5 << 25)
+#define  DPLL_CFGCR0_LINK_RATE_3240	(6 << 25)
+#define  DPLL_CFGCR0_LINK_RATE_4050	(7 << 25)
+#define  DPLL_CFGCR0_DCO_FRACTION_MASK	(0x7fff << 10)
+#define  DPLL_CFGCR0_DCO_FRACTION(x)	((x) << 10)
+#define  DPLL_CFGCR0_DCO_INTEGER_MASK	(0x3ff)
+#define CNL_DPLL_CFGCR0(pll)		_MMIO_PLL(pll, _CNL_DPLL0_CFGCR0, _CNL_DPLL1_CFGCR0)
+
+#define _CNL_DPLL0_CFGCR1		0x6C004
+#define _CNL_DPLL1_CFGCR1		0x6C084
+#define  DPLL_CFGCR1_QDIV_RATIO_MASK	(0xff << 10)
+#define  DPLL_CFGCR1_QDIV_RATIO(x)	((x) << 10)
+#define  DPLL_CFGCR1_QDIV_MODE(x)	((x) << 9)
+#define  DPLL_CFGCR1_KDIV_MASK		(7 << 6)
+#define  DPLL_CFGCR1_KDIV(x)		((x) << 6)
+#define  DPLL_CFGCR1_KDIV_1		(1 << 6)
+#define  DPLL_CFGCR1_KDIV_2		(2 << 6)
+#define  DPLL_CFGCR1_KDIV_4		(4 << 6)
+#define  DPLL_CFGCR1_PDIV_MASK		(0xf << 2)
+#define  DPLL_CFGCR1_PDIV(x)		((x) << 2)
+#define  DPLL_CFGCR1_PDIV_2		(1 << 2)
+#define  DPLL_CFGCR1_PDIV_3		(2 << 2)
+#define  DPLL_CFGCR1_PDIV_5		(4 << 2)
+#define  DPLL_CFGCR1_PDIV_7		(8 << 2)
+#define  DPLL_CFGCR1_CENTRAL_FREQ	(3 << 0)
+#define CNL_DPLL_CFGCR1(pll)		_MMIO_PLL(pll, _CNL_DPLL0_CFGCR1, _CNL_DPLL1_CFGCR1)
+
 /* BXT display engine PLL */
 #define BXT_DE_PLL_CTL			_MMIO(0x6d000)
 #define   BXT_DE_PLL_RATIO(x)		(x)	/* {60,65,100} * 19.2MHz */
diff --git a/drivers/gpu/drm/i915/intel_dpll_mgr.c b/drivers/gpu/drm/i915/intel_dpll_mgr.c
index b4de632..903c38d 100644
--- a/drivers/gpu/drm/i915/intel_dpll_mgr.c
+++ b/drivers/gpu/drm/i915/intel_dpll_mgr.c
@@ -1321,7 +1321,6 @@ static bool skl_ddi_hdmi_pll_dividers(struct intel_crtc *crtc,
 	return true;
 }
 
-
 static bool
 skl_ddi_dp_set_dpll_hw_state(int clock,
 			     struct intel_dpll_hw_state *dpll_hw_state)
@@ -1967,6 +1966,301 @@ struct intel_dpll_mgr {
 	.dump_hw_state = bxt_dump_hw_state,
 };
 
+static void cnl_ddi_pll_enable(struct drm_i915_private *dev_priv,
+			       struct intel_shared_dpll *pll)
+{
+	uint32_t val;
+
+	/* 1. Enable DPLL power in DPLL_ENABLE. */
+	val = I915_READ(CNL_DPLL_ENABLE(pll->id));
+	val |= PLL_POWER_ENABLE;
+	I915_WRITE(CNL_DPLL_ENABLE(pll->id), val);
+
+	/* 2. Wait for DPLL power state enabled in DPLL_ENABLE. */
+	if (intel_wait_for_register(dev_priv,
+				    CNL_DPLL_ENABLE(pll->id),
+				    PLL_POWER_STATE,
+				    PLL_POWER_STATE,
+				    5))
+		DRM_ERROR("PLL %d Power not enabled\n", pll->id);
+
+	/*
+	 * 3. Configure DPLL_CFGCR0 to set SSC enable/disable,
+	 * select DP mode, and set DP link rate.
+	 */
+	val = pll->state.hw_state.cfgcr0;
+	I915_WRITE(CNL_DPLL_CFGCR0(pll->id), val);
+
+	/* 4. Reab back to ensure writes completed */
+	POSTING_READ(CNL_DPLL_CFGCR0(pll->id));
+
+	/* 3. Configure DPLL_CFGCR0 */
+	/* Avoid touch CFGCR1 if HDMI mode is not enabled */
+	if (pll->state.hw_state.cfgcr0 & DPLL_CTRL1_HDMI_MODE(pll->id)) {
+		val = pll->state.hw_state.cfgcr1;
+		I915_WRITE(CNL_DPLL_CFGCR1(pll->id), val);
+		/* 4. Reab back to ensure writes completed */
+		POSTING_READ(CNL_DPLL_CFGCR1(pll->id));
+	}
+
+	/*
+	 * 5. If the frequency will result in a change to the voltage
+	 * requirement, follow the Display Voltage Frequency Switching
+	 * Sequence Before Frequency Change
+	 *
+	 * FIXME: (DVFS) is used to adjust the display voltage to match the
+	 * display clock frequencies
+	 */
+
+	/* 6. Enable DPLL in DPLL_ENABLE. */
+	val = I915_READ(CNL_DPLL_ENABLE(pll->id));
+	val |= PLL_ENABLE;
+	I915_WRITE(CNL_DPLL_ENABLE(pll->id), val);
+
+	/* 7. Wait for PLL lock status in DPLL_ENABLE. */
+	if (intel_wait_for_register(dev_priv,
+				    CNL_DPLL_ENABLE(pll->id),
+				    PLL_LOCK,
+				    PLL_LOCK,
+				    5))
+		DRM_ERROR("PLL %d not locked\n", pll->id);
+
+	/*
+	 * 8. If the frequency will result in a change to the voltage
+	 * requirement, follow the Display Voltage Frequency Switching
+	 * Sequence After Frequency Change
+	 *
+	 * FIXME: (DVFS) is used to adjust the display voltage to match the
+	 * display clock frequencies
+	 */
+
+	/*
+	 * 9. turn on the clock for the DDI and map the DPLL to the DDI
+	 * Done at intel_ddi_clk_select
+	 */
+}
+
+static void cnl_ddi_pll_disable(struct drm_i915_private *dev_priv,
+				struct intel_shared_dpll *pll)
+{
+	uint32_t val;
+
+	/*
+	 * 1. Configure DPCLKA_CFGCR0 to turn off the clock for the DDI.
+	 * Done at intel_ddi_post_disable
+	 */
+
+	/*
+	 * 2. If the frequency will result in a change to the voltage
+	 * requirement, follow the Display Voltage Frequency Switching
+	 * Sequence Before Frequency Change
+	 *
+	 * FIXME: (DVFS) is used to adjust the display voltage to match the
+	 * display clock frequencies
+	 */
+
+	/* 3. Disable DPLL through DPLL_ENABLE. */
+	val = I915_READ(CNL_DPLL_ENABLE(pll->id));
+	val &= ~PLL_ENABLE;
+	I915_WRITE(CNL_DPLL_ENABLE(pll->id), val);
+
+	/* 4. Wait for PLL not locked status in DPLL_ENABLE. */
+	if (intel_wait_for_register(dev_priv,
+				    CNL_DPLL_ENABLE(pll->id),
+				    PLL_LOCK,
+				    0,
+				    5))
+		DRM_ERROR("PLL %d locked\n", pll->id);
+
+	/*
+	 * 5. If the frequency will result in a change to the voltage
+	 * requirement, follow the Display Voltage Frequency Switching
+	 * Sequence After Frequency Change
+	 *
+	 * FIXME: (DVFS) is used to adjust the display voltage to match the
+	 * display clock frequencies
+	 */
+
+	/* 6. Disable DPLL power in DPLL_ENABLE. */
+	val = I915_READ(CNL_DPLL_ENABLE(pll->id));
+	val &= ~PLL_POWER_ENABLE;
+	I915_WRITE(CNL_DPLL_ENABLE(pll->id), val);
+
+	/* 7. Wait for DPLL power state disabled in DPLL_ENABLE. */
+	if (intel_wait_for_register(dev_priv,
+				    CNL_DPLL_ENABLE(pll->id),
+				    PLL_POWER_STATE,
+				    0,
+				    5))
+		DRM_ERROR("PLL %d Power not disabled\n", pll->id);
+}
+
+static bool cnl_ddi_pll_get_hw_state(struct drm_i915_private *dev_priv,
+				     struct intel_shared_dpll *pll,
+				     struct intel_dpll_hw_state *hw_state)
+{
+	uint32_t val;
+	bool ret;
+
+	if (!intel_display_power_get_if_enabled(dev_priv, POWER_DOMAIN_PLLS))
+		return false;
+
+	ret = false;
+
+	val = I915_READ(CNL_DPLL_ENABLE(pll->id));
+	if (!(val & PLL_ENABLE))
+		goto out;
+
+	val = I915_READ(CNL_DPLL_CFGCR0(pll->id));
+	hw_state->cfgcr0 = val;
+
+	/* avoid reading back stale values if HDMI mode is not enabled */
+	if (val & DPLL_CFGCR0_HDMI_MODE) {
+		hw_state->cfgcr1 = I915_READ(CNL_DPLL_CFGCR1(pll->id));
+	}
+	ret = true;
+
+out:
+	intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS);
+
+	return ret;
+}
+
+static bool cnl_ddi_hdmi_pll_dividers(struct intel_crtc *crtc,
+				      struct intel_crtc_state *crtc_state,
+				      int clock)
+{
+	uint32_t cfgcr0, cfgcr1;
+	struct skl_wrpll_params wrpll_params = { 0, };
+
+	cfgcr0 = DPLL_CFGCR0_HDMI_MODE;
+
+	/* FIXME: Proper wrpll calculation done in a following patch */
+	return false;
+
+	cfgcr0 |= DPLL_CFGCR0_DCO_FRACTION(wrpll_params.dco_fraction) |
+		wrpll_params.dco_integer;
+
+	cfgcr1 = DPLL_CFGCR1_QDIV_RATIO(wrpll_params.qdiv_ratio) |
+		DPLL_CFGCR1_QDIV_MODE(wrpll_params.qdiv_mode) |
+		DPLL_CFGCR1_KDIV(wrpll_params.kdiv) |
+		DPLL_CFGCR1_PDIV(wrpll_params.pdiv) |
+		wrpll_params.central_freq |
+		DPLL_CFGCR1_CENTRAL_FREQ;
+
+	memset(&crtc_state->dpll_hw_state, 0,
+	       sizeof(crtc_state->dpll_hw_state));
+
+	crtc_state->dpll_hw_state.cfgcr0 = cfgcr0;
+	crtc_state->dpll_hw_state.cfgcr1 = cfgcr1;
+	return true;
+}
+
+bool cnl_ddi_dp_set_dpll_hw_state(int clock,
+				  struct intel_dpll_hw_state *dpll_hw_state)
+{
+	uint32_t cfgcr0;
+
+	cfgcr0 = DPLL_CFGCR0_SSC_ENABLE;
+
+	switch (clock / 2) {
+	case 81000:
+		cfgcr0 |= DPLL_CFGCR0_LINK_RATE_810;
+		break;
+	case 135000:
+		cfgcr0 |= DPLL_CFGCR0_LINK_RATE_1350;
+		break;
+	case 270000:
+		cfgcr0 |= DPLL_CFGCR0_LINK_RATE_2700;
+		break;
+		/* eDP 1.4 rates */
+	case 162000:
+		cfgcr0 |= DPLL_CFGCR0_LINK_RATE_1620;
+		break;
+	case 108000:
+		cfgcr0 |= DPLL_CFGCR0_LINK_RATE_1080;
+		break;
+	case 216000:
+		cfgcr0 |= DPLL_CFGCR0_LINK_RATE_2160;
+		break;
+	case 324000:
+		/* Some SKUs may require elevated I/O voltage to support this */
+		cfgcr0 |= DPLL_CFGCR0_LINK_RATE_3240;
+		break;
+	case 405000:
+		/* Some SKUs may require elevated I/O voltage to support this */
+		cfgcr0 |= DPLL_CFGCR0_LINK_RATE_4050;
+		break;
+	}
+
+	dpll_hw_state->cfgcr0 = cfgcr0;
+	return true;
+}
+
+static struct intel_shared_dpll *
+cnl_get_dpll(struct intel_crtc *crtc, struct intel_crtc_state *crtc_state,
+	     struct intel_encoder *encoder)
+{
+	struct intel_shared_dpll *pll;
+	int clock = crtc_state->port_clock;
+	bool bret;
+	struct intel_dpll_hw_state dpll_hw_state;
+
+	memset(&dpll_hw_state, 0, sizeof(dpll_hw_state));
+
+	if (encoder->type == INTEL_OUTPUT_HDMI) {
+		bret = cnl_ddi_hdmi_pll_dividers(crtc, crtc_state, clock);
+		if (!bret) {
+			DRM_DEBUG_KMS("Could not get HDMI pll dividers.\n");
+			return NULL;
+		}
+	} else if (encoder->type == INTEL_OUTPUT_DP ||
+		   encoder->type == INTEL_OUTPUT_DP_MST ||
+		   encoder->type == INTEL_OUTPUT_EDP) {
+		bret = cnl_ddi_dp_set_dpll_hw_state(clock, &dpll_hw_state);
+		if (!bret) {
+			DRM_DEBUG_KMS("Could not set DP dpll HW state.\n");
+			return NULL;
+		}
+		crtc_state->dpll_hw_state = dpll_hw_state;
+	} else {
+		DRM_DEBUG_KMS("Skip DPLL setup for encoder %d\n",
+			      encoder->type);
+		return NULL;
+	}
+
+	pll = intel_find_shared_dpll(crtc, crtc_state,
+				     DPLL_ID_SKL_DPLL0,
+				     DPLL_ID_SKL_DPLL2);
+	if (!pll) {
+		DRM_DEBUG_KMS("No PLL selected\n");
+		return NULL;
+	}
+
+	intel_reference_shared_dpll(pll, crtc_state);
+
+	return pll;
+}
+
+static const struct intel_shared_dpll_funcs cnl_ddi_pll_funcs = {
+	.enable = cnl_ddi_pll_enable,
+	.disable = cnl_ddi_pll_disable,
+	.get_hw_state = cnl_ddi_pll_get_hw_state,
+};
+
+static const struct dpll_info cnl_plls[] = {
+	{ "DPLL 0", DPLL_ID_SKL_DPLL0, &cnl_ddi_pll_funcs, 0 },
+	{ "DPLL 1", DPLL_ID_SKL_DPLL1, &cnl_ddi_pll_funcs, 0 },
+	{ "DPLL 2", DPLL_ID_SKL_DPLL2, &cnl_ddi_pll_funcs, 0 },
+	{ NULL, -1, NULL, },
+};
+
+static const struct intel_dpll_mgr cnl_pll_mgr = {
+	.dpll_info = cnl_plls,
+	.get_dpll = cnl_get_dpll,
+	.dump_hw_state = skl_dump_hw_state,
+};
+
 /**
  * intel_shared_dpll_init - Initialize shared DPLLs
  * @dev: drm device
@@ -1980,7 +2274,9 @@ void intel_shared_dpll_init(struct drm_device *dev)
 	const struct dpll_info *dpll_info;
 	int i;
 
-	if (IS_GEN9_BC(dev_priv))
+	if (IS_CANNONLAKE(dev_priv))
+		dpll_mgr = &cnl_pll_mgr;
+	else if (IS_GEN9_BC(dev_priv))
 		dpll_mgr = &skl_pll_mgr;
 	else if (IS_GEN9_LP(dev_priv))
 		dpll_mgr = &bxt_pll_mgr;
diff --git a/drivers/gpu/drm/i915/intel_dpll_mgr.h b/drivers/gpu/drm/i915/intel_dpll_mgr.h
index f8d13a9..f24ccf4 100644
--- a/drivers/gpu/drm/i915/intel_dpll_mgr.h
+++ b/drivers/gpu/drm/i915/intel_dpll_mgr.h
@@ -128,6 +128,10 @@ struct intel_dpll_hw_state {
 	/* HDMI only, 0 when used for DP */
 	uint32_t cfgcr1, cfgcr2;
 
+	/* cnl */
+	uint32_t cfgcr0;
+	/* CNL also uses cfgcr1 */
+
 	/* bxt */
 	uint32_t ebb0, ebb4, pll0, pll1, pll2, pll3, pll6, pll8, pll9, pll10,
 		 pcsdw12;
-- 
1.9.1

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[PATCH 35/67] drm/i915/cnl: Enable wrpll computation for CNL

[Rodrigo Vivi]

From: "Kahola, Mika" <mika.kahola@intel.com>

Enable wrpll computation for Cannonlake platform to support
pll's required for HDMI output. The patch contains the following features

- compute Cannonlake port clock programming
  dividers P, Q, and K.
- compute PLL parameters for Cannonlake. These parameters
  set the values on DPLL registers.
- find the register values to program wrpll for Cannonlake.
  The reference clock can be either 19.2MHz or 24MHz.

v2: rebase
v3: squash wrpll patches into one (Rodrigo)
v4: switch order of getting even dividers (Paulo)
    update divider register values for PDiv and KDiv (Paulo)
    update wrpll computation algorithm (Paulo)
v5: Remove ref clock division by 1000. (Rodrigo)
v6: Rodrigo rebasing on top of latest code.

Signed-off-by: Kahola, Mika <mika.kahola@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
---
 drivers/gpu/drm/i915/intel_dpll_mgr.c | 140 +++++++++++++++++++++++++++++++++-
 1 file changed, 138 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_dpll_mgr.c b/drivers/gpu/drm/i915/intel_dpll_mgr.c
index 903c38d..8e669b6 100644
--- a/drivers/gpu/drm/i915/intel_dpll_mgr.c
+++ b/drivers/gpu/drm/i915/intel_dpll_mgr.c
@@ -2126,17 +2126,153 @@ static bool cnl_ddi_pll_get_hw_state(struct drm_i915_private *dev_priv,
 	return ret;
 }
 
+static void cnl_wrpll_get_multipliers(unsigned int bestdiv,
+				      unsigned int *pdiv,
+				      unsigned int *qdiv,
+				      unsigned int *kdiv)
+{
+	/* even dividers */
+	if (bestdiv % 2 == 0) {
+		if (bestdiv == 2) {
+			*pdiv = 2;
+			*qdiv = 1;
+			*kdiv = 1;
+		} else if (bestdiv % 4 == 0) {
+			*pdiv = 2;
+			*qdiv = bestdiv / 4;
+			*kdiv = 2;
+		} else if (bestdiv % 6 == 0) {
+			*pdiv = 3;
+			*qdiv = bestdiv / 6;
+			*kdiv = 2;
+		} else if (bestdiv % 5 == 0) {
+			*pdiv = 5;
+			*qdiv = bestdiv / 10;
+			*kdiv = 2;
+		} else if (bestdiv % 14 == 0) {
+			*pdiv = 7;
+			*qdiv = bestdiv / 14;
+			*kdiv = 2;
+		}
+	} else {
+		if (bestdiv == 3 || bestdiv == 5 || bestdiv == 7) {
+			*pdiv = bestdiv;
+			*qdiv = 1;
+			*kdiv = 1;
+		} else { /* 9, 15, 21 */
+			*pdiv = bestdiv / 3;
+			*qdiv = 1;
+			*kdiv = 3;
+		}
+	}
+}
+
+static void cnl_wrpll_params_populate(struct skl_wrpll_params *params, uint32_t dco_freq,
+				      uint32_t ref_freq, uint32_t pdiv, uint32_t qdiv,
+				      uint32_t kdiv)
+{
+	switch (kdiv) {
+	case 1:
+		params->kdiv = 1;
+		break;
+	case 2:
+		params->kdiv = 2;
+		break;
+	case 3:
+		params->kdiv = 4;
+		break;
+	default:
+		WARN(1, "Incorrect KDiv\n");
+	}
+
+	switch (pdiv) {
+	case 2:
+		params->pdiv = 1;
+		break;
+	case 3:
+		params->pdiv = 2;
+		break;
+	case 5:
+		params->pdiv = 4;
+		break;
+	case 7:
+		params->pdiv = 8;
+		break;
+	default:
+		WARN(1, "Incorrect PDiv\n");
+	}
+
+	if (kdiv != 2)
+		qdiv = 1;
+
+	params->qdiv_ratio = qdiv;
+	params->qdiv_mode = (qdiv == 1) ? 0 : 1;
+
+	params->dco_integer = div_u64(dco_freq, ref_freq);
+	params->dco_fraction = div_u64((div_u64((uint64_t)dco_freq<<15, (uint64_t)ref_freq) -
+					((uint64_t)params->dco_integer<<15)) * 0x8000, 0x8000);
+}
+
+static bool
+cnl_ddi_calculate_wrpll(int clock /* in Hz */,
+			struct drm_i915_private *dev_priv,
+			struct skl_wrpll_params *wrpll_params)
+{
+	uint64_t afe_clock = clock * 5 / KHz(1); /* clocks in kHz */
+	unsigned int dco_min = 7998 * KHz(1);
+	unsigned int dco_max = 10000 * KHz(1);
+	unsigned int dco_mid = (dco_min + dco_max) / 2;
+
+	static const int dividers[] = {  2,  4,  6,  8, 10, 12,  14,  16,
+					 18, 20, 24, 28, 30, 32,  36,  40,
+					 42, 44, 48, 50, 52, 54,  56,  60,
+					 64, 66, 68, 70, 72, 76,  78,  80,
+					 84, 88, 90, 92, 96, 98, 100, 102,
+					  3,  5,  7,  9, 15, 21 };
+	unsigned int d, dco;
+	unsigned int dco_centrality = 0;
+	unsigned int best_dco_centrality = 999999;
+	unsigned int best_div = 0;
+	unsigned int best_dco = 0;
+	unsigned int pdiv = 0, qdiv = 0, kdiv = 0;
+
+	for (d = 0; d < ARRAY_SIZE(dividers); d++) {
+		dco = afe_clock * dividers[d];
+
+		if ((dco <= dco_max) && (dco >= dco_min)) {
+			dco_centrality = abs(dco - dco_mid);
+
+			if (dco_centrality < best_dco_centrality) {
+				best_dco_centrality = dco_centrality;
+				best_div = dividers[d];
+				best_dco = dco;
+			}
+		}
+	}
+
+	if (best_div == 0)
+		return false;
+
+	cnl_wrpll_get_multipliers(best_div, &pdiv, &qdiv, &kdiv);
+
+	cnl_wrpll_params_populate(wrpll_params, best_dco,
+				  dev_priv->cdclk.hw.ref, pdiv, qdiv, kdiv);
+
+	return true;
+}
+
 static bool cnl_ddi_hdmi_pll_dividers(struct intel_crtc *crtc,
 				      struct intel_crtc_state *crtc_state,
 				      int clock)
 {
+	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 	uint32_t cfgcr0, cfgcr1;
 	struct skl_wrpll_params wrpll_params = { 0, };
 
 	cfgcr0 = DPLL_CFGCR0_HDMI_MODE;
 
-	/* FIXME: Proper wrpll calculation done in a following patch */
-	return false;
+	if (!cnl_ddi_calculate_wrpll(clock * 1000, dev_priv, &wrpll_params))
+		return false;
 
 	cfgcr0 |= DPLL_CFGCR0_DCO_FRACTION(wrpll_params.dco_fraction) |
 		wrpll_params.dco_integer;
-- 
1.9.1

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[PATCH] drm/i915/cnl: Enable wrpll computation for CNL

[Rodrigo Vivi]

From: "Kahola, Mika" <mika.kahola@intel.com>

Enable wrpll computation for Cannonlake platform to support
pll's required for HDMI output. The patch contains the following features

- compute Cannonlake port clock programming
  dividers P, Q, and K.
- compute PLL parameters for Cannonlake. These parameters
  set the values on DPLL registers.
- find the register values to program wrpll for Cannonlake.
  The reference clock can be either 19.2MHz or 24MHz.

v2: rebase
v3: squash wrpll patches into one (Rodrigo)
v4: switch order of getting even dividers (Paulo)
    update divider register values for PDiv and KDiv (Paulo)
    update wrpll computation algorithm (Paulo)
v5: Remove ref clock division by 1000. (Rodrigo)
v6: Rodrigo rebasing on top of latest code.

Signed-off-by: Kahola, Mika <mika.kahola@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
---
 drivers/gpu/drm/i915/intel_dpll_mgr.c | 140 +++++++++++++++++++++++++++++++++-
 1 file changed, 138 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_dpll_mgr.c b/drivers/gpu/drm/i915/intel_dpll_mgr.c
index 903c38d..8e669b6 100644
--- a/drivers/gpu/drm/i915/intel_dpll_mgr.c
+++ b/drivers/gpu/drm/i915/intel_dpll_mgr.c
@@ -2126,17 +2126,153 @@ static bool cnl_ddi_pll_get_hw_state(struct drm_i915_private *dev_priv,
 	return ret;
 }
 
+static void cnl_wrpll_get_multipliers(unsigned int bestdiv,
+				      unsigned int *pdiv,
+				      unsigned int *qdiv,
+				      unsigned int *kdiv)
+{
+	/* even dividers */
+	if (bestdiv % 2 == 0) {
+		if (bestdiv == 2) {
+			*pdiv = 2;
+			*qdiv = 1;
+			*kdiv = 1;
+		} else if (bestdiv % 4 == 0) {
+			*pdiv = 2;
+			*qdiv = bestdiv / 4;
+			*kdiv = 2;
+		} else if (bestdiv % 6 == 0) {
+			*pdiv = 3;
+			*qdiv = bestdiv / 6;
+			*kdiv = 2;
+		} else if (bestdiv % 5 == 0) {
+			*pdiv = 5;
+			*qdiv = bestdiv / 10;
+			*kdiv = 2;
+		} else if (bestdiv % 14 == 0) {
+			*pdiv = 7;
+			*qdiv = bestdiv / 14;
+			*kdiv = 2;
+		}
+	} else {
+		if (bestdiv == 3 || bestdiv == 5 || bestdiv == 7) {
+			*pdiv = bestdiv;
+			*qdiv = 1;
+			*kdiv = 1;
+		} else { /* 9, 15, 21 */
+			*pdiv = bestdiv / 3;
+			*qdiv = 1;
+			*kdiv = 3;
+		}
+	}
+}
+
+static void cnl_wrpll_params_populate(struct skl_wrpll_params *params, uint32_t dco_freq,
+				      uint32_t ref_freq, uint32_t pdiv, uint32_t qdiv,
+				      uint32_t kdiv)
+{
+	switch (kdiv) {
+	case 1:
+		params->kdiv = 1;
+		break;
+	case 2:
+		params->kdiv = 2;
+		break;
+	case 3:
+		params->kdiv = 4;
+		break;
+	default:
+		WARN(1, "Incorrect KDiv\n");
+	}
+
+	switch (pdiv) {
+	case 2:
+		params->pdiv = 1;
+		break;
+	case 3:
+		params->pdiv = 2;
+		break;
+	case 5:
+		params->pdiv = 4;
+		break;
+	case 7:
+		params->pdiv = 8;
+		break;
+	default:
+		WARN(1, "Incorrect PDiv\n");
+	}
+
+	if (kdiv != 2)
+		qdiv = 1;
+
+	params->qdiv_ratio = qdiv;
+	params->qdiv_mode = (qdiv == 1) ? 0 : 1;
+
+	params->dco_integer = div_u64(dco_freq, ref_freq);
+	params->dco_fraction = div_u64((div_u64((uint64_t)dco_freq<<15, (uint64_t)ref_freq) -
+					((uint64_t)params->dco_integer<<15)) * 0x8000, 0x8000);
+}
+
+static bool
+cnl_ddi_calculate_wrpll(int clock /* in Hz */,
+			struct drm_i915_private *dev_priv,
+			struct skl_wrpll_params *wrpll_params)
+{
+	uint64_t afe_clock = clock * 5 / KHz(1); /* clocks in kHz */
+	unsigned int dco_min = 7998 * KHz(1);
+	unsigned int dco_max = 10000 * KHz(1);
+	unsigned int dco_mid = (dco_min + dco_max) / 2;
+
+	static const int dividers[] = {  2,  4,  6,  8, 10, 12,  14,  16,
+					 18, 20, 24, 28, 30, 32,  36,  40,
+					 42, 44, 48, 50, 52, 54,  56,  60,
+					 64, 66, 68, 70, 72, 76,  78,  80,
+					 84, 88, 90, 92, 96, 98, 100, 102,
+					  3,  5,  7,  9, 15, 21 };
+	unsigned int d, dco;
+	unsigned int dco_centrality = 0;
+	unsigned int best_dco_centrality = 999999;
+	unsigned int best_div = 0;
+	unsigned int best_dco = 0;
+	unsigned int pdiv = 0, qdiv = 0, kdiv = 0;
+
+	for (d = 0; d < ARRAY_SIZE(dividers); d++) {
+		dco = afe_clock * dividers[d];
+
+		if ((dco <= dco_max) && (dco >= dco_min)) {
+			dco_centrality = abs(dco - dco_mid);
+
+			if (dco_centrality < best_dco_centrality) {
+				best_dco_centrality = dco_centrality;
+				best_div = dividers[d];
+				best_dco = dco;
+			}
+		}
+	}
+
+	if (best_div == 0)
+		return false;
+
+	cnl_wrpll_get_multipliers(best_div, &pdiv, &qdiv, &kdiv);
+
+	cnl_wrpll_params_populate(wrpll_params, best_dco,
+				  dev_priv->cdclk.hw.ref, pdiv, qdiv, kdiv);
+
+	return true;
+}
+
 static bool cnl_ddi_hdmi_pll_dividers(struct intel_crtc *crtc,
 				      struct intel_crtc_state *crtc_state,
 				      int clock)
 {
+	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 	uint32_t cfgcr0, cfgcr1;
 	struct skl_wrpll_params wrpll_params = { 0, };
 
 	cfgcr0 = DPLL_CFGCR0_HDMI_MODE;
 
-	/* FIXME: Proper wrpll calculation done in a following patch */
-	return false;
+	if (!cnl_ddi_calculate_wrpll(clock * 1000, dev_priv, &wrpll_params))
+		return false;
 
 	cfgcr0 |= DPLL_CFGCR0_DCO_FRACTION(wrpll_params.dco_fraction) |
 		wrpll_params.dco_integer;
-- 
1.9.1

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Re: [PATCH] drm/i915/cnl: Enable wrpll computation for CNL

[Clint Taylor]

Matches pseudo code in BSpec.

Reviewed-by: Clint Taylor <Clinton.A.Taylor@intel.com>


On 06/08/2017 04:03 PM, Rodrigo Vivi wrote:
> From: "Kahola, Mika" <mika.kahola@intel.com>
>
> Enable wrpll computation for Cannonlake platform to support
> pll's required for HDMI output. The patch contains the following features
>
> - compute Cannonlake port clock programming
>    dividers P, Q, and K.
> - compute PLL parameters for Cannonlake. These parameters
>    set the values on DPLL registers.
> - find the register values to program wrpll for Cannonlake.
>    The reference clock can be either 19.2MHz or 24MHz.
>
> v2: rebase
> v3: squash wrpll patches into one (Rodrigo)
> v4: switch order of getting even dividers (Paulo)
>      update divider register values for PDiv and KDiv (Paulo)
>      update wrpll computation algorithm (Paulo)
> v5: Remove ref clock division by 1000. (Rodrigo)
> v6: Rodrigo rebasing on top of latest code.
>
> Signed-off-by: Kahola, Mika <mika.kahola@intel.com>
> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
> ---
>   drivers/gpu/drm/i915/intel_dpll_mgr.c | 140 +++++++++++++++++++++++++++++++++-
>   1 file changed, 138 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_dpll_mgr.c b/drivers/gpu/drm/i915/intel_dpll_mgr.c
> index 903c38d..8e669b6 100644
> --- a/drivers/gpu/drm/i915/intel_dpll_mgr.c
> +++ b/drivers/gpu/drm/i915/intel_dpll_mgr.c
> @@ -2126,17 +2126,153 @@ static bool cnl_ddi_pll_get_hw_state(struct drm_i915_private *dev_priv,
>   	return ret;
>   }
>   
> +static void cnl_wrpll_get_multipliers(unsigned int bestdiv,
> +				      unsigned int *pdiv,
> +				      unsigned int *qdiv,
> +				      unsigned int *kdiv)
> +{
> +	/* even dividers */
> +	if (bestdiv % 2 == 0) {
> +		if (bestdiv == 2) {
> +			*pdiv = 2;
> +			*qdiv = 1;
> +			*kdiv = 1;
> +		} else if (bestdiv % 4 == 0) {
> +			*pdiv = 2;
> +			*qdiv = bestdiv / 4;
> +			*kdiv = 2;
> +		} else if (bestdiv % 6 == 0) {
> +			*pdiv = 3;
> +			*qdiv = bestdiv / 6;
> +			*kdiv = 2;
> +		} else if (bestdiv % 5 == 0) {
> +			*pdiv = 5;
> +			*qdiv = bestdiv / 10;
> +			*kdiv = 2;
> +		} else if (bestdiv % 14 == 0) {
> +			*pdiv = 7;
> +			*qdiv = bestdiv / 14;
> +			*kdiv = 2;
> +		}
> +	} else {
> +		if (bestdiv == 3 || bestdiv == 5 || bestdiv == 7) {
> +			*pdiv = bestdiv;
> +			*qdiv = 1;
> +			*kdiv = 1;
> +		} else { /* 9, 15, 21 */
> +			*pdiv = bestdiv / 3;
> +			*qdiv = 1;
> +			*kdiv = 3;
> +		}
> +	}
> +}
> +
> +static void cnl_wrpll_params_populate(struct skl_wrpll_params *params, uint32_t dco_freq,
> +				      uint32_t ref_freq, uint32_t pdiv, uint32_t qdiv,
> +				      uint32_t kdiv)
> +{
> +	switch (kdiv) {
> +	case 1:
> +		params->kdiv = 1;
> +		break;
> +	case 2:
> +		params->kdiv = 2;
> +		break;
> +	case 3:
> +		params->kdiv = 4;
> +		break;
> +	default:
> +		WARN(1, "Incorrect KDiv\n");
> +	}
> +
> +	switch (pdiv) {
> +	case 2:
> +		params->pdiv = 1;
> +		break;
> +	case 3:
> +		params->pdiv = 2;
> +		break;
> +	case 5:
> +		params->pdiv = 4;
> +		break;
> +	case 7:
> +		params->pdiv = 8;
> +		break;
> +	default:
> +		WARN(1, "Incorrect PDiv\n");
> +	}
> +
> +	if (kdiv != 2)
> +		qdiv = 1;
> +
> +	params->qdiv_ratio = qdiv;
> +	params->qdiv_mode = (qdiv == 1) ? 0 : 1;
> +
> +	params->dco_integer = div_u64(dco_freq, ref_freq);
> +	params->dco_fraction = div_u64((div_u64((uint64_t)dco_freq<<15, (uint64_t)ref_freq) -
> +					((uint64_t)params->dco_integer<<15)) * 0x8000, 0x8000);
> +}
> +
> +static bool
> +cnl_ddi_calculate_wrpll(int clock /* in Hz */,
> +			struct drm_i915_private *dev_priv,
> +			struct skl_wrpll_params *wrpll_params)
> +{
> +	uint64_t afe_clock = clock * 5 / KHz(1); /* clocks in kHz */
> +	unsigned int dco_min = 7998 * KHz(1);
> +	unsigned int dco_max = 10000 * KHz(1);
> +	unsigned int dco_mid = (dco_min + dco_max) / 2;
> +
> +	static const int dividers[] = {  2,  4,  6,  8, 10, 12,  14,  16,
> +					 18, 20, 24, 28, 30, 32,  36,  40,
> +					 42, 44, 48, 50, 52, 54,  56,  60,
> +					 64, 66, 68, 70, 72, 76,  78,  80,
> +					 84, 88, 90, 92, 96, 98, 100, 102,
> +					  3,  5,  7,  9, 15, 21 };
> +	unsigned int d, dco;
> +	unsigned int dco_centrality = 0;
> +	unsigned int best_dco_centrality = 999999;
> +	unsigned int best_div = 0;
> +	unsigned int best_dco = 0;
> +	unsigned int pdiv = 0, qdiv = 0, kdiv = 0;
> +
> +	for (d = 0; d < ARRAY_SIZE(dividers); d++) {
> +		dco = afe_clock * dividers[d];
> +
> +		if ((dco <= dco_max) && (dco >= dco_min)) {
> +			dco_centrality = abs(dco - dco_mid);
> +
> +			if (dco_centrality < best_dco_centrality) {
> +				best_dco_centrality = dco_centrality;
> +				best_div = dividers[d];
> +				best_dco = dco;
> +			}
> +		}
> +	}
> +
> +	if (best_div == 0)
> +		return false;
> +
> +	cnl_wrpll_get_multipliers(best_div, &pdiv, &qdiv, &kdiv);
> +
> +	cnl_wrpll_params_populate(wrpll_params, best_dco,
> +				  dev_priv->cdclk.hw.ref, pdiv, qdiv, kdiv);
> +
> +	return true;
> +}
> +
>   static bool cnl_ddi_hdmi_pll_dividers(struct intel_crtc *crtc,
>   				      struct intel_crtc_state *crtc_state,
>   				      int clock)
>   {
> +	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
>   	uint32_t cfgcr0, cfgcr1;
>   	struct skl_wrpll_params wrpll_params = { 0, };
>   
>   	cfgcr0 = DPLL_CFGCR0_HDMI_MODE;
>   
> -	/* FIXME: Proper wrpll calculation done in a following patch */
> -	return false;
> +	if (!cnl_ddi_calculate_wrpll(clock * 1000, dev_priv, &wrpll_params))
> +		return false;
>   
>   	cfgcr0 |= DPLL_CFGCR0_DCO_FRACTION(wrpll_params.dco_fraction) |
>   		wrpll_params.dco_integer;

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[PATCH 36/67] drm/i915: Add MMIO helper for 6 ports with different offsets.

[Rodrigo Vivi]

Also new registers can have different mmio offsets
per different lane per port.

v2: Use _PICK as PORT3 instead of creating a new
    macro with if per port.

Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index c38c1fd..5777925 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -64,6 +64,10 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
 #define _MMIO_PIPE3(pipe, a, b, c) _MMIO(_PIPE3(pipe, a, b, c))
 #define _PORT3(port, ...) _PICK(port, __VA_ARGS__)
 #define _MMIO_PORT3(pipe, a, b, c) _MMIO(_PORT3(pipe, a, b, c))
+#define _PORT6(port, ...) _PICK(port, __VA_ARGS__)
+#define _MMIO_PORT6(port, a, b, c, d, e, f) _MMIO(_PORT6(port, a, b, c, d, e, f))
+#define _MMIO_PORT6_LN(port, ln, a0, a1, b, c, d, e, f)			\
+	_MMIO(_PORT6(port, a0, b, c, d, e, f) + (ln * (a1 - a0)))
 #define _PHY3(phy, ...) _PICK(phy, __VA_ARGS__)
 #define _MMIO_PHY3(phy, a, b, c) _MMIO(_PHY3(phy, a, b, c))
 
-- 
1.9.1

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Re: [PATCH 36/67] drm/i915: Add MMIO helper for 6 ports with different offsets.

[Manasi Navare]

On Thu, Apr 06, 2017 at 12:15:32PM -0700, Rodrigo Vivi wrote:
> Also new registers can have different mmio offsets
> per different lane per port.
> 
> v2: Use _PICK as PORT3 instead of creating a new
>     macro with if per port.
> 
> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
> ---
>  drivers/gpu/drm/i915/i915_reg.h | 4 ++++
>  1 file changed, 4 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index c38c1fd..5777925 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -64,6 +64,10 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
>  #define _MMIO_PIPE3(pipe, a, b, c) _MMIO(_PIPE3(pipe, a, b, c))
>  #define _PORT3(port, ...) _PICK(port, __VA_ARGS__)
>  #define _MMIO_PORT3(pipe, a, b, c) _MMIO(_PORT3(pipe, a, b, c))
> +#define _PORT6(port, ...) _PICK(port, __VA_ARGS__)

Why do we need to define _PORT6() as a separate macro when all it has to do
is _PICK between given ports so we can jsut use _PORT3 and it will pick amongst the
_VA_ARGS_.

Jani/Ville am I correct?

Manasi
> +#define _MMIO_PORT6(port, a, b, c, d, e, f) _MMIO(_PORT6(port, a, b, c, d, e, f))
> +#define _MMIO_PORT6_LN(port, ln, a0, a1, b, c, d, e, f)			\
> +	_MMIO(_PORT6(port, a0, b, c, d, e, f) + (ln * (a1 - a0)))
>  #define _PHY3(phy, ...) _PICK(phy, __VA_ARGS__)
>  #define _MMIO_PHY3(phy, a, b, c) _MMIO(_PHY3(phy, a, b, c))
>  
> -- 
> 1.9.1
> 
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Re: [PATCH 36/67] drm/i915: Add MMIO helper for 6 ports with different offsets.

[Rodrigo Vivi]

On Wed, May 17, 2017 at 12:20 PM, Manasi Navare
<manasi.d.navare@intel.com> wrote:
> On Thu, Apr 06, 2017 at 12:15:32PM -0700, Rodrigo Vivi wrote:
>> Also new registers can have different mmio offsets
>> per different lane per port.
>>
>> v2: Use _PICK as PORT3 instead of creating a new
>>     macro with if per port.
>>
>> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
>> ---
>>  drivers/gpu/drm/i915/i915_reg.h | 4 ++++
>>  1 file changed, 4 insertions(+)
>>
>> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
>> index c38c1fd..5777925 100644
>> --- a/drivers/gpu/drm/i915/i915_reg.h
>> +++ b/drivers/gpu/drm/i915/i915_reg.h
>> @@ -64,6 +64,10 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
>>  #define _MMIO_PIPE3(pipe, a, b, c) _MMIO(_PIPE3(pipe, a, b, c))
>>  #define _PORT3(port, ...) _PICK(port, __VA_ARGS__)
>>  #define _MMIO_PORT3(pipe, a, b, c) _MMIO(_PORT3(pipe, a, b, c))
>> +#define _PORT6(port, ...) _PICK(port, __VA_ARGS__)
>
> Why do we need to define _PORT6() as a separate macro when all it has to do
> is _PICK between given ports so we can jsut use _PORT3 and it will pick amongst the
> _VA_ARGS_.

It was just my OCD refusing to use "3" for "6"...
Any idea for a better generic name for the PORT3?

>
> Jani/Ville am I correct?
>
> Manasi
>> +#define _MMIO_PORT6(port, a, b, c, d, e, f) _MMIO(_PORT6(port, a, b, c, d, e, f))
>> +#define _MMIO_PORT6_LN(port, ln, a0, a1, b, c, d, e, f)                      \
>> +     _MMIO(_PORT6(port, a0, b, c, d, e, f) + (ln * (a1 - a0)))
>>  #define _PHY3(phy, ...) _PICK(phy, __VA_ARGS__)
>>  #define _MMIO_PHY3(phy, a, b, c) _MMIO(_PHY3(phy, a, b, c))
>>
>> --
>> 1.9.1
>>
>> _______________________________________________
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> _______________________________________________
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-- 
Rodrigo Vivi
Blog: http://blog.vivi.eng.br
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Re: [PATCH 36/67] drm/i915: Add MMIO helper for 6 ports with different offsets.

[Manasi Navare]

Rodrigo,

Any thoughts on the ocmment here regarding defining a new macro _PORT6?
I am facing a similar issue with ICL - whether to define a new macro or use
the existing one _PORT3?

Manasi

On Wed, May 17, 2017 at 12:20:34PM -0700, Manasi Navare wrote:
> On Thu, Apr 06, 2017 at 12:15:32PM -0700, Rodrigo Vivi wrote:
> > Also new registers can have different mmio offsets
> > per different lane per port.
> > 
> > v2: Use _PICK as PORT3 instead of creating a new
> >     macro with if per port.
> > 
> > Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
> > ---
> >  drivers/gpu/drm/i915/i915_reg.h | 4 ++++
> >  1 file changed, 4 insertions(+)
> > 
> > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> > index c38c1fd..5777925 100644
> > --- a/drivers/gpu/drm/i915/i915_reg.h
> > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > @@ -64,6 +64,10 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
> >  #define _MMIO_PIPE3(pipe, a, b, c) _MMIO(_PIPE3(pipe, a, b, c))
> >  #define _PORT3(port, ...) _PICK(port, __VA_ARGS__)
> >  #define _MMIO_PORT3(pipe, a, b, c) _MMIO(_PORT3(pipe, a, b, c))
> > +#define _PORT6(port, ...) _PICK(port, __VA_ARGS__)
> 
> Why do we need to define _PORT6() as a separate macro when all it has to do
> is _PICK between given ports so we can jsut use _PORT3 and it will pick amongst the
> _VA_ARGS_.
> 
> Jani/Ville am I correct?
> 
> Manasi
> > +#define _MMIO_PORT6(port, a, b, c, d, e, f) _MMIO(_PORT6(port, a, b, c, d, e, f))
> > +#define _MMIO_PORT6_LN(port, ln, a0, a1, b, c, d, e, f)			\
> > +	_MMIO(_PORT6(port, a0, b, c, d, e, f) + (ln * (a1 - a0)))
> >  #define _PHY3(phy, ...) _PICK(phy, __VA_ARGS__)
> >  #define _MMIO_PHY3(phy, a, b, c) _MMIO(_PHY3(phy, a, b, c))
> >  
> > -- 
> > 1.9.1
> > 
> > _______________________________________________
> > Intel-gfx mailing list
> > Intel-gfx@lists.freedesktop.org
> > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
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[PATCH 37/67] drm/i915/cnl: Add registers related to voltage swing sequences.

[Rodrigo Vivi]

This are the registers and bits needed for the voltage swing
sequence on Cannonlake.

v2: Remove CL_DW5 that was wrongly defined.
v3: Use (1 << 1) instead of (1<<1) as Paulo suggested
    Change DW2 swing sel upper and lower macros to do the
    bit selection instead of definint a table that doesn't
    match the spec. It is based on a Manasi version of it.
    Credits-to: Manasi.

Cc: Paulo Zanoni <paulo.r.zanoni@intel.com>
Cc: Manasi Navare <manasi.d.navare@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h | 140 ++++++++++++++++++++++++++++++++++++++++
 1 file changed, 140 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 5777925..d4f7460 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -1688,6 +1688,146 @@ enum skl_disp_power_wells {
 #define   OCL2_LDOFUSE_PWR_DIS		(1 << 6)
 #define BXT_PORT_CL1CM_DW30(phy)	_BXT_PHY((phy), _PORT_CL1CM_DW30_BC)
 
+#define _CNL_PORT_PCS_DW1_GRP_AE	0x162304
+#define _CNL_PORT_PCS_DW1_GRP_B		0x162384
+#define _CNL_PORT_PCS_DW1_GRP_C		0x162B04
+#define _CNL_PORT_PCS_DW1_GRP_D		0x162B84
+#define _CNL_PORT_PCS_DW1_GRP_F		0x162A04
+#define _CNL_PORT_PCS_DW1_LN0_AE	0x162404
+#define _CNL_PORT_PCS_DW1_LN0_B		0x162604
+#define _CNL_PORT_PCS_DW1_LN0_C		0x162C04
+#define _CNL_PORT_PCS_DW1_LN0_D		0x162E04
+#define _CNL_PORT_PCS_DW1_LN0_F		0x162804
+#define CNL_PORT_PCS_DW1_GRP(port)	_MMIO_PORT6(port, \
+						    _CNL_PORT_PCS_DW1_GRP_AE, \
+						    _CNL_PORT_PCS_DW1_GRP_B, \
+						    _CNL_PORT_PCS_DW1_GRP_C, \
+						    _CNL_PORT_PCS_DW1_GRP_D, \
+						    _CNL_PORT_PCS_DW1_GRP_AE, \
+						    _CNL_PORT_PCS_DW1_GRP_F)
+#define CNL_PORT_PCS_DW1_LN0(port)	_MMIO_PORT6(port, \
+						    _CNL_PORT_PCS_DW1_LN0_AE, \
+						    _CNL_PORT_PCS_DW1_LN0_B, \
+						    _CNL_PORT_PCS_DW1_LN0_C, \
+						    _CNL_PORT_PCS_DW1_LN0_D, \
+						    _CNL_PORT_PCS_DW1_LN0_AE, \
+						    _CNL_PORT_PCS_DW1_LN0_F)
+#define   COMMON_KEEPER_EN		(1 << 26)
+
+#define _CNL_PORT_TX_DW2_GRP_AE		0x162348
+#define _CNL_PORT_TX_DW2_GRP_B		0x1623C8
+#define _CNL_PORT_TX_DW2_GRP_C		0x162B48
+#define _CNL_PORT_TX_DW2_GRP_D		0x162BC8
+#define _CNL_PORT_TX_DW2_GRP_F		0x162A48
+#define _CNL_PORT_TX_DW2_LN0_AE		0x162448
+#define _CNL_PORT_TX_DW2_LN0_B		0x162648
+#define _CNL_PORT_TX_DW2_LN0_C		0x162C48
+#define _CNL_PORT_TX_DW2_LN0_D		0x162E48
+#define _CNL_PORT_TX_DW2_LN0_F		0x162A48
+#define CNL_PORT_TX_DW2_GRP(port)	_MMIO_PORT6(port, \
+						    _CNL_PORT_TX_DW2_GRP_AE, \
+						    _CNL_PORT_TX_DW2_GRP_B, \
+						    _CNL_PORT_TX_DW2_GRP_C, \
+						    _CNL_PORT_TX_DW2_GRP_D, \
+						    _CNL_PORT_TX_DW2_GRP_AE, \
+						    _CNL_PORT_TX_DW2_GRP_F)
+#define CNL_PORT_TX_DW2_LN0(port)	_MMIO_PORT6(port, \
+						    _CNL_PORT_TX_DW2_LN0_AE, \
+						    _CNL_PORT_TX_DW2_LN0_B, \
+						    _CNL_PORT_TX_DW2_LN0_C, \
+						    _CNL_PORT_TX_DW2_LN0_D, \
+						    _CNL_PORT_TX_DW2_LN0_AE, \
+						    _CNL_PORT_TX_DW2_LN0_F)
+#define   SWING_SEL_UPPER(x)		((x >> 3) << 15)
+#define   SWING_SEL_LOWER(x)		((x & 0x7) << 11)
+#define   RCOMP_SCALAR(x)		((x) << 0)
+
+#define _CNL_PORT_TX_DW4_GRP_AE		0x162350
+#define _CNL_PORT_TX_DW4_GRP_B		0x1623D0
+#define _CNL_PORT_TX_DW4_GRP_C		0x162B50
+#define _CNL_PORT_TX_DW4_GRP_D		0x162BD0
+#define _CNL_PORT_TX_DW4_GRP_F		0x162A50
+#define _CNL_PORT_TX_DW4_LN0_AE		0x162450
+#define _CNL_PORT_TX_DW4_LN1_AE		0x1624D0
+#define _CNL_PORT_TX_DW4_LN0_B		0x162650
+#define _CNL_PORT_TX_DW4_LN0_C		0x162C50
+#define _CNL_PORT_TX_DW4_LN0_D		0x162E50
+#define _CNL_PORT_TX_DW4_LN0_F		0x162850
+#define CNL_PORT_TX_DW4_GRP(port)       _MMIO_PORT6(port, \
+						    _CNL_PORT_TX_DW4_GRP_AE, \
+						    _CNL_PORT_TX_DW4_GRP_B, \
+						    _CNL_PORT_TX_DW4_GRP_C, \
+						    _CNL_PORT_TX_DW4_GRP_D, \
+						    _CNL_PORT_TX_DW4_GRP_AE, \
+						    _CNL_PORT_TX_DW4_GRP_F)
+#define CNL_PORT_TX_DW4_LN(port, ln)       _MMIO_PORT6_LN(port, ln,	\
+						    _CNL_PORT_TX_DW4_LN0_AE, \
+						    _CNL_PORT_TX_DW4_LN1_AE, \
+						    _CNL_PORT_TX_DW4_LN0_B, \
+						    _CNL_PORT_TX_DW4_LN0_C, \
+						    _CNL_PORT_TX_DW4_LN0_D, \
+						    _CNL_PORT_TX_DW4_LN0_AE, \
+						    _CNL_PORT_TX_DW4_LN0_F)
+#define   LOADGEN_SELECT		(1 << 31)
+#define   POST_CURSOR_1(x)		((x) << 12)
+#define   POST_CURSOR_2(x)		((x) << 6)
+#define   CURSOR_COEFF(x)		((x) << 0)
+
+#define _CNL_PORT_TX_DW5_GRP_AE		0x162354
+#define _CNL_PORT_TX_DW5_GRP_B		0x1623D4
+#define _CNL_PORT_TX_DW5_GRP_C		0x162B54
+#define _CNL_PORT_TX_DW5_GRP_D		0x162BD4
+#define _CNL_PORT_TX_DW5_GRP_F		0x162A54
+#define _CNL_PORT_TX_DW5_LN0_AE		0x162454
+#define _CNL_PORT_TX_DW5_LN0_B		0x162654
+#define _CNL_PORT_TX_DW5_LN0_C		0x162C54
+#define _CNL_PORT_TX_DW5_LN0_D		0x162ED4
+#define _CNL_PORT_TX_DW5_LN0_F		0x162854
+#define CNL_PORT_TX_DW5_GRP(port)	_MMIO_PORT6(port, \
+						    _CNL_PORT_TX_DW5_GRP_AE, \
+						    _CNL_PORT_TX_DW5_GRP_B, \
+						    _CNL_PORT_TX_DW5_GRP_C, \
+						    _CNL_PORT_TX_DW5_GRP_D, \
+						    _CNL_PORT_TX_DW5_GRP_AE, \
+						    _CNL_PORT_TX_DW5_GRP_F)
+#define CNL_PORT_TX_DW5_LN0(port)	_MMIO_PORT6(port, \
+						    _CNL_PORT_TX_DW5_LN0_AE, \
+						    _CNL_PORT_TX_DW5_LN0_B, \
+						    _CNL_PORT_TX_DW5_LN0_C, \
+						    _CNL_PORT_TX_DW5_LN0_D, \
+						    _CNL_PORT_TX_DW5_LN0_AE, \
+						    _CNL_PORT_TX_DW5_LN0_F)
+#define   TX_TRAINING_EN		(1 << 31)
+#define   TAP3_DISABLE			(1 << 29)
+#define   SCALING_MODE_SEL		(2<<18)
+#define   RTERM_SELECT(x)		((x) << 3)
+
+#define _CNL_PORT_TX_DW7_GRP_AE		0x16235C
+#define _CNL_PORT_TX_DW7_GRP_B		0x1623DC
+#define _CNL_PORT_TX_DW7_GRP_C		0x162B5C
+#define _CNL_PORT_TX_DW7_GRP_D		0x162BDC
+#define _CNL_PORT_TX_DW7_GRP_F		0x162A5C
+#define _CNL_PORT_TX_DW7_LN0_AE		0x16245C
+#define _CNL_PORT_TX_DW7_LN0_B		0x16265C
+#define _CNL_PORT_TX_DW7_LN0_C		0x162C5C
+#define _CNL_PORT_TX_DW7_LN0_D		0x162EDC
+#define _CNL_PORT_TX_DW7_LN0_F		0x16285C
+#define CNL_PORT_TX_DW7_GRP(port)	_MMIO_PORT6(port, \
+						    _CNL_PORT_TX_DW7_GRP_AE, \
+						    _CNL_PORT_TX_DW7_GRP_B, \
+						    _CNL_PORT_TX_DW7_GRP_C, \
+						    _CNL_PORT_TX_DW7_GRP_D, \
+						    _CNL_PORT_TX_DW7_GRP_AE, \
+						    _CNL_PORT_TX_DW7_GRP_F)
+#define CNL_PORT_TX_DW7_LN0(port)	_MMIO_PORT6(port, \
+						    _CNL_PORT_TX_DW7_LN0_AE, \
+						    _CNL_PORT_TX_DW7_LN0_B, \
+						    _CNL_PORT_TX_DW7_LN0_C, \
+						    _CNL_PORT_TX_DW7_LN0_D, \
+						    _CNL_PORT_TX_DW7_LN0_AE, \
+						    _CNL_PORT_TX_DW7_LN0_F)
+#define   N_SCALAR(x)			((x) << 24)
+
 /* The spec defines this only for BXT PHY0, but lets assume that this
  * would exist for PHY1 too if it had a second channel.
  */
-- 
1.9.1

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Re: [PATCH 37/67] drm/i915/cnl: Add registers related to voltage swing sequences.

[Manasi Navare]

On Thu, Apr 06, 2017 at 12:15:33PM -0700, Rodrigo Vivi wrote:
> This are the registers and bits needed for the voltage swing
> sequence on Cannonlake.
> 
> v2: Remove CL_DW5 that was wrongly defined.
> v3: Use (1 << 1) instead of (1<<1) as Paulo suggested
>     Change DW2 swing sel upper and lower macros to do the
>     bit selection instead of definint a table that doesn't
>     match the spec. It is based on a Manasi version of it.
>     Credits-to: Manasi.
> 
> Cc: Paulo Zanoni <paulo.r.zanoni@intel.com>
> Cc: Manasi Navare <manasi.d.navare@intel.com>
> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
> ---
>  drivers/gpu/drm/i915/i915_reg.h | 140 ++++++++++++++++++++++++++++++++++++++++
>  1 file changed, 140 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 5777925..d4f7460 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -1688,6 +1688,146 @@ enum skl_disp_power_wells {
>  #define   OCL2_LDOFUSE_PWR_DIS		(1 << 6)
>  #define BXT_PORT_CL1CM_DW30(phy)	_BXT_PHY((phy), _PORT_CL1CM_DW30_BC)
>  
> +#define _CNL_PORT_PCS_DW1_GRP_AE	0x162304
> +#define _CNL_PORT_PCS_DW1_GRP_B		0x162384
> +#define _CNL_PORT_PCS_DW1_GRP_C		0x162B04
> +#define _CNL_PORT_PCS_DW1_GRP_D		0x162B84
> +#define _CNL_PORT_PCS_DW1_GRP_F		0x162A04
> +#define _CNL_PORT_PCS_DW1_LN0_AE	0x162404
> +#define _CNL_PORT_PCS_DW1_LN0_B		0x162604
> +#define _CNL_PORT_PCS_DW1_LN0_C		0x162C04
> +#define _CNL_PORT_PCS_DW1_LN0_D		0x162E04
> +#define _CNL_PORT_PCS_DW1_LN0_F		0x162804
> +#define CNL_PORT_PCS_DW1_GRP(port)	_MMIO_PORT6(port, \
> +						    _CNL_PORT_PCS_DW1_GRP_AE, \
> +						    _CNL_PORT_PCS_DW1_GRP_B, \
> +						    _CNL_PORT_PCS_DW1_GRP_C, \
> +						    _CNL_PORT_PCS_DW1_GRP_D, \
> +						    _CNL_PORT_PCS_DW1_GRP_AE, \
> +						    _CNL_PORT_PCS_DW1_GRP_F)
> +#define CNL_PORT_PCS_DW1_LN0(port)	_MMIO_PORT6(port, \
> +						    _CNL_PORT_PCS_DW1_LN0_AE, \
> +						    _CNL_PORT_PCS_DW1_LN0_B, \
> +						    _CNL_PORT_PCS_DW1_LN0_C, \
> +						    _CNL_PORT_PCS_DW1_LN0_D, \
> +						    _CNL_PORT_PCS_DW1_LN0_AE, \
> +						    _CNL_PORT_PCS_DW1_LN0_F)
> +#define   COMMON_KEEPER_EN		(1 << 26)
> +
> +#define _CNL_PORT_TX_DW2_GRP_AE		0x162348
> +#define _CNL_PORT_TX_DW2_GRP_B		0x1623C8
> +#define _CNL_PORT_TX_DW2_GRP_C		0x162B48
> +#define _CNL_PORT_TX_DW2_GRP_D		0x162BC8
> +#define _CNL_PORT_TX_DW2_GRP_F		0x162A48
> +#define _CNL_PORT_TX_DW2_LN0_AE		0x162448
> +#define _CNL_PORT_TX_DW2_LN0_B		0x162648
> +#define _CNL_PORT_TX_DW2_LN0_C		0x162C48
> +#define _CNL_PORT_TX_DW2_LN0_D		0x162E48
> +#define _CNL_PORT_TX_DW2_LN0_F		0x162A48
> +#define CNL_PORT_TX_DW2_GRP(port)	_MMIO_PORT6(port, \
> +						    _CNL_PORT_TX_DW2_GRP_AE, \
> +						    _CNL_PORT_TX_DW2_GRP_B, \
> +						    _CNL_PORT_TX_DW2_GRP_C, \
> +						    _CNL_PORT_TX_DW2_GRP_D, \
> +						    _CNL_PORT_TX_DW2_GRP_AE, \
> +						    _CNL_PORT_TX_DW2_GRP_F)
> +#define CNL_PORT_TX_DW2_LN0(port)	_MMIO_PORT6(port, \
> +						    _CNL_PORT_TX_DW2_LN0_AE, \
> +						    _CNL_PORT_TX_DW2_LN0_B, \
> +						    _CNL_PORT_TX_DW2_LN0_C, \
> +						    _CNL_PORT_TX_DW2_LN0_D, \
> +						    _CNL_PORT_TX_DW2_LN0_AE, \
> +						    _CNL_PORT_TX_DW2_LN0_F)
> +#define   SWING_SEL_UPPER(x)		((x >> 3) << 15)
> +#define   SWING_SEL_LOWER(x)		((x & 0x7) << 11)
> +#define   RCOMP_SCALAR(x)		((x) << 0)
> +
> +#define _CNL_PORT_TX_DW4_GRP_AE		0x162350
> +#define _CNL_PORT_TX_DW4_GRP_B		0x1623D0
> +#define _CNL_PORT_TX_DW4_GRP_C		0x162B50
> +#define _CNL_PORT_TX_DW4_GRP_D		0x162BD0
> +#define _CNL_PORT_TX_DW4_GRP_F		0x162A50
> +#define _CNL_PORT_TX_DW4_LN0_AE		0x162450
> +#define _CNL_PORT_TX_DW4_LN1_AE		0x1624D0
> +#define _CNL_PORT_TX_DW4_LN0_B		0x162650
> +#define _CNL_PORT_TX_DW4_LN0_C		0x162C50
> +#define _CNL_PORT_TX_DW4_LN0_D		0x162E50
> +#define _CNL_PORT_TX_DW4_LN0_F		0x162850
> +#define CNL_PORT_TX_DW4_GRP(port)       _MMIO_PORT6(port, \
> +						    _CNL_PORT_TX_DW4_GRP_AE, \
> +						    _CNL_PORT_TX_DW4_GRP_B, \
> +						    _CNL_PORT_TX_DW4_GRP_C, \
> +						    _CNL_PORT_TX_DW4_GRP_D, \
> +						    _CNL_PORT_TX_DW4_GRP_AE, \
> +						    _CNL_PORT_TX_DW4_GRP_F)
> +#define CNL_PORT_TX_DW4_LN(port, ln)       _MMIO_PORT6_LN(port, ln,	\
> +						    _CNL_PORT_TX_DW4_LN0_AE, \
> +						    _CNL_PORT_TX_DW4_LN1_AE, \
> +						    _CNL_PORT_TX_DW4_LN0_B, \
> +						    _CNL_PORT_TX_DW4_LN0_C, \
> +						    _CNL_PORT_TX_DW4_LN0_D, \
> +						    _CNL_PORT_TX_DW4_LN0_AE, \
> +						    _CNL_PORT_TX_DW4_LN0_F)
> +#define   LOADGEN_SELECT		(1 << 31)
> +#define   POST_CURSOR_1(x)		((x) << 12)
> +#define   POST_CURSOR_2(x)		((x) << 6)
> +#define   CURSOR_COEFF(x)		((x) << 0)
> +
> +#define _CNL_PORT_TX_DW5_GRP_AE		0x162354
> +#define _CNL_PORT_TX_DW5_GRP_B		0x1623D4
> +#define _CNL_PORT_TX_DW5_GRP_C		0x162B54
> +#define _CNL_PORT_TX_DW5_GRP_D		0x162BD4
> +#define _CNL_PORT_TX_DW5_GRP_F		0x162A54
> +#define _CNL_PORT_TX_DW5_LN0_AE		0x162454
> +#define _CNL_PORT_TX_DW5_LN0_B		0x162654
> +#define _CNL_PORT_TX_DW5_LN0_C		0x162C54
> +#define _CNL_PORT_TX_DW5_LN0_D		0x162ED4
> +#define _CNL_PORT_TX_DW5_LN0_F		0x162854
> +#define CNL_PORT_TX_DW5_GRP(port)	_MMIO_PORT6(port, \
> +						    _CNL_PORT_TX_DW5_GRP_AE, \
> +						    _CNL_PORT_TX_DW5_GRP_B, \
> +						    _CNL_PORT_TX_DW5_GRP_C, \
> +						    _CNL_PORT_TX_DW5_GRP_D, \
> +						    _CNL_PORT_TX_DW5_GRP_AE, \
> +						    _CNL_PORT_TX_DW5_GRP_F)
> +#define CNL_PORT_TX_DW5_LN0(port)	_MMIO_PORT6(port, \
> +						    _CNL_PORT_TX_DW5_LN0_AE, \
> +						    _CNL_PORT_TX_DW5_LN0_B, \
> +						    _CNL_PORT_TX_DW5_LN0_C, \
> +						    _CNL_PORT_TX_DW5_LN0_D, \
> +						    _CNL_PORT_TX_DW5_LN0_AE, \
> +						    _CNL_PORT_TX_DW5_LN0_F)
> +#define   TX_TRAINING_EN		(1 << 31)
> +#define   TAP3_DISABLE			(1 << 29)
> +#define   SCALING_MODE_SEL		(2<<18)

Even Scaling mode can be different for different platforms using the
same set of registers. So instead of using a direct value,
use SCALING_MODE_SEL(x)   ((x) << 18)

Reviewed-by for everything else.

Manasi

> +#define   RTERM_SELECT(x)		((x) << 3)
> +
> +#define _CNL_PORT_TX_DW7_GRP_AE		0x16235C
> +#define _CNL_PORT_TX_DW7_GRP_B		0x1623DC
> +#define _CNL_PORT_TX_DW7_GRP_C		0x162B5C
> +#define _CNL_PORT_TX_DW7_GRP_D		0x162BDC
> +#define _CNL_PORT_TX_DW7_GRP_F		0x162A5C
> +#define _CNL_PORT_TX_DW7_LN0_AE		0x16245C
> +#define _CNL_PORT_TX_DW7_LN0_B		0x16265C
> +#define _CNL_PORT_TX_DW7_LN0_C		0x162C5C
> +#define _CNL_PORT_TX_DW7_LN0_D		0x162EDC
> +#define _CNL_PORT_TX_DW7_LN0_F		0x16285C
> +#define CNL_PORT_TX_DW7_GRP(port)	_MMIO_PORT6(port, \
> +						    _CNL_PORT_TX_DW7_GRP_AE, \
> +						    _CNL_PORT_TX_DW7_GRP_B, \
> +						    _CNL_PORT_TX_DW7_GRP_C, \
> +						    _CNL_PORT_TX_DW7_GRP_D, \
> +						    _CNL_PORT_TX_DW7_GRP_AE, \
> +						    _CNL_PORT_TX_DW7_GRP_F)
> +#define CNL_PORT_TX_DW7_LN0(port)	_MMIO_PORT6(port, \
> +						    _CNL_PORT_TX_DW7_LN0_AE, \
> +						    _CNL_PORT_TX_DW7_LN0_B, \
> +						    _CNL_PORT_TX_DW7_LN0_C, \
> +						    _CNL_PORT_TX_DW7_LN0_D, \
> +						    _CNL_PORT_TX_DW7_LN0_AE, \
> +						    _CNL_PORT_TX_DW7_LN0_F)
> +#define   N_SCALAR(x)			((x) << 24)
> +
>  /* The spec defines this only for BXT PHY0, but lets assume that this
>   * would exist for PHY1 too if it had a second channel.
>   */
> -- 
> 1.9.1
> 
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Re: [PATCH 37/67] drm/i915/cnl: Add registers related to voltage swing sequences.

[Vivi, Rodrigo]

On Wed, 2017-05-17 at 17:59 -0700, Manasi Navare wrote:
> On Thu, Apr 06, 2017 at 12:15:33PM -0700, Rodrigo Vivi wrote:
> > This are the registers and bits needed for the voltage swing
> > sequence on Cannonlake.
> > 
> > v2: Remove CL_DW5 that was wrongly defined.
> > v3: Use (1 << 1) instead of (1<<1) as Paulo suggested
> >     Change DW2 swing sel upper and lower macros to do the
> >     bit selection instead of definint a table that doesn't
> >     match the spec. It is based on a Manasi version of it.
> >     Credits-to: Manasi.
> > 
> > Cc: Paulo Zanoni <paulo.r.zanoni@intel.com>
> > Cc: Manasi Navare <manasi.d.navare@intel.com>
> > Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
> > ---
> >  drivers/gpu/drm/i915/i915_reg.h | 140 ++++++++++++++++++++++++++++++++++++++++
> >  1 file changed, 140 insertions(+)
> > 
> > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> > index 5777925..d4f7460 100644
> > --- a/drivers/gpu/drm/i915/i915_reg.h
> > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > @@ -1688,6 +1688,146 @@ enum skl_disp_power_wells {
> >  #define   OCL2_LDOFUSE_PWR_DIS		(1 << 6)
> >  #define BXT_PORT_CL1CM_DW30(phy)	_BXT_PHY((phy), _PORT_CL1CM_DW30_BC)
> >  
> > +#define _CNL_PORT_PCS_DW1_GRP_AE	0x162304
> > +#define _CNL_PORT_PCS_DW1_GRP_B		0x162384
> > +#define _CNL_PORT_PCS_DW1_GRP_C		0x162B04
> > +#define _CNL_PORT_PCS_DW1_GRP_D		0x162B84
> > +#define _CNL_PORT_PCS_DW1_GRP_F		0x162A04
> > +#define _CNL_PORT_PCS_DW1_LN0_AE	0x162404
> > +#define _CNL_PORT_PCS_DW1_LN0_B		0x162604
> > +#define _CNL_PORT_PCS_DW1_LN0_C		0x162C04
> > +#define _CNL_PORT_PCS_DW1_LN0_D		0x162E04
> > +#define _CNL_PORT_PCS_DW1_LN0_F		0x162804
> > +#define CNL_PORT_PCS_DW1_GRP(port)	_MMIO_PORT6(port, \
> > +						    _CNL_PORT_PCS_DW1_GRP_AE, \
> > +						    _CNL_PORT_PCS_DW1_GRP_B, \
> > +						    _CNL_PORT_PCS_DW1_GRP_C, \
> > +						    _CNL_PORT_PCS_DW1_GRP_D, \
> > +						    _CNL_PORT_PCS_DW1_GRP_AE, \
> > +						    _CNL_PORT_PCS_DW1_GRP_F)
> > +#define CNL_PORT_PCS_DW1_LN0(port)	_MMIO_PORT6(port, \
> > +						    _CNL_PORT_PCS_DW1_LN0_AE, \
> > +						    _CNL_PORT_PCS_DW1_LN0_B, \
> > +						    _CNL_PORT_PCS_DW1_LN0_C, \
> > +						    _CNL_PORT_PCS_DW1_LN0_D, \
> > +						    _CNL_PORT_PCS_DW1_LN0_AE, \
> > +						    _CNL_PORT_PCS_DW1_LN0_F)
> > +#define   COMMON_KEEPER_EN		(1 << 26)
> > +
> > +#define _CNL_PORT_TX_DW2_GRP_AE		0x162348
> > +#define _CNL_PORT_TX_DW2_GRP_B		0x1623C8
> > +#define _CNL_PORT_TX_DW2_GRP_C		0x162B48
> > +#define _CNL_PORT_TX_DW2_GRP_D		0x162BC8
> > +#define _CNL_PORT_TX_DW2_GRP_F		0x162A48
> > +#define _CNL_PORT_TX_DW2_LN0_AE		0x162448
> > +#define _CNL_PORT_TX_DW2_LN0_B		0x162648
> > +#define _CNL_PORT_TX_DW2_LN0_C		0x162C48
> > +#define _CNL_PORT_TX_DW2_LN0_D		0x162E48
> > +#define _CNL_PORT_TX_DW2_LN0_F		0x162A48
> > +#define CNL_PORT_TX_DW2_GRP(port)	_MMIO_PORT6(port, \
> > +						    _CNL_PORT_TX_DW2_GRP_AE, \
> > +						    _CNL_PORT_TX_DW2_GRP_B, \
> > +						    _CNL_PORT_TX_DW2_GRP_C, \
> > +						    _CNL_PORT_TX_DW2_GRP_D, \
> > +						    _CNL_PORT_TX_DW2_GRP_AE, \
> > +						    _CNL_PORT_TX_DW2_GRP_F)
> > +#define CNL_PORT_TX_DW2_LN0(port)	_MMIO_PORT6(port, \
> > +						    _CNL_PORT_TX_DW2_LN0_AE, \
> > +						    _CNL_PORT_TX_DW2_LN0_B, \
> > +						    _CNL_PORT_TX_DW2_LN0_C, \
> > +						    _CNL_PORT_TX_DW2_LN0_D, \
> > +						    _CNL_PORT_TX_DW2_LN0_AE, \
> > +						    _CNL_PORT_TX_DW2_LN0_F)
> > +#define   SWING_SEL_UPPER(x)		((x >> 3) << 15)
> > +#define   SWING_SEL_LOWER(x)		((x & 0x7) << 11)
> > +#define   RCOMP_SCALAR(x)		((x) << 0)
> > +
> > +#define _CNL_PORT_TX_DW4_GRP_AE		0x162350
> > +#define _CNL_PORT_TX_DW4_GRP_B		0x1623D0
> > +#define _CNL_PORT_TX_DW4_GRP_C		0x162B50
> > +#define _CNL_PORT_TX_DW4_GRP_D		0x162BD0
> > +#define _CNL_PORT_TX_DW4_GRP_F		0x162A50
> > +#define _CNL_PORT_TX_DW4_LN0_AE		0x162450
> > +#define _CNL_PORT_TX_DW4_LN1_AE		0x1624D0
> > +#define _CNL_PORT_TX_DW4_LN0_B		0x162650
> > +#define _CNL_PORT_TX_DW4_LN0_C		0x162C50
> > +#define _CNL_PORT_TX_DW4_LN0_D		0x162E50
> > +#define _CNL_PORT_TX_DW4_LN0_F		0x162850
> > +#define CNL_PORT_TX_DW4_GRP(port)       _MMIO_PORT6(port, \
> > +						    _CNL_PORT_TX_DW4_GRP_AE, \
> > +						    _CNL_PORT_TX_DW4_GRP_B, \
> > +						    _CNL_PORT_TX_DW4_GRP_C, \
> > +						    _CNL_PORT_TX_DW4_GRP_D, \
> > +						    _CNL_PORT_TX_DW4_GRP_AE, \
> > +						    _CNL_PORT_TX_DW4_GRP_F)
> > +#define CNL_PORT_TX_DW4_LN(port, ln)       _MMIO_PORT6_LN(port, ln,	\
> > +						    _CNL_PORT_TX_DW4_LN0_AE, \
> > +						    _CNL_PORT_TX_DW4_LN1_AE, \
> > +						    _CNL_PORT_TX_DW4_LN0_B, \
> > +						    _CNL_PORT_TX_DW4_LN0_C, \
> > +						    _CNL_PORT_TX_DW4_LN0_D, \
> > +						    _CNL_PORT_TX_DW4_LN0_AE, \
> > +						    _CNL_PORT_TX_DW4_LN0_F)
> > +#define   LOADGEN_SELECT		(1 << 31)
> > +#define   POST_CURSOR_1(x)		((x) << 12)
> > +#define   POST_CURSOR_2(x)		((x) << 6)
> > +#define   CURSOR_COEFF(x)		((x) << 0)
> > +
> > +#define _CNL_PORT_TX_DW5_GRP_AE		0x162354
> > +#define _CNL_PORT_TX_DW5_GRP_B		0x1623D4
> > +#define _CNL_PORT_TX_DW5_GRP_C		0x162B54
> > +#define _CNL_PORT_TX_DW5_GRP_D		0x162BD4
> > +#define _CNL_PORT_TX_DW5_GRP_F		0x162A54
> > +#define _CNL_PORT_TX_DW5_LN0_AE		0x162454
> > +#define _CNL_PORT_TX_DW5_LN0_B		0x162654
> > +#define _CNL_PORT_TX_DW5_LN0_C		0x162C54
> > +#define _CNL_PORT_TX_DW5_LN0_D		0x162ED4
> > +#define _CNL_PORT_TX_DW5_LN0_F		0x162854
> > +#define CNL_PORT_TX_DW5_GRP(port)	_MMIO_PORT6(port, \
> > +						    _CNL_PORT_TX_DW5_GRP_AE, \
> > +						    _CNL_PORT_TX_DW5_GRP_B, \
> > +						    _CNL_PORT_TX_DW5_GRP_C, \
> > +						    _CNL_PORT_TX_DW5_GRP_D, \
> > +						    _CNL_PORT_TX_DW5_GRP_AE, \
> > +						    _CNL_PORT_TX_DW5_GRP_F)
> > +#define CNL_PORT_TX_DW5_LN0(port)	_MMIO_PORT6(port, \
> > +						    _CNL_PORT_TX_DW5_LN0_AE, \
> > +						    _CNL_PORT_TX_DW5_LN0_B, \
> > +						    _CNL_PORT_TX_DW5_LN0_C, \
> > +						    _CNL_PORT_TX_DW5_LN0_D, \
> > +						    _CNL_PORT_TX_DW5_LN0_AE, \
> > +						    _CNL_PORT_TX_DW5_LN0_F)
> > +#define   TX_TRAINING_EN		(1 << 31)
> > +#define   TAP3_DISABLE			(1 << 29)
> > +#define   SCALING_MODE_SEL		(2<<18)
> 
> Even Scaling mode can be different for different platforms using the
> same set of registers. So instead of using a direct value,
> use SCALING_MODE_SEL(x)   ((x) << 18)

agreed. I will change in the next version...

> 
> Reviewed-by for everything else.
> 
> Manasi
> 
> > +#define   RTERM_SELECT(x)		((x) << 3)
> > +
> > +#define _CNL_PORT_TX_DW7_GRP_AE		0x16235C
> > +#define _CNL_PORT_TX_DW7_GRP_B		0x1623DC
> > +#define _CNL_PORT_TX_DW7_GRP_C		0x162B5C
> > +#define _CNL_PORT_TX_DW7_GRP_D		0x162BDC
> > +#define _CNL_PORT_TX_DW7_GRP_F		0x162A5C
> > +#define _CNL_PORT_TX_DW7_LN0_AE		0x16245C
> > +#define _CNL_PORT_TX_DW7_LN0_B		0x16265C
> > +#define _CNL_PORT_TX_DW7_LN0_C		0x162C5C
> > +#define _CNL_PORT_TX_DW7_LN0_D		0x162EDC
> > +#define _CNL_PORT_TX_DW7_LN0_F		0x16285C
> > +#define CNL_PORT_TX_DW7_GRP(port)	_MMIO_PORT6(port, \
> > +						    _CNL_PORT_TX_DW7_GRP_AE, \
> > +						    _CNL_PORT_TX_DW7_GRP_B, \
> > +						    _CNL_PORT_TX_DW7_GRP_C, \
> > +						    _CNL_PORT_TX_DW7_GRP_D, \
> > +						    _CNL_PORT_TX_DW7_GRP_AE, \
> > +						    _CNL_PORT_TX_DW7_GRP_F)
> > +#define CNL_PORT_TX_DW7_LN0(port)	_MMIO_PORT6(port, \
> > +						    _CNL_PORT_TX_DW7_LN0_AE, \
> > +						    _CNL_PORT_TX_DW7_LN0_B, \
> > +						    _CNL_PORT_TX_DW7_LN0_C, \
> > +						    _CNL_PORT_TX_DW7_LN0_D, \
> > +						    _CNL_PORT_TX_DW7_LN0_AE, \
> > +						    _CNL_PORT_TX_DW7_LN0_F)
> > +#define   N_SCALAR(x)			((x) << 24)
> > +
> >  /* The spec defines this only for BXT PHY0, but lets assume that this
> >   * would exist for PHY1 too if it had a second channel.
> >   */
> > -- 
> > 1.9.1
> > 

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Re: [PATCH 37/67] drm/i915/cnl: Add registers related to voltage swing sequences.

[Manasi Navare]

On Wed, May 17, 2017 at 05:59:02PM -0700, Manasi Navare wrote:
> On Thu, Apr 06, 2017 at 12:15:33PM -0700, Rodrigo Vivi wrote:
> > This are the registers and bits needed for the voltage swing
> > sequence on Cannonlake.
> > 
> > v2: Remove CL_DW5 that was wrongly defined.
> > v3: Use (1 << 1) instead of (1<<1) as Paulo suggested
> >     Change DW2 swing sel upper and lower macros to do the
> >     bit selection instead of definint a table that doesn't
> >     match the spec. It is based on a Manasi version of it.
> >     Credits-to: Manasi.
> > 
> > Cc: Paulo Zanoni <paulo.r.zanoni@intel.com>
> > Cc: Manasi Navare <manasi.d.navare@intel.com>
> > Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
> > ---
> >  drivers/gpu/drm/i915/i915_reg.h | 140 ++++++++++++++++++++++++++++++++++++++++
> >  1 file changed, 140 insertions(+)
> > 
> > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> > index 5777925..d4f7460 100644
> > --- a/drivers/gpu/drm/i915/i915_reg.h
> > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > @@ -1688,6 +1688,146 @@ enum skl_disp_power_wells {
> >  #define   OCL2_LDOFUSE_PWR_DIS		(1 << 6)
> >  #define BXT_PORT_CL1CM_DW30(phy)	_BXT_PHY((phy), _PORT_CL1CM_DW30_BC)
> >  
> > +#define _CNL_PORT_PCS_DW1_GRP_AE	0x162304
> > +#define _CNL_PORT_PCS_DW1_GRP_B		0x162384
> > +#define _CNL_PORT_PCS_DW1_GRP_C		0x162B04
> > +#define _CNL_PORT_PCS_DW1_GRP_D		0x162B84
> > +#define _CNL_PORT_PCS_DW1_GRP_F		0x162A04
> > +#define _CNL_PORT_PCS_DW1_LN0_AE	0x162404
> > +#define _CNL_PORT_PCS_DW1_LN0_B		0x162604
> > +#define _CNL_PORT_PCS_DW1_LN0_C		0x162C04
> > +#define _CNL_PORT_PCS_DW1_LN0_D		0x162E04
> > +#define _CNL_PORT_PCS_DW1_LN0_F		0x162804
> > +#define CNL_PORT_PCS_DW1_GRP(port)	_MMIO_PORT6(port, \
> > +						    _CNL_PORT_PCS_DW1_GRP_AE, \
> > +						    _CNL_PORT_PCS_DW1_GRP_B, \
> > +						    _CNL_PORT_PCS_DW1_GRP_C, \
> > +						    _CNL_PORT_PCS_DW1_GRP_D, \
> > +						    _CNL_PORT_PCS_DW1_GRP_AE, \
> > +						    _CNL_PORT_PCS_DW1_GRP_F)
> > +#define CNL_PORT_PCS_DW1_LN0(port)	_MMIO_PORT6(port, \
> > +						    _CNL_PORT_PCS_DW1_LN0_AE, \
> > +						    _CNL_PORT_PCS_DW1_LN0_B, \
> > +						    _CNL_PORT_PCS_DW1_LN0_C, \
> > +						    _CNL_PORT_PCS_DW1_LN0_D, \
> > +						    _CNL_PORT_PCS_DW1_LN0_AE, \
> > +						    _CNL_PORT_PCS_DW1_LN0_F)
> > +#define   COMMON_KEEPER_EN		(1 << 26)
> > +
> > +#define _CNL_PORT_TX_DW2_GRP_AE		0x162348
> > +#define _CNL_PORT_TX_DW2_GRP_B		0x1623C8
> > +#define _CNL_PORT_TX_DW2_GRP_C		0x162B48
> > +#define _CNL_PORT_TX_DW2_GRP_D		0x162BC8
> > +#define _CNL_PORT_TX_DW2_GRP_F		0x162A48
> > +#define _CNL_PORT_TX_DW2_LN0_AE		0x162448
> > +#define _CNL_PORT_TX_DW2_LN0_B		0x162648
> > +#define _CNL_PORT_TX_DW2_LN0_C		0x162C48
> > +#define _CNL_PORT_TX_DW2_LN0_D		0x162E48
> > +#define _CNL_PORT_TX_DW2_LN0_F		0x162A48
> > +#define CNL_PORT_TX_DW2_GRP(port)	_MMIO_PORT6(port, \
> > +						    _CNL_PORT_TX_DW2_GRP_AE, \
> > +						    _CNL_PORT_TX_DW2_GRP_B, \
> > +						    _CNL_PORT_TX_DW2_GRP_C, \
> > +						    _CNL_PORT_TX_DW2_GRP_D, \
> > +						    _CNL_PORT_TX_DW2_GRP_AE, \
> > +						    _CNL_PORT_TX_DW2_GRP_F)
> > +#define CNL_PORT_TX_DW2_LN0(port)	_MMIO_PORT6(port, \
> > +						    _CNL_PORT_TX_DW2_LN0_AE, \
> > +						    _CNL_PORT_TX_DW2_LN0_B, \
> > +						    _CNL_PORT_TX_DW2_LN0_C, \
> > +						    _CNL_PORT_TX_DW2_LN0_D, \
> > +						    _CNL_PORT_TX_DW2_LN0_AE, \
> > +						    _CNL_PORT_TX_DW2_LN0_F)
> > +#define   SWING_SEL_UPPER(x)		((x >> 3) << 15)
> > +#define   SWING_SEL_LOWER(x)		((x & 0x7) << 11)
> > +#define   RCOMP_SCALAR(x)		((x) << 0)
> > +
> > +#define _CNL_PORT_TX_DW4_GRP_AE		0x162350
> > +#define _CNL_PORT_TX_DW4_GRP_B		0x1623D0
> > +#define _CNL_PORT_TX_DW4_GRP_C		0x162B50
> > +#define _CNL_PORT_TX_DW4_GRP_D		0x162BD0
> > +#define _CNL_PORT_TX_DW4_GRP_F		0x162A50
> > +#define _CNL_PORT_TX_DW4_LN0_AE		0x162450
> > +#define _CNL_PORT_TX_DW4_LN1_AE		0x1624D0
> > +#define _CNL_PORT_TX_DW4_LN0_B		0x162650
> > +#define _CNL_PORT_TX_DW4_LN0_C		0x162C50
> > +#define _CNL_PORT_TX_DW4_LN0_D		0x162E50
> > +#define _CNL_PORT_TX_DW4_LN0_F		0x162850
> > +#define CNL_PORT_TX_DW4_GRP(port)       _MMIO_PORT6(port, \
> > +						    _CNL_PORT_TX_DW4_GRP_AE, \
> > +						    _CNL_PORT_TX_DW4_GRP_B, \
> > +						    _CNL_PORT_TX_DW4_GRP_C, \
> > +						    _CNL_PORT_TX_DW4_GRP_D, \
> > +						    _CNL_PORT_TX_DW4_GRP_AE, \
> > +						    _CNL_PORT_TX_DW4_GRP_F)
> > +#define CNL_PORT_TX_DW4_LN(port, ln)       _MMIO_PORT6_LN(port, ln,	\
> > +						    _CNL_PORT_TX_DW4_LN0_AE, \
> > +						    _CNL_PORT_TX_DW4_LN1_AE, \
> > +						    _CNL_PORT_TX_DW4_LN0_B, \
> > +						    _CNL_PORT_TX_DW4_LN0_C, \
> > +						    _CNL_PORT_TX_DW4_LN0_D, \
> > +						    _CNL_PORT_TX_DW4_LN0_AE, \
> > +						    _CNL_PORT_TX_DW4_LN0_F)
> > +#define   LOADGEN_SELECT		(1 << 31)
> > +#define   POST_CURSOR_1(x)		((x) << 12)
> > +#define   POST_CURSOR_2(x)		((x) << 6)
> > +#define   CURSOR_COEFF(x)		((x) << 0)
> > +
> > +#define _CNL_PORT_TX_DW5_GRP_AE		0x162354
> > +#define _CNL_PORT_TX_DW5_GRP_B		0x1623D4
> > +#define _CNL_PORT_TX_DW5_GRP_C		0x162B54
> > +#define _CNL_PORT_TX_DW5_GRP_D		0x162BD4
> > +#define _CNL_PORT_TX_DW5_GRP_F		0x162A54
> > +#define _CNL_PORT_TX_DW5_LN0_AE		0x162454
> > +#define _CNL_PORT_TX_DW5_LN0_B		0x162654
> > +#define _CNL_PORT_TX_DW5_LN0_C		0x162C54
> > +#define _CNL_PORT_TX_DW5_LN0_D		0x162ED4
> > +#define _CNL_PORT_TX_DW5_LN0_F		0x162854
> > +#define CNL_PORT_TX_DW5_GRP(port)	_MMIO_PORT6(port, \
> > +						    _CNL_PORT_TX_DW5_GRP_AE, \
> > +						    _CNL_PORT_TX_DW5_GRP_B, \
> > +						    _CNL_PORT_TX_DW5_GRP_C, \
> > +						    _CNL_PORT_TX_DW5_GRP_D, \
> > +						    _CNL_PORT_TX_DW5_GRP_AE, \
> > +						    _CNL_PORT_TX_DW5_GRP_F)
> > +#define CNL_PORT_TX_DW5_LN0(port)	_MMIO_PORT6(port, \
> > +						    _CNL_PORT_TX_DW5_LN0_AE, \
> > +						    _CNL_PORT_TX_DW5_LN0_B, \
> > +						    _CNL_PORT_TX_DW5_LN0_C, \
> > +						    _CNL_PORT_TX_DW5_LN0_D, \
> > +						    _CNL_PORT_TX_DW5_LN0_AE, \
> > +						    _CNL_PORT_TX_DW5_LN0_F)
> > +#define   TX_TRAINING_EN		(1 << 31)
> > +#define   TAP3_DISABLE			(1 << 29)
> > +#define   SCALING_MODE_SEL		(2<<18)
> 
> Even Scaling mode can be different for different platforms using the
> same set of registers. So instead of using a direct value,
> use SCALING_MODE_SEL(x)   ((x) << 18)
> 
> Reviewed-by for everything else.
> 
> Manasi
>

Hi Rodrigo,

Could you submit a new revision for this with suggested macro for SCALING_MODE_SEL?
I can rebase my ICL patches on top of that then and give r-b for this?

Manasi
 
> > +#define   RTERM_SELECT(x)		((x) << 3)
> > +
> > +#define _CNL_PORT_TX_DW7_GRP_AE		0x16235C
> > +#define _CNL_PORT_TX_DW7_GRP_B		0x1623DC
> > +#define _CNL_PORT_TX_DW7_GRP_C		0x162B5C
> > +#define _CNL_PORT_TX_DW7_GRP_D		0x162BDC
> > +#define _CNL_PORT_TX_DW7_GRP_F		0x162A5C
> > +#define _CNL_PORT_TX_DW7_LN0_AE		0x16245C
> > +#define _CNL_PORT_TX_DW7_LN0_B		0x16265C
> > +#define _CNL_PORT_TX_DW7_LN0_C		0x162C5C
> > +#define _CNL_PORT_TX_DW7_LN0_D		0x162EDC
> > +#define _CNL_PORT_TX_DW7_LN0_F		0x16285C
> > +#define CNL_PORT_TX_DW7_GRP(port)	_MMIO_PORT6(port, \
> > +						    _CNL_PORT_TX_DW7_GRP_AE, \
> > +						    _CNL_PORT_TX_DW7_GRP_B, \
> > +						    _CNL_PORT_TX_DW7_GRP_C, \
> > +						    _CNL_PORT_TX_DW7_GRP_D, \
> > +						    _CNL_PORT_TX_DW7_GRP_AE, \
> > +						    _CNL_PORT_TX_DW7_GRP_F)
> > +#define CNL_PORT_TX_DW7_LN0(port)	_MMIO_PORT6(port, \
> > +						    _CNL_PORT_TX_DW7_LN0_AE, \
> > +						    _CNL_PORT_TX_DW7_LN0_B, \
> > +						    _CNL_PORT_TX_DW7_LN0_C, \
> > +						    _CNL_PORT_TX_DW7_LN0_D, \
> > +						    _CNL_PORT_TX_DW7_LN0_AE, \
> > +						    _CNL_PORT_TX_DW7_LN0_F)
> > +#define   N_SCALAR(x)			((x) << 24)
> > +
> >  /* The spec defines this only for BXT PHY0, but lets assume that this
> >   * would exist for PHY1 too if it had a second channel.
> >   */
> > -- 
> > 1.9.1
> > 
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
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[PATCH] drm/i915/cnl: Add registers related to voltage swing sequences.

[Rodrigo Vivi]

This are the registers and bits needed for the voltage swing
sequence on Cannonlake.

v2: Remove CL_DW5 that was wrongly defined.
v3: Use (1 << 1) instead of (1<<1) as Paulo suggested
    Change DW2 swing sel upper and lower macros to do the
    bit selection instead of definint a table that doesn't
    match the spec. It is based on a Manasi version of it.
    Credits-to: Manasi.
v4: Let SCALING_MODE_SEL flexible. (Manasi)

Cc: Paulo Zanoni <paulo.r.zanoni@intel.com>
Cc: Manasi Navare <manasi.d.navare@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h | 140 ++++++++++++++++++++++++++++++++++++++++
 1 file changed, 140 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index bd59d92..1562cff 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -1696,6 +1696,146 @@ enum skl_disp_power_wells {
 #define   OCL2_LDOFUSE_PWR_DIS		(1 << 6)
 #define BXT_PORT_CL1CM_DW30(phy)	_BXT_PHY((phy), _PORT_CL1CM_DW30_BC)
 
+#define _CNL_PORT_PCS_DW1_GRP_AE	0x162304
+#define _CNL_PORT_PCS_DW1_GRP_B		0x162384
+#define _CNL_PORT_PCS_DW1_GRP_C		0x162B04
+#define _CNL_PORT_PCS_DW1_GRP_D		0x162B84
+#define _CNL_PORT_PCS_DW1_GRP_F		0x162A04
+#define _CNL_PORT_PCS_DW1_LN0_AE	0x162404
+#define _CNL_PORT_PCS_DW1_LN0_B		0x162604
+#define _CNL_PORT_PCS_DW1_LN0_C		0x162C04
+#define _CNL_PORT_PCS_DW1_LN0_D		0x162E04
+#define _CNL_PORT_PCS_DW1_LN0_F		0x162804
+#define CNL_PORT_PCS_DW1_GRP(port)	_MMIO_PORT6(port, \
+						    _CNL_PORT_PCS_DW1_GRP_AE, \
+						    _CNL_PORT_PCS_DW1_GRP_B, \
+						    _CNL_PORT_PCS_DW1_GRP_C, \
+						    _CNL_PORT_PCS_DW1_GRP_D, \
+						    _CNL_PORT_PCS_DW1_GRP_AE, \
+						    _CNL_PORT_PCS_DW1_GRP_F)
+#define CNL_PORT_PCS_DW1_LN0(port)	_MMIO_PORT6(port, \
+						    _CNL_PORT_PCS_DW1_LN0_AE, \
+						    _CNL_PORT_PCS_DW1_LN0_B, \
+						    _CNL_PORT_PCS_DW1_LN0_C, \
+						    _CNL_PORT_PCS_DW1_LN0_D, \
+						    _CNL_PORT_PCS_DW1_LN0_AE, \
+						    _CNL_PORT_PCS_DW1_LN0_F)
+#define   COMMON_KEEPER_EN		(1 << 26)
+
+#define _CNL_PORT_TX_DW2_GRP_AE		0x162348
+#define _CNL_PORT_TX_DW2_GRP_B		0x1623C8
+#define _CNL_PORT_TX_DW2_GRP_C		0x162B48
+#define _CNL_PORT_TX_DW2_GRP_D		0x162BC8
+#define _CNL_PORT_TX_DW2_GRP_F		0x162A48
+#define _CNL_PORT_TX_DW2_LN0_AE		0x162448
+#define _CNL_PORT_TX_DW2_LN0_B		0x162648
+#define _CNL_PORT_TX_DW2_LN0_C		0x162C48
+#define _CNL_PORT_TX_DW2_LN0_D		0x162E48
+#define _CNL_PORT_TX_DW2_LN0_F		0x162A48
+#define CNL_PORT_TX_DW2_GRP(port)	_MMIO_PORT6(port, \
+						    _CNL_PORT_TX_DW2_GRP_AE, \
+						    _CNL_PORT_TX_DW2_GRP_B, \
+						    _CNL_PORT_TX_DW2_GRP_C, \
+						    _CNL_PORT_TX_DW2_GRP_D, \
+						    _CNL_PORT_TX_DW2_GRP_AE, \
+						    _CNL_PORT_TX_DW2_GRP_F)
+#define CNL_PORT_TX_DW2_LN0(port)	_MMIO_PORT6(port, \
+						    _CNL_PORT_TX_DW2_LN0_AE, \
+						    _CNL_PORT_TX_DW2_LN0_B, \
+						    _CNL_PORT_TX_DW2_LN0_C, \
+						    _CNL_PORT_TX_DW2_LN0_D, \
+						    _CNL_PORT_TX_DW2_LN0_AE, \
+						    _CNL_PORT_TX_DW2_LN0_F)
+#define   SWING_SEL_UPPER(x)		((x >> 3) << 15)
+#define   SWING_SEL_LOWER(x)		((x & 0x7) << 11)
+#define   RCOMP_SCALAR(x)		((x) << 0)
+
+#define _CNL_PORT_TX_DW4_GRP_AE		0x162350
+#define _CNL_PORT_TX_DW4_GRP_B		0x1623D0
+#define _CNL_PORT_TX_DW4_GRP_C		0x162B50
+#define _CNL_PORT_TX_DW4_GRP_D		0x162BD0
+#define _CNL_PORT_TX_DW4_GRP_F		0x162A50
+#define _CNL_PORT_TX_DW4_LN0_AE		0x162450
+#define _CNL_PORT_TX_DW4_LN1_AE		0x1624D0
+#define _CNL_PORT_TX_DW4_LN0_B		0x162650
+#define _CNL_PORT_TX_DW4_LN0_C		0x162C50
+#define _CNL_PORT_TX_DW4_LN0_D		0x162E50
+#define _CNL_PORT_TX_DW4_LN0_F		0x162850
+#define CNL_PORT_TX_DW4_GRP(port)       _MMIO_PORT6(port, \
+						    _CNL_PORT_TX_DW4_GRP_AE, \
+						    _CNL_PORT_TX_DW4_GRP_B, \
+						    _CNL_PORT_TX_DW4_GRP_C, \
+						    _CNL_PORT_TX_DW4_GRP_D, \
+						    _CNL_PORT_TX_DW4_GRP_AE, \
+						    _CNL_PORT_TX_DW4_GRP_F)
+#define CNL_PORT_TX_DW4_LN(port, ln)       _MMIO_PORT6_LN(port, ln,	\
+						    _CNL_PORT_TX_DW4_LN0_AE, \
+						    _CNL_PORT_TX_DW4_LN1_AE, \
+						    _CNL_PORT_TX_DW4_LN0_B, \
+						    _CNL_PORT_TX_DW4_LN0_C, \
+						    _CNL_PORT_TX_DW4_LN0_D, \
+						    _CNL_PORT_TX_DW4_LN0_AE, \
+						    _CNL_PORT_TX_DW4_LN0_F)
+#define   LOADGEN_SELECT		(1 << 31)
+#define   POST_CURSOR_1(x)		((x) << 12)
+#define   POST_CURSOR_2(x)		((x) << 6)
+#define   CURSOR_COEFF(x)		((x) << 0)
+
+#define _CNL_PORT_TX_DW5_GRP_AE		0x162354
+#define _CNL_PORT_TX_DW5_GRP_B		0x1623D4
+#define _CNL_PORT_TX_DW5_GRP_C		0x162B54
+#define _CNL_PORT_TX_DW5_GRP_D		0x162BD4
+#define _CNL_PORT_TX_DW5_GRP_F		0x162A54
+#define _CNL_PORT_TX_DW5_LN0_AE		0x162454
+#define _CNL_PORT_TX_DW5_LN0_B		0x162654
+#define _CNL_PORT_TX_DW5_LN0_C		0x162C54
+#define _CNL_PORT_TX_DW5_LN0_D		0x162ED4
+#define _CNL_PORT_TX_DW5_LN0_F		0x162854
+#define CNL_PORT_TX_DW5_GRP(port)	_MMIO_PORT6(port, \
+						    _CNL_PORT_TX_DW5_GRP_AE, \
+						    _CNL_PORT_TX_DW5_GRP_B, \
+						    _CNL_PORT_TX_DW5_GRP_C, \
+						    _CNL_PORT_TX_DW5_GRP_D, \
+						    _CNL_PORT_TX_DW5_GRP_AE, \
+						    _CNL_PORT_TX_DW5_GRP_F)
+#define CNL_PORT_TX_DW5_LN0(port)	_MMIO_PORT6(port, \
+						    _CNL_PORT_TX_DW5_LN0_AE, \
+						    _CNL_PORT_TX_DW5_LN0_B, \
+						    _CNL_PORT_TX_DW5_LN0_C, \
+						    _CNL_PORT_TX_DW5_LN0_D, \
+						    _CNL_PORT_TX_DW5_LN0_AE, \
+						    _CNL_PORT_TX_DW5_LN0_F)
+#define   TX_TRAINING_EN		(1 << 31)
+#define   TAP3_DISABLE			(1 << 29)
+#define   SCALING_MODE_SEL		((x) << 18)
+#define   RTERM_SELECT(x)		((x) << 3)
+
+#define _CNL_PORT_TX_DW7_GRP_AE		0x16235C
+#define _CNL_PORT_TX_DW7_GRP_B		0x1623DC
+#define _CNL_PORT_TX_DW7_GRP_C		0x162B5C
+#define _CNL_PORT_TX_DW7_GRP_D		0x162BDC
+#define _CNL_PORT_TX_DW7_GRP_F		0x162A5C
+#define _CNL_PORT_TX_DW7_LN0_AE		0x16245C
+#define _CNL_PORT_TX_DW7_LN0_B		0x16265C
+#define _CNL_PORT_TX_DW7_LN0_C		0x162C5C
+#define _CNL_PORT_TX_DW7_LN0_D		0x162EDC
+#define _CNL_PORT_TX_DW7_LN0_F		0x16285C
+#define CNL_PORT_TX_DW7_GRP(port)	_MMIO_PORT6(port, \
+						    _CNL_PORT_TX_DW7_GRP_AE, \
+						    _CNL_PORT_TX_DW7_GRP_B, \
+						    _CNL_PORT_TX_DW7_GRP_C, \
+						    _CNL_PORT_TX_DW7_GRP_D, \
+						    _CNL_PORT_TX_DW7_GRP_AE, \
+						    _CNL_PORT_TX_DW7_GRP_F)
+#define CNL_PORT_TX_DW7_LN0(port)	_MMIO_PORT6(port, \
+						    _CNL_PORT_TX_DW7_LN0_AE, \
+						    _CNL_PORT_TX_DW7_LN0_B, \
+						    _CNL_PORT_TX_DW7_LN0_C, \
+						    _CNL_PORT_TX_DW7_LN0_D, \
+						    _CNL_PORT_TX_DW7_LN0_AE, \
+						    _CNL_PORT_TX_DW7_LN0_F)
+#define   N_SCALAR(x)			((x) << 24)
+
 /* The spec defines this only for BXT PHY0, but lets assume that this
  * would exist for PHY1 too if it had a second channel.
  */
-- 
1.9.1

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[PATCH] drm/i915/cnl: Add registers related to voltage swing sequences.

[Rodrigo Vivi]

This are the registers and bits needed for the voltage swing
sequence on Cannonlake.

v2: Remove CL_DW5 that was wrongly defined.
v3: Use (1 << 1) instead of (1<<1) as Paulo suggested
    Change DW2 swing sel upper and lower macros to do the
    bit selection instead of definint a table that doesn't
    match the spec. It is based on a Manasi version of it.
    Credits-to: Manasi.
v4: Let SCALING_MODE_SEL flexible. (Manasi)

Cc: Paulo Zanoni <paulo.r.zanoni@intel.com>
Cc: Manasi Navare <manasi.d.navare@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h | 140 ++++++++++++++++++++++++++++++++++++++++
 1 file changed, 140 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index bd59d92..0d2063e 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -1696,6 +1696,146 @@ enum skl_disp_power_wells {
 #define   OCL2_LDOFUSE_PWR_DIS		(1 << 6)
 #define BXT_PORT_CL1CM_DW30(phy)	_BXT_PHY((phy), _PORT_CL1CM_DW30_BC)
 
+#define _CNL_PORT_PCS_DW1_GRP_AE	0x162304
+#define _CNL_PORT_PCS_DW1_GRP_B		0x162384
+#define _CNL_PORT_PCS_DW1_GRP_C		0x162B04
+#define _CNL_PORT_PCS_DW1_GRP_D		0x162B84
+#define _CNL_PORT_PCS_DW1_GRP_F		0x162A04
+#define _CNL_PORT_PCS_DW1_LN0_AE	0x162404
+#define _CNL_PORT_PCS_DW1_LN0_B		0x162604
+#define _CNL_PORT_PCS_DW1_LN0_C		0x162C04
+#define _CNL_PORT_PCS_DW1_LN0_D		0x162E04
+#define _CNL_PORT_PCS_DW1_LN0_F		0x162804
+#define CNL_PORT_PCS_DW1_GRP(port)	_MMIO_PORT6(port, \
+						    _CNL_PORT_PCS_DW1_GRP_AE, \
+						    _CNL_PORT_PCS_DW1_GRP_B, \
+						    _CNL_PORT_PCS_DW1_GRP_C, \
+						    _CNL_PORT_PCS_DW1_GRP_D, \
+						    _CNL_PORT_PCS_DW1_GRP_AE, \
+						    _CNL_PORT_PCS_DW1_GRP_F)
+#define CNL_PORT_PCS_DW1_LN0(port)	_MMIO_PORT6(port, \
+						    _CNL_PORT_PCS_DW1_LN0_AE, \
+						    _CNL_PORT_PCS_DW1_LN0_B, \
+						    _CNL_PORT_PCS_DW1_LN0_C, \
+						    _CNL_PORT_PCS_DW1_LN0_D, \
+						    _CNL_PORT_PCS_DW1_LN0_AE, \
+						    _CNL_PORT_PCS_DW1_LN0_F)
+#define   COMMON_KEEPER_EN		(1 << 26)
+
+#define _CNL_PORT_TX_DW2_GRP_AE		0x162348
+#define _CNL_PORT_TX_DW2_GRP_B		0x1623C8
+#define _CNL_PORT_TX_DW2_GRP_C		0x162B48
+#define _CNL_PORT_TX_DW2_GRP_D		0x162BC8
+#define _CNL_PORT_TX_DW2_GRP_F		0x162A48
+#define _CNL_PORT_TX_DW2_LN0_AE		0x162448
+#define _CNL_PORT_TX_DW2_LN0_B		0x162648
+#define _CNL_PORT_TX_DW2_LN0_C		0x162C48
+#define _CNL_PORT_TX_DW2_LN0_D		0x162E48
+#define _CNL_PORT_TX_DW2_LN0_F		0x162A48
+#define CNL_PORT_TX_DW2_GRP(port)	_MMIO_PORT6(port, \
+						    _CNL_PORT_TX_DW2_GRP_AE, \
+						    _CNL_PORT_TX_DW2_GRP_B, \
+						    _CNL_PORT_TX_DW2_GRP_C, \
+						    _CNL_PORT_TX_DW2_GRP_D, \
+						    _CNL_PORT_TX_DW2_GRP_AE, \
+						    _CNL_PORT_TX_DW2_GRP_F)
+#define CNL_PORT_TX_DW2_LN0(port)	_MMIO_PORT6(port, \
+						    _CNL_PORT_TX_DW2_LN0_AE, \
+						    _CNL_PORT_TX_DW2_LN0_B, \
+						    _CNL_PORT_TX_DW2_LN0_C, \
+						    _CNL_PORT_TX_DW2_LN0_D, \
+						    _CNL_PORT_TX_DW2_LN0_AE, \
+						    _CNL_PORT_TX_DW2_LN0_F)
+#define   SWING_SEL_UPPER(x)		((x >> 3) << 15)
+#define   SWING_SEL_LOWER(x)		((x & 0x7) << 11)
+#define   RCOMP_SCALAR(x)		((x) << 0)
+
+#define _CNL_PORT_TX_DW4_GRP_AE		0x162350
+#define _CNL_PORT_TX_DW4_GRP_B		0x1623D0
+#define _CNL_PORT_TX_DW4_GRP_C		0x162B50
+#define _CNL_PORT_TX_DW4_GRP_D		0x162BD0
+#define _CNL_PORT_TX_DW4_GRP_F		0x162A50
+#define _CNL_PORT_TX_DW4_LN0_AE		0x162450
+#define _CNL_PORT_TX_DW4_LN1_AE		0x1624D0
+#define _CNL_PORT_TX_DW4_LN0_B		0x162650
+#define _CNL_PORT_TX_DW4_LN0_C		0x162C50
+#define _CNL_PORT_TX_DW4_LN0_D		0x162E50
+#define _CNL_PORT_TX_DW4_LN0_F		0x162850
+#define CNL_PORT_TX_DW4_GRP(port)       _MMIO_PORT6(port, \
+						    _CNL_PORT_TX_DW4_GRP_AE, \
+						    _CNL_PORT_TX_DW4_GRP_B, \
+						    _CNL_PORT_TX_DW4_GRP_C, \
+						    _CNL_PORT_TX_DW4_GRP_D, \
+						    _CNL_PORT_TX_DW4_GRP_AE, \
+						    _CNL_PORT_TX_DW4_GRP_F)
+#define CNL_PORT_TX_DW4_LN(port, ln)       _MMIO_PORT6_LN(port, ln,	\
+						    _CNL_PORT_TX_DW4_LN0_AE, \
+						    _CNL_PORT_TX_DW4_LN1_AE, \
+						    _CNL_PORT_TX_DW4_LN0_B, \
+						    _CNL_PORT_TX_DW4_LN0_C, \
+						    _CNL_PORT_TX_DW4_LN0_D, \
+						    _CNL_PORT_TX_DW4_LN0_AE, \
+						    _CNL_PORT_TX_DW4_LN0_F)
+#define   LOADGEN_SELECT		(1 << 31)
+#define   POST_CURSOR_1(x)		((x) << 12)
+#define   POST_CURSOR_2(x)		((x) << 6)
+#define   CURSOR_COEFF(x)		((x) << 0)
+
+#define _CNL_PORT_TX_DW5_GRP_AE		0x162354
+#define _CNL_PORT_TX_DW5_GRP_B		0x1623D4
+#define _CNL_PORT_TX_DW5_GRP_C		0x162B54
+#define _CNL_PORT_TX_DW5_GRP_D		0x162BD4
+#define _CNL_PORT_TX_DW5_GRP_F		0x162A54
+#define _CNL_PORT_TX_DW5_LN0_AE		0x162454
+#define _CNL_PORT_TX_DW5_LN0_B		0x162654
+#define _CNL_PORT_TX_DW5_LN0_C		0x162C54
+#define _CNL_PORT_TX_DW5_LN0_D		0x162ED4
+#define _CNL_PORT_TX_DW5_LN0_F		0x162854
+#define CNL_PORT_TX_DW5_GRP(port)	_MMIO_PORT6(port, \
+						    _CNL_PORT_TX_DW5_GRP_AE, \
+						    _CNL_PORT_TX_DW5_GRP_B, \
+						    _CNL_PORT_TX_DW5_GRP_C, \
+						    _CNL_PORT_TX_DW5_GRP_D, \
+						    _CNL_PORT_TX_DW5_GRP_AE, \
+						    _CNL_PORT_TX_DW5_GRP_F)
+#define CNL_PORT_TX_DW5_LN0(port)	_MMIO_PORT6(port, \
+						    _CNL_PORT_TX_DW5_LN0_AE, \
+						    _CNL_PORT_TX_DW5_LN0_B, \
+						    _CNL_PORT_TX_DW5_LN0_C, \
+						    _CNL_PORT_TX_DW5_LN0_D, \
+						    _CNL_PORT_TX_DW5_LN0_AE, \
+						    _CNL_PORT_TX_DW5_LN0_F)
+#define   TX_TRAINING_EN		(1 << 31)
+#define   TAP3_DISABLE			(1 << 29)
+#define   SCALING_MODE_SEL(x)		((x) << 18)
+#define   RTERM_SELECT(x)		((x) << 3)
+
+#define _CNL_PORT_TX_DW7_GRP_AE		0x16235C
+#define _CNL_PORT_TX_DW7_GRP_B		0x1623DC
+#define _CNL_PORT_TX_DW7_GRP_C		0x162B5C
+#define _CNL_PORT_TX_DW7_GRP_D		0x162BDC
+#define _CNL_PORT_TX_DW7_GRP_F		0x162A5C
+#define _CNL_PORT_TX_DW7_LN0_AE		0x16245C
+#define _CNL_PORT_TX_DW7_LN0_B		0x16265C
+#define _CNL_PORT_TX_DW7_LN0_C		0x162C5C
+#define _CNL_PORT_TX_DW7_LN0_D		0x162EDC
+#define _CNL_PORT_TX_DW7_LN0_F		0x16285C
+#define CNL_PORT_TX_DW7_GRP(port)	_MMIO_PORT6(port, \
+						    _CNL_PORT_TX_DW7_GRP_AE, \
+						    _CNL_PORT_TX_DW7_GRP_B, \
+						    _CNL_PORT_TX_DW7_GRP_C, \
+						    _CNL_PORT_TX_DW7_GRP_D, \
+						    _CNL_PORT_TX_DW7_GRP_AE, \
+						    _CNL_PORT_TX_DW7_GRP_F)
+#define CNL_PORT_TX_DW7_LN0(port)	_MMIO_PORT6(port, \
+						    _CNL_PORT_TX_DW7_LN0_AE, \
+						    _CNL_PORT_TX_DW7_LN0_B, \
+						    _CNL_PORT_TX_DW7_LN0_C, \
+						    _CNL_PORT_TX_DW7_LN0_D, \
+						    _CNL_PORT_TX_DW7_LN0_AE, \
+						    _CNL_PORT_TX_DW7_LN0_F)
+#define   N_SCALAR(x)			((x) << 24)
+
 /* The spec defines this only for BXT PHY0, but lets assume that this
  * would exist for PHY1 too if it had a second channel.
  */
-- 
1.9.1

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Re: [PATCH] drm/i915/cnl: Add registers related to voltage swing sequences.

[Manasi Navare]

On Mon, Jun 05, 2017 at 01:46:20PM -0700, Rodrigo Vivi wrote:
> This are the registers and bits needed for the voltage swing
> sequence on Cannonlake.
> 
> v2: Remove CL_DW5 that was wrongly defined.
> v3: Use (1 << 1) instead of (1<<1) as Paulo suggested
>     Change DW2 swing sel upper and lower macros to do the
>     bit selection instead of definint a table that doesn't
>     match the spec. It is based on a Manasi version of it.
>     Credits-to: Manasi.
> v4: Let SCALING_MODE_SEL flexible. (Manasi)
> 
> Cc: Paulo Zanoni <paulo.r.zanoni@intel.com>
> Cc: Manasi Navare <manasi.d.navare@intel.com>
> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
 Reviewed-by: Manasi Navare <manadi.d.navare@intel.com>
> ---
>  drivers/gpu/drm/i915/i915_reg.h | 140 ++++++++++++++++++++++++++++++++++++++++
>  1 file changed, 140 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index bd59d92..0d2063e 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -1696,6 +1696,146 @@ enum skl_disp_power_wells {
>  #define   OCL2_LDOFUSE_PWR_DIS		(1 << 6)
>  #define BXT_PORT_CL1CM_DW30(phy)	_BXT_PHY((phy), _PORT_CL1CM_DW30_BC)
>  
> +#define _CNL_PORT_PCS_DW1_GRP_AE	0x162304
> +#define _CNL_PORT_PCS_DW1_GRP_B		0x162384
> +#define _CNL_PORT_PCS_DW1_GRP_C		0x162B04
> +#define _CNL_PORT_PCS_DW1_GRP_D		0x162B84
> +#define _CNL_PORT_PCS_DW1_GRP_F		0x162A04
> +#define _CNL_PORT_PCS_DW1_LN0_AE	0x162404
> +#define _CNL_PORT_PCS_DW1_LN0_B		0x162604
> +#define _CNL_PORT_PCS_DW1_LN0_C		0x162C04
> +#define _CNL_PORT_PCS_DW1_LN0_D		0x162E04
> +#define _CNL_PORT_PCS_DW1_LN0_F		0x162804
> +#define CNL_PORT_PCS_DW1_GRP(port)	_MMIO_PORT6(port, \
> +						    _CNL_PORT_PCS_DW1_GRP_AE, \
> +						    _CNL_PORT_PCS_DW1_GRP_B, \
> +						    _CNL_PORT_PCS_DW1_GRP_C, \
> +						    _CNL_PORT_PCS_DW1_GRP_D, \
> +						    _CNL_PORT_PCS_DW1_GRP_AE, \
> +						    _CNL_PORT_PCS_DW1_GRP_F)
> +#define CNL_PORT_PCS_DW1_LN0(port)	_MMIO_PORT6(port, \
> +						    _CNL_PORT_PCS_DW1_LN0_AE, \
> +						    _CNL_PORT_PCS_DW1_LN0_B, \
> +						    _CNL_PORT_PCS_DW1_LN0_C, \
> +						    _CNL_PORT_PCS_DW1_LN0_D, \
> +						    _CNL_PORT_PCS_DW1_LN0_AE, \
> +						    _CNL_PORT_PCS_DW1_LN0_F)
> +#define   COMMON_KEEPER_EN		(1 << 26)
> +
> +#define _CNL_PORT_TX_DW2_GRP_AE		0x162348
> +#define _CNL_PORT_TX_DW2_GRP_B		0x1623C8
> +#define _CNL_PORT_TX_DW2_GRP_C		0x162B48
> +#define _CNL_PORT_TX_DW2_GRP_D		0x162BC8
> +#define _CNL_PORT_TX_DW2_GRP_F		0x162A48
> +#define _CNL_PORT_TX_DW2_LN0_AE		0x162448
> +#define _CNL_PORT_TX_DW2_LN0_B		0x162648
> +#define _CNL_PORT_TX_DW2_LN0_C		0x162C48
> +#define _CNL_PORT_TX_DW2_LN0_D		0x162E48
> +#define _CNL_PORT_TX_DW2_LN0_F		0x162A48
> +#define CNL_PORT_TX_DW2_GRP(port)	_MMIO_PORT6(port, \
> +						    _CNL_PORT_TX_DW2_GRP_AE, \
> +						    _CNL_PORT_TX_DW2_GRP_B, \
> +						    _CNL_PORT_TX_DW2_GRP_C, \
> +						    _CNL_PORT_TX_DW2_GRP_D, \
> +						    _CNL_PORT_TX_DW2_GRP_AE, \
> +						    _CNL_PORT_TX_DW2_GRP_F)
> +#define CNL_PORT_TX_DW2_LN0(port)	_MMIO_PORT6(port, \
> +						    _CNL_PORT_TX_DW2_LN0_AE, \
> +						    _CNL_PORT_TX_DW2_LN0_B, \
> +						    _CNL_PORT_TX_DW2_LN0_C, \
> +						    _CNL_PORT_TX_DW2_LN0_D, \
> +						    _CNL_PORT_TX_DW2_LN0_AE, \
> +						    _CNL_PORT_TX_DW2_LN0_F)
> +#define   SWING_SEL_UPPER(x)		((x >> 3) << 15)
> +#define   SWING_SEL_LOWER(x)		((x & 0x7) << 11)
> +#define   RCOMP_SCALAR(x)		((x) << 0)
> +
> +#define _CNL_PORT_TX_DW4_GRP_AE		0x162350
> +#define _CNL_PORT_TX_DW4_GRP_B		0x1623D0
> +#define _CNL_PORT_TX_DW4_GRP_C		0x162B50
> +#define _CNL_PORT_TX_DW4_GRP_D		0x162BD0
> +#define _CNL_PORT_TX_DW4_GRP_F		0x162A50
> +#define _CNL_PORT_TX_DW4_LN0_AE		0x162450
> +#define _CNL_PORT_TX_DW4_LN1_AE		0x1624D0
> +#define _CNL_PORT_TX_DW4_LN0_B		0x162650
> +#define _CNL_PORT_TX_DW4_LN0_C		0x162C50
> +#define _CNL_PORT_TX_DW4_LN0_D		0x162E50
> +#define _CNL_PORT_TX_DW4_LN0_F		0x162850
> +#define CNL_PORT_TX_DW4_GRP(port)       _MMIO_PORT6(port, \
> +						    _CNL_PORT_TX_DW4_GRP_AE, \
> +						    _CNL_PORT_TX_DW4_GRP_B, \
> +						    _CNL_PORT_TX_DW4_GRP_C, \
> +						    _CNL_PORT_TX_DW4_GRP_D, \
> +						    _CNL_PORT_TX_DW4_GRP_AE, \
> +						    _CNL_PORT_TX_DW4_GRP_F)
> +#define CNL_PORT_TX_DW4_LN(port, ln)       _MMIO_PORT6_LN(port, ln,	\
> +						    _CNL_PORT_TX_DW4_LN0_AE, \
> +						    _CNL_PORT_TX_DW4_LN1_AE, \
> +						    _CNL_PORT_TX_DW4_LN0_B, \
> +						    _CNL_PORT_TX_DW4_LN0_C, \
> +						    _CNL_PORT_TX_DW4_LN0_D, \
> +						    _CNL_PORT_TX_DW4_LN0_AE, \
> +						    _CNL_PORT_TX_DW4_LN0_F)
> +#define   LOADGEN_SELECT		(1 << 31)
> +#define   POST_CURSOR_1(x)		((x) << 12)
> +#define   POST_CURSOR_2(x)		((x) << 6)
> +#define   CURSOR_COEFF(x)		((x) << 0)
> +
> +#define _CNL_PORT_TX_DW5_GRP_AE		0x162354
> +#define _CNL_PORT_TX_DW5_GRP_B		0x1623D4
> +#define _CNL_PORT_TX_DW5_GRP_C		0x162B54
> +#define _CNL_PORT_TX_DW5_GRP_D		0x162BD4
> +#define _CNL_PORT_TX_DW5_GRP_F		0x162A54
> +#define _CNL_PORT_TX_DW5_LN0_AE		0x162454
> +#define _CNL_PORT_TX_DW5_LN0_B		0x162654
> +#define _CNL_PORT_TX_DW5_LN0_C		0x162C54
> +#define _CNL_PORT_TX_DW5_LN0_D		0x162ED4
> +#define _CNL_PORT_TX_DW5_LN0_F		0x162854
> +#define CNL_PORT_TX_DW5_GRP(port)	_MMIO_PORT6(port, \
> +						    _CNL_PORT_TX_DW5_GRP_AE, \
> +						    _CNL_PORT_TX_DW5_GRP_B, \
> +						    _CNL_PORT_TX_DW5_GRP_C, \
> +						    _CNL_PORT_TX_DW5_GRP_D, \
> +						    _CNL_PORT_TX_DW5_GRP_AE, \
> +						    _CNL_PORT_TX_DW5_GRP_F)
> +#define CNL_PORT_TX_DW5_LN0(port)	_MMIO_PORT6(port, \
> +						    _CNL_PORT_TX_DW5_LN0_AE, \
> +						    _CNL_PORT_TX_DW5_LN0_B, \
> +						    _CNL_PORT_TX_DW5_LN0_C, \
> +						    _CNL_PORT_TX_DW5_LN0_D, \
> +						    _CNL_PORT_TX_DW5_LN0_AE, \
> +						    _CNL_PORT_TX_DW5_LN0_F)
> +#define   TX_TRAINING_EN		(1 << 31)
> +#define   TAP3_DISABLE			(1 << 29)
> +#define   SCALING_MODE_SEL(x)		((x) << 18)
> +#define   RTERM_SELECT(x)		((x) << 3)
> +
> +#define _CNL_PORT_TX_DW7_GRP_AE		0x16235C
> +#define _CNL_PORT_TX_DW7_GRP_B		0x1623DC
> +#define _CNL_PORT_TX_DW7_GRP_C		0x162B5C
> +#define _CNL_PORT_TX_DW7_GRP_D		0x162BDC
> +#define _CNL_PORT_TX_DW7_GRP_F		0x162A5C
> +#define _CNL_PORT_TX_DW7_LN0_AE		0x16245C
> +#define _CNL_PORT_TX_DW7_LN0_B		0x16265C
> +#define _CNL_PORT_TX_DW7_LN0_C		0x162C5C
> +#define _CNL_PORT_TX_DW7_LN0_D		0x162EDC
> +#define _CNL_PORT_TX_DW7_LN0_F		0x16285C
> +#define CNL_PORT_TX_DW7_GRP(port)	_MMIO_PORT6(port, \
> +						    _CNL_PORT_TX_DW7_GRP_AE, \
> +						    _CNL_PORT_TX_DW7_GRP_B, \
> +						    _CNL_PORT_TX_DW7_GRP_C, \
> +						    _CNL_PORT_TX_DW7_GRP_D, \
> +						    _CNL_PORT_TX_DW7_GRP_AE, \
> +						    _CNL_PORT_TX_DW7_GRP_F)
> +#define CNL_PORT_TX_DW7_LN0(port)	_MMIO_PORT6(port, \
> +						    _CNL_PORT_TX_DW7_LN0_AE, \
> +						    _CNL_PORT_TX_DW7_LN0_B, \
> +						    _CNL_PORT_TX_DW7_LN0_C, \
> +						    _CNL_PORT_TX_DW7_LN0_D, \
> +						    _CNL_PORT_TX_DW7_LN0_AE, \
> +						    _CNL_PORT_TX_DW7_LN0_F)
> +#define   N_SCALAR(x)			((x) << 24)
> +
>  /* The spec defines this only for BXT PHY0, but lets assume that this
>   * would exist for PHY1 too if it had a second channel.
>   */
> -- 
> 1.9.1
> 
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[PATCH] drm/i915/cnl: Implement voltage swing sequence.

[Rodrigo Vivi]

This is an important part of the DDI initalization as well as
for changing the voltage during DisplayPort link training.

This new sequence for Cannonlake is more like Broxton style
but still with different registers, different table and
different steps.

v2: Do not write to DW4_GRP to avoid overwrite individual loadgen.
    Fix PORT_CL_DW5 SUS Clock Config set.
v3: As previous platforms use only eDP table if low voltage was
    requested.
v4: fix Werror:maybe uninitialized (Paulo)
v5: Rebase on top of dw2_swing_sel changes
    on previous patches.

Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h  |   1 +
 drivers/gpu/drm/i915/intel_ddi.c | 176 ++++++++++++++++++++++++++++++++++++++-
 drivers/gpu/drm/i915/intel_dp.c  |   2 +-
 3 files changed, 177 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 0d2063e..e61376f 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -1671,6 +1671,7 @@ enum skl_disp_power_wells {
 
 #define CNL_PORT_CL1CM_DW5		_MMIO(0x162014)
 #define   CL_POWER_DOWN_ENABLE		(1 << 4)
+#define   SUS_CLOCK_CONFIG		(3 << 0)
 
 #define _PORT_CL1CM_DW9_A		0x162024
 #define _PORT_CL1CM_DW9_BC		0x6C024
diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
index 9f34038..19f433e 100644
--- a/drivers/gpu/drm/i915/intel_ddi.c
+++ b/drivers/gpu/drm/i915/intel_ddi.c
@@ -1720,6 +1720,173 @@ u8 intel_ddi_dp_voltage_max(struct intel_encoder *encoder)
 		DP_TRAIN_VOLTAGE_SWING_MASK;
 }
 
+static const struct cnl_ddi_buf_trans *
+cnl_get_buf_trans_hdmi(struct drm_i915_private *dev_priv,
+		       u32 voltage, int *n_entries)
+{
+	if (voltage == VOLTAGE_INFO_0_85V) {
+		*n_entries = ARRAY_SIZE(cnl_ddi_translations_hdmi_0_85V);
+		return cnl_ddi_translations_hdmi_0_85V;
+	} else if (voltage == VOLTAGE_INFO_0_95V) {
+		*n_entries = ARRAY_SIZE(cnl_ddi_translations_hdmi_0_95V);
+		return cnl_ddi_translations_hdmi_0_95V;
+	} else if (voltage == VOLTAGE_INFO_1_05V) {
+		*n_entries = ARRAY_SIZE(cnl_ddi_translations_hdmi_1_05V);
+		return cnl_ddi_translations_hdmi_1_05V;
+	}
+	return NULL;
+}
+
+static const struct cnl_ddi_buf_trans *
+cnl_get_buf_trans_dp(struct drm_i915_private *dev_priv,
+		     u32 voltage, int *n_entries)
+{
+	if (voltage == VOLTAGE_INFO_0_85V) {
+		*n_entries = ARRAY_SIZE(cnl_ddi_translations_dp_0_85V);
+		return cnl_ddi_translations_dp_0_85V;
+	} else if (voltage == VOLTAGE_INFO_0_95V) {
+		*n_entries = ARRAY_SIZE(cnl_ddi_translations_dp_0_95V);
+		return cnl_ddi_translations_dp_0_95V;
+	} else if (voltage == VOLTAGE_INFO_1_05V) {
+		*n_entries = ARRAY_SIZE(cnl_ddi_translations_dp_1_05V);
+		return cnl_ddi_translations_dp_1_05V;
+	}
+	return NULL;
+}
+
+static const struct cnl_ddi_buf_trans *
+cnl_get_buf_trans_edp(struct drm_i915_private *dev_priv,
+		      u32 voltage, int *n_entries)
+{
+	if (dev_priv->vbt.edp.low_vswing) {
+		if (voltage == VOLTAGE_INFO_0_85V) {
+			*n_entries = ARRAY_SIZE(cnl_ddi_translations_edp_0_85V);
+			return cnl_ddi_translations_dp_0_85V;
+		} else if (voltage == VOLTAGE_INFO_0_95V) {
+			*n_entries = ARRAY_SIZE(cnl_ddi_translations_edp_0_95V);
+			return cnl_ddi_translations_edp_0_95V;
+		} else if (voltage == VOLTAGE_INFO_1_05V) {
+			*n_entries = ARRAY_SIZE(cnl_ddi_translations_edp_1_05V);
+			return cnl_ddi_translations_edp_1_05V;
+		}
+		return NULL;
+	} else {
+		return cnl_get_buf_trans_dp(dev_priv, voltage, n_entries);
+	}
+}
+
+static void cnl_ddi_vswing_program(struct drm_i915_private *dev_priv,
+				    u32 level, enum port port, int type)
+{
+	const struct cnl_ddi_buf_trans *ddi_translations = NULL;
+	u32 n_entries, val, voltage;
+	int ln;
+
+	/*
+	 * Values for each port type are listed in
+	 * voltage swing programming tables.
+	 * Vccio voltage found in PORT_COMP_DW3.
+	 */
+	voltage = I915_READ(CNL_PORT_COMP_DW3) & VOLTAGE_INFO_MASK;
+
+	if (type == INTEL_OUTPUT_HDMI) {
+		ddi_translations = cnl_get_buf_trans_hdmi(dev_priv,
+							  voltage, &n_entries);
+	} else if (type == INTEL_OUTPUT_DP) {
+		ddi_translations = cnl_get_buf_trans_dp(dev_priv,
+							voltage, &n_entries);
+	} else if (type == INTEL_OUTPUT_EDP) {
+		ddi_translations = cnl_get_buf_trans_edp(dev_priv,
+							 voltage, &n_entries);
+	}
+
+	if (ddi_translations == NULL) {
+		MISSING_CASE(voltage);
+		return;
+	}
+
+	if (level >= n_entries) {
+		DRM_DEBUG_KMS("DDI translation not found for level %d. Using %d instead.", level, n_entries - 1);
+		level = n_entries - 1;
+	}
+
+	/* Set PORT_TX_DW5 Scaling Mode Sel to 010b. */
+	val = I915_READ(CNL_PORT_TX_DW5_LN0(port));
+	val |= SCALING_MODE_SEL;
+	I915_WRITE(CNL_PORT_TX_DW5_GRP(port), val);
+
+	/* Program PORT_TX_DW2 */
+	val = I915_READ(CNL_PORT_TX_DW2_LN0(port));
+	val |= SWING_SEL_UPPER(ddi_translations[level].dw2_swing_sel);
+	val |= SWING_SEL_LOWER(ddi_translations[level].dw2_swing_sel);
+	/* Rcomp scalar is fixed as 0x98 for every table entry */
+	val |= RCOMP_SCALAR(0x98);
+	I915_WRITE(CNL_PORT_TX_DW2_GRP(port), val);
+
+        /* Program PORT_TX_DW4 */
+	/* We cannot write to GRP. It would overrite individual loadgen */
+	for (ln = 0; ln < 4; ln++) {
+		val = I915_READ(CNL_PORT_TX_DW4_LN(port, ln));
+		val |= POST_CURSOR_1(ddi_translations[level].dw4_post_cursor_1);
+		val |= POST_CURSOR_2(ddi_translations[level].dw4_post_cursor_2);
+		val |= CURSOR_COEFF(ddi_translations[level].dw4_cursor_coeff);
+		I915_WRITE(CNL_PORT_TX_DW4_LN(port, ln), val);
+	}
+
+        /* Program PORT_TX_DW5 */
+	/* All DW5 values are fixed for every table entry */
+	val = I915_READ(CNL_PORT_TX_DW5_LN0(port));
+	val |= RTERM_SELECT(6);
+	val |= TAP3_DISABLE;
+	I915_WRITE(CNL_PORT_TX_DW5_GRP(port), val);
+
+        /* Program PORT_TX_DW7 */
+	val = I915_READ(CNL_PORT_TX_DW7_LN0(port));
+	val |= N_SCALAR(ddi_translations[level].dw7_n_scalar);
+	I915_WRITE(CNL_PORT_TX_DW7_GRP(port), val);
+}
+
+static void cnl_ddi_vswing_sequence(struct drm_i915_private *dev_priv,
+				    u32 level, enum port port, int type)
+{
+	u32 val;
+
+	/*
+	 * 1. If port type is eDP or DP,
+	 * set PORT_PCS_DW1 cmnkeeper_enable to 1b,
+	 * else clear to 0b.
+	 */
+	val = I915_READ(CNL_PORT_PCS_DW1_LN0(port));
+	if (type == INTEL_OUTPUT_EDP || type == INTEL_OUTPUT_DP)
+		val |= COMMON_KEEPER_EN;
+	else
+		val &= ~COMMON_KEEPER_EN;
+	I915_WRITE(CNL_PORT_PCS_DW1_GRP(port), val);
+
+	/* 2. Program loadgen select */
+	/*
+	 * FIXME: Program PORT_TX_DW4_LN depending on Bit rate and used lanes
+	 */
+
+	/* 3. Set PORT_CL_DW5 SUS Clock Config to 11b */
+	val = I915_READ(CNL_PORT_CL1CM_DW5);
+	val |= SUS_CLOCK_CONFIG;
+	I915_WRITE(CNL_PORT_CL1CM_DW5, val);
+
+	/* 4. Clear training enable to change swing values */
+	val = I915_READ(CNL_PORT_TX_DW5_LN0(port));
+	val &= ~TX_TRAINING_EN;
+	I915_WRITE(CNL_PORT_TX_DW5_GRP(port), val);
+
+	/* 5. Program swing and de-emphasis */
+	cnl_ddi_vswing_program(dev_priv, level, port, type);
+
+	/* 6. Set training enable to trigger update */
+	val = I915_READ(CNL_PORT_TX_DW5_LN0(port));
+	val |= TX_TRAINING_EN;
+	I915_WRITE(CNL_PORT_TX_DW5_GRP(port), val);
+}
+
 static uint32_t translate_signal_level(int signal_levels)
 {
 	int i;
@@ -1752,7 +1919,11 @@ uint32_t ddi_signal_levels(struct intel_dp *intel_dp)
 		skl_ddi_set_iboost(encoder, level);
 	else if (IS_GEN9_LP(dev_priv))
 		bxt_ddi_vswing_sequence(dev_priv, level, port, encoder->type);
-
+	else if (IS_CANNONLAKE(dev_priv)) {
+		cnl_ddi_vswing_sequence(dev_priv, level, port, encoder->type);
+		/* DDI_BUF_CTL bits 27:24 are reserved on CNL */
+		return 0;
+	}
 	return DDI_BUF_TRANS_SELECT(level);
 }
 
@@ -1850,6 +2021,9 @@ static void intel_ddi_pre_enable_hdmi(struct intel_encoder *encoder,
 	else if (IS_GEN9_LP(dev_priv))
 		bxt_ddi_vswing_sequence(dev_priv, level, port,
 					INTEL_OUTPUT_HDMI);
+	else if (IS_CANNONLAKE(dev_priv))
+		cnl_ddi_vswing_sequence(dev_priv, level, port,
+					INTEL_OUTPUT_HDMI);
 
 	intel_hdmi->set_infoframes(drm_encoder,
 				   has_hdmi_sink,
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 1a27c72..ecf9dfc 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -3462,7 +3462,7 @@ static uint32_t chv_signal_levels(struct intel_dp *intel_dp)
 	if (HAS_DDI(dev_priv)) {
 		signal_levels = ddi_signal_levels(intel_dp);
 
-		if (IS_GEN9_LP(dev_priv))
+		if (IS_GEN9_LP(dev_priv) || IS_CANNONLAKE(dev_priv))
 			signal_levels = 0;
 		else
 			mask = DDI_BUF_EMP_MASK;
-- 
1.9.1

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[PATCH] drm/i915/cnl: Implement voltage swing sequence.

[Rodrigo Vivi]

This is an important part of the DDI initalization as well as
for changing the voltage during DisplayPort link training.

This new sequence for Cannonlake is more like Broxton style
but still with different registers, different table and
different steps.

v2: Do not write to DW4_GRP to avoid overwrite individual loadgen.
    Fix PORT_CL_DW5 SUS Clock Config set.
v3: As previous platforms use only eDP table if low voltage was
    requested.
v4: fix Werror:maybe uninitialized (Paulo)
v5: Rebase on top of dw2_swing_sel changes
    on previous patches.
v6: Using flexible SCALING_MODE_SEL(x).

Cc: Manasi Navare <manasi.d.navare@intel.com>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h  |   1 +
 drivers/gpu/drm/i915/intel_ddi.c | 176 ++++++++++++++++++++++++++++++++++++++-
 drivers/gpu/drm/i915/intel_dp.c  |   2 +-
 3 files changed, 177 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 0d2063e..e61376f 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -1671,6 +1671,7 @@ enum skl_disp_power_wells {
 
 #define CNL_PORT_CL1CM_DW5		_MMIO(0x162014)
 #define   CL_POWER_DOWN_ENABLE		(1 << 4)
+#define   SUS_CLOCK_CONFIG		(3 << 0)
 
 #define _PORT_CL1CM_DW9_A		0x162024
 #define _PORT_CL1CM_DW9_BC		0x6C024
diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
index 9f34038..56b0a2c 100644
--- a/drivers/gpu/drm/i915/intel_ddi.c
+++ b/drivers/gpu/drm/i915/intel_ddi.c
@@ -1720,6 +1720,173 @@ u8 intel_ddi_dp_voltage_max(struct intel_encoder *encoder)
 		DP_TRAIN_VOLTAGE_SWING_MASK;
 }
 
+static const struct cnl_ddi_buf_trans *
+cnl_get_buf_trans_hdmi(struct drm_i915_private *dev_priv,
+		       u32 voltage, int *n_entries)
+{
+	if (voltage == VOLTAGE_INFO_0_85V) {
+		*n_entries = ARRAY_SIZE(cnl_ddi_translations_hdmi_0_85V);
+		return cnl_ddi_translations_hdmi_0_85V;
+	} else if (voltage == VOLTAGE_INFO_0_95V) {
+		*n_entries = ARRAY_SIZE(cnl_ddi_translations_hdmi_0_95V);
+		return cnl_ddi_translations_hdmi_0_95V;
+	} else if (voltage == VOLTAGE_INFO_1_05V) {
+		*n_entries = ARRAY_SIZE(cnl_ddi_translations_hdmi_1_05V);
+		return cnl_ddi_translations_hdmi_1_05V;
+	}
+	return NULL;
+}
+
+static const struct cnl_ddi_buf_trans *
+cnl_get_buf_trans_dp(struct drm_i915_private *dev_priv,
+		     u32 voltage, int *n_entries)
+{
+	if (voltage == VOLTAGE_INFO_0_85V) {
+		*n_entries = ARRAY_SIZE(cnl_ddi_translations_dp_0_85V);
+		return cnl_ddi_translations_dp_0_85V;
+	} else if (voltage == VOLTAGE_INFO_0_95V) {
+		*n_entries = ARRAY_SIZE(cnl_ddi_translations_dp_0_95V);
+		return cnl_ddi_translations_dp_0_95V;
+	} else if (voltage == VOLTAGE_INFO_1_05V) {
+		*n_entries = ARRAY_SIZE(cnl_ddi_translations_dp_1_05V);
+		return cnl_ddi_translations_dp_1_05V;
+	}
+	return NULL;
+}
+
+static const struct cnl_ddi_buf_trans *
+cnl_get_buf_trans_edp(struct drm_i915_private *dev_priv,
+		      u32 voltage, int *n_entries)
+{
+	if (dev_priv->vbt.edp.low_vswing) {
+		if (voltage == VOLTAGE_INFO_0_85V) {
+			*n_entries = ARRAY_SIZE(cnl_ddi_translations_edp_0_85V);
+			return cnl_ddi_translations_dp_0_85V;
+		} else if (voltage == VOLTAGE_INFO_0_95V) {
+			*n_entries = ARRAY_SIZE(cnl_ddi_translations_edp_0_95V);
+			return cnl_ddi_translations_edp_0_95V;
+		} else if (voltage == VOLTAGE_INFO_1_05V) {
+			*n_entries = ARRAY_SIZE(cnl_ddi_translations_edp_1_05V);
+			return cnl_ddi_translations_edp_1_05V;
+		}
+		return NULL;
+	} else {
+		return cnl_get_buf_trans_dp(dev_priv, voltage, n_entries);
+	}
+}
+
+static void cnl_ddi_vswing_program(struct drm_i915_private *dev_priv,
+				    u32 level, enum port port, int type)
+{
+	const struct cnl_ddi_buf_trans *ddi_translations = NULL;
+	u32 n_entries, val, voltage;
+	int ln;
+
+	/*
+	 * Values for each port type are listed in
+	 * voltage swing programming tables.
+	 * Vccio voltage found in PORT_COMP_DW3.
+	 */
+	voltage = I915_READ(CNL_PORT_COMP_DW3) & VOLTAGE_INFO_MASK;
+
+	if (type == INTEL_OUTPUT_HDMI) {
+		ddi_translations = cnl_get_buf_trans_hdmi(dev_priv,
+							  voltage, &n_entries);
+	} else if (type == INTEL_OUTPUT_DP) {
+		ddi_translations = cnl_get_buf_trans_dp(dev_priv,
+							voltage, &n_entries);
+	} else if (type == INTEL_OUTPUT_EDP) {
+		ddi_translations = cnl_get_buf_trans_edp(dev_priv,
+							 voltage, &n_entries);
+	}
+
+	if (ddi_translations == NULL) {
+		MISSING_CASE(voltage);
+		return;
+	}
+
+	if (level >= n_entries) {
+		DRM_DEBUG_KMS("DDI translation not found for level %d. Using %d instead.", level, n_entries - 1);
+		level = n_entries - 1;
+	}
+
+	/* Set PORT_TX_DW5 Scaling Mode Sel to 010b. */
+	val = I915_READ(CNL_PORT_TX_DW5_LN0(port));
+	val |= SCALING_MODE_SEL(2);
+	I915_WRITE(CNL_PORT_TX_DW5_GRP(port), val);
+
+	/* Program PORT_TX_DW2 */
+	val = I915_READ(CNL_PORT_TX_DW2_LN0(port));
+	val |= SWING_SEL_UPPER(ddi_translations[level].dw2_swing_sel);
+	val |= SWING_SEL_LOWER(ddi_translations[level].dw2_swing_sel);
+	/* Rcomp scalar is fixed as 0x98 for every table entry */
+	val |= RCOMP_SCALAR(0x98);
+	I915_WRITE(CNL_PORT_TX_DW2_GRP(port), val);
+
+        /* Program PORT_TX_DW4 */
+	/* We cannot write to GRP. It would overrite individual loadgen */
+	for (ln = 0; ln < 4; ln++) {
+		val = I915_READ(CNL_PORT_TX_DW4_LN(port, ln));
+		val |= POST_CURSOR_1(ddi_translations[level].dw4_post_cursor_1);
+		val |= POST_CURSOR_2(ddi_translations[level].dw4_post_cursor_2);
+		val |= CURSOR_COEFF(ddi_translations[level].dw4_cursor_coeff);
+		I915_WRITE(CNL_PORT_TX_DW4_LN(port, ln), val);
+	}
+
+        /* Program PORT_TX_DW5 */
+	/* All DW5 values are fixed for every table entry */
+	val = I915_READ(CNL_PORT_TX_DW5_LN0(port));
+	val |= RTERM_SELECT(6);
+	val |= TAP3_DISABLE;
+	I915_WRITE(CNL_PORT_TX_DW5_GRP(port), val);
+
+        /* Program PORT_TX_DW7 */
+	val = I915_READ(CNL_PORT_TX_DW7_LN0(port));
+	val |= N_SCALAR(ddi_translations[level].dw7_n_scalar);
+	I915_WRITE(CNL_PORT_TX_DW7_GRP(port), val);
+}
+
+static void cnl_ddi_vswing_sequence(struct drm_i915_private *dev_priv,
+				    u32 level, enum port port, int type)
+{
+	u32 val;
+
+	/*
+	 * 1. If port type is eDP or DP,
+	 * set PORT_PCS_DW1 cmnkeeper_enable to 1b,
+	 * else clear to 0b.
+	 */
+	val = I915_READ(CNL_PORT_PCS_DW1_LN0(port));
+	if (type == INTEL_OUTPUT_EDP || type == INTEL_OUTPUT_DP)
+		val |= COMMON_KEEPER_EN;
+	else
+		val &= ~COMMON_KEEPER_EN;
+	I915_WRITE(CNL_PORT_PCS_DW1_GRP(port), val);
+
+	/* 2. Program loadgen select */
+	/*
+	 * FIXME: Program PORT_TX_DW4_LN depending on Bit rate and used lanes
+	 */
+
+	/* 3. Set PORT_CL_DW5 SUS Clock Config to 11b */
+	val = I915_READ(CNL_PORT_CL1CM_DW5);
+	val |= SUS_CLOCK_CONFIG;
+	I915_WRITE(CNL_PORT_CL1CM_DW5, val);
+
+	/* 4. Clear training enable to change swing values */
+	val = I915_READ(CNL_PORT_TX_DW5_LN0(port));
+	val &= ~TX_TRAINING_EN;
+	I915_WRITE(CNL_PORT_TX_DW5_GRP(port), val);
+
+	/* 5. Program swing and de-emphasis */
+	cnl_ddi_vswing_program(dev_priv, level, port, type);
+
+	/* 6. Set training enable to trigger update */
+	val = I915_READ(CNL_PORT_TX_DW5_LN0(port));
+	val |= TX_TRAINING_EN;
+	I915_WRITE(CNL_PORT_TX_DW5_GRP(port), val);
+}
+
 static uint32_t translate_signal_level(int signal_levels)
 {
 	int i;
@@ -1752,7 +1919,11 @@ uint32_t ddi_signal_levels(struct intel_dp *intel_dp)
 		skl_ddi_set_iboost(encoder, level);
 	else if (IS_GEN9_LP(dev_priv))
 		bxt_ddi_vswing_sequence(dev_priv, level, port, encoder->type);
-
+	else if (IS_CANNONLAKE(dev_priv)) {
+		cnl_ddi_vswing_sequence(dev_priv, level, port, encoder->type);
+		/* DDI_BUF_CTL bits 27:24 are reserved on CNL */
+		return 0;
+	}
 	return DDI_BUF_TRANS_SELECT(level);
 }
 
@@ -1850,6 +2021,9 @@ static void intel_ddi_pre_enable_hdmi(struct intel_encoder *encoder,
 	else if (IS_GEN9_LP(dev_priv))
 		bxt_ddi_vswing_sequence(dev_priv, level, port,
 					INTEL_OUTPUT_HDMI);
+	else if (IS_CANNONLAKE(dev_priv))
+		cnl_ddi_vswing_sequence(dev_priv, level, port,
+					INTEL_OUTPUT_HDMI);
 
 	intel_hdmi->set_infoframes(drm_encoder,
 				   has_hdmi_sink,
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 1a27c72..ecf9dfc 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -3462,7 +3462,7 @@ static uint32_t chv_signal_levels(struct intel_dp *intel_dp)
 	if (HAS_DDI(dev_priv)) {
 		signal_levels = ddi_signal_levels(intel_dp);
 
-		if (IS_GEN9_LP(dev_priv))
+		if (IS_GEN9_LP(dev_priv) || IS_CANNONLAKE(dev_priv))
 			signal_levels = 0;
 		else
 			mask = DDI_BUF_EMP_MASK;
-- 
1.9.1

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Re: [PATCH] drm/i915/cnl: Implement voltage swing sequence.

[Manasi Navare]

On Mon, Jun 05, 2017 at 01:53:07PM -0700, Rodrigo Vivi wrote:
> This is an important part of the DDI initalization as well as
> for changing the voltage during DisplayPort link training.
> 
> This new sequence for Cannonlake is more like Broxton style
> but still with different registers, different table and
> different steps.
> 
> v2: Do not write to DW4_GRP to avoid overwrite individual loadgen.
>     Fix PORT_CL_DW5 SUS Clock Config set.
> v3: As previous platforms use only eDP table if low voltage was
>     requested.
> v4: fix Werror:maybe uninitialized (Paulo)
> v5: Rebase on top of dw2_swing_sel changes
>     on previous patches.
> v6: Using flexible SCALING_MODE_SEL(x).
> 
> Cc: Manasi Navare <manasi.d.navare@intel.com>
> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
 Reviewed-by: Manasi Navare <manasi.d.navare@intel.com>


> ---
>  drivers/gpu/drm/i915/i915_reg.h  |   1 +
>  drivers/gpu/drm/i915/intel_ddi.c | 176 ++++++++++++++++++++++++++++++++++++++-
>  drivers/gpu/drm/i915/intel_dp.c  |   2 +-
>  3 files changed, 177 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 0d2063e..e61376f 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -1671,6 +1671,7 @@ enum skl_disp_power_wells {
>  
>  #define CNL_PORT_CL1CM_DW5		_MMIO(0x162014)
>  #define   CL_POWER_DOWN_ENABLE		(1 << 4)
> +#define   SUS_CLOCK_CONFIG		(3 << 0)
>  
>  #define _PORT_CL1CM_DW9_A		0x162024
>  #define _PORT_CL1CM_DW9_BC		0x6C024
> diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
> index 9f34038..56b0a2c 100644
> --- a/drivers/gpu/drm/i915/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/intel_ddi.c
> @@ -1720,6 +1720,173 @@ u8 intel_ddi_dp_voltage_max(struct intel_encoder *encoder)
>  		DP_TRAIN_VOLTAGE_SWING_MASK;
>  }
>  
> +static const struct cnl_ddi_buf_trans *
> +cnl_get_buf_trans_hdmi(struct drm_i915_private *dev_priv,
> +		       u32 voltage, int *n_entries)
> +{
> +	if (voltage == VOLTAGE_INFO_0_85V) {
> +		*n_entries = ARRAY_SIZE(cnl_ddi_translations_hdmi_0_85V);
> +		return cnl_ddi_translations_hdmi_0_85V;
> +	} else if (voltage == VOLTAGE_INFO_0_95V) {
> +		*n_entries = ARRAY_SIZE(cnl_ddi_translations_hdmi_0_95V);
> +		return cnl_ddi_translations_hdmi_0_95V;
> +	} else if (voltage == VOLTAGE_INFO_1_05V) {
> +		*n_entries = ARRAY_SIZE(cnl_ddi_translations_hdmi_1_05V);
> +		return cnl_ddi_translations_hdmi_1_05V;
> +	}
> +	return NULL;
> +}
> +
> +static const struct cnl_ddi_buf_trans *
> +cnl_get_buf_trans_dp(struct drm_i915_private *dev_priv,
> +		     u32 voltage, int *n_entries)
> +{
> +	if (voltage == VOLTAGE_INFO_0_85V) {
> +		*n_entries = ARRAY_SIZE(cnl_ddi_translations_dp_0_85V);
> +		return cnl_ddi_translations_dp_0_85V;
> +	} else if (voltage == VOLTAGE_INFO_0_95V) {
> +		*n_entries = ARRAY_SIZE(cnl_ddi_translations_dp_0_95V);
> +		return cnl_ddi_translations_dp_0_95V;
> +	} else if (voltage == VOLTAGE_INFO_1_05V) {
> +		*n_entries = ARRAY_SIZE(cnl_ddi_translations_dp_1_05V);
> +		return cnl_ddi_translations_dp_1_05V;
> +	}
> +	return NULL;
> +}
> +
> +static const struct cnl_ddi_buf_trans *
> +cnl_get_buf_trans_edp(struct drm_i915_private *dev_priv,
> +		      u32 voltage, int *n_entries)
> +{
> +	if (dev_priv->vbt.edp.low_vswing) {
> +		if (voltage == VOLTAGE_INFO_0_85V) {
> +			*n_entries = ARRAY_SIZE(cnl_ddi_translations_edp_0_85V);
> +			return cnl_ddi_translations_dp_0_85V;
> +		} else if (voltage == VOLTAGE_INFO_0_95V) {
> +			*n_entries = ARRAY_SIZE(cnl_ddi_translations_edp_0_95V);
> +			return cnl_ddi_translations_edp_0_95V;
> +		} else if (voltage == VOLTAGE_INFO_1_05V) {
> +			*n_entries = ARRAY_SIZE(cnl_ddi_translations_edp_1_05V);
> +			return cnl_ddi_translations_edp_1_05V;
> +		}
> +		return NULL;
> +	} else {
> +		return cnl_get_buf_trans_dp(dev_priv, voltage, n_entries);
> +	}
> +}
> +
> +static void cnl_ddi_vswing_program(struct drm_i915_private *dev_priv,
> +				    u32 level, enum port port, int type)
> +{
> +	const struct cnl_ddi_buf_trans *ddi_translations = NULL;
> +	u32 n_entries, val, voltage;
> +	int ln;
> +
> +	/*
> +	 * Values for each port type are listed in
> +	 * voltage swing programming tables.
> +	 * Vccio voltage found in PORT_COMP_DW3.
> +	 */
> +	voltage = I915_READ(CNL_PORT_COMP_DW3) & VOLTAGE_INFO_MASK;
> +
> +	if (type == INTEL_OUTPUT_HDMI) {
> +		ddi_translations = cnl_get_buf_trans_hdmi(dev_priv,
> +							  voltage, &n_entries);
> +	} else if (type == INTEL_OUTPUT_DP) {
> +		ddi_translations = cnl_get_buf_trans_dp(dev_priv,
> +							voltage, &n_entries);
> +	} else if (type == INTEL_OUTPUT_EDP) {
> +		ddi_translations = cnl_get_buf_trans_edp(dev_priv,
> +							 voltage, &n_entries);
> +	}
> +
> +	if (ddi_translations == NULL) {
> +		MISSING_CASE(voltage);
> +		return;
> +	}
> +
> +	if (level >= n_entries) {
> +		DRM_DEBUG_KMS("DDI translation not found for level %d. Using %d instead.", level, n_entries - 1);
> +		level = n_entries - 1;
> +	}
> +
> +	/* Set PORT_TX_DW5 Scaling Mode Sel to 010b. */
> +	val = I915_READ(CNL_PORT_TX_DW5_LN0(port));
> +	val |= SCALING_MODE_SEL(2);
> +	I915_WRITE(CNL_PORT_TX_DW5_GRP(port), val);
> +
> +	/* Program PORT_TX_DW2 */
> +	val = I915_READ(CNL_PORT_TX_DW2_LN0(port));
> +	val |= SWING_SEL_UPPER(ddi_translations[level].dw2_swing_sel);
> +	val |= SWING_SEL_LOWER(ddi_translations[level].dw2_swing_sel);
> +	/* Rcomp scalar is fixed as 0x98 for every table entry */
> +	val |= RCOMP_SCALAR(0x98);
> +	I915_WRITE(CNL_PORT_TX_DW2_GRP(port), val);
> +
> +        /* Program PORT_TX_DW4 */
> +	/* We cannot write to GRP. It would overrite individual loadgen */
> +	for (ln = 0; ln < 4; ln++) {
> +		val = I915_READ(CNL_PORT_TX_DW4_LN(port, ln));
> +		val |= POST_CURSOR_1(ddi_translations[level].dw4_post_cursor_1);
> +		val |= POST_CURSOR_2(ddi_translations[level].dw4_post_cursor_2);
> +		val |= CURSOR_COEFF(ddi_translations[level].dw4_cursor_coeff);
> +		I915_WRITE(CNL_PORT_TX_DW4_LN(port, ln), val);
> +	}
> +
> +        /* Program PORT_TX_DW5 */
> +	/* All DW5 values are fixed for every table entry */
> +	val = I915_READ(CNL_PORT_TX_DW5_LN0(port));
> +	val |= RTERM_SELECT(6);
> +	val |= TAP3_DISABLE;
> +	I915_WRITE(CNL_PORT_TX_DW5_GRP(port), val);
> +
> +        /* Program PORT_TX_DW7 */
> +	val = I915_READ(CNL_PORT_TX_DW7_LN0(port));
> +	val |= N_SCALAR(ddi_translations[level].dw7_n_scalar);
> +	I915_WRITE(CNL_PORT_TX_DW7_GRP(port), val);
> +}
> +
> +static void cnl_ddi_vswing_sequence(struct drm_i915_private *dev_priv,
> +				    u32 level, enum port port, int type)
> +{
> +	u32 val;
> +
> +	/*
> +	 * 1. If port type is eDP or DP,
> +	 * set PORT_PCS_DW1 cmnkeeper_enable to 1b,
> +	 * else clear to 0b.
> +	 */
> +	val = I915_READ(CNL_PORT_PCS_DW1_LN0(port));
> +	if (type == INTEL_OUTPUT_EDP || type == INTEL_OUTPUT_DP)
> +		val |= COMMON_KEEPER_EN;
> +	else
> +		val &= ~COMMON_KEEPER_EN;
> +	I915_WRITE(CNL_PORT_PCS_DW1_GRP(port), val);
> +
> +	/* 2. Program loadgen select */
> +	/*
> +	 * FIXME: Program PORT_TX_DW4_LN depending on Bit rate and used lanes
> +	 */
> +
> +	/* 3. Set PORT_CL_DW5 SUS Clock Config to 11b */
> +	val = I915_READ(CNL_PORT_CL1CM_DW5);
> +	val |= SUS_CLOCK_CONFIG;
> +	I915_WRITE(CNL_PORT_CL1CM_DW5, val);
> +
> +	/* 4. Clear training enable to change swing values */
> +	val = I915_READ(CNL_PORT_TX_DW5_LN0(port));
> +	val &= ~TX_TRAINING_EN;
> +	I915_WRITE(CNL_PORT_TX_DW5_GRP(port), val);
> +
> +	/* 5. Program swing and de-emphasis */
> +	cnl_ddi_vswing_program(dev_priv, level, port, type);
> +
> +	/* 6. Set training enable to trigger update */
> +	val = I915_READ(CNL_PORT_TX_DW5_LN0(port));
> +	val |= TX_TRAINING_EN;
> +	I915_WRITE(CNL_PORT_TX_DW5_GRP(port), val);
> +}
> +
>  static uint32_t translate_signal_level(int signal_levels)
>  {
>  	int i;
> @@ -1752,7 +1919,11 @@ uint32_t ddi_signal_levels(struct intel_dp *intel_dp)
>  		skl_ddi_set_iboost(encoder, level);
>  	else if (IS_GEN9_LP(dev_priv))
>  		bxt_ddi_vswing_sequence(dev_priv, level, port, encoder->type);
> -
> +	else if (IS_CANNONLAKE(dev_priv)) {
> +		cnl_ddi_vswing_sequence(dev_priv, level, port, encoder->type);
> +		/* DDI_BUF_CTL bits 27:24 are reserved on CNL */
> +		return 0;
> +	}
>  	return DDI_BUF_TRANS_SELECT(level);
>  }
>  
> @@ -1850,6 +2021,9 @@ static void intel_ddi_pre_enable_hdmi(struct intel_encoder *encoder,
>  	else if (IS_GEN9_LP(dev_priv))
>  		bxt_ddi_vswing_sequence(dev_priv, level, port,
>  					INTEL_OUTPUT_HDMI);
> +	else if (IS_CANNONLAKE(dev_priv))
> +		cnl_ddi_vswing_sequence(dev_priv, level, port,
> +					INTEL_OUTPUT_HDMI);
>  
>  	intel_hdmi->set_infoframes(drm_encoder,
>  				   has_hdmi_sink,
> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> index 1a27c72..ecf9dfc 100644
> --- a/drivers/gpu/drm/i915/intel_dp.c
> +++ b/drivers/gpu/drm/i915/intel_dp.c
> @@ -3462,7 +3462,7 @@ static uint32_t chv_signal_levels(struct intel_dp *intel_dp)
>  	if (HAS_DDI(dev_priv)) {
>  		signal_levels = ddi_signal_levels(intel_dp);
>  
> -		if (IS_GEN9_LP(dev_priv))
> +		if (IS_GEN9_LP(dev_priv) || IS_CANNONLAKE(dev_priv))
>  			signal_levels = 0;
>  		else
>  			mask = DDI_BUF_EMP_MASK;
> -- 
> 1.9.1
> 
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[PATCH 38/67] drm/i915/cnl: Add DDI Buffer translation tables for Cannonlake.

[Rodrigo Vivi]

These tables are used on voltage wswing sequence initialization
on Cannonlake.

It is a complete new format now in use by the voltage swing team,
not following any other standard in use by any other platform.
Also the registers are different as well. So let's redefine
the translation table for Cannonlake.

The table is huge. So we minimized with the fields that are
different or might be different anytime soon. The common
values will be hardcoded on the voltage swing sequence.

v2: Merge the lower and the upper bits to match the spec table
    and make review easier. This was possible with the good
    idea for Manasi with a better way to handle it on the bit
    macro definition presented on previous patch.
    Credits-to: Manasi

Cc: Manasi Navare <manasi.d.navare@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
---
 drivers/gpu/drm/i915/intel_ddi.c | 140 +++++++++++++++++++++++++++++++++++++++
 1 file changed, 140 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
index 2a901bf..3c31a22 100644
--- a/drivers/gpu/drm/i915/intel_ddi.c
+++ b/drivers/gpu/drm/i915/intel_ddi.c
@@ -353,6 +353,146 @@ struct bxt_ddi_buf_trans {
 	{ 154, 0x9A, 1, 128, true },	/* 9:	1200		0   */
 };
 
+struct cnl_ddi_buf_trans {
+	u32 dw2_swing_sel;
+	u32 dw7_n_scalar;
+	u32 dw4_cursor_coeff;
+	u32 dw4_post_cursor_2;
+	u32 dw4_post_cursor_1;
+};
+
+/* Voltage Swing Programming for VccIO 0.85V for DP */
+static const struct cnl_ddi_buf_trans cnl_ddi_translations_dp_0_85V[] = {
+						/* NT mV Trans mV db    */
+	{ 0xA, 0x5D, 0x3F, 0x00, 0x00 },	/* 350   350      0.0   */
+	{ 0xA, 0x6A, 0x38, 0x00, 0x07 },	/* 350   500      3.1   */
+	{ 0xB, 0x7A, 0x32, 0x00, 0x0D },	/* 350   700      6.0   */
+	{ 0x6, 0x7C, 0x2D, 0x00, 0x12 },	/* 350   900      8.2   */
+	{ 0xA, 0x69, 0x3F, 0x00, 0x00 },	/* 500   500      0.0   */
+	{ 0xB, 0x7A, 0x36, 0x00, 0x09 },	/* 500   700      2.9   */
+	{ 0x6, 0x7C, 0x30, 0x00, 0x0F },	/* 500   900      5.1   */
+	{ 0xB, 0x7D, 0x3C, 0x00, 0x03 },	/* 650   725      0.9   */
+	{ 0x6, 0x7C, 0x34, 0x00, 0x0B },	/* 600   900      3.5   */
+	{ 0x6, 0x7B, 0x3F, 0x00, 0x00 },	/* 900   900      0.0   */
+};
+
+/* Voltage Swing Programming for VccIO 0.85V for HDMI */
+static const struct cnl_ddi_buf_trans cnl_ddi_translations_hdmi_0_85V[] = {
+						/* NT mV Trans mV db    */
+	{ 0xA, 0x60, 0x3F, 0x00, 0x00 },	/* 450   450      0.0   */
+	{ 0xB, 0x73, 0x36, 0x00, 0x09 },	/* 450   650      3.2   */
+	{ 0x6, 0x7F, 0x31, 0x00, 0x0E },	/* 450   850      5.5   */
+	{ 0xB, 0x73, 0x3F, 0x00, 0x00 },	/* 650   650      0.0   */
+	{ 0x6, 0x7F, 0x37, 0x00, 0x08 },	/* 650   850      2.3   */
+	{ 0x6, 0x7F, 0x3F, 0x00, 0x00 },	/* 850   850      0.0   */
+	{ 0x6, 0x7F, 0x35, 0x00, 0x0A },	/* 600   850      3.0   */
+};
+
+/* Voltage Swing Programming for VccIO 0.85V for eDP */
+static const struct cnl_ddi_buf_trans cnl_ddi_translations_edp_0_85V[] = {
+						/* NT mV Trans mV db    */
+	{ 0xA, 0x66, 0x3A, 0x00, 0x05 },	/* 384   500      2.3   */
+	{ 0x0, 0x7F, 0x38, 0x00, 0x07 },	/* 153   200      2.3   */
+	{ 0x8, 0x7F, 0x38, 0x00, 0x07 },	/* 192   250      2.3   */
+	{ 0x1, 0x7F, 0x38, 0x00, 0x07 },	/* 230   300      2.3   */
+	{ 0x9, 0x7F, 0x38, 0x00, 0x07 },	/* 269   350      2.3   */
+	{ 0xA, 0x66, 0x3C, 0x00, 0x03 },	/* 446   500      1.0   */
+	{ 0xB, 0x70, 0x3C, 0x00, 0x03 },	/* 460   600      2.3   */
+	{ 0xC, 0x75, 0x3C, 0x00, 0x03 },	/* 537   700      2.3   */
+	{ 0x2, 0x7F, 0x3F, 0x00, 0x00 },	/* 400   400      0.0   */
+};
+
+/* Voltage Swing Programming for VccIO 0.95V for DP */
+static const struct cnl_ddi_buf_trans cnl_ddi_translations_dp_0_95V[] = {
+						/* NT mV Trans mV db    */
+	{ 0xA, 0x5D, 0x3F, 0x00, 0x00 },	/* 350   350      0.0   */
+	{ 0xA, 0x6A, 0x38, 0x00, 0x07 },	/* 350   500      3.1   */
+	{ 0xB, 0x7A, 0x32, 0x00, 0x0D },	/* 350   700      6.0   */
+	{ 0x6, 0x7C, 0x2D, 0x00, 0x12 },	/* 350   900      8.2   */
+	{ 0xA, 0x69, 0x3F, 0x00, 0x00 },	/* 500   500      0.0   */
+	{ 0xB, 0x7A, 0x36, 0x00, 0x09 },	/* 500   700      2.9   */
+	{ 0x6, 0x7C, 0x30, 0x00, 0x0F },	/* 500   900      5.1   */
+	{ 0xB, 0x7D, 0x3C, 0x00, 0x03 },	/* 650   725      0.9   */
+	{ 0x6, 0x7C, 0x34, 0x00, 0x0B },	/* 600   900      3.5   */
+	{ 0x6, 0x7B, 0x3F, 0x00, 0x00 },	/* 900   900      0.0   */
+};
+
+/* Voltage Swing Programming for VccIO 0.95V for HDMI */
+static const struct cnl_ddi_buf_trans cnl_ddi_translations_hdmi_0_95V[] = {
+						/* NT mV Trans mV db    */
+	{ 0xA, 0x5C, 0x3F, 0x00, 0x00 },	/* 400   400      0.0   */
+	{ 0xB, 0x69, 0x37, 0x00, 0x08 },	/* 400   600      3.5   */
+	{ 0x5, 0x76, 0x31, 0x00, 0x0E },	/* 400   800      6.0   */
+	{ 0xA, 0x5E, 0x3F, 0x00, 0x00 },	/* 450   450      0.0   */
+	{ 0xB, 0x69, 0x3F, 0x00, 0x00 },	/* 600   600      0.0   */
+	{ 0xB, 0x79, 0x35, 0x00, 0x0A },	/* 600   850      3.0   */
+	{ 0x6, 0x7D, 0x32, 0x00, 0x0D },	/* 600   1000     4.4   */
+	{ 0x5, 0x76, 0x3F, 0x00, 0x00 },	/* 800   800      0.0   */
+	{ 0x6, 0x7D, 0x39, 0x00, 0x06 },	/* 800   1000     1.9   */
+	{ 0x6, 0x7F, 0x39, 0x00, 0x06 },	/* 850   1050     1.8   */
+	{ 0x6, 0x7F, 0x3F, 0x00, 0x00 },	/* 1050  1050     0.0   */
+};
+
+/* Voltage Swing Programming for VccIO 0.95V for eDP */
+static const struct cnl_ddi_buf_trans cnl_ddi_translations_edp_0_95V[] = {
+						/* NT mV Trans mV db    */
+	{ 0xA, 0x61, 0x3A, 0x00, 0x05 },	/* 384   500      2.3   */
+	{ 0x0, 0x7F, 0x38, 0x00, 0x07 },	/* 153   200      2.3   */
+	{ 0x8, 0x7F, 0x38, 0x00, 0x07 },	/* 192   250      2.3   */
+	{ 0x1, 0x7F, 0x38, 0x00, 0x07 },	/* 230   300      2.3   */
+	{ 0x9, 0x7F, 0x38, 0x00, 0x07 },	/* 269   350      2.3   */
+	{ 0xA, 0x61, 0x3C, 0x00, 0x03 },	/* 446   500      1.0   */
+	{ 0xB, 0x68, 0x39, 0x00, 0x06 },	/* 460   600      2.3   */
+	{ 0xC, 0x6E, 0x39, 0x00, 0x06 },	/* 537   700      2.3   */
+	{ 0x4, 0x7F, 0x3A, 0x00, 0x05 },	/* 460   600      2.3   */
+	{ 0x2, 0x7F, 0x3F, 0x00, 0x00 },	/* 400   400      0.0   */
+};
+
+/* Voltage Swing Programming for VccIO 1.05V for DP */
+static const struct cnl_ddi_buf_trans cnl_ddi_translations_dp_1_05V[] = {
+						/* NT mV Trans mV db    */
+	{ 0xA, 0x58, 0x3F, 0x00, 0x00 },	/* 400   400      0.0   */
+	{ 0xB, 0x64, 0x37, 0x00, 0x08 },	/* 400   600      3.5   */
+	{ 0x5, 0x70, 0x31, 0x00, 0x0E },	/* 400   800      6.0   */
+	{ 0x6, 0x7F, 0x2C, 0x00, 0x13 },	/* 400   1050     8.4   */
+	{ 0xB, 0x64, 0x3F, 0x00, 0x00 },	/* 600   600      0.0   */
+	{ 0x5, 0x73, 0x35, 0x00, 0x0A },	/* 600   850      3.0   */
+	{ 0x6, 0x7F, 0x30, 0x00, 0x0F },	/* 550   1050     5.6   */
+	{ 0x5, 0x76, 0x3E, 0x00, 0x01 },	/* 850   900      0.5   */
+	{ 0x6, 0x7F, 0x36, 0x00, 0x09 },	/* 750   1050     2.9   */
+	{ 0x6, 0x7F, 0x3F, 0x00, 0x00 },	/* 1050  1050     0.0   */
+};
+
+/* Voltage Swing Programming for VccIO 1.05V for HDMI */
+static const struct cnl_ddi_buf_trans cnl_ddi_translations_hdmi_1_05V[] = {
+						/* NT mV Trans mV db    */
+	{ 0xA, 0x58, 0x3F, 0x00, 0x00 },	/* 400   400      0.0   */
+	{ 0xB, 0x64, 0x37, 0x00, 0x08 },	/* 400   600      3.5   */
+	{ 0x5, 0x70, 0x31, 0x00, 0x0E },	/* 400   800      6.0   */
+	{ 0xA, 0x5B, 0x3F, 0x00, 0x00 },	/* 450   450      0.0   */
+	{ 0xB, 0x64, 0x3F, 0x00, 0x00 },	/* 600   600      0.0   */
+	{ 0x5, 0x73, 0x35, 0x00, 0x0A },	/* 600   850      3.0   */
+	{ 0x6, 0x7C, 0x32, 0x00, 0x0D },	/* 600   1000     4.4   */
+	{ 0x5, 0x70, 0x3F, 0x00, 0x00 },	/* 800   800      0.0   */
+	{ 0x6, 0x7C, 0x39, 0x00, 0x06 },	/* 800   1000     1.9   */
+	{ 0x6, 0x7F, 0x39, 0x00, 0x06 },	/* 850   1050     1.8   */
+	{ 0x6, 0x7F, 0x3F, 0x00, 0x00 },	/* 1050  1050     0.0   */
+};
+
+/* Voltage Swing Programming for VccIO 1.05V for eDP */
+static const struct cnl_ddi_buf_trans cnl_ddi_translations_edp_1_05V[] = {
+						/* NT mV Trans mV db    */
+	{ 0xA, 0x5E, 0x3A, 0x00, 0x05 },	/* 384   500      2.3   */
+	{ 0x0, 0x7F, 0x38, 0x00, 0x07 },	/* 153   200      2.3   */
+	{ 0x8, 0x7F, 0x38, 0x00, 0x07 },	/* 192   250      2.3   */
+	{ 0x1, 0x7F, 0x38, 0x00, 0x07 },	/* 230   300      2.3   */
+	{ 0x9, 0x7F, 0x38, 0x00, 0x07 },	/* 269   350      2.3   */
+	{ 0xA, 0x5E, 0x3C, 0x00, 0x03 },	/* 446   500      1.0   */
+	{ 0xB, 0x64, 0x39, 0x00, 0x06 },	/* 460   600      2.3   */
+	{ 0xE, 0x6A, 0x39, 0x00, 0x06 },	/* 537   700      2.3   */
+	{ 0x2, 0x7F, 0x3F, 0x00, 0x00 },	/* 400   400      0.0   */
+};
+
 enum port intel_ddi_get_encoder_port(struct intel_encoder *encoder)
 {
 	switch (encoder->type) {
-- 
1.9.1

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Re: [PATCH 38/67] drm/i915/cnl: Add DDI Buffer translation tables for Cannonlake.

[Manasi Navare]

On Thu, Apr 06, 2017 at 12:15:34PM -0700, Rodrigo Vivi wrote:
> These tables are used on voltage wswing sequence initialization
> on Cannonlake.
> 
> It is a complete new format now in use by the voltage swing team,
> not following any other standard in use by any other platform.
> Also the registers are different as well. So let's redefine
> the translation table for Cannonlake.
> 
> The table is huge. So we minimized with the fields that are
> different or might be different anytime soon. The common
> values will be hardcoded on the voltage swing sequence.
> 
> v2: Merge the lower and the upper bits to match the spec table
>     and make review easier. This was possible with the good
>     idea for Manasi with a better way to handle it on the bit
>     macro definition presented on previous patch.
>     Credits-to: Manasi
>

The translation table values were verified against Bspec.

So Reviewed-by: Manasi Navare <manasi.d.navare@intel.com> 
> Cc: Manasi Navare <manasi.d.navare@intel.com>
> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
> ---
>  drivers/gpu/drm/i915/intel_ddi.c | 140 +++++++++++++++++++++++++++++++++++++++
>  1 file changed, 140 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
> index 2a901bf..3c31a22 100644
> --- a/drivers/gpu/drm/i915/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/intel_ddi.c
> @@ -353,6 +353,146 @@ struct bxt_ddi_buf_trans {
>  	{ 154, 0x9A, 1, 128, true },	/* 9:	1200		0   */
>  };
>  
> +struct cnl_ddi_buf_trans {
> +	u32 dw2_swing_sel;
> +	u32 dw7_n_scalar;
> +	u32 dw4_cursor_coeff;
> +	u32 dw4_post_cursor_2;
> +	u32 dw4_post_cursor_1;
> +};
> +
> +/* Voltage Swing Programming for VccIO 0.85V for DP */
> +static const struct cnl_ddi_buf_trans cnl_ddi_translations_dp_0_85V[] = {
> +						/* NT mV Trans mV db    */
> +	{ 0xA, 0x5D, 0x3F, 0x00, 0x00 },	/* 350   350      0.0   */
> +	{ 0xA, 0x6A, 0x38, 0x00, 0x07 },	/* 350   500      3.1   */
> +	{ 0xB, 0x7A, 0x32, 0x00, 0x0D },	/* 350   700      6.0   */
> +	{ 0x6, 0x7C, 0x2D, 0x00, 0x12 },	/* 350   900      8.2   */
> +	{ 0xA, 0x69, 0x3F, 0x00, 0x00 },	/* 500   500      0.0   */
> +	{ 0xB, 0x7A, 0x36, 0x00, 0x09 },	/* 500   700      2.9   */
> +	{ 0x6, 0x7C, 0x30, 0x00, 0x0F },	/* 500   900      5.1   */
> +	{ 0xB, 0x7D, 0x3C, 0x00, 0x03 },	/* 650   725      0.9   */
> +	{ 0x6, 0x7C, 0x34, 0x00, 0x0B },	/* 600   900      3.5   */
> +	{ 0x6, 0x7B, 0x3F, 0x00, 0x00 },	/* 900   900      0.0   */
> +};
> +
> +/* Voltage Swing Programming for VccIO 0.85V for HDMI */
> +static const struct cnl_ddi_buf_trans cnl_ddi_translations_hdmi_0_85V[] = {
> +						/* NT mV Trans mV db    */
> +	{ 0xA, 0x60, 0x3F, 0x00, 0x00 },	/* 450   450      0.0   */
> +	{ 0xB, 0x73, 0x36, 0x00, 0x09 },	/* 450   650      3.2   */
> +	{ 0x6, 0x7F, 0x31, 0x00, 0x0E },	/* 450   850      5.5   */
> +	{ 0xB, 0x73, 0x3F, 0x00, 0x00 },	/* 650   650      0.0   */
> +	{ 0x6, 0x7F, 0x37, 0x00, 0x08 },	/* 650   850      2.3   */
> +	{ 0x6, 0x7F, 0x3F, 0x00, 0x00 },	/* 850   850      0.0   */
> +	{ 0x6, 0x7F, 0x35, 0x00, 0x0A },	/* 600   850      3.0   */
> +};
> +
> +/* Voltage Swing Programming for VccIO 0.85V for eDP */
> +static const struct cnl_ddi_buf_trans cnl_ddi_translations_edp_0_85V[] = {
> +						/* NT mV Trans mV db    */
> +	{ 0xA, 0x66, 0x3A, 0x00, 0x05 },	/* 384   500      2.3   */
> +	{ 0x0, 0x7F, 0x38, 0x00, 0x07 },	/* 153   200      2.3   */
> +	{ 0x8, 0x7F, 0x38, 0x00, 0x07 },	/* 192   250      2.3   */
> +	{ 0x1, 0x7F, 0x38, 0x00, 0x07 },	/* 230   300      2.3   */
> +	{ 0x9, 0x7F, 0x38, 0x00, 0x07 },	/* 269   350      2.3   */
> +	{ 0xA, 0x66, 0x3C, 0x00, 0x03 },	/* 446   500      1.0   */
> +	{ 0xB, 0x70, 0x3C, 0x00, 0x03 },	/* 460   600      2.3   */
> +	{ 0xC, 0x75, 0x3C, 0x00, 0x03 },	/* 537   700      2.3   */
> +	{ 0x2, 0x7F, 0x3F, 0x00, 0x00 },	/* 400   400      0.0   */
> +};
> +
> +/* Voltage Swing Programming for VccIO 0.95V for DP */
> +static const struct cnl_ddi_buf_trans cnl_ddi_translations_dp_0_95V[] = {
> +						/* NT mV Trans mV db    */
> +	{ 0xA, 0x5D, 0x3F, 0x00, 0x00 },	/* 350   350      0.0   */
> +	{ 0xA, 0x6A, 0x38, 0x00, 0x07 },	/* 350   500      3.1   */
> +	{ 0xB, 0x7A, 0x32, 0x00, 0x0D },	/* 350   700      6.0   */
> +	{ 0x6, 0x7C, 0x2D, 0x00, 0x12 },	/* 350   900      8.2   */
> +	{ 0xA, 0x69, 0x3F, 0x00, 0x00 },	/* 500   500      0.0   */
> +	{ 0xB, 0x7A, 0x36, 0x00, 0x09 },	/* 500   700      2.9   */
> +	{ 0x6, 0x7C, 0x30, 0x00, 0x0F },	/* 500   900      5.1   */
> +	{ 0xB, 0x7D, 0x3C, 0x00, 0x03 },	/* 650   725      0.9   */
> +	{ 0x6, 0x7C, 0x34, 0x00, 0x0B },	/* 600   900      3.5   */
> +	{ 0x6, 0x7B, 0x3F, 0x00, 0x00 },	/* 900   900      0.0   */
> +};
> +
> +/* Voltage Swing Programming for VccIO 0.95V for HDMI */
> +static const struct cnl_ddi_buf_trans cnl_ddi_translations_hdmi_0_95V[] = {
> +						/* NT mV Trans mV db    */
> +	{ 0xA, 0x5C, 0x3F, 0x00, 0x00 },	/* 400   400      0.0   */
> +	{ 0xB, 0x69, 0x37, 0x00, 0x08 },	/* 400   600      3.5   */
> +	{ 0x5, 0x76, 0x31, 0x00, 0x0E },	/* 400   800      6.0   */
> +	{ 0xA, 0x5E, 0x3F, 0x00, 0x00 },	/* 450   450      0.0   */
> +	{ 0xB, 0x69, 0x3F, 0x00, 0x00 },	/* 600   600      0.0   */
> +	{ 0xB, 0x79, 0x35, 0x00, 0x0A },	/* 600   850      3.0   */
> +	{ 0x6, 0x7D, 0x32, 0x00, 0x0D },	/* 600   1000     4.4   */
> +	{ 0x5, 0x76, 0x3F, 0x00, 0x00 },	/* 800   800      0.0   */
> +	{ 0x6, 0x7D, 0x39, 0x00, 0x06 },	/* 800   1000     1.9   */
> +	{ 0x6, 0x7F, 0x39, 0x00, 0x06 },	/* 850   1050     1.8   */
> +	{ 0x6, 0x7F, 0x3F, 0x00, 0x00 },	/* 1050  1050     0.0   */
> +};
> +
> +/* Voltage Swing Programming for VccIO 0.95V for eDP */
> +static const struct cnl_ddi_buf_trans cnl_ddi_translations_edp_0_95V[] = {
> +						/* NT mV Trans mV db    */
> +	{ 0xA, 0x61, 0x3A, 0x00, 0x05 },	/* 384   500      2.3   */
> +	{ 0x0, 0x7F, 0x38, 0x00, 0x07 },	/* 153   200      2.3   */
> +	{ 0x8, 0x7F, 0x38, 0x00, 0x07 },	/* 192   250      2.3   */
> +	{ 0x1, 0x7F, 0x38, 0x00, 0x07 },	/* 230   300      2.3   */
> +	{ 0x9, 0x7F, 0x38, 0x00, 0x07 },	/* 269   350      2.3   */
> +	{ 0xA, 0x61, 0x3C, 0x00, 0x03 },	/* 446   500      1.0   */
> +	{ 0xB, 0x68, 0x39, 0x00, 0x06 },	/* 460   600      2.3   */
> +	{ 0xC, 0x6E, 0x39, 0x00, 0x06 },	/* 537   700      2.3   */
> +	{ 0x4, 0x7F, 0x3A, 0x00, 0x05 },	/* 460   600      2.3   */
> +	{ 0x2, 0x7F, 0x3F, 0x00, 0x00 },	/* 400   400      0.0   */
> +};
> +
> +/* Voltage Swing Programming for VccIO 1.05V for DP */
> +static const struct cnl_ddi_buf_trans cnl_ddi_translations_dp_1_05V[] = {
> +						/* NT mV Trans mV db    */
> +	{ 0xA, 0x58, 0x3F, 0x00, 0x00 },	/* 400   400      0.0   */
> +	{ 0xB, 0x64, 0x37, 0x00, 0x08 },	/* 400   600      3.5   */
> +	{ 0x5, 0x70, 0x31, 0x00, 0x0E },	/* 400   800      6.0   */
> +	{ 0x6, 0x7F, 0x2C, 0x00, 0x13 },	/* 400   1050     8.4   */
> +	{ 0xB, 0x64, 0x3F, 0x00, 0x00 },	/* 600   600      0.0   */
> +	{ 0x5, 0x73, 0x35, 0x00, 0x0A },	/* 600   850      3.0   */
> +	{ 0x6, 0x7F, 0x30, 0x00, 0x0F },	/* 550   1050     5.6   */
> +	{ 0x5, 0x76, 0x3E, 0x00, 0x01 },	/* 850   900      0.5   */
> +	{ 0x6, 0x7F, 0x36, 0x00, 0x09 },	/* 750   1050     2.9   */
> +	{ 0x6, 0x7F, 0x3F, 0x00, 0x00 },	/* 1050  1050     0.0   */
> +};
> +
> +/* Voltage Swing Programming for VccIO 1.05V for HDMI */
> +static const struct cnl_ddi_buf_trans cnl_ddi_translations_hdmi_1_05V[] = {
> +						/* NT mV Trans mV db    */
> +	{ 0xA, 0x58, 0x3F, 0x00, 0x00 },	/* 400   400      0.0   */
> +	{ 0xB, 0x64, 0x37, 0x00, 0x08 },	/* 400   600      3.5   */
> +	{ 0x5, 0x70, 0x31, 0x00, 0x0E },	/* 400   800      6.0   */
> +	{ 0xA, 0x5B, 0x3F, 0x00, 0x00 },	/* 450   450      0.0   */
> +	{ 0xB, 0x64, 0x3F, 0x00, 0x00 },	/* 600   600      0.0   */
> +	{ 0x5, 0x73, 0x35, 0x00, 0x0A },	/* 600   850      3.0   */
> +	{ 0x6, 0x7C, 0x32, 0x00, 0x0D },	/* 600   1000     4.4   */
> +	{ 0x5, 0x70, 0x3F, 0x00, 0x00 },	/* 800   800      0.0   */
> +	{ 0x6, 0x7C, 0x39, 0x00, 0x06 },	/* 800   1000     1.9   */
> +	{ 0x6, 0x7F, 0x39, 0x00, 0x06 },	/* 850   1050     1.8   */
> +	{ 0x6, 0x7F, 0x3F, 0x00, 0x00 },	/* 1050  1050     0.0   */
> +};
> +
> +/* Voltage Swing Programming for VccIO 1.05V for eDP */
> +static const struct cnl_ddi_buf_trans cnl_ddi_translations_edp_1_05V[] = {
> +						/* NT mV Trans mV db    */
> +	{ 0xA, 0x5E, 0x3A, 0x00, 0x05 },	/* 384   500      2.3   */
> +	{ 0x0, 0x7F, 0x38, 0x00, 0x07 },	/* 153   200      2.3   */
> +	{ 0x8, 0x7F, 0x38, 0x00, 0x07 },	/* 192   250      2.3   */
> +	{ 0x1, 0x7F, 0x38, 0x00, 0x07 },	/* 230   300      2.3   */
> +	{ 0x9, 0x7F, 0x38, 0x00, 0x07 },	/* 269   350      2.3   */
> +	{ 0xA, 0x5E, 0x3C, 0x00, 0x03 },	/* 446   500      1.0   */
> +	{ 0xB, 0x64, 0x39, 0x00, 0x06 },	/* 460   600      2.3   */
> +	{ 0xE, 0x6A, 0x39, 0x00, 0x06 },	/* 537   700      2.3   */
> +	{ 0x2, 0x7F, 0x3F, 0x00, 0x00 },	/* 400   400      0.0   */
> +};
> +
>  enum port intel_ddi_get_encoder_port(struct intel_encoder *encoder)
>  {
>  	switch (encoder->type) {
> -- 
> 1.9.1
> 
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[PATCH 39/67] drm/i915/cnl: Implement voltage swing sequence.

[Rodrigo Vivi]

This is an important part of the DDI initalization as well as
for changing the voltage during DisplayPort link training.

This new sequence for Cannonlake is more like Broxton style
but still with different registers, different table and
different steps.

v2: Do not write to DW4_GRP to avoid overwrite individual loadgen.
    Fix PORT_CL_DW5 SUS Clock Config set.
v3: As previous platforms use only eDP table if low voltage was
    requested.
v4: fix Werror:maybe uninitialized (Paulo)
v5: Rebase on top of dw2_swing_sel changes
    on previous patches.

Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h  |   1 +
 drivers/gpu/drm/i915/intel_ddi.c | 176 ++++++++++++++++++++++++++++++++++++++-
 drivers/gpu/drm/i915/intel_dp.c  |   2 +-
 3 files changed, 177 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index d4f7460..55ffec7 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -1663,6 +1663,7 @@ enum skl_disp_power_wells {
 
 #define CNL_PORT_CL1CM_DW5		_MMIO(0x162014)
 #define   CL_POWER_DOWN_ENABLE		(1 << 4)
+#define   SUS_CLOCK_CONFIG		(3 << 0)
 
 #define _PORT_CL1CM_DW9_A		0x162024
 #define _PORT_CL1CM_DW9_BC		0x6C024
diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
index 3c31a22..a4d7061 100644
--- a/drivers/gpu/drm/i915/intel_ddi.c
+++ b/drivers/gpu/drm/i915/intel_ddi.c
@@ -1720,6 +1720,173 @@ u8 intel_ddi_dp_voltage_max(struct intel_encoder *encoder)
 		DP_TRAIN_VOLTAGE_SWING_MASK;
 }
 
+static const struct cnl_ddi_buf_trans *
+cnl_get_buf_trans_hdmi(struct drm_i915_private *dev_priv,
+		       u32 voltage, int *n_entries)
+{
+	if (voltage == VOLTAGE_INFO_0_85V) {
+		*n_entries = ARRAY_SIZE(cnl_ddi_translations_hdmi_0_85V);
+		return cnl_ddi_translations_hdmi_0_85V;
+	} else if (voltage == VOLTAGE_INFO_0_95V) {
+		*n_entries = ARRAY_SIZE(cnl_ddi_translations_hdmi_0_95V);
+		return cnl_ddi_translations_hdmi_0_95V;
+	} else if (voltage == VOLTAGE_INFO_1_05V) {
+		*n_entries = ARRAY_SIZE(cnl_ddi_translations_hdmi_1_05V);
+		return cnl_ddi_translations_hdmi_1_05V;
+	}
+	return NULL;
+}
+
+static const struct cnl_ddi_buf_trans *
+cnl_get_buf_trans_dp(struct drm_i915_private *dev_priv,
+		     u32 voltage, int *n_entries)
+{
+	if (voltage == VOLTAGE_INFO_0_85V) {
+		*n_entries = ARRAY_SIZE(cnl_ddi_translations_dp_0_85V);
+		return cnl_ddi_translations_dp_0_85V;
+	} else if (voltage == VOLTAGE_INFO_0_95V) {
+		*n_entries = ARRAY_SIZE(cnl_ddi_translations_dp_0_95V);
+		return cnl_ddi_translations_dp_0_95V;
+	} else if (voltage == VOLTAGE_INFO_1_05V) {
+		*n_entries = ARRAY_SIZE(cnl_ddi_translations_dp_1_05V);
+		return cnl_ddi_translations_dp_1_05V;
+	}
+	return NULL;
+}
+
+static const struct cnl_ddi_buf_trans *
+cnl_get_buf_trans_edp(struct drm_i915_private *dev_priv,
+		      u32 voltage, int *n_entries)
+{
+	if (dev_priv->vbt.edp.low_vswing) {
+		if (voltage == VOLTAGE_INFO_0_85V) {
+			*n_entries = ARRAY_SIZE(cnl_ddi_translations_edp_0_85V);
+			return cnl_ddi_translations_dp_0_85V;
+		} else if (voltage == VOLTAGE_INFO_0_95V) {
+			*n_entries = ARRAY_SIZE(cnl_ddi_translations_edp_0_95V);
+			return cnl_ddi_translations_edp_0_95V;
+		} else if (voltage == VOLTAGE_INFO_1_05V) {
+			*n_entries = ARRAY_SIZE(cnl_ddi_translations_edp_1_05V);
+			return cnl_ddi_translations_edp_1_05V;
+		}
+		return NULL;
+	} else {
+		return cnl_get_buf_trans_dp(dev_priv, voltage, n_entries);
+	}
+}
+
+static void cnl_ddi_vswing_program(struct drm_i915_private *dev_priv,
+				    u32 level, enum port port, int type)
+{
+	const struct cnl_ddi_buf_trans *ddi_translations = NULL;
+	u32 n_entries, val, voltage;
+	int ln;
+
+	/*
+	 * Values for each port type are listed in
+	 * voltage swing programming tables.
+	 * Vccio voltage found in PORT_COMP_DW3.
+	 */
+	voltage = I915_READ(CNL_PORT_COMP_DW3) & VOLTAGE_INFO_MASK;
+
+	if (type == INTEL_OUTPUT_HDMI) {
+		ddi_translations = cnl_get_buf_trans_hdmi(dev_priv,
+							  voltage, &n_entries);
+	} else if (type == INTEL_OUTPUT_DP) {
+		ddi_translations = cnl_get_buf_trans_dp(dev_priv,
+							voltage, &n_entries);
+	} else if (type == INTEL_OUTPUT_EDP) {
+		ddi_translations = cnl_get_buf_trans_edp(dev_priv,
+							 voltage, &n_entries);
+	}
+
+	if (ddi_translations == NULL) {
+		MISSING_CASE(voltage);
+		return;
+	}
+
+	if (level >= n_entries) {
+		DRM_DEBUG_KMS("DDI translation not found for level %d. Using %d instead.", level, n_entries - 1);
+		level = n_entries - 1;
+	}
+
+	/* Set PORT_TX_DW5 Scaling Mode Sel to 010b. */
+	val = I915_READ(CNL_PORT_TX_DW5_LN0(port));
+	val |= SCALING_MODE_SEL;
+	I915_WRITE(CNL_PORT_TX_DW5_GRP(port), val);
+
+	/* Program PORT_TX_DW2 */
+	val = I915_READ(CNL_PORT_TX_DW2_LN0(port));
+	val |= SWING_SEL_UPPER(ddi_translations[level].dw2_swing_sel);
+	val |= SWING_SEL_LOWER(ddi_translations[level].dw2_swing_sel);
+	/* Rcomp scalar is fixed as 0x98 for every table entry */
+	val |= RCOMP_SCALAR(0x98);
+	I915_WRITE(CNL_PORT_TX_DW2_GRP(port), val);
+
+        /* Program PORT_TX_DW4 */
+	/* We cannot write to GRP. It would overrite individual loadgen */
+	for (ln = 0; ln < 4; ln++) {
+		val = I915_READ(CNL_PORT_TX_DW4_LN(port, ln));
+		val |= POST_CURSOR_1(ddi_translations[level].dw4_post_cursor_1);
+		val |= POST_CURSOR_2(ddi_translations[level].dw4_post_cursor_2);
+		val |= CURSOR_COEFF(ddi_translations[level].dw4_cursor_coeff);
+		I915_WRITE(CNL_PORT_TX_DW4_LN(port, ln), val);
+	}
+
+        /* Program PORT_TX_DW5 */
+	/* All DW5 values are fixed for every table entry */
+	val = I915_READ(CNL_PORT_TX_DW5_LN0(port));
+	val |= RTERM_SELECT(6);
+	val |= TAP3_DISABLE;
+	I915_WRITE(CNL_PORT_TX_DW5_GRP(port), val);
+
+        /* Program PORT_TX_DW7 */
+	val = I915_READ(CNL_PORT_TX_DW7_LN0(port));
+	val |= N_SCALAR(ddi_translations[level].dw7_n_scalar);
+	I915_WRITE(CNL_PORT_TX_DW7_GRP(port), val);
+}
+
+static void cnl_ddi_vswing_sequence(struct drm_i915_private *dev_priv,
+				    u32 level, enum port port, int type)
+{
+	u32 val;
+
+	/*
+	 * 1. If port type is eDP or DP,
+	 * set PORT_PCS_DW1 cmnkeeper_enable to 1b,
+	 * else clear to 0b.
+	 */
+	val = I915_READ(CNL_PORT_PCS_DW1_LN0(port));
+	if (type == INTEL_OUTPUT_EDP || type == INTEL_OUTPUT_DP)
+		val |= COMMON_KEEPER_EN;
+	else
+		val &= ~COMMON_KEEPER_EN;
+	I915_WRITE(CNL_PORT_PCS_DW1_GRP(port), val);
+
+	/* 2. Program loadgen select */
+	/*
+	 * FIXME: Program PORT_TX_DW4_LN depending on Bit rate and used lanes
+	 */
+
+	/* 3. Set PORT_CL_DW5 SUS Clock Config to 11b */
+	val = I915_READ(CNL_PORT_CL1CM_DW5);
+	val |= SUS_CLOCK_CONFIG;
+	I915_WRITE(CNL_PORT_CL1CM_DW5, val);
+
+	/* 4. Clear training enable to change swing values */
+	val = I915_READ(CNL_PORT_TX_DW5_LN0(port));
+	val &= ~TX_TRAINING_EN;
+	I915_WRITE(CNL_PORT_TX_DW5_GRP(port), val);
+
+	/* 5. Program swing and de-emphasis */
+	cnl_ddi_vswing_program(dev_priv, level, port, type);
+
+	/* 6. Set training enable to trigger update */
+	val = I915_READ(CNL_PORT_TX_DW5_LN0(port));
+	val |= TX_TRAINING_EN;
+	I915_WRITE(CNL_PORT_TX_DW5_GRP(port), val);
+}
+
 static uint32_t translate_signal_level(int signal_levels)
 {
 	int i;
@@ -1752,7 +1919,11 @@ uint32_t ddi_signal_levels(struct intel_dp *intel_dp)
 		skl_ddi_set_iboost(encoder, level);
 	else if (IS_GEN9_LP(dev_priv))
 		bxt_ddi_vswing_sequence(dev_priv, level, port, encoder->type);
-
+	else if (IS_CANNONLAKE(dev_priv)) {
+		cnl_ddi_vswing_sequence(dev_priv, level, port, encoder->type);
+		/* DDI_BUF_CTL bits 27:24 are reserved on CNL */
+		return 0;
+	}
 	return DDI_BUF_TRANS_SELECT(level);
 }
 
@@ -1850,6 +2021,9 @@ static void intel_ddi_pre_enable_hdmi(struct intel_encoder *encoder,
 	else if (IS_GEN9_LP(dev_priv))
 		bxt_ddi_vswing_sequence(dev_priv, level, port,
 					INTEL_OUTPUT_HDMI);
+	else if (IS_CANNONLAKE(dev_priv))
+		cnl_ddi_vswing_sequence(dev_priv, level, port,
+					INTEL_OUTPUT_HDMI);
 
 	intel_hdmi->set_infoframes(drm_encoder,
 				   has_hdmi_sink,
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index da111cb..b7adf0a 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -3471,7 +3471,7 @@ static uint32_t chv_signal_levels(struct intel_dp *intel_dp)
 	if (HAS_DDI(dev_priv)) {
 		signal_levels = ddi_signal_levels(intel_dp);
 
-		if (IS_GEN9_LP(dev_priv))
+		if (IS_GEN9_LP(dev_priv) || IS_CANNONLAKE(dev_priv))
 			signal_levels = 0;
 		else
 			mask = DDI_BUF_EMP_MASK;
-- 
1.9.1

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Re: [PATCH 39/67] drm/i915/cnl: Implement voltage swing sequence.

[Manasi Navare]

On Thu, Apr 06, 2017 at 12:15:35PM -0700, Rodrigo Vivi wrote:
> This is an important part of the DDI initalization as well as
> for changing the voltage during DisplayPort link training.
> 
> This new sequence for Cannonlake is more like Broxton style
> but still with different registers, different table and
> different steps.
> 
> v2: Do not write to DW4_GRP to avoid overwrite individual loadgen.
>     Fix PORT_CL_DW5 SUS Clock Config set.
> v3: As previous platforms use only eDP table if low voltage was
>     requested.
> v4: fix Werror:maybe uninitialized (Paulo)
> v5: Rebase on top of dw2_swing_sel changes
>     on previous patches.
> 
> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
> ---
>  drivers/gpu/drm/i915/i915_reg.h  |   1 +
>  drivers/gpu/drm/i915/intel_ddi.c | 176 ++++++++++++++++++++++++++++++++++++++-
>  drivers/gpu/drm/i915/intel_dp.c  |   2 +-
>  3 files changed, 177 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index d4f7460..55ffec7 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -1663,6 +1663,7 @@ enum skl_disp_power_wells {
>  
>  #define CNL_PORT_CL1CM_DW5		_MMIO(0x162014)
>  #define   CL_POWER_DOWN_ENABLE		(1 << 4)
> +#define   SUS_CLOCK_CONFIG		(3 << 0)
>  
>  #define _PORT_CL1CM_DW9_A		0x162024
>  #define _PORT_CL1CM_DW9_BC		0x6C024
> diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
> index 3c31a22..a4d7061 100644
> --- a/drivers/gpu/drm/i915/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/intel_ddi.c
> @@ -1720,6 +1720,173 @@ u8 intel_ddi_dp_voltage_max(struct intel_encoder *encoder)
>  		DP_TRAIN_VOLTAGE_SWING_MASK;
>  }
>  
> +static const struct cnl_ddi_buf_trans *
> +cnl_get_buf_trans_hdmi(struct drm_i915_private *dev_priv,
> +		       u32 voltage, int *n_entries)
> +{
> +	if (voltage == VOLTAGE_INFO_0_85V) {
> +		*n_entries = ARRAY_SIZE(cnl_ddi_translations_hdmi_0_85V);
> +		return cnl_ddi_translations_hdmi_0_85V;
> +	} else if (voltage == VOLTAGE_INFO_0_95V) {
> +		*n_entries = ARRAY_SIZE(cnl_ddi_translations_hdmi_0_95V);
> +		return cnl_ddi_translations_hdmi_0_95V;
> +	} else if (voltage == VOLTAGE_INFO_1_05V) {
> +		*n_entries = ARRAY_SIZE(cnl_ddi_translations_hdmi_1_05V);
> +		return cnl_ddi_translations_hdmi_1_05V;
> +	}
> +	return NULL;
> +}
> +
> +static const struct cnl_ddi_buf_trans *
> +cnl_get_buf_trans_dp(struct drm_i915_private *dev_priv,
> +		     u32 voltage, int *n_entries)
> +{
> +	if (voltage == VOLTAGE_INFO_0_85V) {
> +		*n_entries = ARRAY_SIZE(cnl_ddi_translations_dp_0_85V);
> +		return cnl_ddi_translations_dp_0_85V;
> +	} else if (voltage == VOLTAGE_INFO_0_95V) {
> +		*n_entries = ARRAY_SIZE(cnl_ddi_translations_dp_0_95V);
> +		return cnl_ddi_translations_dp_0_95V;
> +	} else if (voltage == VOLTAGE_INFO_1_05V) {
> +		*n_entries = ARRAY_SIZE(cnl_ddi_translations_dp_1_05V);
> +		return cnl_ddi_translations_dp_1_05V;
> +	}
> +	return NULL;
> +}
> +
> +static const struct cnl_ddi_buf_trans *
> +cnl_get_buf_trans_edp(struct drm_i915_private *dev_priv,
> +		      u32 voltage, int *n_entries)
> +{
> +	if (dev_priv->vbt.edp.low_vswing) {
> +		if (voltage == VOLTAGE_INFO_0_85V) {
> +			*n_entries = ARRAY_SIZE(cnl_ddi_translations_edp_0_85V);
> +			return cnl_ddi_translations_dp_0_85V;
> +		} else if (voltage == VOLTAGE_INFO_0_95V) {
> +			*n_entries = ARRAY_SIZE(cnl_ddi_translations_edp_0_95V);
> +			return cnl_ddi_translations_edp_0_95V;
> +		} else if (voltage == VOLTAGE_INFO_1_05V) {
> +			*n_entries = ARRAY_SIZE(cnl_ddi_translations_edp_1_05V);
> +			return cnl_ddi_translations_edp_1_05V;
> +		}
> +		return NULL;
> +	} else {
> +		return cnl_get_buf_trans_dp(dev_priv, voltage, n_entries);
> +	}
> +}
> +
> +static void cnl_ddi_vswing_program(struct drm_i915_private *dev_priv,
> +				    u32 level, enum port port, int type)
> +{
> +	const struct cnl_ddi_buf_trans *ddi_translations = NULL;
> +	u32 n_entries, val, voltage;
> +	int ln;
> +
> +	/*
> +	 * Values for each port type are listed in
> +	 * voltage swing programming tables.
> +	 * Vccio voltage found in PORT_COMP_DW3.
> +	 */
> +	voltage = I915_READ(CNL_PORT_COMP_DW3) & VOLTAGE_INFO_MASK;
> +
> +	if (type == INTEL_OUTPUT_HDMI) {
> +		ddi_translations = cnl_get_buf_trans_hdmi(dev_priv,
> +							  voltage, &n_entries);
> +	} else if (type == INTEL_OUTPUT_DP) {
> +		ddi_translations = cnl_get_buf_trans_dp(dev_priv,
> +							voltage, &n_entries);
> +	} else if (type == INTEL_OUTPUT_EDP) {
> +		ddi_translations = cnl_get_buf_trans_edp(dev_priv,
> +							 voltage, &n_entries);
> +	}
> +
> +	if (ddi_translations == NULL) {
> +		MISSING_CASE(voltage);
> +		return;
> +	}
> +
> +	if (level >= n_entries) {
> +		DRM_DEBUG_KMS("DDI translation not found for level %d. Using %d instead.", level, n_entries - 1);
> +		level = n_entries - 1;
> +	}
> +
> +	/* Set PORT_TX_DW5 Scaling Mode Sel to 010b. */
> +	val = I915_READ(CNL_PORT_TX_DW5_LN0(port));
> +	val |= SCALING_MODE_SEL;

Make the change based on new macro for SCALING_MODE_SEL
So it will be val |= SCALING_MODE_SEL(0x2);

Manasi

> +	I915_WRITE(CNL_PORT_TX_DW5_GRP(port), val);
> +
> +	/* Program PORT_TX_DW2 */
> +	val = I915_READ(CNL_PORT_TX_DW2_LN0(port));
> +	val |= SWING_SEL_UPPER(ddi_translations[level].dw2_swing_sel);
> +	val |= SWING_SEL_LOWER(ddi_translations[level].dw2_swing_sel);
> +	/* Rcomp scalar is fixed as 0x98 for every table entry */
> +	val |= RCOMP_SCALAR(0x98);
> +	I915_WRITE(CNL_PORT_TX_DW2_GRP(port), val);
> +
> +        /* Program PORT_TX_DW4 */
> +	/* We cannot write to GRP. It would overrite individual loadgen */
> +	for (ln = 0; ln < 4; ln++) {
> +		val = I915_READ(CNL_PORT_TX_DW4_LN(port, ln));
> +		val |= POST_CURSOR_1(ddi_translations[level].dw4_post_cursor_1);
> +		val |= POST_CURSOR_2(ddi_translations[level].dw4_post_cursor_2);
> +		val |= CURSOR_COEFF(ddi_translations[level].dw4_cursor_coeff);
> +		I915_WRITE(CNL_PORT_TX_DW4_LN(port, ln), val);
> +	}
> +
> +        /* Program PORT_TX_DW5 */
> +	/* All DW5 values are fixed for every table entry */
> +	val = I915_READ(CNL_PORT_TX_DW5_LN0(port));
> +	val |= RTERM_SELECT(6);
> +	val |= TAP3_DISABLE;
> +	I915_WRITE(CNL_PORT_TX_DW5_GRP(port), val);
> +
> +        /* Program PORT_TX_DW7 */
> +	val = I915_READ(CNL_PORT_TX_DW7_LN0(port));
> +	val |= N_SCALAR(ddi_translations[level].dw7_n_scalar);
> +	I915_WRITE(CNL_PORT_TX_DW7_GRP(port), val);
> +}
> +
> +static void cnl_ddi_vswing_sequence(struct drm_i915_private *dev_priv,
> +				    u32 level, enum port port, int type)
> +{
> +	u32 val;
> +
> +	/*
> +	 * 1. If port type is eDP or DP,
> +	 * set PORT_PCS_DW1 cmnkeeper_enable to 1b,
> +	 * else clear to 0b.
> +	 */
> +	val = I915_READ(CNL_PORT_PCS_DW1_LN0(port));
> +	if (type == INTEL_OUTPUT_EDP || type == INTEL_OUTPUT_DP)
> +		val |= COMMON_KEEPER_EN;
> +	else
> +		val &= ~COMMON_KEEPER_EN;
> +	I915_WRITE(CNL_PORT_PCS_DW1_GRP(port), val);
> +
> +	/* 2. Program loadgen select */
> +	/*
> +	 * FIXME: Program PORT_TX_DW4_LN depending on Bit rate and used lanes
> +	 */
> +
> +	/* 3. Set PORT_CL_DW5 SUS Clock Config to 11b */
> +	val = I915_READ(CNL_PORT_CL1CM_DW5);
> +	val |= SUS_CLOCK_CONFIG;
> +	I915_WRITE(CNL_PORT_CL1CM_DW5, val);
> +
> +	/* 4. Clear training enable to change swing values */
> +	val = I915_READ(CNL_PORT_TX_DW5_LN0(port));
> +	val &= ~TX_TRAINING_EN;
> +	I915_WRITE(CNL_PORT_TX_DW5_GRP(port), val);
> +
> +	/* 5. Program swing and de-emphasis */
> +	cnl_ddi_vswing_program(dev_priv, level, port, type);
> +
> +	/* 6. Set training enable to trigger update */
> +	val = I915_READ(CNL_PORT_TX_DW5_LN0(port));
> +	val |= TX_TRAINING_EN;
> +	I915_WRITE(CNL_PORT_TX_DW5_GRP(port), val);
> +}
> +
>  static uint32_t translate_signal_level(int signal_levels)
>  {
>  	int i;
> @@ -1752,7 +1919,11 @@ uint32_t ddi_signal_levels(struct intel_dp *intel_dp)
>  		skl_ddi_set_iboost(encoder, level);
>  	else if (IS_GEN9_LP(dev_priv))
>  		bxt_ddi_vswing_sequence(dev_priv, level, port, encoder->type);
> -
> +	else if (IS_CANNONLAKE(dev_priv)) {
> +		cnl_ddi_vswing_sequence(dev_priv, level, port, encoder->type);
> +		/* DDI_BUF_CTL bits 27:24 are reserved on CNL */
> +		return 0;
> +	}
>  	return DDI_BUF_TRANS_SELECT(level);
>  }
>  
> @@ -1850,6 +2021,9 @@ static void intel_ddi_pre_enable_hdmi(struct intel_encoder *encoder,
>  	else if (IS_GEN9_LP(dev_priv))
>  		bxt_ddi_vswing_sequence(dev_priv, level, port,
>  					INTEL_OUTPUT_HDMI);
> +	else if (IS_CANNONLAKE(dev_priv))
> +		cnl_ddi_vswing_sequence(dev_priv, level, port,
> +					INTEL_OUTPUT_HDMI);
>  
>  	intel_hdmi->set_infoframes(drm_encoder,
>  				   has_hdmi_sink,
> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> index da111cb..b7adf0a 100644
> --- a/drivers/gpu/drm/i915/intel_dp.c
> +++ b/drivers/gpu/drm/i915/intel_dp.c
> @@ -3471,7 +3471,7 @@ static uint32_t chv_signal_levels(struct intel_dp *intel_dp)
>  	if (HAS_DDI(dev_priv)) {
>  		signal_levels = ddi_signal_levels(intel_dp);
>  
> -		if (IS_GEN9_LP(dev_priv))
> +		if (IS_GEN9_LP(dev_priv) || IS_CANNONLAKE(dev_priv))
>  			signal_levels = 0;
>  		else
>  			mask = DDI_BUF_EMP_MASK;
> -- 
> 1.9.1
> 
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [PATCH 39/67] drm/i915/cnl: Implement voltage swing sequence.

[Vivi, Rodrigo]

On Wed, 2017-05-17 at 18:13 -0700, Manasi Navare wrote:
> On Thu, Apr 06, 2017 at 12:15:35PM -0700, Rodrigo Vivi wrote:
> > This is an important part of the DDI initalization as well as
> > for changing the voltage during DisplayPort link training.
> > 
> > This new sequence for Cannonlake is more like Broxton style
> > but still with different registers, different table and
> > different steps.
> > 
> > v2: Do not write to DW4_GRP to avoid overwrite individual loadgen.
> >     Fix PORT_CL_DW5 SUS Clock Config set.
> > v3: As previous platforms use only eDP table if low voltage was
> >     requested.
> > v4: fix Werror:maybe uninitialized (Paulo)
> > v5: Rebase on top of dw2_swing_sel changes
> >     on previous patches.
> > 
> > Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
> > ---
> >  drivers/gpu/drm/i915/i915_reg.h  |   1 +
> >  drivers/gpu/drm/i915/intel_ddi.c | 176 ++++++++++++++++++++++++++++++++++++++-
> >  drivers/gpu/drm/i915/intel_dp.c  |   2 +-
> >  3 files changed, 177 insertions(+), 2 deletions(-)
> > 
> > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> > index d4f7460..55ffec7 100644
> > --- a/drivers/gpu/drm/i915/i915_reg.h
> > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > @@ -1663,6 +1663,7 @@ enum skl_disp_power_wells {
> >  
> >  #define CNL_PORT_CL1CM_DW5		_MMIO(0x162014)
> >  #define   CL_POWER_DOWN_ENABLE		(1 << 4)
> > +#define   SUS_CLOCK_CONFIG		(3 << 0)
> >  
> >  #define _PORT_CL1CM_DW9_A		0x162024
> >  #define _PORT_CL1CM_DW9_BC		0x6C024
> > diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
> > index 3c31a22..a4d7061 100644
> > --- a/drivers/gpu/drm/i915/intel_ddi.c
> > +++ b/drivers/gpu/drm/i915/intel_ddi.c
> > @@ -1720,6 +1720,173 @@ u8 intel_ddi_dp_voltage_max(struct intel_encoder *encoder)
> >  		DP_TRAIN_VOLTAGE_SWING_MASK;
> >  }
> >  
> > +static const struct cnl_ddi_buf_trans *
> > +cnl_get_buf_trans_hdmi(struct drm_i915_private *dev_priv,
> > +		       u32 voltage, int *n_entries)
> > +{
> > +	if (voltage == VOLTAGE_INFO_0_85V) {
> > +		*n_entries = ARRAY_SIZE(cnl_ddi_translations_hdmi_0_85V);
> > +		return cnl_ddi_translations_hdmi_0_85V;
> > +	} else if (voltage == VOLTAGE_INFO_0_95V) {
> > +		*n_entries = ARRAY_SIZE(cnl_ddi_translations_hdmi_0_95V);
> > +		return cnl_ddi_translations_hdmi_0_95V;
> > +	} else if (voltage == VOLTAGE_INFO_1_05V) {
> > +		*n_entries = ARRAY_SIZE(cnl_ddi_translations_hdmi_1_05V);
> > +		return cnl_ddi_translations_hdmi_1_05V;
> > +	}
> > +	return NULL;
> > +}
> > +
> > +static const struct cnl_ddi_buf_trans *
> > +cnl_get_buf_trans_dp(struct drm_i915_private *dev_priv,
> > +		     u32 voltage, int *n_entries)
> > +{
> > +	if (voltage == VOLTAGE_INFO_0_85V) {
> > +		*n_entries = ARRAY_SIZE(cnl_ddi_translations_dp_0_85V);
> > +		return cnl_ddi_translations_dp_0_85V;
> > +	} else if (voltage == VOLTAGE_INFO_0_95V) {
> > +		*n_entries = ARRAY_SIZE(cnl_ddi_translations_dp_0_95V);
> > +		return cnl_ddi_translations_dp_0_95V;
> > +	} else if (voltage == VOLTAGE_INFO_1_05V) {
> > +		*n_entries = ARRAY_SIZE(cnl_ddi_translations_dp_1_05V);
> > +		return cnl_ddi_translations_dp_1_05V;
> > +	}
> > +	return NULL;
> > +}
> > +
> > +static const struct cnl_ddi_buf_trans *
> > +cnl_get_buf_trans_edp(struct drm_i915_private *dev_priv,
> > +		      u32 voltage, int *n_entries)
> > +{
> > +	if (dev_priv->vbt.edp.low_vswing) {
> > +		if (voltage == VOLTAGE_INFO_0_85V) {
> > +			*n_entries = ARRAY_SIZE(cnl_ddi_translations_edp_0_85V);
> > +			return cnl_ddi_translations_dp_0_85V;
> > +		} else if (voltage == VOLTAGE_INFO_0_95V) {
> > +			*n_entries = ARRAY_SIZE(cnl_ddi_translations_edp_0_95V);
> > +			return cnl_ddi_translations_edp_0_95V;
> > +		} else if (voltage == VOLTAGE_INFO_1_05V) {
> > +			*n_entries = ARRAY_SIZE(cnl_ddi_translations_edp_1_05V);
> > +			return cnl_ddi_translations_edp_1_05V;
> > +		}
> > +		return NULL;
> > +	} else {
> > +		return cnl_get_buf_trans_dp(dev_priv, voltage, n_entries);
> > +	}
> > +}
> > +
> > +static void cnl_ddi_vswing_program(struct drm_i915_private *dev_priv,
> > +				    u32 level, enum port port, int type)
> > +{
> > +	const struct cnl_ddi_buf_trans *ddi_translations = NULL;
> > +	u32 n_entries, val, voltage;
> > +	int ln;
> > +
> > +	/*
> > +	 * Values for each port type are listed in
> > +	 * voltage swing programming tables.
> > +	 * Vccio voltage found in PORT_COMP_DW3.
> > +	 */
> > +	voltage = I915_READ(CNL_PORT_COMP_DW3) & VOLTAGE_INFO_MASK;
> > +
> > +	if (type == INTEL_OUTPUT_HDMI) {
> > +		ddi_translations = cnl_get_buf_trans_hdmi(dev_priv,
> > +							  voltage, &n_entries);
> > +	} else if (type == INTEL_OUTPUT_DP) {
> > +		ddi_translations = cnl_get_buf_trans_dp(dev_priv,
> > +							voltage, &n_entries);
> > +	} else if (type == INTEL_OUTPUT_EDP) {
> > +		ddi_translations = cnl_get_buf_trans_edp(dev_priv,
> > +							 voltage, &n_entries);
> > +	}
> > +
> > +	if (ddi_translations == NULL) {
> > +		MISSING_CASE(voltage);
> > +		return;
> > +	}
> > +
> > +	if (level >= n_entries) {
> > +		DRM_DEBUG_KMS("DDI translation not found for level %d. Using %d instead.", level, n_entries - 1);
> > +		level = n_entries - 1;
> > +	}
> > +
> > +	/* Set PORT_TX_DW5 Scaling Mode Sel to 010b. */
> > +	val = I915_READ(CNL_PORT_TX_DW5_LN0(port));
> > +	val |= SCALING_MODE_SEL;
> 
> Make the change based on new macro for SCALING_MODE_SEL
> So it will be val |= SCALING_MODE_SEL(0x2);

thanks,
with that I have your rv-b?

> 
> Manasi
> 
> > +	I915_WRITE(CNL_PORT_TX_DW5_GRP(port), val);
> > +
> > +	/* Program PORT_TX_DW2 */
> > +	val = I915_READ(CNL_PORT_TX_DW2_LN0(port));
> > +	val |= SWING_SEL_UPPER(ddi_translations[level].dw2_swing_sel);
> > +	val |= SWING_SEL_LOWER(ddi_translations[level].dw2_swing_sel);
> > +	/* Rcomp scalar is fixed as 0x98 for every table entry */
> > +	val |= RCOMP_SCALAR(0x98);
> > +	I915_WRITE(CNL_PORT_TX_DW2_GRP(port), val);
> > +
> > +        /* Program PORT_TX_DW4 */
> > +	/* We cannot write to GRP. It would overrite individual loadgen */
> > +	for (ln = 0; ln < 4; ln++) {
> > +		val = I915_READ(CNL_PORT_TX_DW4_LN(port, ln));
> > +		val |= POST_CURSOR_1(ddi_translations[level].dw4_post_cursor_1);
> > +		val |= POST_CURSOR_2(ddi_translations[level].dw4_post_cursor_2);
> > +		val |= CURSOR_COEFF(ddi_translations[level].dw4_cursor_coeff);
> > +		I915_WRITE(CNL_PORT_TX_DW4_LN(port, ln), val);
> > +	}
> > +
> > +        /* Program PORT_TX_DW5 */
> > +	/* All DW5 values are fixed for every table entry */
> > +	val = I915_READ(CNL_PORT_TX_DW5_LN0(port));
> > +	val |= RTERM_SELECT(6);
> > +	val |= TAP3_DISABLE;
> > +	I915_WRITE(CNL_PORT_TX_DW5_GRP(port), val);
> > +
> > +        /* Program PORT_TX_DW7 */
> > +	val = I915_READ(CNL_PORT_TX_DW7_LN0(port));
> > +	val |= N_SCALAR(ddi_translations[level].dw7_n_scalar);
> > +	I915_WRITE(CNL_PORT_TX_DW7_GRP(port), val);
> > +}
> > +
> > +static void cnl_ddi_vswing_sequence(struct drm_i915_private *dev_priv,
> > +				    u32 level, enum port port, int type)
> > +{
> > +	u32 val;
> > +
> > +	/*
> > +	 * 1. If port type is eDP or DP,
> > +	 * set PORT_PCS_DW1 cmnkeeper_enable to 1b,
> > +	 * else clear to 0b.
> > +	 */
> > +	val = I915_READ(CNL_PORT_PCS_DW1_LN0(port));
> > +	if (type == INTEL_OUTPUT_EDP || type == INTEL_OUTPUT_DP)
> > +		val |= COMMON_KEEPER_EN;
> > +	else
> > +		val &= ~COMMON_KEEPER_EN;
> > +	I915_WRITE(CNL_PORT_PCS_DW1_GRP(port), val);
> > +
> > +	/* 2. Program loadgen select */
> > +	/*
> > +	 * FIXME: Program PORT_TX_DW4_LN depending on Bit rate and used lanes
> > +	 */
> > +
> > +	/* 3. Set PORT_CL_DW5 SUS Clock Config to 11b */
> > +	val = I915_READ(CNL_PORT_CL1CM_DW5);
> > +	val |= SUS_CLOCK_CONFIG;
> > +	I915_WRITE(CNL_PORT_CL1CM_DW5, val);
> > +
> > +	/* 4. Clear training enable to change swing values */
> > +	val = I915_READ(CNL_PORT_TX_DW5_LN0(port));
> > +	val &= ~TX_TRAINING_EN;
> > +	I915_WRITE(CNL_PORT_TX_DW5_GRP(port), val);
> > +
> > +	/* 5. Program swing and de-emphasis */
> > +	cnl_ddi_vswing_program(dev_priv, level, port, type);
> > +
> > +	/* 6. Set training enable to trigger update */
> > +	val = I915_READ(CNL_PORT_TX_DW5_LN0(port));
> > +	val |= TX_TRAINING_EN;
> > +	I915_WRITE(CNL_PORT_TX_DW5_GRP(port), val);
> > +}
> > +
> >  static uint32_t translate_signal_level(int signal_levels)
> >  {
> >  	int i;
> > @@ -1752,7 +1919,11 @@ uint32_t ddi_signal_levels(struct intel_dp *intel_dp)
> >  		skl_ddi_set_iboost(encoder, level);
> >  	else if (IS_GEN9_LP(dev_priv))
> >  		bxt_ddi_vswing_sequence(dev_priv, level, port, encoder->type);
> > -
> > +	else if (IS_CANNONLAKE(dev_priv)) {
> > +		cnl_ddi_vswing_sequence(dev_priv, level, port, encoder->type);
> > +		/* DDI_BUF_CTL bits 27:24 are reserved on CNL */
> > +		return 0;
> > +	}
> >  	return DDI_BUF_TRANS_SELECT(level);
> >  }
> >  
> > @@ -1850,6 +2021,9 @@ static void intel_ddi_pre_enable_hdmi(struct intel_encoder *encoder,
> >  	else if (IS_GEN9_LP(dev_priv))
> >  		bxt_ddi_vswing_sequence(dev_priv, level, port,
> >  					INTEL_OUTPUT_HDMI);
> > +	else if (IS_CANNONLAKE(dev_priv))
> > +		cnl_ddi_vswing_sequence(dev_priv, level, port,
> > +					INTEL_OUTPUT_HDMI);
> >  
> >  	intel_hdmi->set_infoframes(drm_encoder,
> >  				   has_hdmi_sink,
> > diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> > index da111cb..b7adf0a 100644
> > --- a/drivers/gpu/drm/i915/intel_dp.c
> > +++ b/drivers/gpu/drm/i915/intel_dp.c
> > @@ -3471,7 +3471,7 @@ static uint32_t chv_signal_levels(struct intel_dp *intel_dp)
> >  	if (HAS_DDI(dev_priv)) {
> >  		signal_levels = ddi_signal_levels(intel_dp);
> >  
> > -		if (IS_GEN9_LP(dev_priv))
> > +		if (IS_GEN9_LP(dev_priv) || IS_CANNONLAKE(dev_priv))
> >  			signal_levels = 0;
> >  		else
> >  			mask = DDI_BUF_EMP_MASK;
> > -- 
> > 1.9.1
> > 
> > _______________________________________________
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> > Intel-gfx@lists.freedesktop.org
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[PATCH 40/67] drm/i915/cnl: Enable loadgen_select bit for vswing sequence

[Rodrigo Vivi]

From: Clint Taylor <clinton.a.taylor@intel.com>

vswing programming sequence step 2 requires the Loadgen_select bit to
be set in PORT_TX_DW4 lane reigsters per table defined by Bit rate and
lane width. Implemented the change that was marked as FIXME in the
driver.

v2: (Rodrigo) checkpatch fixes.

Signed-off-by: Clint Taylor <clinton.a.taylor@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
---
 drivers/gpu/drm/i915/intel_ddi.c | 38 ++++++++++++++++++++++++++++++++------
 1 file changed, 32 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
index a4d7061..3f461c3 100644
--- a/drivers/gpu/drm/i915/intel_ddi.c
+++ b/drivers/gpu/drm/i915/intel_ddi.c
@@ -1846,10 +1846,24 @@ static void cnl_ddi_vswing_program(struct drm_i915_private *dev_priv,
 	I915_WRITE(CNL_PORT_TX_DW7_GRP(port), val);
 }
 
-static void cnl_ddi_vswing_sequence(struct drm_i915_private *dev_priv,
-				    u32 level, enum port port, int type)
+static void cnl_ddi_vswing_sequence(struct intel_encoder *encoder, u32 level)
 {
+	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
+	struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
+	enum port port = intel_ddi_get_encoder_port(encoder);
+	int type = encoder->type;
+	int width = 0;
+	int rate = 0;
 	u32 val;
+	int ln = 0;
+
+	if ((intel_dp) && (type == INTEL_OUTPUT_EDP || type == INTEL_OUTPUT_DP)) {
+		width = intel_dp->lane_count;
+		rate = intel_dp->link_rate;
+	} else {
+		width = 4;
+		/* Rate is always < than 6GHz for HDMI */
+	}
 
 	/*
 	 * 1. If port type is eDP or DP,
@@ -1865,8 +1879,21 @@ static void cnl_ddi_vswing_sequence(struct drm_i915_private *dev_priv,
 
 	/* 2. Program loadgen select */
 	/*
-	 * FIXME: Program PORT_TX_DW4_LN depending on Bit rate and used lanes
+	 * Program PORT_TX_DW4_LN depending on Bit rate and used lanes
+	 * <= 6 GHz and 4 lanes (LN0=0, LN1=1, LN2=1, LN3=1)
+	 * <= 6 GHz and 1,2 lanes (LN0=0, LN1=1, LN2=1, LN3=0)
+	 * > 6 GHz (LN0=0, LN1=0, LN2=0, LN3=0)
 	 */
+	for (ln = 0; ln <= 3; ln++) {
+		val = I915_READ(CNL_PORT_TX_DW4_LN(port, ln));
+		val &= ~LOADGEN_SELECT;
+
+		if (((rate < 600000) && (width == 4) && (ln >= 1))  ||
+		    ((rate < 600000) && (width < 4) && ((ln == 1) || (ln == 2)))) {
+			val |= LOADGEN_SELECT;
+		}
+		I915_WRITE(CNL_PORT_TX_DW4_LN(port, ln), val);
+	}
 
 	/* 3. Set PORT_CL_DW5 SUS Clock Config to 11b */
 	val = I915_READ(CNL_PORT_CL1CM_DW5);
@@ -1920,7 +1947,7 @@ uint32_t ddi_signal_levels(struct intel_dp *intel_dp)
 	else if (IS_GEN9_LP(dev_priv))
 		bxt_ddi_vswing_sequence(dev_priv, level, port, encoder->type);
 	else if (IS_CANNONLAKE(dev_priv)) {
-		cnl_ddi_vswing_sequence(dev_priv, level, port, encoder->type);
+		cnl_ddi_vswing_sequence(encoder, level);
 		/* DDI_BUF_CTL bits 27:24 are reserved on CNL */
 		return 0;
 	}
@@ -2022,8 +2049,7 @@ static void intel_ddi_pre_enable_hdmi(struct intel_encoder *encoder,
 		bxt_ddi_vswing_sequence(dev_priv, level, port,
 					INTEL_OUTPUT_HDMI);
 	else if (IS_CANNONLAKE(dev_priv))
-		cnl_ddi_vswing_sequence(dev_priv, level, port,
-					INTEL_OUTPUT_HDMI);
+		cnl_ddi_vswing_sequence(encoder, level);
 
 	intel_hdmi->set_infoframes(drm_encoder,
 				   has_hdmi_sink,
-- 
1.9.1

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Re: [PATCH 40/67] drm/i915/cnl: Enable loadgen_select bit for vswing sequence

[Ville Syrjälä]

On Thu, Apr 06, 2017 at 12:15:36PM -0700, Rodrigo Vivi wrote:
> From: Clint Taylor <clinton.a.taylor@intel.com>
> 
> vswing programming sequence step 2 requires the Loadgen_select bit to
> be set in PORT_TX_DW4 lane reigsters per table defined by Bit rate and
> lane width. Implemented the change that was marked as FIXME in the
> driver.
> 
> v2: (Rodrigo) checkpatch fixes.
> 
> Signed-off-by: Clint Taylor <clinton.a.taylor@intel.com>
> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
> ---
>  drivers/gpu/drm/i915/intel_ddi.c | 38 ++++++++++++++++++++++++++++++++------
>  1 file changed, 32 insertions(+), 6 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
> index a4d7061..3f461c3 100644
> --- a/drivers/gpu/drm/i915/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/intel_ddi.c
> @@ -1846,10 +1846,24 @@ static void cnl_ddi_vswing_program(struct drm_i915_private *dev_priv,
>  	I915_WRITE(CNL_PORT_TX_DW7_GRP(port), val);
>  }
>  
> -static void cnl_ddi_vswing_sequence(struct drm_i915_private *dev_priv,
> -				    u32 level, enum port port, int type)
> +static void cnl_ddi_vswing_sequence(struct intel_encoder *encoder, u32 level)

This change looks unrelated. And it reminds me that I should resurrect
my remaining encoder->type fixings...

>  {
> +	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> +	struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
> +	enum port port = intel_ddi_get_encoder_port(encoder);
> +	int type = encoder->type;

> +	int width = 0;
> +	int rate = 0;
>  	u32 val;
> +	int ln = 0;
> +
> +	if ((intel_dp) && (type == INTEL_OUTPUT_EDP || type == INTEL_OUTPUT_DP)) {

intel_dp isn't needed outside this branch, so the declaration could be
moved here.

> +		width = intel_dp->lane_count;
> +		rate = intel_dp->link_rate;
> +	} else {
> +		width = 4;
> +		/* Rate is always < than 6GHz for HDMI */
> +	}
>  
>  	/*
>  	 * 1. If port type is eDP or DP,
> @@ -1865,8 +1879,21 @@ static void cnl_ddi_vswing_sequence(struct drm_i915_private *dev_priv,
>  
>  	/* 2. Program loadgen select */
>  	/*
> -	 * FIXME: Program PORT_TX_DW4_LN depending on Bit rate and used lanes
> +	 * Program PORT_TX_DW4_LN depending on Bit rate and used lanes
> +	 * <= 6 GHz and 4 lanes (LN0=0, LN1=1, LN2=1, LN3=1)
> +	 * <= 6 GHz and 1,2 lanes (LN0=0, LN1=1, LN2=1, LN3=0)
> +	 * > 6 GHz (LN0=0, LN1=0, LN2=0, LN3=0)
>  	 */
> +	for (ln = 0; ln <= 3; ln++) {

< 4 would look more typical.

> +		val = I915_READ(CNL_PORT_TX_DW4_LN(port, ln));
> +		val &= ~LOADGEN_SELECT;
> +
> +		if (((rate < 600000) && (width == 4) && (ln >= 1))  ||
> +		    ((rate < 600000) && (width < 4) && ((ln == 1) || (ln == 2)))) {

< looks wrong based on the comment. Should be <=

Looks lispy. Could trim some of the parens.

> +			val |= LOADGEN_SELECT;
> +		}
> +		I915_WRITE(CNL_PORT_TX_DW4_LN(port, ln), val);
> +	}
>  
>  	/* 3. Set PORT_CL_DW5 SUS Clock Config to 11b */
>  	val = I915_READ(CNL_PORT_CL1CM_DW5);
> @@ -1920,7 +1947,7 @@ uint32_t ddi_signal_levels(struct intel_dp *intel_dp)
>  	else if (IS_GEN9_LP(dev_priv))
>  		bxt_ddi_vswing_sequence(dev_priv, level, port, encoder->type);
>  	else if (IS_CANNONLAKE(dev_priv)) {
> -		cnl_ddi_vswing_sequence(dev_priv, level, port, encoder->type);
> +		cnl_ddi_vswing_sequence(encoder, level);
>  		/* DDI_BUF_CTL bits 27:24 are reserved on CNL */
>  		return 0;
>  	}
> @@ -2022,8 +2049,7 @@ static void intel_ddi_pre_enable_hdmi(struct intel_encoder *encoder,
>  		bxt_ddi_vswing_sequence(dev_priv, level, port,
>  					INTEL_OUTPUT_HDMI);
>  	else if (IS_CANNONLAKE(dev_priv))
> -		cnl_ddi_vswing_sequence(dev_priv, level, port,
> -					INTEL_OUTPUT_HDMI);
> +		cnl_ddi_vswing_sequence(encoder, level);
>  
>  	intel_hdmi->set_infoframes(drm_encoder,
>  				   has_hdmi_sink,
> -- 
> 1.9.1
> 
> _______________________________________________
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-- 
Ville Syrjälä
Intel OTC
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Re: [PATCH 40/67] drm/i915/cnl: Enable loadgen_select bit for vswing sequence

[Manasi Navare]

On Thu, Apr 06, 2017 at 12:15:36PM -0700, Rodrigo Vivi wrote:
> From: Clint Taylor <clinton.a.taylor@intel.com>
> 
> vswing programming sequence step 2 requires the Loadgen_select bit to
> be set in PORT_TX_DW4 lane reigsters per table defined by Bit rate and
> lane width. Implemented the change that was marked as FIXME in the
> driver.
> 
> v2: (Rodrigo) checkpatch fixes.
> 
> Signed-off-by: Clint Taylor <clinton.a.taylor@intel.com>
> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
 Reviewed-by: Manasi Navare <manasi.d.navare@intel.com>

> ---
>  drivers/gpu/drm/i915/intel_ddi.c | 38 ++++++++++++++++++++++++++++++++------
>  1 file changed, 32 insertions(+), 6 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
> index a4d7061..3f461c3 100644
> --- a/drivers/gpu/drm/i915/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/intel_ddi.c
> @@ -1846,10 +1846,24 @@ static void cnl_ddi_vswing_program(struct drm_i915_private *dev_priv,
>  	I915_WRITE(CNL_PORT_TX_DW7_GRP(port), val);
>  }
>  
> -static void cnl_ddi_vswing_sequence(struct drm_i915_private *dev_priv,
> -				    u32 level, enum port port, int type)
> +static void cnl_ddi_vswing_sequence(struct intel_encoder *encoder, u32 level)
>  {
> +	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> +	struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
> +	enum port port = intel_ddi_get_encoder_port(encoder);
> +	int type = encoder->type;
> +	int width = 0;
> +	int rate = 0;
>  	u32 val;
> +	int ln = 0;
> +
> +	if ((intel_dp) && (type == INTEL_OUTPUT_EDP || type == INTEL_OUTPUT_DP)) {
> +		width = intel_dp->lane_count;
> +		rate = intel_dp->link_rate;
> +	} else {
> +		width = 4;
> +		/* Rate is always < than 6GHz for HDMI */
> +	}
>  
>  	/*
>  	 * 1. If port type is eDP or DP,
> @@ -1865,8 +1879,21 @@ static void cnl_ddi_vswing_sequence(struct drm_i915_private *dev_priv,
>  
>  	/* 2. Program loadgen select */
>  	/*
> -	 * FIXME: Program PORT_TX_DW4_LN depending on Bit rate and used lanes
> +	 * Program PORT_TX_DW4_LN depending on Bit rate and used lanes
> +	 * <= 6 GHz and 4 lanes (LN0=0, LN1=1, LN2=1, LN3=1)
> +	 * <= 6 GHz and 1,2 lanes (LN0=0, LN1=1, LN2=1, LN3=0)
> +	 * > 6 GHz (LN0=0, LN1=0, LN2=0, LN3=0)
>  	 */
> +	for (ln = 0; ln <= 3; ln++) {
> +		val = I915_READ(CNL_PORT_TX_DW4_LN(port, ln));
> +		val &= ~LOADGEN_SELECT;
> +
> +		if (((rate < 600000) && (width == 4) && (ln >= 1))  ||
> +		    ((rate < 600000) && (width < 4) && ((ln == 1) || (ln == 2)))) {
> +			val |= LOADGEN_SELECT;
> +		}

Verified this from the Bspec values of loadgen_select for specific link rate
and lane count.

Manasi
> +		I915_WRITE(CNL_PORT_TX_DW4_LN(port, ln), val);
> +	}
>  
>  	/* 3. Set PORT_CL_DW5 SUS Clock Config to 11b */
>  	val = I915_READ(CNL_PORT_CL1CM_DW5);
> @@ -1920,7 +1947,7 @@ uint32_t ddi_signal_levels(struct intel_dp *intel_dp)
>  	else if (IS_GEN9_LP(dev_priv))
>  		bxt_ddi_vswing_sequence(dev_priv, level, port, encoder->type);
>  	else if (IS_CANNONLAKE(dev_priv)) {
> -		cnl_ddi_vswing_sequence(dev_priv, level, port, encoder->type);
> +		cnl_ddi_vswing_sequence(encoder, level);
>  		/* DDI_BUF_CTL bits 27:24 are reserved on CNL */
>  		return 0;
>  	}
> @@ -2022,8 +2049,7 @@ static void intel_ddi_pre_enable_hdmi(struct intel_encoder *encoder,
>  		bxt_ddi_vswing_sequence(dev_priv, level, port,
>  					INTEL_OUTPUT_HDMI);
>  	else if (IS_CANNONLAKE(dev_priv))
> -		cnl_ddi_vswing_sequence(dev_priv, level, port,
> -					INTEL_OUTPUT_HDMI);
> +		cnl_ddi_vswing_sequence(encoder, level);
>  
>  	intel_hdmi->set_infoframes(drm_encoder,
>  				   has_hdmi_sink,
> -- 
> 1.9.1
> 
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[PATCH 41/67] drm/i915/cnl: Add slice and subslice information to debugfs.

[Rodrigo Vivi]

A missing part that maybe it is better to squash to commit
"drm/i915/cnl: Configure EU slice power gating." later
but before upstreaming it.

Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
---
 drivers/gpu/drm/i915/i915_debugfs.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
index da22aba..d07257b 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -4541,7 +4541,7 @@ static void gen9_sseu_device_status(struct drm_i915_private *dev_priv,
 
 		sseu->slice_mask |= BIT(s);
 
-		if (IS_GEN9_BC(dev_priv))
+		if (IS_GEN9_BC(dev_priv) || IS_CANNONLAKE(dev_priv))
 			sseu->subslice_mask =
 				INTEL_INFO(dev_priv)->sseu.subslice_mask;
 
-- 
1.9.1

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[PATCH 42/67] drm/i915/DMC/CNL: Load DMC on CNL

[Rodrigo Vivi]

From: Anusha Srivatsa <anusha.srivatsa@intel.com>

This patch loads the DMC on CNL.The firmware version
is 1.04.

v2: (Rodrigo) Remove MODULE_FIRMWARE.

Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
---
 drivers/gpu/drm/i915/i915_pci.c  |  1 +
 drivers/gpu/drm/i915/intel_csr.c | 11 +++++++++--
 2 files changed, 10 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index c84ef7c..bace848 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -437,6 +437,7 @@
 	.platform = INTEL_CANNONLAKE,
 	.gen = 10,
 	.ddb_size = 1024,
+	.has_csr = 1,
 };
 
 /*
diff --git a/drivers/gpu/drm/i915/intel_csr.c b/drivers/gpu/drm/i915/intel_csr.c
index 1575bde..496a965 100644
--- a/drivers/gpu/drm/i915/intel_csr.c
+++ b/drivers/gpu/drm/i915/intel_csr.c
@@ -37,6 +37,9 @@
 #define I915_CSR_GLK "i915/glk_dmc_ver1_04.bin"
 #define GLK_CSR_VERSION_REQUIRED	CSR_VERSION(1, 4)
 
+#define I915_CSR_CNL "i915/cnl_dmc_ver1_04.bin"
+#define CNL_CSR_VERSION_REQUIRED	CSR_VERSION(1, 4)
+
 #define I915_CSR_KBL "i915/kbl_dmc_ver1_01.bin"
 MODULE_FIRMWARE(I915_CSR_KBL);
 #define KBL_CSR_VERSION_REQUIRED	CSR_VERSION(1, 1)
@@ -289,7 +292,9 @@ static uint32_t *parse_csr_fw(struct drm_i915_private *dev_priv,
 
 	csr->version = css_header->version;
 
-	if (IS_GEMINILAKE(dev_priv)) {
+	if (IS_CANNONLAKE(dev_priv)) {
+		required_version = CNL_CSR_VERSION_REQUIRED;
+	} else if (IS_GEMINILAKE(dev_priv)) {
 		required_version = GLK_CSR_VERSION_REQUIRED;
 	} else if (IS_KABYLAKE(dev_priv)) {
 		required_version = KBL_CSR_VERSION_REQUIRED;
@@ -438,7 +443,9 @@ void intel_csr_ucode_init(struct drm_i915_private *dev_priv)
 	if (!HAS_CSR(dev_priv))
 		return;
 
-	if (IS_GEMINILAKE(dev_priv))
+	if (IS_CANNONLAKE(dev_priv))
+		csr->fw_path = I915_CSR_CNL;
+	else if (IS_GEMINILAKE(dev_priv))
 		csr->fw_path = I915_CSR_GLK;
 	else if (IS_KABYLAKE(dev_priv))
 		csr->fw_path = I915_CSR_KBL;
-- 
1.9.1

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Re: [PATCH 42/67] drm/i915/DMC/CNL: Load DMC on CNL

[Animesh Manna]

On 4/7/2017 12:45 AM, Rodrigo Vivi wrote:
> From: Anusha Srivatsa <anusha.srivatsa@intel.com>
>
> This patch loads the DMC on CNL.The firmware version
> is 1.04.
>
> v2: (Rodrigo) Remove MODULE_FIRMWARE.
>
> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
> Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
> ---
>   drivers/gpu/drm/i915/i915_pci.c  |  1 +
>   drivers/gpu/drm/i915/intel_csr.c | 11 +++++++++--
>   2 files changed, 10 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
> index c84ef7c..bace848 100644
> --- a/drivers/gpu/drm/i915/i915_pci.c
> +++ b/drivers/gpu/drm/i915/i915_pci.c
> @@ -437,6 +437,7 @@
>   	.platform = INTEL_CANNONLAKE,
>   	.gen = 10,
>   	.ddb_size = 1024,
> +	.has_csr = 1,
>   };
>   
>   /*
> diff --git a/drivers/gpu/drm/i915/intel_csr.c b/drivers/gpu/drm/i915/intel_csr.c
> index 1575bde..496a965 100644
> --- a/drivers/gpu/drm/i915/intel_csr.c
> +++ b/drivers/gpu/drm/i915/intel_csr.c
> @@ -37,6 +37,9 @@
>   #define I915_CSR_GLK "i915/glk_dmc_ver1_04.bin"
>   #define GLK_CSR_VERSION_REQUIRED	CSR_VERSION(1, 4)
>   
> +#define I915_CSR_CNL "i915/cnl_dmc_ver1_04.bin"
> +#define CNL_CSR_VERSION_REQUIRED	CSR_VERSION(1, 4)
> +
>   #define I915_CSR_KBL "i915/kbl_dmc_ver1_01.bin"
>   MODULE_FIRMWARE(I915_CSR_KBL);
>   #define KBL_CSR_VERSION_REQUIRED	CSR_VERSION(1, 1)
> @@ -289,7 +292,9 @@ static uint32_t *parse_csr_fw(struct drm_i915_private *dev_priv,
>   
>   	csr->version = css_header->version;
>   
> -	if (IS_GEMINILAKE(dev_priv)) {
> +	if (IS_CANNONLAKE(dev_priv)) {
> +		required_version = CNL_CSR_VERSION_REQUIRED;
> +	} else if (IS_GEMINILAKE(dev_priv)) {
>   		required_version = GLK_CSR_VERSION_REQUIRED;
>   	} else if (IS_KABYLAKE(dev_priv)) {
>   		required_version = KBL_CSR_VERSION_REQUIRED;
> @@ -438,7 +443,9 @@ void intel_csr_ucode_init(struct drm_i915_private *dev_priv)
>   	if (!HAS_CSR(dev_priv))
>   		return;
>   
> -	if (IS_GEMINILAKE(dev_priv))
> +	if (IS_CANNONLAKE(dev_priv))
> +		csr->fw_path = I915_CSR_CNL;
> +	else if (IS_GEMINILAKE(dev_priv))
>   		csr->fw_path = I915_CSR_GLK;
>   	else if (IS_KABYLAKE(dev_priv))
>   		csr->fw_path = I915_CSR_KBL;

Changes looks good to me.

Reviewed-by: Animesh Manna <animesh.manna@intel.com>

Regards,

Animesh


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[PATCH 43/67] drm/i915: Use HAS_CSR instead of gen number on DMC load.

[Rodrigo Vivi]

Since we have HAS_CSR tied to the platform definition
let's use this instead of checking per platform.

One less thing to worry when adding support to new platforms.

Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
---
 drivers/gpu/drm/i915/intel_csr.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/intel_csr.c b/drivers/gpu/drm/i915/intel_csr.c
index 496a965..eecee65 100644
--- a/drivers/gpu/drm/i915/intel_csr.c
+++ b/drivers/gpu/drm/i915/intel_csr.c
@@ -241,7 +241,7 @@ void intel_csr_load_program(struct drm_i915_private *dev_priv)
 	u32 *payload = dev_priv->csr.dmc_payload;
 	uint32_t i, fw_size;
 
-	if (!IS_GEN9(dev_priv)) {
+	if (!HAS_CSR(dev_priv)) {
 		DRM_ERROR("No CSR support available for this platform\n");
 		return;
 	}
-- 
1.9.1

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Re: [PATCH 43/67] drm/i915: Use HAS_CSR instead of gen number on DMC load.

[Animesh Manna]

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On 4/7/2017 12:45 AM, Rodrigo Vivi wrote:
> Since we have HAS_CSR tied to the platform definition
> let's use this instead of checking per platform.
>
> One less thing to worry when adding support to new platforms.
>
> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
> ---
>   drivers/gpu/drm/i915/intel_csr.c | 2 +-
>   1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_csr.c b/drivers/gpu/drm/i915/intel_csr.c
> index 496a965..eecee65 100644
> --- a/drivers/gpu/drm/i915/intel_csr.c
> +++ b/drivers/gpu/drm/i915/intel_csr.c
> @@ -241,7 +241,7 @@ void intel_csr_load_program(struct drm_i915_private *dev_priv)
>   	u32 *payload = dev_priv->csr.dmc_payload;
>   	uint32_t i, fw_size;
>   
> -	if (!IS_GEN9(dev_priv)) {
> +	if (!HAS_CSR(dev_priv)) {
>   		DRM_ERROR("No CSR support available for this platform\n");
>   		return;
>   	}

Changes looks good to me.

Reviewed-by: Animesh Manna<animesh.manna@intel.com>

Regards,

Animesh



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[-- Attachment #2: Type: text/plain, Size: 160 bytes --]

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[PATCH 44/67] drm/i915/cnl: DC3 to DC5 counters available on CNL.

[Rodrigo Vivi]

There is no confirmation if the DC5 to DC6 is available on CNL
though. But I could see DC3 to DC5 counter increasing reliably.
So let's at least add this one.

Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
---
 drivers/gpu/drm/i915/i915_debugfs.c | 5 ++++-
 1 file changed, 4 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
index d07257b..2ae79a6 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -2859,7 +2859,10 @@ static int i915_dmc_info(struct seq_file *m, void *unused)
 	seq_printf(m, "version: %d.%d\n", CSR_VERSION_MAJOR(csr->version),
 		   CSR_VERSION_MINOR(csr->version));
 
-	if (IS_SKYLAKE(dev_priv) && csr->version >= CSR_VERSION(1, 6)) {
+	if (IS_CANNONLAKE(dev_priv)) {
+		seq_printf(m, "DC3 -> DC5 count: %d\n",
+			   I915_READ(SKL_CSR_DC3_DC5_COUNT));
+	} else if (IS_SKYLAKE(dev_priv) && csr->version >= CSR_VERSION(1, 6)) {
 		seq_printf(m, "DC3 -> DC5 count: %d\n",
 			   I915_READ(SKL_CSR_DC3_DC5_COUNT));
 		seq_printf(m, "DC5 -> DC6 count: %d\n",
-- 
1.9.1

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Re: [PATCH 44/67] drm/i915/cnl: DC3 to DC5 counters available on CNL.

[Animesh Manna]

On 4/7/2017 12:45 AM, Rodrigo Vivi wrote:
> There is no confirmation if the DC5 to DC6 is available on CNL
> though. But I could see DC3 to DC5 counter increasing reliably.
> So let's at least add this one.
>
> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
> ---
>   drivers/gpu/drm/i915/i915_debugfs.c | 5 ++++-
>   1 file changed, 4 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
> index d07257b..2ae79a6 100644
> --- a/drivers/gpu/drm/i915/i915_debugfs.c
> +++ b/drivers/gpu/drm/i915/i915_debugfs.c
> @@ -2859,7 +2859,10 @@ static int i915_dmc_info(struct seq_file *m, void *unused)
>   	seq_printf(m, "version: %d.%d\n", CSR_VERSION_MAJOR(csr->version),
>   		   CSR_VERSION_MINOR(csr->version));
>   
> -	if (IS_SKYLAKE(dev_priv) && csr->version >= CSR_VERSION(1, 6)) {
> +	if (IS_CANNONLAKE(dev_priv)) {
> +		seq_printf(m, "DC3 -> DC5 count: %d\n",
> +			   I915_READ(SKL_CSR_DC3_DC5_COUNT));

Have not found any info regarding DC5/DC6-counter in bspec for CNL.
I assume H/W team stop exposing these counter as I can not see DC5/DC6 counter details for other platform other than gen9(skl/bxt).
Not sure is it ok to rely on something which is not confirmed.

Regards,
Animesh

> +	} else if (IS_SKYLAKE(dev_priv) && csr->version >= CSR_VERSION(1, 6)) {
>   		seq_printf(m, "DC3 -> DC5 count: %d\n",
>   			   I915_READ(SKL_CSR_DC3_DC5_COUNT));
>   		seq_printf(m, "DC5 -> DC6 count: %d\n",

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[PATCH 45/67] drm/i915/cnl: Add max allowed Cannonlake DC.

[Rodrigo Vivi]

This is a follow-up after enabling DC states with
commit: "drm/i915/DMC/CNL: Load DMC on CNL".

Cc: Anusha Srivatsa <anusha.srivatsa@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
---
 drivers/gpu/drm/i915/intel_runtime_pm.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c b/drivers/gpu/drm/i915/intel_runtime_pm.c
index 5c3c6ec..a05fbd4 100644
--- a/drivers/gpu/drm/i915/intel_runtime_pm.c
+++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
@@ -2419,7 +2419,7 @@ static uint32_t get_allowed_dc_mask(const struct drm_i915_private *dev_priv,
 	int requested_dc;
 	int max_dc;
 
-	if (IS_GEN9_BC(dev_priv)) {
+	if (IS_GEN9_BC(dev_priv) || IS_CANNONLAKE(dev_priv)) {
 		max_dc = 2;
 		mask = 0;
 	} else if (IS_GEN9_LP(dev_priv)) {
-- 
1.9.1

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[PATCH 46/67] drm/i915/cnl: Add allowed DP rates for Cannonlake.

[Rodrigo Vivi]

One warning is that in order to get DPLL Link rates
3240 and 4050 that allows 648000 and 810000 is that:
"Some SKUs may require elevated I/O voltage to support
this."

v2: Rebase on top of source_rates changes.

Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
---
 drivers/gpu/drm/i915/intel_dp.c | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index b7adf0a..90d437ec 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -97,6 +97,9 @@ struct dp_link_dpll {
 				  324000, 432000, 540000 };
 static const int skl_rates[] = { 162000, 216000, 270000,
 				  324000, 432000, 540000 };
+static const int cnl_rates[] = { 162000, 216000, 270000,
+				 324000, 432000, 540000,
+				 648000, 810000 };
 static const int default_rates[] = { 162000, 270000, 540000 };
 
 /**
@@ -247,6 +250,9 @@ static u8 intel_dp_max_lane_count(struct intel_dp *intel_dp)
 	if (IS_GEN9_LP(dev_priv)) {
 		source_rates = bxt_rates;
 		size = ARRAY_SIZE(bxt_rates);
+	} else if (IS_CANNONLAKE(dev_priv)) {
+		source_rates = cnl_rates;
+		size = ARRAY_SIZE(cnl_rates);
 	} else if (IS_GEN9_BC(dev_priv)) {
 		source_rates = skl_rates;
 		size = ARRAY_SIZE(skl_rates);
-- 
1.9.1

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[PATCH 47/67] drm/i915/cnl: Dump the right pll registers when dumping pipe config.

[Rodrigo Vivi]

Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
---
 drivers/gpu/drm/i915/intel_dpll_mgr.c | 11 ++++++++++-
 1 file changed, 10 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/intel_dpll_mgr.c b/drivers/gpu/drm/i915/intel_dpll_mgr.c
index 8e669b6..7a2f1be 100644
--- a/drivers/gpu/drm/i915/intel_dpll_mgr.c
+++ b/drivers/gpu/drm/i915/intel_dpll_mgr.c
@@ -2378,6 +2378,15 @@ bool cnl_ddi_dp_set_dpll_hw_state(int clock,
 	return pll;
 }
 
+static void cnl_dump_hw_state(struct drm_i915_private *dev_priv,
+			      struct intel_dpll_hw_state *hw_state)
+{
+	DRM_DEBUG_KMS("dpll_hw_state: "
+		      "cfgcr0: 0x%x, cfgcr1: 0x%x\n",
+		      hw_state->cfgcr0,
+		      hw_state->cfgcr1);
+}
+
 static const struct intel_shared_dpll_funcs cnl_ddi_pll_funcs = {
 	.enable = cnl_ddi_pll_enable,
 	.disable = cnl_ddi_pll_disable,
@@ -2394,7 +2403,7 @@ bool cnl_ddi_dp_set_dpll_hw_state(int clock,
 static const struct intel_dpll_mgr cnl_pll_mgr = {
 	.dpll_info = cnl_plls,
 	.get_dpll = cnl_get_dpll,
-	.dump_hw_state = skl_dump_hw_state,
+	.dump_hw_state = cnl_dump_hw_state,
 };
 
 /**
-- 
1.9.1

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[PATCH 48/67] drm/i915/cnl: Get DDI clock based on PLLs.

[Rodrigo Vivi]

PLLs are the source clocks for the DDIs so in order
to determine the ddi clock we need to check the PLL
configuration.

v2: Mika pointed out that 24 was hardcoded while it
    should consider ref clock that can be either 24KHz
    or 19.2KHz on CNL.

Reviewed-by: Mika Kahola <mika.kahola@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h  |   2 +
 drivers/gpu/drm/i915/intel_ddi.c | 111 +++++++++++++++++++++++++++++++++++++++
 2 files changed, 113 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 55ffec7..51ffbee 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -8329,6 +8329,7 @@ enum {
 #define  DPLL_CFGCR0_LINK_RATE_3240	(6 << 25)
 #define  DPLL_CFGCR0_LINK_RATE_4050	(7 << 25)
 #define  DPLL_CFGCR0_DCO_FRACTION_MASK	(0x7fff << 10)
+#define  DPLL_CFGCR0_DCO_FRAC_SHIFT	(10)
 #define  DPLL_CFGCR0_DCO_FRACTION(x)	((x) << 10)
 #define  DPLL_CFGCR0_DCO_INTEGER_MASK	(0x3ff)
 #define CNL_DPLL_CFGCR0(pll)		_MMIO_PLL(pll, _CNL_DPLL0_CFGCR0, _CNL_DPLL1_CFGCR0)
@@ -8336,6 +8337,7 @@ enum {
 #define _CNL_DPLL0_CFGCR1		0x6C004
 #define _CNL_DPLL1_CFGCR1		0x6C084
 #define  DPLL_CFGCR1_QDIV_RATIO_MASK	(0xff << 10)
+#define  DPLL_CFGCR1_QDIV_RATIO_SHIFT	(10)
 #define  DPLL_CFGCR1_QDIV_RATIO(x)	((x) << 10)
 #define  DPLL_CFGCR1_QDIV_MODE(x)	((x) << 9)
 #define  DPLL_CFGCR1_KDIV_MASK		(7 << 6)
diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
index 3f461c3..dd804c0 100644
--- a/drivers/gpu/drm/i915/intel_ddi.c
+++ b/drivers/gpu/drm/i915/intel_ddi.c
@@ -1102,6 +1102,62 @@ static int skl_calc_wrpll_link(struct drm_i915_private *dev_priv,
 	return dco_freq / (p0 * p1 * p2 * 5);
 }
 
+static int cnl_calc_wrpll_link(struct drm_i915_private *dev_priv,
+			       uint32_t pll_id)
+{
+	uint32_t cfgcr0, cfgcr1;
+	uint32_t p0, p1, p2, dco_freq, ref_clock;
+
+	cfgcr0 = I915_READ(CNL_DPLL_CFGCR0(pll_id));
+	cfgcr1 = I915_READ(CNL_DPLL_CFGCR1(pll_id));
+
+	p0 = cfgcr1 & DPLL_CFGCR1_PDIV_MASK;
+	p2 = cfgcr1 & DPLL_CFGCR1_KDIV_MASK;
+
+	if (cfgcr1 & DPLL_CFGCR1_QDIV_MODE(1))
+		p1 = (cfgcr1 & DPLL_CFGCR1_QDIV_RATIO_MASK) >>
+			DPLL_CFGCR1_QDIV_RATIO_SHIFT;
+	else
+		p1 = 1;
+
+
+	switch (p0) {
+	case DPLL_CFGCR1_PDIV_2:
+		p0 = 2;
+		break;
+	case DPLL_CFGCR1_PDIV_3:
+		p0 = 3;
+		break;
+	case DPLL_CFGCR1_PDIV_5:
+		p0 = 5;
+		break;
+	case DPLL_CFGCR1_PDIV_7:
+		p0 = 7;
+		break;
+	}
+
+	switch (p2) {
+	case DPLL_CFGCR1_KDIV_1:
+		p2 = 1;
+		break;
+	case DPLL_CFGCR1_KDIV_2:
+		p2 = 2;
+		break;
+	case DPLL_CFGCR1_KDIV_4:
+		p2 = 4;
+		break;
+	}
+
+	ref_clock = dev_priv->cdclk.hw.ref;
+
+	dco_freq = (cfgcr0 & DPLL_CFGCR0_DCO_INTEGER_MASK) * ref_clock;
+
+	dco_freq += (((cfgcr0 & DPLL_CFGCR0_DCO_FRACTION_MASK) >>
+		      DPLL_CFGCR0_DCO_FRAC_SHIFT) * ref_clock) / 0x8000;
+
+	return dco_freq / (p0 * p1 * p2 * 5);
+}
+
 static void ddi_dotclock_get(struct intel_crtc_state *pipe_config)
 {
 	int dotclock;
@@ -1123,6 +1179,59 @@ static void ddi_dotclock_get(struct intel_crtc_state *pipe_config)
 	pipe_config->base.adjusted_mode.crtc_clock = dotclock;
 }
 
+static void cnl_ddi_clock_get(struct intel_encoder *encoder,
+			      struct intel_crtc_state *pipe_config)
+{
+	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
+	int link_clock = 0;
+	uint32_t cfgcr0, pll_id;
+
+	pll_id = intel_get_shared_dpll_id(dev_priv, pipe_config->shared_dpll);
+
+	cfgcr0 = I915_READ(CNL_DPLL_CFGCR0(pll_id));
+
+	if (cfgcr0 & DPLL_CFGCR0_HDMI_MODE) {
+		link_clock = cnl_calc_wrpll_link(dev_priv, pll_id);
+	} else {
+		link_clock = cfgcr0 & DPLL_CFGCR0_LINK_RATE_MASK;
+
+		switch (link_clock) {
+		case DPLL_CFGCR0_LINK_RATE_810:
+			link_clock = 81000;
+			break;
+		case DPLL_CFGCR0_LINK_RATE_1080:
+			link_clock = 108000;
+			break;
+		case DPLL_CFGCR0_LINK_RATE_1350:
+			link_clock = 135000;
+			break;
+		case DPLL_CFGCR0_LINK_RATE_1620:
+			link_clock = 162000;
+			break;
+		case DPLL_CFGCR0_LINK_RATE_2160:
+			link_clock = 216000;
+			break;
+		case DPLL_CFGCR0_LINK_RATE_2700:
+			link_clock = 270000;
+			break;
+		case DPLL_CFGCR0_LINK_RATE_3240:
+			link_clock = 324000;
+			break;
+		case DPLL_CFGCR0_LINK_RATE_4050:
+			link_clock = 405000;
+			break;
+		default:
+			WARN(1, "Unsupported link rate\n");
+			break;
+		}
+		link_clock *= 2;
+	}
+
+	pipe_config->port_clock = link_clock;
+
+	ddi_dotclock_get(pipe_config);
+}
+
 static void skl_ddi_clock_get(struct intel_encoder *encoder,
 				struct intel_crtc_state *pipe_config)
 {
@@ -1266,6 +1375,8 @@ void intel_ddi_clock_get(struct intel_encoder *encoder,
 		skl_ddi_clock_get(encoder, pipe_config);
 	else if (IS_GEN9_LP(dev_priv))
 		bxt_ddi_clock_get(encoder, pipe_config);
+	else if (IS_CANNONLAKE(dev_priv))
+		cnl_ddi_clock_get(encoder, pipe_config);
 }
 
 void intel_ddi_set_pipe_settings(const struct intel_crtc_state *crtc_state)
-- 
1.9.1

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[PATCH 49/67] drm/i915/cnl: Avoid old DDI translation functions on Cannonlake.

[Rodrigo Vivi]

Cannonlake uses a different swing voltage initalization
sequence scheme that doesn't require these old functions.

All other DDI, voltage swing and PLLs initialialization
and configuration are already in place for Cannonlake.
This patch only removes unecessary steps probably saving
us from some useless warnings.

Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
---
 drivers/gpu/drm/i915/intel_ddi.c | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
index dd804c0..1773e17 100644
--- a/drivers/gpu/drm/i915/intel_ddi.c
+++ b/drivers/gpu/drm/i915/intel_ddi.c
@@ -595,7 +595,7 @@ static int intel_ddi_hdmi_level(struct drm_i915_private *dev_priv, enum port por
 
 	hdmi_level = dev_priv->vbt.ddi_port_info[port].hdmi_level_shift;
 
-	if (IS_GEN9_LP(dev_priv))
+	if (IS_GEN9_LP(dev_priv) || INTEL_GEN(dev_priv) >= 10)
 		return hdmi_level;
 
 	if (IS_GEN9_BC(dev_priv)) {
@@ -687,7 +687,7 @@ static void intel_prepare_dp_ddi_buffers(struct intel_encoder *encoder)
 	enum port port = intel_ddi_get_encoder_port(encoder);
 	const struct ddi_buf_trans *ddi_translations;
 
-	if (IS_GEN9_LP(dev_priv))
+	if (IS_GEN9_LP(dev_priv) || INTEL_GEN(dev_priv) >= 10)
 		return;
 
 	switch (encoder->type) {
@@ -740,7 +740,7 @@ static void intel_prepare_hdmi_ddi_buffers(struct intel_encoder *encoder)
 	enum port port = intel_ddi_get_encoder_port(encoder);
 	const struct ddi_buf_trans *ddi_translations_hdmi;
 
-	if (IS_GEN9_LP(dev_priv))
+	if (IS_GEN9_LP(dev_priv) || INTEL_GEN(dev_priv) >= 10)
 		return;
 
 	hdmi_level = intel_ddi_hdmi_level(dev_priv, port);
-- 
1.9.1

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[PATCH 50/67] drm/i915/gen10+: use the SKL code for reading WM latencies

[Rodrigo Vivi]

From: Paulo Zanoni <paulo.r.zanoni@intel.com>

Gen 10 should use the exact same code as Gen 9, so change the check to
take this into consideration, and also assume that future platforms
will run this code.

Also add a MISSING_CASE(), just in case we do something wrong, instead
of silently failing.

Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
---
 drivers/gpu/drm/i915/intel_pm.c | 6 ++++--
 1 file changed, 4 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 4c07b91..a2b2509 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -2291,7 +2291,7 @@ static void ilk_compute_wm_level(const struct drm_i915_private *dev_priv,
 static void intel_read_wm_latency(struct drm_i915_private *dev_priv,
 				  uint16_t wm[8])
 {
-	if (IS_GEN9(dev_priv)) {
+	if (INTEL_GEN(dev_priv) >= 9) {
 		uint32_t val;
 		int ret, i;
 		int level, max_level = ilk_wm_max_level(dev_priv);
@@ -2351,7 +2351,7 @@ static void intel_read_wm_latency(struct drm_i915_private *dev_priv,
 		}
 
 		/*
-		 * WaWmMemoryReadLatency:skl,glk
+		 * WaWmMemoryReadLatency:skl+,glk
 		 *
 		 * punit doesn't take into account the read latency so we need
 		 * to add 2us to the various latency levels we retrieve from the
@@ -2390,6 +2390,8 @@ static void intel_read_wm_latency(struct drm_i915_private *dev_priv,
 		wm[0] = 7;
 		wm[1] = (mltr >> MLTR_WM1_SHIFT) & ILK_SRLT_MASK;
 		wm[2] = (mltr >> MLTR_WM2_SHIFT) & ILK_SRLT_MASK;
+	} else {
+		MISSING_CASE(INTEL_DEVID(dev_priv));
 	}
 }
 
-- 
1.9.1

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Re: [PATCH 50/67] drm/i915/gen10+: use the SKL code for reading WM latencies

[Ville Syrjälä]

On Thu, Apr 06, 2017 at 12:15:46PM -0700, Rodrigo Vivi wrote:
> From: Paulo Zanoni <paulo.r.zanoni@intel.com>
> 
> Gen 10 should use the exact same code as Gen 9, so change the check to
> take this into consideration, and also assume that future platforms
> will run this code.
> 
> Also add a MISSING_CASE(), just in case we do something wrong, instead
> of silently failing.
> 
> Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
> ---
>  drivers/gpu/drm/i915/intel_pm.c | 6 ++++--
>  1 file changed, 4 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index 4c07b91..a2b2509 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -2291,7 +2291,7 @@ static void ilk_compute_wm_level(const struct drm_i915_private *dev_priv,
>  static void intel_read_wm_latency(struct drm_i915_private *dev_priv,
>  				  uint16_t wm[8])
>  {
> -	if (IS_GEN9(dev_priv)) {
> +	if (INTEL_GEN(dev_priv) >= 9) {
>  		uint32_t val;
>  		int ret, i;
>  		int level, max_level = ilk_wm_max_level(dev_priv);
> @@ -2351,7 +2351,7 @@ static void intel_read_wm_latency(struct drm_i915_private *dev_priv,
>  		}
>  
>  		/*
> -		 * WaWmMemoryReadLatency:skl,glk
> +		 * WaWmMemoryReadLatency:skl+,glk

When we did we start to use the '+' notation in the w/a notes?

What would it mean to say 'skl+,glk'? Is BXT included or not?

>  		 *
>  		 * punit doesn't take into account the read latency so we need
>  		 * to add 2us to the various latency levels we retrieve from the
> @@ -2390,6 +2390,8 @@ static void intel_read_wm_latency(struct drm_i915_private *dev_priv,
>  		wm[0] = 7;
>  		wm[1] = (mltr >> MLTR_WM1_SHIFT) & ILK_SRLT_MASK;
>  		wm[2] = (mltr >> MLTR_WM2_SHIFT) & ILK_SRLT_MASK;
> +	} else {
> +		MISSING_CASE(INTEL_DEVID(dev_priv));
>  	}
>  }
>  
> -- 
> 1.9.1
> 
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
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Re: [PATCH 50/67] drm/i915/gen10+: use the SKL code for reading WM latencies

[Paulo Zanoni]

Em Seg, 2017-04-24 às 21:22 +0300, Ville Syrjälä escreveu:
> On Thu, Apr 06, 2017 at 12:15:46PM -0700, Rodrigo Vivi wrote:
> > 
> > From: Paulo Zanoni <paulo.r.zanoni@intel.com>
> > 
> > Gen 10 should use the exact same code as Gen 9, so change the check
> > to
> > take this into consideration, and also assume that future platforms
> > will run this code.
> > 
> > Also add a MISSING_CASE(), just in case we do something wrong,
> > instead
> > of silently failing.
> > 
> > Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
> > Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
> > ---
> >  drivers/gpu/drm/i915/intel_pm.c | 6 ++++--
> >  1 file changed, 4 insertions(+), 2 deletions(-)
> > 
> > diff --git a/drivers/gpu/drm/i915/intel_pm.c
> > b/drivers/gpu/drm/i915/intel_pm.c
> > index 4c07b91..a2b2509 100644
> > --- a/drivers/gpu/drm/i915/intel_pm.c
> > +++ b/drivers/gpu/drm/i915/intel_pm.c
> > @@ -2291,7 +2291,7 @@ static void ilk_compute_wm_level(const struct
> > drm_i915_private *dev_priv,
> >  static void intel_read_wm_latency(struct drm_i915_private
> > *dev_priv,
> >  				  uint16_t wm[8])
> >  {
> > -	if (IS_GEN9(dev_priv)) {
> > +	if (INTEL_GEN(dev_priv) >= 9) {
> >  		uint32_t val;
> >  		int ret, i;
> >  		int level, max_level = ilk_wm_max_level(dev_priv);
> > @@ -2351,7 +2351,7 @@ static void intel_read_wm_latency(struct
> > drm_i915_private *dev_priv,
> >  		}
> >  
> >  		/*
> > -		 * WaWmMemoryReadLatency:skl,glk
> > +		 * WaWmMemoryReadLatency:skl+,glk
> 
> When we did we start to use the '+' notation in the w/a notes?

The + is because this code, when written, was going to be run for every
gen >= 9. Stuff changed, rebases happened, so I guess I'll need to re-
check to see that's still the case.

> 
> What would it mean to say 'skl+,glk'? Is BXT included or not?

When I originally wrote this patch, I changed from "skl" to "skl+",
there was no glk, and it was added by not-me during some rebase at some
point.

> 
> > 
> >  		 *
> >  		 * punit doesn't take into account the read
> > latency so we need
> >  		 * to add 2us to the various latency levels we
> > retrieve from the
> > @@ -2390,6 +2390,8 @@ static void intel_read_wm_latency(struct
> > drm_i915_private *dev_priv,
> >  		wm[0] = 7;
> >  		wm[1] = (mltr >> MLTR_WM1_SHIFT) & ILK_SRLT_MASK;
> >  		wm[2] = (mltr >> MLTR_WM2_SHIFT) & ILK_SRLT_MASK;
> > +	} else {
> > +		MISSING_CASE(INTEL_DEVID(dev_priv));
> >  	}
> >  }
> >  
> > -- 
> > 1.9.1
> > 
> > _______________________________________________
> > Intel-gfx mailing list
> > Intel-gfx@lists.freedesktop.org
> > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
> 
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Re: [PATCH 50/67] drm/i915/gen10+: use the SKL code for reading WM latencies

[Ville Syrjälä]

On Mon, Apr 24, 2017 at 04:10:41PM -0300, Paulo Zanoni wrote:
> Em Seg, 2017-04-24 às 21:22 +0300, Ville Syrjälä escreveu:
> > On Thu, Apr 06, 2017 at 12:15:46PM -0700, Rodrigo Vivi wrote:
> > > 
> > > From: Paulo Zanoni <paulo.r.zanoni@intel.com>
> > > 
> > > Gen 10 should use the exact same code as Gen 9, so change the check
> > > to
> > > take this into consideration, and also assume that future platforms
> > > will run this code.
> > > 
> > > Also add a MISSING_CASE(), just in case we do something wrong,
> > > instead
> > > of silently failing.
> > > 
> > > Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
> > > Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
> > > ---
> > >  drivers/gpu/drm/i915/intel_pm.c | 6 ++++--
> > >  1 file changed, 4 insertions(+), 2 deletions(-)
> > > 
> > > diff --git a/drivers/gpu/drm/i915/intel_pm.c
> > > b/drivers/gpu/drm/i915/intel_pm.c
> > > index 4c07b91..a2b2509 100644
> > > --- a/drivers/gpu/drm/i915/intel_pm.c
> > > +++ b/drivers/gpu/drm/i915/intel_pm.c
> > > @@ -2291,7 +2291,7 @@ static void ilk_compute_wm_level(const struct
> > > drm_i915_private *dev_priv,
> > >  static void intel_read_wm_latency(struct drm_i915_private
> > > *dev_priv,
> > >  				  uint16_t wm[8])
> > >  {
> > > -	if (IS_GEN9(dev_priv)) {
> > > +	if (INTEL_GEN(dev_priv) >= 9) {
> > >  		uint32_t val;
> > >  		int ret, i;
> > >  		int level, max_level = ilk_wm_max_level(dev_priv);
> > > @@ -2351,7 +2351,7 @@ static void intel_read_wm_latency(struct
> > > drm_i915_private *dev_priv,
> > >  		}
> > >  
> > >  		/*
> > > -		 * WaWmMemoryReadLatency:skl,glk
> > > +		 * WaWmMemoryReadLatency:skl+,glk
> > 
> > When we did we start to use the '+' notation in the w/a notes?
> 
> The + is because this code, when written, was going to be run for every
> gen >= 9. Stuff changed, rebases happened, so I guess I'll need to re-
> check to see that's still the case.
> 
> > 
> > What would it mean to say 'skl+,glk'? Is BXT included or not?
> 
> When I originally wrote this patch, I changed from "skl" to "skl+",
> there was no glk, and it was added by not-me during some rebase at some
> point.

Well, up to now we've never used + in these. So maybe just list ever
platform explicitly. Makes it clear where it really applies. The + stuff
gets hard when the w/a is no longer needed by some more recent platform.

> 
> > 
> > > 
> > >  		 *
> > >  		 * punit doesn't take into account the read
> > > latency so we need
> > >  		 * to add 2us to the various latency levels we
> > > retrieve from the
> > > @@ -2390,6 +2390,8 @@ static void intel_read_wm_latency(struct
> > > drm_i915_private *dev_priv,
> > >  		wm[0] = 7;
> > >  		wm[1] = (mltr >> MLTR_WM1_SHIFT) & ILK_SRLT_MASK;
> > >  		wm[2] = (mltr >> MLTR_WM2_SHIFT) & ILK_SRLT_MASK;
> > > +	} else {
> > > +		MISSING_CASE(INTEL_DEVID(dev_priv));
> > >  	}
> > >  }
> > >  
> > > -- 
> > > 1.9.1
> > > 
> > > _______________________________________________
> > > Intel-gfx mailing list
> > > Intel-gfx@lists.freedesktop.org
> > > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
> > 

-- 
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[PATCH 51/67] drm/i915/cnl: Enable SAGV for Cannonlake.

[Rodrigo Vivi]

For now inherit from previous platforms.

Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
---
 drivers/gpu/drm/i915/intel_pm.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index a2b2509..20a0701 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -3084,7 +3084,7 @@ static bool skl_needs_memory_bw_wa(struct intel_atomic_state *state)
 static bool
 intel_has_sagv(struct drm_i915_private *dev_priv)
 {
-	if (IS_KABYLAKE(dev_priv))
+	if (IS_KABYLAKE(dev_priv) || IS_CANNONLAKE(dev_priv))
 		return true;
 
 	if (IS_SKYLAKE(dev_priv) &&
-- 
1.9.1

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[PATCH 52/67] drm/i915/gen10: fix the gen 10 SAGV block time

[Rodrigo Vivi]

From: Paulo Zanoni <paulo.r.zanoni@intel.com>

A previous commit added CNL to intel_has_sagv(), but forgot to adjust
the SAGV block time to gen 10 platforms.

Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
---
 drivers/gpu/drm/i915/intel_pm.c | 13 ++++++-------
 1 file changed, 6 insertions(+), 7 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 20a0701..7ce56f1 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -3065,8 +3065,6 @@ bool ilk_disable_lp_wm(struct drm_device *dev)
 	return _ilk_disable_lp_wm(dev_priv, WM_DIRTY_LP_ALL);
 }
 
-#define SKL_SAGV_BLOCK_TIME	30 /* µs */
-
 /*
  * FIXME: We still don't have the proper code detect if we need to apply the WA,
  * so assume we'll always need it in order to avoid underruns.
@@ -3190,12 +3188,13 @@ bool intel_can_enable_sagv(struct drm_atomic_state *state)
 	struct intel_crtc_state *cstate;
 	enum pipe pipe;
 	int level, latency;
+	int sagv_block_time_us = IS_GEN9(dev_priv) ? 30 : 20;
 
 	if (!intel_has_sagv(dev_priv))
 		return false;
 
 	/*
-	 * SKL workaround: bspec recommends we disable the SAGV when we have
+	 * SKL+ workaround: bspec recommends we disable the SAGV when we have
 	 * more then one pipe enabled
 	 *
 	 * If there are no active CRTCs, no additional checks need be performed
@@ -3234,11 +3233,11 @@ bool intel_can_enable_sagv(struct drm_atomic_state *state)
 			latency += 15;
 
 		/*
-		 * If any of the planes on this pipe don't enable wm levels
-		 * that incur memory latencies higher then 30µs we can't enable
-		 * the SAGV
+		 * If any of the planes on this pipe don't enable wm levels that
+		 * incur memory latencies higher than sagv_block_time_us we
+		 * can't enable the SAGV.
 		 */
-		if (latency < SKL_SAGV_BLOCK_TIME)
+		if (latency < sagv_block_time_us)
 			return false;
 	}
 
-- 
1.9.1

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[PATCH 53/67] drm/i915/cnl: don't apply the GEN9/CNL:A WM WAs to CNL:B+

[Rodrigo Vivi]

From: Paulo Zanoni <paulo.r.zanoni@intel.com>

TODO: Right now we only have 2 of the 4 WAs implemented. There's one
missing for render decompression and another for transition
watermarks. When we upstream this patch, let's check if those missing
WAs are also implemented. We may also consider not even adding the A0
WA to the upstream tree.

Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
---
 drivers/gpu/drm/i915/intel_pm.c | 7 ++++++-
 1 file changed, 6 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 7ce56f1..83b80fa 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -3076,6 +3076,9 @@ static bool skl_needs_memory_bw_wa(struct intel_atomic_state *state)
 	if (IS_GEN9_BC(dev_priv) || IS_BROXTON(dev_priv))
 		return true;
 
+	if (IS_CNL_REVID(dev_priv, CNL_REVID_A0, CNL_REVID_A0))
+		return true;
+
 	return false;
 }
 
@@ -3871,7 +3874,9 @@ static int skl_compute_plane_wm(const struct drm_i915_private *dev_priv,
 	res_lines = DIV_ROUND_UP(selected_result.val,
 				 plane_blocks_per_line.val);
 
-	if (level >= 1 && level <= 7) {
+	if ((IS_GEN9(dev_priv) ||
+	     IS_CNL_REVID(dev_priv, CNL_REVID_A0, CNL_REVID_A0)) &&
+	    level >= 1 && level <= 7) {
 		if (y_tiled) {
 			res_blocks += fixed_16_16_to_u32_round_up(y_tile_minimum);
 			res_lines += y_min_scanlines;
-- 
1.9.1

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Re: [PATCH 53/67] drm/i915/cnl: don't apply the GEN9/CNL:A WM WAs to CNL:B+

[Mahesh Kumar]

Hi,


On Friday 07 April 2017 12:45 AM, Rodrigo Vivi wrote:
> From: Paulo Zanoni <paulo.r.zanoni@intel.com>
>
> TODO: Right now we only have 2 of the 4 WAs implemented. There's one
> missing for render decompression and another for transition
> watermarks. When we upstream this patch, let's check if those missing
> WAs are also implemented. We may also consider not even adding the A0
> WA to the upstream tree.
>
> Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
> ---
>   drivers/gpu/drm/i915/intel_pm.c | 7 ++++++-
>   1 file changed, 6 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index 7ce56f1..83b80fa 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -3076,6 +3076,9 @@ static bool skl_needs_memory_bw_wa(struct intel_atomic_state *state)
>   	if (IS_GEN9_BC(dev_priv) || IS_BROXTON(dev_priv))
>   		return true;
>   
> +	if (IS_CNL_REVID(dev_priv, CNL_REVID_A0, CNL_REVID_A0))
> +		return true;
> +
As per BSpec Memory Bandwidth related WA needed only for GEN9, WA#893

-Mahesh
>   	return false;
>   }
>   
> @@ -3871,7 +3874,9 @@ static int skl_compute_plane_wm(const struct drm_i915_private *dev_priv,
>   	res_lines = DIV_ROUND_UP(selected_result.val,
>   				 plane_blocks_per_line.val);
>   
> -	if (level >= 1 && level <= 7) {
> +	if ((IS_GEN9(dev_priv) ||
> +	     IS_CNL_REVID(dev_priv, CNL_REVID_A0, CNL_REVID_A0)) &&
> +	    level >= 1 && level <= 7) {
>   		if (y_tiled) {
>   			res_blocks += fixed_16_16_to_u32_round_up(y_tile_minimum);
>   			res_lines += y_min_scanlines;

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[PATCH 54/67] drm/i915/gen10: fix WM latency printing

[Rodrigo Vivi]

From: Paulo Zanoni <paulo.r.zanoni@intel.com>

Gen 10 is just like Gen 9, so let's consider that all the future
platforms are going to be like gen 9 instead of being like gen8-.

Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
---
 drivers/gpu/drm/i915/intel_pm.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 83b80fa..0194d55 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -2447,7 +2447,7 @@ static void intel_print_wm_latency(struct drm_i915_private *dev_priv,
 		 * - latencies are in us on gen9.
 		 * - before then, WM1+ latency values are in 0.5us units
 		 */
-		if (IS_GEN9(dev_priv))
+		if (INTEL_GEN(dev_priv) >= 9)
 			latency *= 10;
 		else if (level > 0)
 			latency *= 5;
-- 
1.9.1

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[PATCH 55/67] drm/i915/gen10: implement gen 10 watermarks calculations

[Rodrigo Vivi]

From: Paulo Zanoni <paulo.r.zanoni@intel.com>

They're slightly different than the gen 9 calculations.

TODO: before upstraming this, check if the spec is still the same.

Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
---
 drivers/gpu/drm/i915/intel_pm.c | 27 ++++++++++++++++++++-------
 1 file changed, 20 insertions(+), 7 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 0194d55..b07369a 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -3692,8 +3692,9 @@ void skl_ddb_get_hw_state(struct drm_i915_private *dev_priv,
  * should allow pixel_rate up to ~2 GHz which seems sufficient since max
  * 2xcdclk is 1350 MHz and the pixel rate should never exceed that.
 */
-static uint_fixed_16_16_t skl_wm_method1(uint32_t pixel_rate, uint8_t cpp,
-					 uint32_t latency)
+static uint_fixed_16_16_t
+skl_wm_method1(const struct drm_i915_private *dev_priv, uint32_t pixel_rate,
+	       uint8_t cpp, uint32_t latency)
 {
 	uint32_t wm_intermediate_val;
 	uint_fixed_16_16_t ret;
@@ -3703,6 +3704,10 @@ static uint_fixed_16_16_t skl_wm_method1(uint32_t pixel_rate, uint8_t cpp,
 
 	wm_intermediate_val = latency * pixel_rate * cpp;
 	ret = fixed_16_16_div_round_up_u64(wm_intermediate_val, 1000 * 512);
+
+	if (INTEL_GEN(dev_priv) >= 10)
+		ret.val += 1 << 16;
+
 	return ret;
 }
 
@@ -3836,11 +3841,15 @@ static int skl_compute_plane_wm(const struct drm_i915_private *dev_priv,
 
 	plane_bytes_per_line = width * cpp;
 	if (y_tiled) {
-		interm_pbpl = DIV_ROUND_UP(plane_bytes_per_line *
-					   y_min_scanlines, 512);
+		interm_pbpl = plane_bytes_per_line * y_min_scanlines;
+
+		if (INTEL_GEN(dev_priv) >= 10)
+			interm_pbpl++;
+
+		interm_pbpl = DIV_ROUND_UP(interm_pbpl, 512);
 		plane_blocks_per_line =
 		      fixed_16_16_div_round_up(interm_pbpl, y_min_scanlines);
-	} else if (x_tiled) {
+	} else if (x_tiled && INTEL_GEN(dev_priv) == 9) {
 		interm_pbpl = DIV_ROUND_UP(plane_bytes_per_line, 512);
 		plane_blocks_per_line = u32_to_fixed_16_16(interm_pbpl);
 	} else {
@@ -3848,7 +3857,7 @@ static int skl_compute_plane_wm(const struct drm_i915_private *dev_priv,
 		plane_blocks_per_line = u32_to_fixed_16_16(interm_pbpl);
 	}
 
-	method1 = skl_wm_method1(plane_pixel_rate, cpp, latency);
+	method1 = skl_wm_method1(dev_priv, plane_pixel_rate, cpp, latency);
 	method2 = skl_wm_method2(plane_pixel_rate,
 				 cstate->base.adjusted_mode.crtc_htotal,
 				 latency,
@@ -3865,7 +3874,11 @@ static int skl_compute_plane_wm(const struct drm_i915_private *dev_priv,
 			selected_result = method2;
 		else if ((ddb_allocation /
 			fixed_16_16_to_u32_round_up(plane_blocks_per_line)) >= 1)
-			selected_result = min_fixed_16_16(method1, method2);
+			if (INTEL_GEN(dev_priv) == 9)
+				selected_result = min_fixed_16_16(method1,
+								  method2);
+			else
+				selected_result = method2;
 		else
 			selected_result = method1;
 	}
-- 
1.9.1

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Re: [PATCH 55/67] drm/i915/gen10: implement gen 10 watermarks calculations

[Ander Conselvan De Oliveira]

On Thu, 2017-04-06 at 12:15 -0700, Rodrigo Vivi wrote:
> From: Paulo Zanoni <paulo.r.zanoni@intel.com>
> 
> They're slightly different than the gen 9 calculations.

I missed this at first, but GLK should follow the gen10 watermark programming as
it has a gen10 display.

> 
> TODO: before upstraming this, check if the spec is still the same.
> 
> Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
> ---
>  drivers/gpu/drm/i915/intel_pm.c | 27 ++++++++++++++++++++-------
>  1 file changed, 20 insertions(+), 7 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index 0194d55..b07369a 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -3692,8 +3692,9 @@ void skl_ddb_get_hw_state(struct drm_i915_private *dev_priv,
>   * should allow pixel_rate up to ~2 GHz which seems sufficient since max
>   * 2xcdclk is 1350 MHz and the pixel rate should never exceed that.
>  */
> -static uint_fixed_16_16_t skl_wm_method1(uint32_t pixel_rate, uint8_t cpp,
> -					 uint32_t latency)
> +static uint_fixed_16_16_t
> +skl_wm_method1(const struct drm_i915_private *dev_priv, uint32_t pixel_rate,
> +	       uint8_t cpp, uint32_t latency)
>  {
>  	uint32_t wm_intermediate_val;
>  	uint_fixed_16_16_t ret;
> @@ -3703,6 +3704,10 @@ static uint_fixed_16_16_t skl_wm_method1(uint32_t pixel_rate, uint8_t cpp,
>  
>  	wm_intermediate_val = latency * pixel_rate * cpp;
>  	ret = fixed_16_16_div_round_up_u64(wm_intermediate_val, 1000 * 512);
> +
> +	if (INTEL_GEN(dev_priv) >= 10)

|| IS_GLK

> +		ret.val += 1 << 16;
> +
>  	return ret;
>  }
>  
> @@ -3836,11 +3841,15 @@ static int skl_compute_plane_wm(const struct drm_i915_private *dev_priv,
>  
>  	plane_bytes_per_line = width * cpp;
>  	if (y_tiled) {
> -		interm_pbpl = DIV_ROUND_UP(plane_bytes_per_line *
> -					   y_min_scanlines, 512);
> +		interm_pbpl = plane_bytes_per_line * y_min_scanlines;
> +
> +		if (INTEL_GEN(dev_priv) >= 10)
> +			interm_pbpl++;
> +
> +		interm_pbpl = DIV_ROUND_UP(interm_pbpl, 512);

If I'm reading the spec right, the +1 should be done after the division by 512.

>  		plane_blocks_per_line =
>  		      fixed_16_16_div_round_up(interm_pbpl, y_min_scanlines);
> -	} else if (x_tiled) {
> +	} else if (x_tiled && INTEL_GEN(dev_priv) == 9) {

&& !IS_GLK

>  		interm_pbpl = DIV_ROUND_UP(plane_bytes_per_line, 512);
>  		plane_blocks_per_line = u32_to_fixed_16_16(interm_pbpl);
>  	} else {
> @@ -3848,7 +3857,7 @@ static int skl_compute_plane_wm(const struct drm_i915_private *dev_priv,
>  		plane_blocks_per_line = u32_to_fixed_16_16(interm_pbpl);
>  	}
>  
> -	method1 = skl_wm_method1(plane_pixel_rate, cpp, latency);
> +	method1 = skl_wm_method1(dev_priv, plane_pixel_rate, cpp, latency);
>  	method2 = skl_wm_method2(plane_pixel_rate,
>  				 cstate->base.adjusted_mode.crtc_htotal,
>  				 latency,
> @@ -3865,7 +3874,11 @@ static int skl_compute_plane_wm(const struct drm_i915_private *dev_priv,
>  			selected_result = method2;
>  		else if ((ddb_allocation /
>  			fixed_16_16_to_u32_round_up(plane_blocks_per_line)) >= 1)
> -			selected_result = min_fixed_16_16(method1, method2);
> +			if (INTEL_GEN(dev_priv) == 9)

&& !IS_GLK
> +				selected_result = min_fixed_16_16(method1,
> +								  method2);
> +			else
> +				selected_result = method2;
>  		else
>  			selected_result = method1;
>  	}
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[PATCH 56/67] drm/i915/cnl: Reuse skl_wm_get_hw_state on Cannonlake.

[Rodrigo Vivi]

Otherwise it reuses the ilk that has a completely different
wm.

Cc: Paulo Zanoni <paulo.r.zanoni@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
---
 drivers/gpu/drm/i915/intel_display.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 4d0ae98..3adee22 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -15549,7 +15549,7 @@ static void intel_modeset_readout_hw_state(struct drm_device *dev)
 	if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
 		vlv_wm_get_hw_state(dev);
 		vlv_wm_sanitize(dev_priv);
-	} else if (IS_GEN9(dev_priv)) {
+	} else if (INTEL_GEN(dev_priv) >= 9) {
 		skl_wm_get_hw_state(dev);
 	} else if (HAS_PCH_SPLIT(dev_priv)) {
 		ilk_wm_get_hw_state(dev);
-- 
1.9.1

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[PATCH 57/67] x86/gpu: CNL uses the same GMS values as SKL

[Rodrigo Vivi]

From: Paulo Zanoni <paulo.r.zanoni@intel.com>

So don't forget to reserve its stolen memory bits.

TODO: Cc the appropriate maintainers outside Intel before submitting
the patch to the public mailing lists.

Acked-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
---
 arch/x86/kernel/early-quirks.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/x86/kernel/early-quirks.c b/arch/x86/kernel/early-quirks.c
index 23c4f1c..afba51a 100644
--- a/arch/x86/kernel/early-quirks.c
+++ b/arch/x86/kernel/early-quirks.c
@@ -527,6 +527,7 @@ struct intel_early_ops {
 	INTEL_BXT_IDS(&gen9_early_ops),
 	INTEL_KBL_IDS(&gen9_early_ops),
 	INTEL_GLK_IDS(&gen9_early_ops),
+	INTEL_CNL_IDS(&gen9_early_ops),
 };
 
 static void __init
-- 
1.9.1

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[PATCH] x86/gpu: CNL uses the same GMS values as SKL

[Rodrigo Vivi]

From: Paulo Zanoni <paulo.r.zanoni@intel.com>

So don't forget to reserve its stolen memory bits.

v2: Adding right Cc.

Cc: Ingo Molnar <mingo@kernel.org>
Cc: H. Peter Anvin <hpa@zytor.com>
Cc: Ander Conselvan de Oliveira <ander.conselvan.de.oliveira@intel.com>
Cc: x86@kernel.org
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
---
 arch/x86/kernel/early-quirks.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/x86/kernel/early-quirks.c b/arch/x86/kernel/early-quirks.c
index 23c4f1c..afba51a 100644
--- a/arch/x86/kernel/early-quirks.c
+++ b/arch/x86/kernel/early-quirks.c
@@ -527,6 +527,7 @@ struct intel_early_ops {
 	INTEL_BXT_IDS(&gen9_early_ops),
 	INTEL_KBL_IDS(&gen9_early_ops),
 	INTEL_GLK_IDS(&gen9_early_ops),
+	INTEL_CNL_IDS(&gen9_early_ops),
 };
 
 static void __init
-- 
1.9.1

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Re: [PATCH] x86/gpu: CNL uses the same GMS values as SKL

[kbuild test robot]

[-- Attachment #1: Type: text/plain, Size: 1889 bytes --]

Hi Paulo,

[auto build test ERROR on next-20170405]
[cannot apply to tip/x86/core v4.9-rc8 v4.9-rc7 v4.9-rc6 v4.11-rc5]
[if your patch is applied to the wrong git tree, please drop us a note to help improve the system]

url:    https://github.com/0day-ci/linux/commits/Rodrigo-Vivi/x86-gpu-CNL-uses-the-same-GMS-values-as-SKL/20170408-024552
config: i386-randconfig-x071-04050905 (attached as .config)
compiler: gcc-6 (Debian 6.2.0-3) 6.2.0 20160901
reproduce:
        # save the attached .config to linux build tree
        make ARCH=i386 

All errors (new ones prefixed by >>):

>> arch/x86/kernel/early-quirks.c:530:2: error: implicit declaration of function 'INTEL_CNL_IDS' [-Werror=implicit-function-declaration]
     INTEL_CNL_IDS(&gen9_early_ops),
     ^~~~~~~~~~~~~
   arch/x86/kernel/early-quirks.c:530:2: error: initializer element is not constant
   arch/x86/kernel/early-quirks.c:530:2: note: (near initialization for 'intel_early_ids[187].vendor')
   arch/x86/kernel/early-quirks.c:501:67: warning: missing braces around initializer [-Wmissing-braces]
    static const struct pci_device_id intel_early_ids[] __initconst = {
                                                                      ^
   arch/x86/kernel/early-quirks.c:501:67: note: (near initialization for 'intel_early_ids')
   cc1: some warnings being treated as errors

vim +/INTEL_CNL_IDS +530 arch/x86/kernel/early-quirks.c

   524		INTEL_BDW_IDS(&gen8_early_ops),
   525		INTEL_CHV_IDS(&chv_early_ops),
   526		INTEL_SKL_IDS(&gen9_early_ops),
   527		INTEL_BXT_IDS(&gen9_early_ops),
   528		INTEL_KBL_IDS(&gen9_early_ops),
   529		INTEL_GLK_IDS(&gen9_early_ops),
 > 530		INTEL_CNL_IDS(&gen9_early_ops),
   531	};
   532	
   533	static void __init

---
0-DAY kernel test infrastructure                Open Source Technology Center
https://lists.01.org/pipermail/kbuild-all                   Intel Corporation

[-- Attachment #2: .config.gz --]
[-- Type: application/gzip, Size: 27409 bytes --]

[-- Attachment #3: Type: text/plain, Size: 160 bytes --]

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Re: [PATCH] x86/gpu: CNL uses the same GMS values as SKL

[Paulo Zanoni]

Em Sáb, 2017-04-08 às 03:21 +0800, kbuild test robot escreveu:
> Hi Paulo,
> 
> [auto build test ERROR on next-20170405]
> [cannot apply to tip/x86/core v4.9-rc8 v4.9-rc7 v4.9-rc6 v4.11-rc5]
> [if your patch is applied to the wrong git tree, please drop us a
> note to help improve the system]

This patch is part of the CNL enabling series of 67 patches that was
just posted to intel-gfx. It won't apply unless you also apply the 57
patches that came first, and the base tree for the series is drm-intel-
nightly, not x86/core.

The ideal plan would be to have an ack from the x86 maintainers and
then apply this to the i915.ko tree. I suppose this is what was done
with the previous patches that touched this function.

> 
> url:    https://github.com/0day-ci/linux/commits/Rodrigo-Vivi/x86-gpu
> -CNL-uses-the-same-GMS-values-as-SKL/20170408-024552
> config: i386-randconfig-x071-04050905 (attached as .config)
> compiler: gcc-6 (Debian 6.2.0-3) 6.2.0 20160901
> reproduce:
>         # save the attached .config to linux build tree
>         make ARCH=i386 
> 
> All errors (new ones prefixed by >>):
> 
> > 
> > > 
> > > arch/x86/kernel/early-quirks.c:530:2: error: implicit declaration
> > > of function 'INTEL_CNL_IDS' [-Werror=implicit-function-
> > > declaration]
>      INTEL_CNL_IDS(&gen9_early_ops),
>      ^~~~~~~~~~~~~
>    arch/x86/kernel/early-quirks.c:530:2: error: initializer element
> is not constant
>    arch/x86/kernel/early-quirks.c:530:2: note: (near initialization
> for 'intel_early_ids[187].vendor')
>    arch/x86/kernel/early-quirks.c:501:67: warning: missing braces
> around initializer [-Wmissing-braces]
>     static const struct pci_device_id intel_early_ids[] __initconst =
> {
>                                                                      
>  ^
>    arch/x86/kernel/early-quirks.c:501:67: note: (near initialization
> for 'intel_early_ids')
>    cc1: some warnings being treated as errors
> 
> vim +/INTEL_CNL_IDS +530 arch/x86/kernel/early-quirks.c
> 
>    524		INTEL_BDW_IDS(&gen8_early_ops),
>    525		INTEL_CHV_IDS(&chv_early_ops),
>    526		INTEL_SKL_IDS(&gen9_early_ops),
>    527		INTEL_BXT_IDS(&gen9_early_ops),
>    528		INTEL_KBL_IDS(&gen9_early_ops),
>    529		INTEL_GLK_IDS(&gen9_early_ops),
>  > 530		INTEL_CNL_IDS(&gen9_early_ops),
>    531	};
>    532	
>    533	static void __init
> 
> ---
> 0-DAY kernel test infrastructure                Open Source
> Technology Center
> https://lists.01.org/pipermail/kbuild-all                   Intel
> Corporation
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Re: [kbuild-all] [PATCH] x86/gpu: CNL uses the same GMS values as SKL

[Ye Xiaolong]

On 04/07, Paulo Zanoni wrote:
>Em Sáb, 2017-04-08 às 03:21 +0800, kbuild test robot escreveu:
>> Hi Paulo,
>> 
>> [auto build test ERROR on next-20170405]
>> [cannot apply to tip/x86/core v4.9-rc8 v4.9-rc7 v4.9-rc6 v4.11-rc5]
>> [if your patch is applied to the wrong git tree, please drop us a
>> note to help improve the system]
>
>This patch is part of the CNL enabling series of 67 patches that was
>just posted to intel-gfx. It won't apply unless you also apply the 57

Thanks for the info, now we realized that it's just 1 patch out of the big
patchset, in-reply-to the patch it replaces. We are developing features to 
auto-detect such kind of patch and avoid apply it individually.

>patches that came first, and the base tree for the series is drm-intel-
>nightly, not x86/core.

Got it, we'll improve it.

Thanks,
Xiaolong
>
>The ideal plan would be to have an ack from the x86 maintainers and
>then apply this to the i915.ko tree. I suppose this is what was done
>with the previous patches that touched this function.
>
>> 
>> url:    https://github.com/0day-ci/linux/commits/Rodrigo-Vivi/x86-gpu
>> -CNL-uses-the-same-GMS-values-as-SKL/20170408-024552
>> config: i386-randconfig-x071-04050905 (attached as .config)
>> compiler: gcc-6 (Debian 6.2.0-3) 6.2.0 20160901
>> reproduce:
>>         # save the attached .config to linux build tree
>>         make ARCH=i386 
>> 
>> All errors (new ones prefixed by >>):
>> 
>> > 
>> > > 
>> > > arch/x86/kernel/early-quirks.c:530:2: error: implicit declaration
>> > > of function 'INTEL_CNL_IDS' [-Werror=implicit-function-
>> > > declaration]
>>      INTEL_CNL_IDS(&gen9_early_ops),
>>      ^~~~~~~~~~~~~
>>    arch/x86/kernel/early-quirks.c:530:2: error: initializer element
>> is not constant
>>    arch/x86/kernel/early-quirks.c:530:2: note: (near initialization
>> for 'intel_early_ids[187].vendor')
>>    arch/x86/kernel/early-quirks.c:501:67: warning: missing braces
>> around initializer [-Wmissing-braces]
>>     static const struct pci_device_id intel_early_ids[] __initconst =
>> {
>>                                                                      
>>  ^
>>    arch/x86/kernel/early-quirks.c:501:67: note: (near initialization
>> for 'intel_early_ids')
>>    cc1: some warnings being treated as errors
>> 
>> vim +/INTEL_CNL_IDS +530 arch/x86/kernel/early-quirks.c
>> 
>>    524		INTEL_BDW_IDS(&gen8_early_ops),
>>    525		INTEL_CHV_IDS(&chv_early_ops),
>>    526		INTEL_SKL_IDS(&gen9_early_ops),
>>    527		INTEL_BXT_IDS(&gen9_early_ops),
>>    528		INTEL_KBL_IDS(&gen9_early_ops),
>>    529		INTEL_GLK_IDS(&gen9_early_ops),
>>  > 530		INTEL_CNL_IDS(&gen9_early_ops),
>>    531	};
>>    532	
>>    533	static void __init
>> 
>> ---
>> 0-DAY kernel test infrastructure                Open Source
>> Technology Center
>> https://lists.01.org/pipermail/kbuild-all                   Intel
>> Corporation
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Re: [PATCH] x86/gpu: CNL uses the same GMS values as SKL

[Thomas Gleixner]

On Thu, 6 Apr 2017, Rodrigo Vivi wrote:

> From: Paulo Zanoni <paulo.r.zanoni@intel.com>
> 
> So don't forget to reserve its stolen memory bits.
> 
> v2: Adding right Cc.
> 
> Cc: Ingo Molnar <mingo@kernel.org>
> Cc: H. Peter Anvin <hpa@zytor.com>
> Cc: Ander Conselvan de Oliveira <ander.conselvan.de.oliveira@intel.com>
> Cc: x86@kernel.org
> Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>

Acked-by: Thomas Gleixner <tglx@linutronix.de>
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[PATCH 58/67] drm/i915/cnl: Cannonlake color init.

[Rodrigo Vivi]

Cannonlake has same color setup as Geminilake.
Legacy color load luts doesn't work anymore on Cannonlake+.

Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
---
 drivers/gpu/drm/i915/i915_pci.c      | 1 +
 drivers/gpu/drm/i915/intel_color.c   | 2 +-
 drivers/gpu/drm/i915/intel_display.c | 4 ++--
 drivers/gpu/drm/i915/intel_sprite.c  | 2 +-
 4 files changed, 5 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index bace848..1e8e0ac 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -438,6 +438,7 @@
 	.gen = 10,
 	.ddb_size = 1024,
 	.has_csr = 1,
+	.color = { .degamma_lut_size = 0, .gamma_lut_size = 1024 }
 };
 
 /*
diff --git a/drivers/gpu/drm/i915/intel_color.c b/drivers/gpu/drm/i915/intel_color.c
index 306c6b0..f85d575 100644
--- a/drivers/gpu/drm/i915/intel_color.c
+++ b/drivers/gpu/drm/i915/intel_color.c
@@ -615,7 +615,7 @@ void intel_color_init(struct drm_crtc *crtc)
 		   IS_BROXTON(dev_priv)) {
 		dev_priv->display.load_csc_matrix = i9xx_load_csc_matrix;
 		dev_priv->display.load_luts = broadwell_load_luts;
-	} else if (IS_GEMINILAKE(dev_priv)) {
+	} else if (IS_GEMINILAKE(dev_priv) || IS_CANNONLAKE(dev_priv)) {
 		dev_priv->display.load_csc_matrix = i9xx_load_csc_matrix;
 		dev_priv->display.load_luts = glk_load_luts;
 	} else {
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 3adee22..697c112 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -3302,7 +3302,7 @@ u32 skl_plane_ctl(const struct intel_crtc_state *crtc_state,
 
 	plane_ctl = PLANE_CTL_ENABLE;
 
-	if (!IS_GEMINILAKE(dev_priv)) {
+	if (!IS_GEMINILAKE(dev_priv) && !IS_CANNONLAKE(dev_priv)) {
 		plane_ctl |=
 			PLANE_CTL_PIPE_GAMMA_ENABLE |
 			PLANE_CTL_PIPE_CSC_ENABLE |
@@ -3359,7 +3359,7 @@ static void skylake_update_primary_plane(struct drm_plane *plane,
 
 	spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
 
-	if (IS_GEMINILAKE(dev_priv)) {
+	if (IS_GEMINILAKE(dev_priv) || IS_CANNONLAKE(dev_priv)) {
 		I915_WRITE_FW(PLANE_COLOR_CTL(pipe, plane_id),
 			      PLANE_COLOR_PIPE_GAMMA_ENABLE |
 			      PLANE_COLOR_PIPE_CSC_ENABLE |
diff --git a/drivers/gpu/drm/i915/intel_sprite.c b/drivers/gpu/drm/i915/intel_sprite.c
index f7d4314..a002c1a 100644
--- a/drivers/gpu/drm/i915/intel_sprite.c
+++ b/drivers/gpu/drm/i915/intel_sprite.c
@@ -240,7 +240,7 @@ void intel_pipe_update_end(struct intel_crtc *crtc, struct intel_flip_work *work
 
 	spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
 
-	if (IS_GEMINILAKE(dev_priv)) {
+	if (IS_GEMINILAKE(dev_priv) || IS_CANNONLAKE(dev_priv)) {
 		I915_WRITE_FW(PLANE_COLOR_CTL(pipe, plane_id),
 			      PLANE_COLOR_PIPE_GAMMA_ENABLE |
 			      PLANE_COLOR_PIPE_CSC_ENABLE |
-- 
1.9.1

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Re: [PATCH 58/67] drm/i915/cnl: Cannonlake color init.

[Ville Syrjälä]

On Thu, Apr 06, 2017 at 12:15:54PM -0700, Rodrigo Vivi wrote:
> Cannonlake has same color setup as Geminilake.
> Legacy color load luts doesn't work anymore on Cannonlake+.

Not sure what that means. The legacy 8bpc LUT i no longer there?
The code still depends on that working, and we also still expose the C8
format which at least used to depend on the legacy LUT.

> 
> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
> ---
>  drivers/gpu/drm/i915/i915_pci.c      | 1 +
>  drivers/gpu/drm/i915/intel_color.c   | 2 +-
>  drivers/gpu/drm/i915/intel_display.c | 4 ++--
>  drivers/gpu/drm/i915/intel_sprite.c  | 2 +-
>  4 files changed, 5 insertions(+), 4 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
> index bace848..1e8e0ac 100644
> --- a/drivers/gpu/drm/i915/i915_pci.c
> +++ b/drivers/gpu/drm/i915/i915_pci.c
> @@ -438,6 +438,7 @@
>  	.gen = 10,
>  	.ddb_size = 1024,
>  	.has_csr = 1,
> +	.color = { .degamma_lut_size = 0, .gamma_lut_size = 1024 }
>  };
>  
>  /*
> diff --git a/drivers/gpu/drm/i915/intel_color.c b/drivers/gpu/drm/i915/intel_color.c
> index 306c6b0..f85d575 100644
> --- a/drivers/gpu/drm/i915/intel_color.c
> +++ b/drivers/gpu/drm/i915/intel_color.c
> @@ -615,7 +615,7 @@ void intel_color_init(struct drm_crtc *crtc)
>  		   IS_BROXTON(dev_priv)) {
>  		dev_priv->display.load_csc_matrix = i9xx_load_csc_matrix;
>  		dev_priv->display.load_luts = broadwell_load_luts;
> -	} else if (IS_GEMINILAKE(dev_priv)) {
> +	} else if (IS_GEMINILAKE(dev_priv) || IS_CANNONLAKE(dev_priv)) {
>  		dev_priv->display.load_csc_matrix = i9xx_load_csc_matrix;
>  		dev_priv->display.load_luts = glk_load_luts;
>  	} else {
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index 3adee22..697c112 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -3302,7 +3302,7 @@ u32 skl_plane_ctl(const struct intel_crtc_state *crtc_state,
>  
>  	plane_ctl = PLANE_CTL_ENABLE;
>  
> -	if (!IS_GEMINILAKE(dev_priv)) {
> +	if (!IS_GEMINILAKE(dev_priv) && !IS_CANNONLAKE(dev_priv)) {
>  		plane_ctl |=
>  			PLANE_CTL_PIPE_GAMMA_ENABLE |
>  			PLANE_CTL_PIPE_CSC_ENABLE |
> @@ -3359,7 +3359,7 @@ static void skylake_update_primary_plane(struct drm_plane *plane,
>  
>  	spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
>  
> -	if (IS_GEMINILAKE(dev_priv)) {
> +	if (IS_GEMINILAKE(dev_priv) || IS_CANNONLAKE(dev_priv)) {
>  		I915_WRITE_FW(PLANE_COLOR_CTL(pipe, plane_id),
>  			      PLANE_COLOR_PIPE_GAMMA_ENABLE |
>  			      PLANE_COLOR_PIPE_CSC_ENABLE |
> diff --git a/drivers/gpu/drm/i915/intel_sprite.c b/drivers/gpu/drm/i915/intel_sprite.c
> index f7d4314..a002c1a 100644
> --- a/drivers/gpu/drm/i915/intel_sprite.c
> +++ b/drivers/gpu/drm/i915/intel_sprite.c
> @@ -240,7 +240,7 @@ void intel_pipe_update_end(struct intel_crtc *crtc, struct intel_flip_work *work
>  
>  	spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
>  
> -	if (IS_GEMINILAKE(dev_priv)) {
> +	if (IS_GEMINILAKE(dev_priv) || IS_CANNONLAKE(dev_priv)) {
>  		I915_WRITE_FW(PLANE_COLOR_CTL(pipe, plane_id),
>  			      PLANE_COLOR_PIPE_GAMMA_ENABLE |
>  			      PLANE_COLOR_PIPE_CSC_ENABLE |
> -- 
> 1.9.1
> 
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
Ville Syrjälä
Intel OTC
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Re: [PATCH 58/67] drm/i915/cnl: Cannonlake color init.

[Vivi, Rodrigo]

> On Apr 24, 2017, at 10:57 AM, Ville Syrjälä <ville.syrjala@linux.intel.com> wrote:
> 
>> On Thu, Apr 06, 2017 at 12:15:54PM -0700, Rodrigo Vivi wrote:
>> Cannonlake has same color setup as Geminilake.
>> Legacy color load luts doesn't work anymore on Cannonlake+.
> 
> Not sure what that means. The legacy 8bpc LUT i no longer there?
> The code still depends on that working, and we also still expose the C8
> format which at least used to depend on the legacy LUT.

Not sure... what I tried to say is that by using old sequences available for luts we just get black screen... while in previous platforms I remember that old setup sequences working while we didn't have the new ones...

> 
>> 
>> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
>> ---
>> drivers/gpu/drm/i915/i915_pci.c      | 1 +
>> drivers/gpu/drm/i915/intel_color.c   | 2 +-
>> drivers/gpu/drm/i915/intel_display.c | 4 ++--
>> drivers/gpu/drm/i915/intel_sprite.c  | 2 +-
>> 4 files changed, 5 insertions(+), 4 deletions(-)
>> 
>> diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
>> index bace848..1e8e0ac 100644
>> --- a/drivers/gpu/drm/i915/i915_pci.c
>> +++ b/drivers/gpu/drm/i915/i915_pci.c
>> @@ -438,6 +438,7 @@
>>    .gen = 10,
>>    .ddb_size = 1024,
>>    .has_csr = 1,
>> +    .color = { .degamma_lut_size = 0, .gamma_lut_size = 1024 }
>> };
>> 
>> /*
>> diff --git a/drivers/gpu/drm/i915/intel_color.c b/drivers/gpu/drm/i915/intel_color.c
>> index 306c6b0..f85d575 100644
>> --- a/drivers/gpu/drm/i915/intel_color.c
>> +++ b/drivers/gpu/drm/i915/intel_color.c
>> @@ -615,7 +615,7 @@ void intel_color_init(struct drm_crtc *crtc)
>>           IS_BROXTON(dev_priv)) {
>>        dev_priv->display.load_csc_matrix = i9xx_load_csc_matrix;
>>        dev_priv->display.load_luts = broadwell_load_luts;
>> -    } else if (IS_GEMINILAKE(dev_priv)) {
>> +    } else if (IS_GEMINILAKE(dev_priv) || IS_CANNONLAKE(dev_priv)) {
>>        dev_priv->display.load_csc_matrix = i9xx_load_csc_matrix;
>>        dev_priv->display.load_luts = glk_load_luts;
>>    } else {
>> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
>> index 3adee22..697c112 100644
>> --- a/drivers/gpu/drm/i915/intel_display.c
>> +++ b/drivers/gpu/drm/i915/intel_display.c
>> @@ -3302,7 +3302,7 @@ u32 skl_plane_ctl(const struct intel_crtc_state *crtc_state,
>> 
>>    plane_ctl = PLANE_CTL_ENABLE;
>> 
>> -    if (!IS_GEMINILAKE(dev_priv)) {
>> +    if (!IS_GEMINILAKE(dev_priv) && !IS_CANNONLAKE(dev_priv)) {
>>        plane_ctl |=
>>            PLANE_CTL_PIPE_GAMMA_ENABLE |
>>            PLANE_CTL_PIPE_CSC_ENABLE |
>> @@ -3359,7 +3359,7 @@ static void skylake_update_primary_plane(struct drm_plane *plane,
>> 
>>    spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
>> 
>> -    if (IS_GEMINILAKE(dev_priv)) {
>> +    if (IS_GEMINILAKE(dev_priv) || IS_CANNONLAKE(dev_priv)) {
>>        I915_WRITE_FW(PLANE_COLOR_CTL(pipe, plane_id),
>>                  PLANE_COLOR_PIPE_GAMMA_ENABLE |
>>                  PLANE_COLOR_PIPE_CSC_ENABLE |
>> diff --git a/drivers/gpu/drm/i915/intel_sprite.c b/drivers/gpu/drm/i915/intel_sprite.c
>> index f7d4314..a002c1a 100644
>> --- a/drivers/gpu/drm/i915/intel_sprite.c
>> +++ b/drivers/gpu/drm/i915/intel_sprite.c
>> @@ -240,7 +240,7 @@ void intel_pipe_update_end(struct intel_crtc *crtc, struct intel_flip_work *work
>> 
>>    spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
>> 
>> -    if (IS_GEMINILAKE(dev_priv)) {
>> +    if (IS_GEMINILAKE(dev_priv) || IS_CANNONLAKE(dev_priv)) {
>>        I915_WRITE_FW(PLANE_COLOR_CTL(pipe, plane_id),
>>                  PLANE_COLOR_PIPE_GAMMA_ENABLE |
>>                  PLANE_COLOR_PIPE_CSC_ENABLE |
>> -- 
>> 1.9.1
>> 
>> _______________________________________________
>> Intel-gfx mailing list
>> Intel-gfx@lists.freedesktop.org
>> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
> 
> -- 
> Ville Syrjälä
> Intel OTC
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Re: [PATCH 58/67] drm/i915/cnl: Cannonlake color init.

[Ander Conselvan De Oliveira]

On Tue, 2017-04-25 at 05:29 +0000, Vivi, Rodrigo wrote:
> > On Apr 24, 2017, at 10:57 AM, Ville Syrjälä <ville.syrjala@linux.intel.com> wrote:
> > 
> > > On Thu, Apr 06, 2017 at 12:15:54PM -0700, Rodrigo Vivi wrote:
> > > Cannonlake has same color setup as Geminilake.
> > > Legacy color load luts doesn't work anymore on Cannonlake+.
> > 
> > Not sure what that means. The legacy 8bpc LUT i no longer there?

As far as I can tell the legacy 8bpc LUT is still there in CNL, but I might be
reading the spec wrong. 

> > The code still depends on that working, and we also still expose the C8
> > format which at least used to depend on the legacy LUT.
> 
> Not sure... what I tried to say is that by using old sequences available for luts we just get black screen... while in previous platforms I remember that old setup sequences working while we didn't have the new ones...

That's probably the pre-CSC gamma table. It doesn't have its own enable bit and
instead it is enabled whenever CSC is (which we always do). But since the
default value for that table is all zeroes, enabling CSC without setting it up
causes black screens.

Ander

> 
> > 
> > > 
> > > Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
> > > ---
> > > drivers/gpu/drm/i915/i915_pci.c      | 1 +
> > > drivers/gpu/drm/i915/intel_color.c   | 2 +-
> > > drivers/gpu/drm/i915/intel_display.c | 4 ++--
> > > drivers/gpu/drm/i915/intel_sprite.c  | 2 +-
> > > 4 files changed, 5 insertions(+), 4 deletions(-)
> > > 
> > > diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
> > > index bace848..1e8e0ac 100644
> > > --- a/drivers/gpu/drm/i915/i915_pci.c
> > > +++ b/drivers/gpu/drm/i915/i915_pci.c
> > > @@ -438,6 +438,7 @@
> > >    .gen = 10,
> > >    .ddb_size = 1024,
> > >    .has_csr = 1,
> > > +    .color = { .degamma_lut_size = 0, .gamma_lut_size = 1024 }
> > > };
> > > 
> > > /*
> > > diff --git a/drivers/gpu/drm/i915/intel_color.c b/drivers/gpu/drm/i915/intel_color.c
> > > index 306c6b0..f85d575 100644
> > > --- a/drivers/gpu/drm/i915/intel_color.c
> > > +++ b/drivers/gpu/drm/i915/intel_color.c
> > > @@ -615,7 +615,7 @@ void intel_color_init(struct drm_crtc *crtc)
> > >           IS_BROXTON(dev_priv)) {
> > >        dev_priv->display.load_csc_matrix = i9xx_load_csc_matrix;
> > >        dev_priv->display.load_luts = broadwell_load_luts;
> > > -    } else if (IS_GEMINILAKE(dev_priv)) {
> > > +    } else if (IS_GEMINILAKE(dev_priv) || IS_CANNONLAKE(dev_priv)) {
> > >        dev_priv->display.load_csc_matrix = i9xx_load_csc_matrix;
> > >        dev_priv->display.load_luts = glk_load_luts;
> > >    } else {
> > > diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> > > index 3adee22..697c112 100644
> > > --- a/drivers/gpu/drm/i915/intel_display.c
> > > +++ b/drivers/gpu/drm/i915/intel_display.c
> > > @@ -3302,7 +3302,7 @@ u32 skl_plane_ctl(const struct intel_crtc_state *crtc_state,
> > > 
> > >    plane_ctl = PLANE_CTL_ENABLE;
> > > 
> > > -    if (!IS_GEMINILAKE(dev_priv)) {
> > > +    if (!IS_GEMINILAKE(dev_priv) && !IS_CANNONLAKE(dev_priv)) {
> > >        plane_ctl |=
> > >            PLANE_CTL_PIPE_GAMMA_ENABLE |
> > >            PLANE_CTL_PIPE_CSC_ENABLE |
> > > @@ -3359,7 +3359,7 @@ static void skylake_update_primary_plane(struct drm_plane *plane,
> > > 
> > >    spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
> > > 
> > > -    if (IS_GEMINILAKE(dev_priv)) {
> > > +    if (IS_GEMINILAKE(dev_priv) || IS_CANNONLAKE(dev_priv)) {
> > >        I915_WRITE_FW(PLANE_COLOR_CTL(pipe, plane_id),
> > >                  PLANE_COLOR_PIPE_GAMMA_ENABLE |
> > >                  PLANE_COLOR_PIPE_CSC_ENABLE |
> > > diff --git a/drivers/gpu/drm/i915/intel_sprite.c b/drivers/gpu/drm/i915/intel_sprite.c
> > > index f7d4314..a002c1a 100644
> > > --- a/drivers/gpu/drm/i915/intel_sprite.c
> > > +++ b/drivers/gpu/drm/i915/intel_sprite.c
> > > @@ -240,7 +240,7 @@ void intel_pipe_update_end(struct intel_crtc *crtc, struct intel_flip_work *work
> > > 
> > >    spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
> > > 
> > > -    if (IS_GEMINILAKE(dev_priv)) {
> > > +    if (IS_GEMINILAKE(dev_priv) || IS_CANNONLAKE(dev_priv)) {
> > >        I915_WRITE_FW(PLANE_COLOR_CTL(pipe, plane_id),
> > >                  PLANE_COLOR_PIPE_GAMMA_ENABLE |
> > >                  PLANE_COLOR_PIPE_CSC_ENABLE |
> > > -- 
> > > 1.9.1
> > > 
> > > _______________________________________________
> > > Intel-gfx mailing list
> > > Intel-gfx@lists.freedesktop.org
> > > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
> > 
> > -- 
> > Ville Syrjälä
> > Intel OTC
> 
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
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[PATCH 59/67] drm/i915/cnl: Fix Cannonlake scaler mode programing.

[Rodrigo Vivi]

As Geminilake scalers Cannonlake also don't need and don't have
the "high quality" mode programming.

Cc: Ander Conselvan de Oliveira <ander.conselvan.de.oliveira@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
---
 drivers/gpu/drm/i915/intel_atomic.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/intel_atomic.c b/drivers/gpu/drm/i915/intel_atomic.c
index 50fb1f7..7c36b20 100644
--- a/drivers/gpu/drm/i915/intel_atomic.c
+++ b/drivers/gpu/drm/i915/intel_atomic.c
@@ -248,7 +248,7 @@ int intel_atomic_setup_scalers(struct drm_i915_private *dev_priv,
 		}
 
 		/* set scaler mode */
-		if (IS_GEMINILAKE(dev_priv)) {
+		if (IS_GEMINILAKE(dev_priv) || IS_CANNONLAKE(dev_priv)) {
 			scaler_state->scalers[*scaler_id].mode = 0;
 		} else if (num_scalers_need == 1 && intel_crtc->pipe != PIPE_C) {
 			/*
-- 
1.9.1

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Re: [PATCH 59/67] drm/i915/cnl: Fix Cannonlake scaler mode programing.

[Ville Syrjälä]

On Thu, Apr 06, 2017 at 12:15:55PM -0700, Rodrigo Vivi wrote:
> As Geminilake scalers Cannonlake also don't need and don't have
> the "high quality" mode programming.
> 
> Cc: Ander Conselvan de Oliveira <ander.conselvan.de.oliveira@intel.com>
> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
> ---
>  drivers/gpu/drm/i915/intel_atomic.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_atomic.c b/drivers/gpu/drm/i915/intel_atomic.c
> index 50fb1f7..7c36b20 100644
> --- a/drivers/gpu/drm/i915/intel_atomic.c
> +++ b/drivers/gpu/drm/i915/intel_atomic.c
> @@ -248,7 +248,7 @@ int intel_atomic_setup_scalers(struct drm_i915_private *dev_priv,
>  		}
>  
>  		/* set scaler mode */
> -		if (IS_GEMINILAKE(dev_priv)) {
> +		if (IS_GEMINILAKE(dev_priv) || IS_CANNONLAKE(dev_priv)) {
>  			scaler_state->scalers[*scaler_id].mode = 0;

So this now controls normal vs. adaptive mode. We don't program anything
for the adaptive mode so far so we definitely shouldn't enable it.

Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

>  		} else if (num_scalers_need == 1 && intel_crtc->pipe != PIPE_C) {
>  			/*
> -- 
> 1.9.1
> 
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
Ville Syrjälä
Intel OTC
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[PATCH 60/67] drm/i915/cnl: Enable fifo underrun for Cannonlake.

[Rodrigo Vivi]

Also in a way that reuse bdw+ for all next platforms.

Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
---
 drivers/gpu/drm/i915/intel_fifo_underrun.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/intel_fifo_underrun.c b/drivers/gpu/drm/i915/intel_fifo_underrun.c
index 966e255..d484862 100644
--- a/drivers/gpu/drm/i915/intel_fifo_underrun.c
+++ b/drivers/gpu/drm/i915/intel_fifo_underrun.c
@@ -262,7 +262,7 @@ static bool __intel_set_cpu_fifo_underrun_reporting(struct drm_device *dev,
 		ironlake_set_fifo_underrun_reporting(dev, pipe, enable);
 	else if (IS_GEN7(dev_priv))
 		ivybridge_set_fifo_underrun_reporting(dev, pipe, enable, old);
-	else if (IS_GEN8(dev_priv) || IS_GEN9(dev_priv))
+	else if (INTEL_GEN(dev_priv) >= 8)
 		broadwell_set_fifo_underrun_reporting(dev, pipe, enable);
 
 	return old;
-- 
1.9.1

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Re: [PATCH 60/67] drm/i915/cnl: Enable fifo underrun for Cannonlake.

[Mika Kahola]

Looks ok to me.

On Thu, 2017-04-06 at 12:15 -0700, Rodrigo Vivi wrote:
> Also in a way that reuse bdw+ for all next platforms.
> 
> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Reviewed-by: Mika Kahola <mika.kahola@intel.com>

> ---
>  drivers/gpu/drm/i915/intel_fifo_underrun.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_fifo_underrun.c
> b/drivers/gpu/drm/i915/intel_fifo_underrun.c
> index 966e255..d484862 100644
> --- a/drivers/gpu/drm/i915/intel_fifo_underrun.c
> +++ b/drivers/gpu/drm/i915/intel_fifo_underrun.c
> @@ -262,7 +262,7 @@ static bool
> __intel_set_cpu_fifo_underrun_reporting(struct drm_device *dev,
>  		ironlake_set_fifo_underrun_reporting(dev, pipe,
> enable);
>  	else if (IS_GEN7(dev_priv))
>  		ivybridge_set_fifo_underrun_reporting(dev, pipe,
> enable, old);
> -	else if (IS_GEN8(dev_priv) || IS_GEN9(dev_priv))
> +	else if (INTEL_GEN(dev_priv) >= 8)
>  		broadwell_set_fifo_underrun_reporting(dev, pipe,
> enable);
>  
>  	return old;
-- 
Mika Kahola - Intel OTC

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[PATCH 61/67] drm/i915/cnl: Setup PAT Index.

[Rodrigo Vivi]

Different from previous platforms, on CNL+ there's separated
registers for separated indexes.

v2: Remove comments regarding uncertainty around the table.
v3: Remove extra line (by Ben)

Cc: Clint Taylor <clinton.a.taylor@intel.com>
Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Reviewed-by: Ben Widawsky <benjamin.widawsky@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
---
 drivers/gpu/drm/i915/i915_gem_gtt.c | 26 ++++++++++++++++++++++++--
 drivers/gpu/drm/i915/i915_reg.h     |  1 +
 2 files changed, 25 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c
index 3c8457d..95034b0 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -2654,6 +2654,24 @@ static int ggtt_probe_common(struct i915_ggtt *ggtt, u64 size)
 	return 0;
 }
 
+static void cnl_setup_private_ppat(struct drm_i915_private *dev_priv)
+{
+	/* XXX: spec is unclear if this is still needed for CNL+ */
+	if (!USES_PPGTT(dev_priv)) {
+		I915_WRITE(GEN10_PAT_INDEX(0), GEN8_PPAT_UC);
+		return;
+	}
+
+	I915_WRITE(GEN10_PAT_INDEX(0), GEN8_PPAT_WB | GEN8_PPAT_LLC);
+	I915_WRITE(GEN10_PAT_INDEX(1), GEN8_PPAT_WC | GEN8_PPAT_LLCELLC);
+	I915_WRITE(GEN10_PAT_INDEX(2), GEN8_PPAT_WT | GEN8_PPAT_LLCELLC);
+	I915_WRITE(GEN10_PAT_INDEX(3), GEN8_PPAT_UC);
+	I915_WRITE(GEN10_PAT_INDEX(4), GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(0));
+	I915_WRITE(GEN10_PAT_INDEX(5), GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(1));
+	I915_WRITE(GEN10_PAT_INDEX(6), GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(2));
+	I915_WRITE(GEN10_PAT_INDEX(7), GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(3));
+}
+
 /* The GGTT and PPGTT need a private PPAT setup in order to handle cacheability
  * bits. When using advanced contexts each context stores its own PAT, but
  * writing this data shouldn't be harmful even in those cases. */
@@ -2764,7 +2782,9 @@ static int gen8_gmch_probe(struct i915_ggtt *ggtt)
 
 	ggtt->base.total = (size / sizeof(gen8_pte_t)) << PAGE_SHIFT;
 
-	if (IS_CHERRYVIEW(dev_priv) || IS_GEN9_LP(dev_priv))
+	if (INTEL_GEN(dev_priv) >= 10)
+		cnl_setup_private_ppat(dev_priv);
+	else if (IS_CHERRYVIEW(dev_priv) || IS_GEN9_LP(dev_priv))
 		chv_setup_private_ppat(dev_priv);
 	else
 		bdw_setup_private_ppat(dev_priv);
@@ -3031,7 +3051,9 @@ void i915_gem_restore_gtt_mappings(struct drm_i915_private *dev_priv)
 	ggtt->base.closed = false;
 
 	if (INTEL_GEN(dev_priv) >= 8) {
-		if (IS_CHERRYVIEW(dev_priv) || IS_GEN9_LP(dev_priv))
+		if (INTEL_GEN(dev_priv) >= 10)
+			cnl_setup_private_ppat(dev_priv);
+		else if (IS_CHERRYVIEW(dev_priv) || IS_GEN9_LP(dev_priv))
 			chv_setup_private_ppat(dev_priv);
 		else
 			bdw_setup_private_ppat(dev_priv);
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 51ffbee..b96de50 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -2125,6 +2125,7 @@ enum skl_disp_power_wells {
 #define DONE_REG		_MMIO(0x40b0)
 #define GEN8_PRIVATE_PAT_LO	_MMIO(0x40e0)
 #define GEN8_PRIVATE_PAT_HI	_MMIO(0x40e0 + 4)
+#define GEN10_PAT_INDEX(index)	_MMIO(0x40e0 + index*4)
 #define BSD_HWS_PGA_GEN7	_MMIO(0x04180)
 #define BLT_HWS_PGA_GEN7	_MMIO(0x04280)
 #define VEBOX_HWS_PGA_GEN7	_MMIO(0x04380)
-- 
1.9.1

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[PATCH 62/67] drm/i915/cnl: Add support slice/subslice/eu configs

[Rodrigo Vivi]

From: Ben Widawsky <ben@bwidawsk.net>

Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
---
 drivers/gpu/drm/i915/i915_drv.h          |  5 +++-
 drivers/gpu/drm/i915/i915_reg.h          | 21 +++++++++++++++
 drivers/gpu/drm/i915/intel_device_info.c | 45 +++++++++++++++++++++++++++++++-
 3 files changed, 69 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 7dda202..fc787dd 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -845,7 +845,10 @@ struct sseu_dev_info {
 	u8 slice_mask;
 	u8 subslice_mask;
 	u8 eu_total;
-	u8 eu_per_subslice;
+	union {
+		u8 per_subslice_eu_disable_mask[3][3];
+		u8 eu_per_subslice;
+	};
 	u8 min_eu_in_pool;
 	/* For each slice, which subslice(s) has(have) 7 EUs (bitfield)? */
 	u8 subslice_7eu[3];
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index b96de50..67f306e 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -2515,6 +2515,11 @@ enum skl_disp_power_wells {
 #define   GEN9_F2_SS_DIS_SHIFT		20
 #define   GEN9_F2_SS_DIS_MASK		(0xf << GEN9_F2_SS_DIS_SHIFT)
 
+#define   GEN10_F2_S_ENA_SHIFT		22
+#define   GEN10_F2_S_ENA_MASK		(0x7 << GEN10_F2_S_ENA_SHIFT)
+#define   GEN10_F2_SS_DIS_SHIFT		18
+#define   GEN10_F2_SS_DIS_MASK		(0x7 << GEN10_F2_SS_DIS_SHIFT)
+
 #define GEN8_EU_DISABLE0		_MMIO(0x9134)
 #define   GEN8_EU_DIS0_S0_MASK		0xffffff
 #define   GEN8_EU_DIS0_S1_SHIFT		24
@@ -2530,6 +2535,22 @@ enum skl_disp_power_wells {
 
 #define GEN9_EU_DISABLE(slice)		_MMIO(0x9134 + (slice)*0x4)
 
+#define GEN10_EU_DIS0_S0_SHIFT		0
+#define GEN10_EU_DIS0_S0_MASK		(0xff << GEN10_EU_DIS0_S0_SHIFT)
+#define GEN10_EU_DIS0_S1_SHIFT		8
+#define GEN10_EU_DIS0_S1_MASK		(0xff << GEN10_EU_DIS0_S1_SHIFT)
+#define GEN10_EU_DIS0_S2_SHIFT		16
+#define GEN10_EU_DIS0_S2_MASK		(0xff << GEN10_EU_DIS0_S2_SHIFT)
+#define GEN10_EU_DIS1_S0_SHIFT		24
+#define GEN10_EU_DIS1_S0_MASK		(0xff << GEN10_EU_DIS1_S0_SHIFT)
+#define GEN10_EU_DIS1_S1_SHIFT		0
+#define GEN10_EU_DIS1_S1_MASK		(0xff << GEN10_EU_DIS1_S1_SHIFT)
+#define GEN10_EU_DIS2_S0_SHIFT		8
+#define GEN10_EU_DIS2_S0_MASK		(0xff << GEN10_EU_DIS2_S0_SHIFT)
+#define GEN10_EU_DIS2_S1_SHIFT		16
+#define GEN10_EU_DIS2_S1_MASK		(0xff << GEN10_EU_DIS2_S1_SHIFT)
+/* Spec defines more, but they can't be valid */
+
 #define GEN6_BSD_SLEEP_PSMI_CONTROL	_MMIO(0x12050)
 #define   GEN6_BSD_SLEEP_MSG_DISABLE	(1 << 0)
 #define   GEN6_BSD_SLEEP_FLUSH_DISABLE	(1 << 2)
diff --git a/drivers/gpu/drm/i915/intel_device_info.c b/drivers/gpu/drm/i915/intel_device_info.c
index 5ae9a80..a2c59ab 100644
--- a/drivers/gpu/drm/i915/intel_device_info.c
+++ b/drivers/gpu/drm/i915/intel_device_info.c
@@ -81,6 +81,47 @@ void intel_device_info_dump(struct drm_i915_private *dev_priv)
 #undef PRINT_FLAG
 }
 
+static void gen10_sseu_info_init(struct drm_i915_private *dev_priv)
+{
+	struct sseu_dev_info *sseu = &mkwrite_device_info(dev_priv)->sseu;
+	const u32 fuse2 = I915_READ(GEN8_FUSE2);
+	u32 temp, i, j;
+
+	sseu->slice_mask = (fuse2 & GEN10_F2_S_ENA_MASK) >> GEN10_F2_S_ENA_SHIFT;
+	sseu->subslice_mask = (1 << 3) - 1;
+	sseu->subslice_mask &= ~((fuse2 & GEN10_F2_SS_DIS_MASK) >>
+				 GEN10_F2_SS_DIS_SHIFT);
+
+	temp = I915_READ(GEN8_EU_DISABLE0);
+	sseu->per_subslice_eu_disable_mask[0][0] =
+		(temp & GEN10_EU_DIS0_S0_MASK) >> GEN10_EU_DIS0_S0_SHIFT;
+	sseu->per_subslice_eu_disable_mask[0][1] =
+		(temp & GEN10_EU_DIS0_S1_MASK) >> GEN10_EU_DIS0_S1_SHIFT;
+	sseu->per_subslice_eu_disable_mask[0][2] =
+		(temp & GEN10_EU_DIS0_S2_MASK) >> GEN10_EU_DIS0_S2_SHIFT;
+	sseu->per_subslice_eu_disable_mask[1][0] =
+		(temp & GEN10_EU_DIS1_S0_MASK) >> GEN10_EU_DIS1_S0_SHIFT;
+
+	temp = I915_READ(GEN8_EU_DISABLE1);
+	sseu->per_subslice_eu_disable_mask[1][1] =
+		(temp & GEN10_EU_DIS1_S1_MASK) >> GEN10_EU_DIS1_S1_SHIFT;
+	sseu->per_subslice_eu_disable_mask[2][0] =
+		(temp & GEN10_EU_DIS2_S0_MASK) >> GEN10_EU_DIS2_S0_SHIFT;
+	sseu->per_subslice_eu_disable_mask[2][1] =
+		(temp & GEN10_EU_DIS2_S1_MASK) >> GEN10_EU_DIS2_S1_SHIFT;
+
+	for (i = 0; i < 3; i++)
+		for (j = 0; j < 3; j++)
+			sseu->eu_total +=
+				hweight8(~sseu->per_subslice_eu_disable_mask[i][j]);
+
+	/* On CNL, I cannot find any restrictions on power gating. */
+	sseu->has_slice_pg = 1;
+	sseu->has_subslice_pg = 1;
+	sseu->has_eu_pg = 1;
+}
+
+
 static void cherryview_sseu_info_init(struct drm_i915_private *dev_priv)
 {
 	struct sseu_dev_info *sseu = &mkwrite_device_info(dev_priv)->sseu;
@@ -408,8 +449,10 @@ void intel_device_info_runtime_init(struct drm_i915_private *dev_priv)
 		cherryview_sseu_info_init(dev_priv);
 	else if (IS_BROADWELL(dev_priv))
 		broadwell_sseu_info_init(dev_priv);
-	else if (INTEL_INFO(dev_priv)->gen >= 9)
+	else if (INTEL_INFO(dev_priv)->gen == 9)
 		gen9_sseu_info_init(dev_priv);
+	else if (INTEL_INFO(dev_priv)->gen >= 10)
+		gen10_sseu_info_init(dev_priv);
 
 	info->has_snoop = !info->has_llc;
 
-- 
1.9.1

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[PATCH 63/67] drm/i915/cnl: Avoid ioremap_wc on Cannonlake as well.

[Rodrigo Vivi]

WC is apparently not an option for CNL+ on GTT here.
Trying to use it we get hard hangs.

Credits-to: Ben Widawsky <benjamin.widawsky@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
---
 drivers/gpu/drm/i915/i915_gem_gtt.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c
index 95034b0..32b664a 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -2634,7 +2634,7 @@ static int ggtt_probe_common(struct i915_ggtt *ggtt, u64 size)
 	 * resort to an uncached mapping. The WC issue is easily caught by the
 	 * readback check when writing GTT PTE entries.
 	 */
-	if (IS_GEN9_LP(dev_priv))
+	if (IS_GEN9_LP(dev_priv) || INTEL_GEN(dev_priv) >= 10)
 		ggtt->gsm = ioremap_nocache(phys_addr, size);
 	else
 		ggtt->gsm = ioremap_wc(phys_addr, size);
-- 
1.9.1

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[PATCH 64/67] drm/i915/cnl: WaThrottleEUPerfToAvoidTDBackPressure:cnl(pre-prod)

[Rodrigo Vivi]

Wa for B-stepping only.

A for a hang issue that requires throttling EU performace
to 12.5% to avoid back pressure to thread dispatch

Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h        | 1 +
 drivers/gpu/drm/i915/intel_engine_cs.c | 4 ++++
 2 files changed, 5 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 67f306e..8b25119 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -7839,6 +7839,7 @@ enum {
 #define   FLOW_CONTROL_ENABLE		(1<<15)
 #define   PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE	(1<<8)
 #define   STALL_DOP_GATING_DISABLE		(1<<5)
+#define   THROTTLE_12_5				(7<<2)
 
 #define GEN7_ROW_CHICKEN2		_MMIO(0xe4f4)
 #define GEN7_ROW_CHICKEN2_GT2		_MMIO(0xf4f4)
diff --git a/drivers/gpu/drm/i915/intel_engine_cs.c b/drivers/gpu/drm/i915/intel_engine_cs.c
index b5599fa..754b370 100644
--- a/drivers/gpu/drm/i915/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/intel_engine_cs.c
@@ -951,6 +951,10 @@ static int cnl_init_workarounds(struct intel_engine_cs *engine)
 	struct drm_i915_private *dev_priv = engine->i915;
 	int ret;
 
+	/* WaThrottleEUPerfToAvoidTDBackPressure:cnl(pre-prod) */
+	if (IS_CNL_REVID(dev_priv, CNL_REVID_B0, CNL_REVID_B0))
+		WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN, THROTTLE_12_5);
+
 	/* WaDisableReplayBufferBankArbitrationOptimization:cnl */
 	WA_SET_BIT_MASKED(COMMON_SLICE_CHICKEN2,
 			  GEN8_SBE_DISABLE_REPLAY_BUF_OPTIMIZATION);
-- 
1.9.1

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Re: [PATCH 64/67] drm/i915/cnl: WaThrottleEUPerfToAvoidTDBackPressure:cnl(pre-prod)

[Oscar Mateo]

On 04/06/2017 12:16 PM, Rodrigo Vivi wrote:
> Wa for B-stepping only.
>
> A for a hang issue that requires throttling EU performace
> to 12.5% to avoid back pressure to thread dispatch
>
> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
> ---
>   drivers/gpu/drm/i915/i915_reg.h        | 1 +
>   drivers/gpu/drm/i915/intel_engine_cs.c | 4 ++++
>   2 files changed, 5 insertions(+)

Reviewed-by: Oscar Mateo <oscar.mateo@intel.com>

> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 67f306e..8b25119 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -7839,6 +7839,7 @@ enum {
>   #define   FLOW_CONTROL_ENABLE		(1<<15)
>   #define   PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE	(1<<8)
>   #define   STALL_DOP_GATING_DISABLE		(1<<5)
> +#define   THROTTLE_12_5				(7<<2)
>   
>   #define GEN7_ROW_CHICKEN2		_MMIO(0xe4f4)
>   #define GEN7_ROW_CHICKEN2_GT2		_MMIO(0xf4f4)
> diff --git a/drivers/gpu/drm/i915/intel_engine_cs.c b/drivers/gpu/drm/i915/intel_engine_cs.c
> index b5599fa..754b370 100644
> --- a/drivers/gpu/drm/i915/intel_engine_cs.c
> +++ b/drivers/gpu/drm/i915/intel_engine_cs.c
> @@ -951,6 +951,10 @@ static int cnl_init_workarounds(struct intel_engine_cs *engine)
>   	struct drm_i915_private *dev_priv = engine->i915;
>   	int ret;
>   
> +	/* WaThrottleEUPerfToAvoidTDBackPressure:cnl(pre-prod) */
> +	if (IS_CNL_REVID(dev_priv, CNL_REVID_B0, CNL_REVID_B0))
> +		WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN, THROTTLE_12_5);
> +
>   	/* WaDisableReplayBufferBankArbitrationOptimization:cnl */
>   	WA_SET_BIT_MASKED(COMMON_SLICE_CHICKEN2,
>   			  GEN8_SBE_DISABLE_REPLAY_BUF_OPTIMIZATION);

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[PATCH 65/67] drm/i915/cnl: Enable Audio Pin Buffer.

[Rodrigo Vivi]

Starting on CNL, we need to enable Audio Pin Buffer.

By the spec it seems that this is part of audio programming,
so let's give them the hability to set/unset this as needed.

v2: With a hook so audio driver can control it.
v3: Put back reg definition lost on v2.

Cc: Jani Nikula <jani.nikula@intel.com>
Cc: Sanyog Kale <sanyog.r.kale@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h    |  3 +++
 drivers/gpu/drm/i915/intel_audio.c | 16 ++++++++++++++++
 include/drm/i915_component.h       |  6 ++++++
 3 files changed, 25 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 8b25119..80d25e6 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -2632,6 +2632,9 @@ enum skl_disp_power_wells {
 #define I915_HDMI_LPE_AUDIO_BASE	(VLV_DISPLAY_BASE + 0x65000)
 #define I915_HDMI_LPE_AUDIO_SIZE	0x1000
 
+#define AUDIO_PIN_BUF_CTL		_MMIO(0x48414)
+#define AUDIO_PIN_BUF_ENABLE		(1 << 31)
+
 /* DisplayPort Audio w/ LPE */
 #define VLV_AUD_CHICKEN_BIT_REG		_MMIO(VLV_DISPLAY_BASE + 0x62F38)
 #define VLV_CHICKEN_BIT_DBG_ENABLE	(1 << 0)
diff --git a/drivers/gpu/drm/i915/intel_audio.c b/drivers/gpu/drm/i915/intel_audio.c
index 52c207e..fb78c7c 100644
--- a/drivers/gpu/drm/i915/intel_audio.c
+++ b/drivers/gpu/drm/i915/intel_audio.c
@@ -876,6 +876,21 @@ static int i915_audio_component_get_eld(struct device *kdev, int port,
 	return ret;
 }
 
+static void i915_audio_component_pin_buf(struct device *kdev, bool enable)
+{
+	struct drm_i915_private *dev_priv = kdev_to_i915(kdev);
+
+	if (!IS_CANNONLAKE(dev_priv))
+		return;
+
+	if (enable)
+		I915_WRITE(AUDIO_PIN_BUF_CTL, I915_READ(AUDIO_PIN_BUF_CTL) |
+			   AUDIO_PIN_BUF_ENABLE);
+	else
+		I915_WRITE(AUDIO_PIN_BUF_CTL, I915_READ(AUDIO_PIN_BUF_CTL) &
+			   ~AUDIO_PIN_BUF_ENABLE);
+}
+
 static const struct i915_audio_component_ops i915_audio_component_ops = {
 	.owner		= THIS_MODULE,
 	.get_power	= i915_audio_component_get_power,
@@ -884,6 +899,7 @@ static int i915_audio_component_get_eld(struct device *kdev, int port,
 	.get_cdclk_freq	= i915_audio_component_get_cdclk_freq,
 	.sync_audio_rate = i915_audio_component_sync_audio_rate,
 	.get_eld	= i915_audio_component_get_eld,
+	.pin_buf	= i915_audio_component_pin_buf,
 };
 
 static int i915_audio_component_bind(struct device *i915_kdev,
diff --git a/include/drm/i915_component.h b/include/drm/i915_component.h
index 545c6e0..b8875d4 100644
--- a/include/drm/i915_component.h
+++ b/include/drm/i915_component.h
@@ -79,6 +79,12 @@ struct i915_audio_component_ops {
 	 */
 	int (*get_eld)(struct device *, int port, int pipe, bool *enabled,
 		       unsigned char *buf, int max_bytes);
+	/**
+	 * @pin_buf: Enable or disable pin buffer.
+	 *
+	 * Allow audio driver the toggle pin buffer.
+	 */
+	void (*pin_buf)(struct device *, bool enable);
 };
 
 /**
-- 
1.9.1

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[PATCH 66/67] drm/i915/cnl: LSPCON support is gen9+

[Rodrigo Vivi]

There is no platform specific change needed for LSPCON
support on Cannonlake. So let's make it gen9+.

Cc: Shashank Sharma <shashank.sharma@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
---
 drivers/gpu/drm/i915/i915_drv.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index fc787dd..bf336bd 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -2986,7 +2986,7 @@ static inline struct scatterlist *__sg_next(struct scatterlist *sg)
 
 #define HAS_GMCH_DISPLAY(dev_priv) ((dev_priv)->info.has_gmch_display)
 
-#define HAS_LSPCON(dev_priv) (IS_GEN9(dev_priv))
+#define HAS_LSPCON(dev_priv) (INTEL_GEN(dev_priv) >= 9)
 
 /* DPF == dynamic parity feature */
 #define HAS_L3_DPF(dev_priv) ((dev_priv)->info.has_l3_dpf)
-- 
1.9.1

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Re: [PATCH 66/67] drm/i915/cnl: LSPCON support is gen9+

[Sharma, Shashank]

Reviewed-by: Shashank Sharma <shashank.sharma@intel.com>

Regards
Shashank
-----Original Message-----
From: Vivi, Rodrigo 
Sent: Thursday, April 6, 2017 10:16 PM
To: intel-gfx@lists.freedesktop.org
Cc: Vivi, Rodrigo <rodrigo.vivi@intel.com>; Sharma, Shashank <shashank.sharma@intel.com>
Subject: [PATCH 66/67] drm/i915/cnl: LSPCON support is gen9+

There is no platform specific change needed for LSPCON support on Cannonlake. So let's make it gen9+.

Cc: Shashank Sharma <shashank.sharma@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
---
 drivers/gpu/drm/i915/i915_drv.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index fc787dd..bf336bd 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -2986,7 +2986,7 @@ static inline struct scatterlist *__sg_next(struct scatterlist *sg)
 
 #define HAS_GMCH_DISPLAY(dev_priv) ((dev_priv)->info.has_gmch_display)
 
-#define HAS_LSPCON(dev_priv) (IS_GEN9(dev_priv))
+#define HAS_LSPCON(dev_priv) (INTEL_GEN(dev_priv) >= 9)
 
 /* DPF == dynamic parity feature */
 #define HAS_L3_DPF(dev_priv) ((dev_priv)->info.has_l3_dpf)
--
1.9.1

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[PATCH 67/67] drm/i915/cnl: Adjust min pixel rate.

[Rodrigo Vivi]

Cannonlake also needs to adjust the minimal pixel rate
as gen9 platforms. Specially for the Azalia audio case.

Cc: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
Cc: Sanyog Kale <sanyog.r.kale@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
---
 drivers/gpu/drm/i915/intel_cdclk.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/intel_cdclk.c b/drivers/gpu/drm/i915/intel_cdclk.c
index a8c254b..604c565 100644
--- a/drivers/gpu/drm/i915/intel_cdclk.c
+++ b/drivers/gpu/drm/i915/intel_cdclk.c
@@ -1777,7 +1777,7 @@ static int intel_max_pixel_rate(struct drm_atomic_state *state)
 
 		pixel_rate = crtc_state->pixel_rate;
 
-		if (IS_BROADWELL(dev_priv) || IS_GEN9(dev_priv))
+		if (IS_BROADWELL(dev_priv) || INTEL_GEN(dev_priv) >= 9)
 			pixel_rate =
 				bdw_adjust_min_pipe_pixel_rate(crtc_state,
 							       pixel_rate);
-- 
1.9.1

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✗ Fi.CI.BAT: warning for series starting with [01/67] drm/i915/cnp: Introduce Cannonpoint PCH. (rev2)

[Patchwork]

== Series Details ==

Series: series starting with [01/67] drm/i915/cnp: Introduce Cannonpoint PCH. (rev2)
URL   : https://patchwork.freedesktop.org/series/22607/
State : warning

== Summary ==

Series 22607v2 Series without cover letter
https://patchwork.freedesktop.org/api/1.0/series/22607/revisions/2/mbox/

Test gem_exec_suspend:
        Subgroup basic-s4-devices:
                pass       -> DMESG-WARN (fi-bxt-t5700) fdo#100125
                dmesg-warn -> PASS       (fi-kbl-7560u) fdo#100125
Test kms_pipe_crc_basic:
        Subgroup suspend-read-crc-pipe-a:
                pass       -> DMESG-WARN (fi-bxt-t5700)

fdo#100125 https://bugs.freedesktop.org/show_bug.cgi?id=100125

fi-bdw-5557u     total:278  pass:267  dwarn:0   dfail:0   fail:0   skip:11  time: 428s
fi-bdw-gvtdvm    total:278  pass:256  dwarn:8   dfail:0   fail:0   skip:14  time: 427s
fi-bsw-n3050     total:278  pass:242  dwarn:0   dfail:0   fail:0   skip:36  time: 578s
fi-bxt-j4205     total:278  pass:259  dwarn:0   dfail:0   fail:0   skip:19  time: 508s
fi-bxt-t5700     total:278  pass:256  dwarn:2   dfail:0   fail:0   skip:20  time: 531s
fi-byt-j1900     total:278  pass:254  dwarn:0   dfail:0   fail:0   skip:24  time: 488s
fi-byt-n2820     total:278  pass:250  dwarn:0   dfail:0   fail:0   skip:28  time: 478s
fi-hsw-4770      total:278  pass:262  dwarn:0   dfail:0   fail:0   skip:16  time: 415s
fi-hsw-4770r     total:278  pass:262  dwarn:0   dfail:0   fail:0   skip:16  time: 404s
fi-ilk-650       total:278  pass:228  dwarn:0   dfail:0   fail:0   skip:50  time: 418s
fi-ivb-3520m     total:278  pass:260  dwarn:0   dfail:0   fail:0   skip:18  time: 496s
fi-ivb-3770      total:278  pass:260  dwarn:0   dfail:0   fail:0   skip:18  time: 488s
fi-kbl-7500u     total:278  pass:260  dwarn:0   dfail:0   fail:0   skip:18  time: 452s
fi-kbl-7560u     total:278  pass:268  dwarn:0   dfail:0   fail:0   skip:10  time: 565s
fi-skl-6260u     total:278  pass:268  dwarn:0   dfail:0   fail:0   skip:10  time: 457s
fi-skl-6700hq    total:278  pass:261  dwarn:0   dfail:0   fail:0   skip:17  time: 576s
fi-skl-6700k     total:278  pass:256  dwarn:4   dfail:0   fail:0   skip:18  time: 461s
fi-skl-6770hq    total:278  pass:268  dwarn:0   dfail:0   fail:0   skip:10  time: 486s
fi-skl-gvtdvm    total:278  pass:265  dwarn:0   dfail:0   fail:0   skip:13  time: 436s
fi-snb-2520m     total:278  pass:250  dwarn:0   dfail:0   fail:0   skip:28  time: 529s
fi-snb-2600      total:278  pass:249  dwarn:0   dfail:0   fail:0   skip:29  time: 401s

3d39d8905c145cdae5a79fe6d0a3c6fd70ff8a2f drm-tip: 2017y-04m-06d-19h-30m-56s UTC integration manifest
de5c231 drm/i915/cnl: Adjust min pixel rate.
610e574 drm/i915/cnl: LSPCON support is gen9+
7b113d8 drm/i915/cnl: Enable Audio Pin Buffer.
9a28e23 drm/i915/cnl: WaThrottleEUPerfToAvoidTDBackPressure:cnl(pre-prod)
55fc13e drm/i915/cnl: Avoid ioremap_wc on Cannonlake as well.
5467baa drm/i915/cnl: Add support slice/subslice/eu configs
2189011 drm/i915/cnl: Setup PAT Index.
b4c1580 drm/i915/cnl: Enable fifo underrun for Cannonlake.
198ffbe drm/i915/cnl: Fix Cannonlake scaler mode programing.
932cc61 drm/i915/cnl: Cannonlake color init.
fd56199 x86/gpu: CNL uses the same GMS values as SKL
80d6cbf drm/i915/cnl: Reuse skl_wm_get_hw_state on Cannonlake.
b14fc1f drm/i915/gen10: implement gen 10 watermarks calculations
e963ecf drm/i915/gen10: fix WM latency printing
ad36893 drm/i915/cnl: don't apply the GEN9/CNL:A WM WAs to CNL:B+
9d0cb4c drm/i915/gen10: fix the gen 10 SAGV block time
969080d drm/i915/cnl: Enable SAGV for Cannonlake.
6848c02 drm/i915/gen10+: use the SKL code for reading WM latencies
7d957c2 drm/i915/cnl: Avoid old DDI translation functions on Cannonlake.
727da8c drm/i915/cnl: Get DDI clock based on PLLs.
f1be50b drm/i915/cnl: Dump the right pll registers when dumping pipe config.
da6b705 drm/i915/cnl: Add allowed DP rates for Cannonlake.
1aca31d drm/i915/cnl: Add max allowed Cannonlake DC.
a472e4a drm/i915/cnl: DC3 to DC5 counters available on CNL.
ff18629 drm/i915: Use HAS_CSR instead of gen number on DMC load.
49dc2aa drm/i915/DMC/CNL: Load DMC on CNL
95134c5 drm/i915/cnl: Add slice and subslice information to debugfs.
98fe777 drm/i915/cnl: Enable loadgen_select bit for vswing sequence
5552ef0 drm/i915/cnl: Implement voltage swing sequence.
a8e6e92 drm/i915/cnl: Add DDI Buffer translation tables for Cannonlake.
b947944 drm/i915/cnl: Add registers related to voltage swing sequences.
ce96013 drm/i915: Add MMIO helper for 6 ports with different offsets.
aaed686 drm/i915/cnl: Enable wrpll computation for CNL
b0aea9f drm/i915/cnl: Initialize PLLs
0197733 drm/i915: Configure DPLL's for Cannonlake
c4a3b27 drm/i915/cnl: DDI - PLL mapping
1b4e307 drm/i915/cnl: Allow dynamic cdclk changes on CNL
ce259ea drm/i915/cnl: Implement CNL display init/unit sequence
6703c79 drm/i915/cnl: Implement .set_cdclk() for CNL
6213086 drm/i915/cnl: Implement .get_display_clock_speed() for CNL
148d387 drm/i915/cnl: Also need power well sanitize.
960bcaf drm/i915/cnl: Add power wells for CNL
1d470e7 drm/i915/cnl: Inherit RPS stuff from previous platforms.
e6f6b61 drm/i915/cnl: Add force wake for gen10.
d6a2af3 drm/i915/gen10: Set value of Indirect Context Offset for gen10
c6c56c6 drm/i915/cnl: Add RT cache flush pipe control w/a
18cb173 drm/i915/cnl: Update the context size
3768ac8 drm/i915/cnl: Cannonlake has same MOCS table than Skylake.
5a622ed drm/i915/cnl: Configure EU slice power gating.
ecefc1a drm/i915/cnl: Add initial gen10 golden states.
46ce6d0 drm/i915/cnl: CNL has an increased DDB size
f8373b3 drm/i915/cnl: Cannonlake has 4 planes (3 sprites) per pipe
e0db005 drm/i915/cnl: Apply large line width optimization
3698be4 drm/i915/cnl: WaDisableEnhancedSBEVertexCaching
8c0338b drm/i915/cnl: Add WaDisableReplayBufferBankArbitrationOptimization
e70f18c drm/i915/cnl: Introduce initial Cannonlake Workarounds.
4d8b7c8 drm/i915/cnl: add IS_CNL_REVID macro
d36dad4 drm/i915/cnl: Add Cannonlake PCI IDs for Y-skus.
5a52856 drm/i915/cnl: Add Cannonlake PCI IDs for U-skus.
88c1b6a drm/i915/cnl: Cannonlake uses CNP PCH.
33b7b03 drm/i915/cnl: Introduce Cannonlake platform defition.
d5c5de7 drm/i915/cnp: Panel Power sequence changes for CNP PCH.
a31f255 drm/i915/cnp: add CNP gmbus support
7ae4ea8 drm/i915/cnp: Add Backlight support to CNP PCH.
c0b3bb9 drm/i915/cnp: Get/set proper Raw clock frequency on CNP.
e744968 drm/i915/cnp: Add PCI ID for Cannonpoint LP PCH
79d50ef drm/i915/cnp: Introduce Cannonpoint PCH.

== Logs ==

For more details see: https://intel-gfx-ci.01.org/CI/Patchwork_4427/
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✗ Fi.CI.BAT: warning for series starting with [01/67] drm/i915/cnp: Introduce Cannonpoint PCH. (rev3)

[Patchwork]

== Series Details ==

Series: series starting with [01/67] drm/i915/cnp: Introduce Cannonpoint PCH. (rev3)
URL   : https://patchwork.freedesktop.org/series/22607/
State : warning

== Summary ==

Series 22607v3 Series without cover letter
https://patchwork.freedesktop.org/api/1.0/series/22607/revisions/3/mbox/

Test kms_pipe_crc_basic:
        Subgroup suspend-read-crc-pipe-a:
                pass       -> DMESG-WARN (fi-bxt-t5700)

fi-bdw-5557u     total:278  pass:267  dwarn:0   dfail:0   fail:0   skip:11  time: 438s
fi-bdw-gvtdvm    total:278  pass:256  dwarn:8   dfail:0   fail:0   skip:14  time: 426s
fi-bsw-n3050     total:278  pass:242  dwarn:0   dfail:0   fail:0   skip:36  time: 565s
fi-bxt-j4205     total:278  pass:259  dwarn:0   dfail:0   fail:0   skip:19  time: 511s
fi-bxt-t5700     total:278  pass:257  dwarn:1   dfail:0   fail:0   skip:20  time: 548s
fi-byt-j1900     total:278  pass:254  dwarn:0   dfail:0   fail:0   skip:24  time: 490s
fi-byt-n2820     total:278  pass:250  dwarn:0   dfail:0   fail:0   skip:28  time: 478s
fi-hsw-4770      total:278  pass:262  dwarn:0   dfail:0   fail:0   skip:16  time: 408s
fi-hsw-4770r     total:278  pass:262  dwarn:0   dfail:0   fail:0   skip:16  time: 407s
fi-ilk-650       total:278  pass:228  dwarn:0   dfail:0   fail:0   skip:50  time: 430s
fi-ivb-3520m     total:278  pass:260  dwarn:0   dfail:0   fail:0   skip:18  time: 493s
fi-ivb-3770      total:278  pass:260  dwarn:0   dfail:0   fail:0   skip:18  time: 467s
fi-kbl-7500u     total:278  pass:260  dwarn:0   dfail:0   fail:0   skip:18  time: 454s
fi-kbl-7560u     total:278  pass:268  dwarn:0   dfail:0   fail:0   skip:10  time: 567s
fi-skl-6260u     total:278  pass:268  dwarn:0   dfail:0   fail:0   skip:10  time: 450s
fi-skl-6700hq    total:278  pass:261  dwarn:0   dfail:0   fail:0   skip:17  time: 580s
fi-skl-6700k     total:278  pass:256  dwarn:4   dfail:0   fail:0   skip:18  time: 461s
fi-skl-6770hq    total:278  pass:268  dwarn:0   dfail:0   fail:0   skip:10  time: 487s
fi-skl-gvtdvm    total:278  pass:265  dwarn:0   dfail:0   fail:0   skip:13  time: 429s
fi-snb-2520m     total:278  pass:250  dwarn:0   dfail:0   fail:0   skip:28  time: 530s
fi-snb-2600      total:278  pass:249  dwarn:0   dfail:0   fail:0   skip:29  time: 402s

7aafd5c8395fea9a79fbee82de4ffc63c04790d6 drm-tip: 2017y-04m-06d-21h-02m-00s UTC integration manifest
7624f54 drm/i915/cnl: Adjust min pixel rate.
3378c91 drm/i915/cnl: LSPCON support is gen9+
8b06dc4 drm/i915/cnl: Enable Audio Pin Buffer.
d2c1f3f drm/i915/cnl: WaThrottleEUPerfToAvoidTDBackPressure:cnl(pre-prod)
08465fd drm/i915/cnl: Avoid ioremap_wc on Cannonlake as well.
b4d1879 drm/i915/cnl: Add support slice/subslice/eu configs
2b1a220 drm/i915/cnl: Setup PAT Index.
7b4497d drm/i915/cnl: Enable fifo underrun for Cannonlake.
7833f55 drm/i915/cnl: Fix Cannonlake scaler mode programing.
96f694b drm/i915/cnl: Cannonlake color init.
dfe9719 x86/gpu: CNL uses the same GMS values as SKL
bdb4899 drm/i915/cnl: Reuse skl_wm_get_hw_state on Cannonlake.
bbee9e7 drm/i915/gen10: implement gen 10 watermarks calculations
7b85e06 drm/i915/gen10: fix WM latency printing
62d4e30 drm/i915/cnl: don't apply the GEN9/CNL:A WM WAs to CNL:B+
c0a1786 drm/i915/gen10: fix the gen 10 SAGV block time
55462a3 drm/i915/cnl: Enable SAGV for Cannonlake.
f73c379 drm/i915/gen10+: use the SKL code for reading WM latencies
9b050c9 drm/i915/cnl: Avoid old DDI translation functions on Cannonlake.
39c17e6 drm/i915/cnl: Get DDI clock based on PLLs.
e40493b drm/i915/cnl: Dump the right pll registers when dumping pipe config.
39258f0 drm/i915/cnl: Add allowed DP rates for Cannonlake.
04e9b41 drm/i915/cnl: Add max allowed Cannonlake DC.
f1d4b71 drm/i915/cnl: DC3 to DC5 counters available on CNL.
232cc4b drm/i915: Use HAS_CSR instead of gen number on DMC load.
9ecef92 drm/i915/DMC/CNL: Load DMC on CNL
9073eae drm/i915/cnl: Add slice and subslice information to debugfs.
fb45b88 drm/i915/cnl: Enable loadgen_select bit for vswing sequence
e2d0803 drm/i915/cnl: Implement voltage swing sequence.
d4edcf00 drm/i915/cnl: Add DDI Buffer translation tables for Cannonlake.
aadad4a drm/i915/cnl: Add registers related to voltage swing sequences.
af4d0d1 drm/i915: Add MMIO helper for 6 ports with different offsets.
0b62b8f drm/i915/cnl: Enable wrpll computation for CNL
52b5618 drm/i915/cnl: Initialize PLLs
383b9b6 drm/i915: Configure DPLL's for Cannonlake
49011b6 drm/i915/cnl: DDI - PLL mapping
e6a5ead drm/i915/cnl: Allow dynamic cdclk changes on CNL
07e5df5 drm/i915/cnl: Implement CNL display init/unit sequence
55eada5 drm/i915/cnl: Implement .set_cdclk() for CNL
6ac53af drm/i915/cnl: Implement .get_display_clock_speed() for CNL
4923ac5 drm/i915/cnl: Also need power well sanitize.
4298771 drm/i915/cnl: Add power wells for CNL
39a5338 drm/i915/cnl: Inherit RPS stuff from previous platforms.
96ec06c drm/i915/cnl: Add force wake for gen10.
608930b drm/i915/gen10: Set value of Indirect Context Offset for gen10
ff47c55 drm/i915/cnl: Add RT cache flush pipe control w/a
263a836 drm/i915/cnl: Update the context size
098c373 drm/i915/cnl: Cannonlake has same MOCS table than Skylake.
c823a26 drm/i915/cnl: Configure EU slice power gating.
9b6fbd8 drm/i915/cnl: Add initial gen10 golden states.
1f3d6ae drm/i915/cnl: CNL has an increased DDB size
0dbc7aa drm/i915/cnl: Cannonlake has 4 planes (3 sprites) per pipe
89443b5 drm/i915/cnl: Apply large line width optimization
6dc1125 drm/i915/cnl: WaDisableEnhancedSBEVertexCaching
3cfc58c drm/i915/cnl: Add WaDisableReplayBufferBankArbitrationOptimization
5218894 drm/i915/cnl: Introduce initial Cannonlake Workarounds.
48a37d5 drm/i915/cnl: add IS_CNL_REVID macro
8ec25d8 drm/i915/cnl: Add Cannonlake PCI IDs for Y-skus.
e4323e4 drm/i915/cnl: Add Cannonlake PCI IDs for U-skus.
8410481 drm/i915/cnl: Cannonlake uses CNP PCH.
b9a3231 drm/i915/cnl: Introduce Cannonlake platform defition.
21bf60c drm/i915/cnp: Panel Power sequence changes for CNP PCH.
3270f68 drm/i915/cnp: add CNP gmbus support
d2a3b99 drm/i915/cnp: Add Backlight support to CNP PCH.
3f611350b drm/i915/cnp: Get/set proper Raw clock frequency on CNP.
1d21ab6 drm/i915/cnp: Add PCI ID for Cannonpoint LP PCH
631938c drm/i915/cnp: Introduce Cannonpoint PCH.

== Logs ==

For more details see: https://intel-gfx-ci.01.org/CI/Patchwork_4434/
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Re: [PATCH 01/67] drm/i915/cnp: Introduce Cannonpoint PCH.

[Srivatsa, Anusha]

>-----Original Message-----
>From: Intel-gfx [mailto:intel-gfx-bounces@lists.freedesktop.org] On Behalf Of
>Rodrigo Vivi
>Sent: Thursday, April 6, 2017 12:15 PM
>To: intel-gfx@lists.freedesktop.org
>Cc: Vivi, Rodrigo <rodrigo.vivi@intel.com>
>Subject: [Intel-gfx] [PATCH 01/67] drm/i915/cnp: Introduce Cannonpoint PCH.
>
>Most of south engine display that is in PCH is still the same as SPT and KBP, except
>for this key differences:
>
>- Backlight: Backlight programming changed in CNP PCH.
>- Panel Power: Sligh programming changed in CNP PCH.
>- GMBUS and GPIO: The pin mapping has changed in CNP PCH.
>
>All of these changes follow more the BXT style.
>
>v2: Update definition to use dev_priv isntead of dev (Tvrtko).
>
>Cc: Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com>
>Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>

Reviewed-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
> drivers/gpu/drm/i915/i915_drv.c | 3 +++  drivers/gpu/drm/i915/i915_drv.h | 3
>+++  drivers/gpu/drm/i915/i915_irq.c | 6 ++++--
> 3 files changed, 10 insertions(+), 2 deletions(-)
>
>diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
>index bd85e38..05e3f3f 100644
>--- a/drivers/gpu/drm/i915/i915_drv.c
>+++ b/drivers/gpu/drm/i915/i915_drv.c
>@@ -216,6 +216,9 @@ static void intel_detect_pch(struct drm_i915_private
>*dev_priv)
> 				DRM_DEBUG_KMS("Found KabyPoint PCH\n");
> 				WARN_ON(!IS_SKYLAKE(dev_priv) &&
> 					!IS_KABYLAKE(dev_priv));
>+			} else if (id == INTEL_PCH_CNP_DEVICE_ID_TYPE) {
>+				dev_priv->pch_type = PCH_CNP;
>+				DRM_DEBUG_KMS("Found CannonPoint
>PCH\n");
> 			} else if ((id == INTEL_PCH_P2X_DEVICE_ID_TYPE) ||
> 				   (id == INTEL_PCH_P3X_DEVICE_ID_TYPE) ||
> 				   ((id == INTEL_PCH_QEMU_DEVICE_ID_TYPE)
>&& diff --git a/drivers/gpu/drm/i915/i915_drv.h
>b/drivers/gpu/drm/i915/i915_drv.h index c9b0949..d798976 100644
>--- a/drivers/gpu/drm/i915/i915_drv.h
>+++ b/drivers/gpu/drm/i915/i915_drv.h
>@@ -1209,6 +1209,7 @@ enum intel_pch {
> 	PCH_LPT,	/* Lynxpoint PCH */
> 	PCH_SPT,        /* Sunrisepoint PCH */
> 	PCH_KBP,        /* Kabypoint PCH */
>+	PCH_CNP,        /* Cannonpoint PCH */
> 	PCH_NOP,
> };
>
>@@ -2948,11 +2949,13 @@ static inline struct scatterlist *__sg_next(struct
>scatterlist *sg)
> #define INTEL_PCH_SPT_DEVICE_ID_TYPE		0xA100
> #define INTEL_PCH_SPT_LP_DEVICE_ID_TYPE		0x9D00
> #define INTEL_PCH_KBP_DEVICE_ID_TYPE		0xA200
>+#define INTEL_PCH_CNP_DEVICE_ID_TYPE		0xA300
> #define INTEL_PCH_P2X_DEVICE_ID_TYPE		0x7100
> #define INTEL_PCH_P3X_DEVICE_ID_TYPE		0x7000
> #define INTEL_PCH_QEMU_DEVICE_ID_TYPE		0x2900 /* qemu q35
>has 2918 */
>
> #define INTEL_PCH_TYPE(dev_priv) ((dev_priv)->pch_type)
>+#define HAS_PCH_CNP(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_CNP)
> #define HAS_PCH_KBP(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_KBP)
>#define HAS_PCH_SPT(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_SPT)
>#define HAS_PCH_LPT(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_LPT) diff --
>git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c index
>d9d1969..698eb76 100644
>--- a/drivers/gpu/drm/i915/i915_irq.c
>+++ b/drivers/gpu/drm/i915/i915_irq.c
>@@ -2582,7 +2582,8 @@ static void bxt_hpd_irq_handler(struct
>drm_i915_private *dev_priv,
> 			I915_WRITE(SDEIIR, iir);
> 			ret = IRQ_HANDLED;
>
>-			if (HAS_PCH_SPT(dev_priv) || HAS_PCH_KBP(dev_priv))
>+			if (HAS_PCH_SPT(dev_priv) || HAS_PCH_KBP(dev_priv) ||
>+			    HAS_PCH_CNP(dev_priv))
> 				spt_irq_handler(dev_priv, iir);
> 			else
> 				cpt_irq_handler(dev_priv, iir);
>@@ -4322,7 +4323,8 @@ void intel_irq_init(struct drm_i915_private *dev_priv)
> 		dev->driver->disable_vblank = gen8_disable_vblank;
> 		if (IS_GEN9_LP(dev_priv))
> 			dev_priv->display.hpd_irq_setup = bxt_hpd_irq_setup;
>-		else if (HAS_PCH_SPT(dev_priv) || HAS_PCH_KBP(dev_priv))
>+		else if (HAS_PCH_SPT(dev_priv) || HAS_PCH_KBP(dev_priv) ||
>+			 HAS_PCH_CNP(dev_priv))
> 			dev_priv->display.hpd_irq_setup = spt_hpd_irq_setup;
> 		else
> 			dev_priv->display.hpd_irq_setup = ilk_hpd_irq_setup;
>--
>1.9.1
>
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