* [PATCH 01/15] drm/i915: really simple gemfs
2017-05-31 18:51 [PATCH 00/15] huge gtt pages Matthew Auld
@ 2017-05-31 18:51 ` Matthew Auld
2017-05-31 19:16 ` Chris Wilson
2017-06-01 10:49 ` Joonas Lahtinen
2017-05-31 18:51 ` [PATCH 02/15] drm/i915: enable THP for gemfs Matthew Auld
` (14 subsequent siblings)
15 siblings, 2 replies; 30+ messages in thread
From: Matthew Auld @ 2017-05-31 18:51 UTC (permalink / raw)
To: intel-gfx
Not a fully blown gemfs, just our very own tmpfs kernel mount. Doing so
moves us away from the shmemfs shm_mnt, and gives us the much needed
flexibility to do things like set our own mount options, namely huge=
which should allow us to enable the use of transparent-huge-pages for
our shmem backed objects.
Signed-off-by: Matthew Auld <matthew.auld@intel.com>
Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
---
drivers/gpu/drm/i915/Makefile | 1 +
drivers/gpu/drm/i915/i915_drv.h | 13 +++
drivers/gpu/drm/i915/i915_gem.c | 30 ++++++-
drivers/gpu/drm/i915/i915_gemfs.c | 105 +++++++++++++++++++++++
drivers/gpu/drm/i915/selftests/mock_gem_device.c | 12 ++-
5 files changed, 159 insertions(+), 2 deletions(-)
create mode 100644 drivers/gpu/drm/i915/i915_gemfs.c
diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index 16dccf550412..1a70af7d51ec 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -46,6 +46,7 @@ i915-y += i915_cmd_parser.o \
i915_gem_tiling.o \
i915_gem_timeline.o \
i915_gem_userptr.o \
+ i915_gemfs.o \
i915_trace_points.o \
i915_vma.o \
intel_breadcrumbs.o \
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index d2a57493ac2e..ca3196e2566f 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -2227,6 +2227,9 @@ struct drm_i915_private {
DECLARE_HASHTABLE(mm_structs, 7);
struct mutex mm_lock;
+ /* Our tmpfs instance used for shmem backed objects */
+ struct vfsmount *gemfs_mnt;
+
/* The hw wants to have a stable context identifier for the lifetime
* of the context (for OA, PASID, faults, etc). This is limited
* in execlists to 21 bits.
@@ -4169,4 +4172,14 @@ static inline bool i915_gem_object_is_coherent(struct drm_i915_gem_object *obj)
HAS_LLC(to_i915(obj->base.dev)));
}
+/* i915_gemfs.c */
+struct vfsmount *i915_gemfs_create(void);
+
+void i915_gemfs_destroy(struct vfsmount *gemfs_mnt);
+
+struct file *i915_gemfs_file_setup(struct vfsmount *gemfs_mnt,
+ const char *name, size_t size);
+
+int i915_gemfs_unlink(struct file *filp);
+
#endif
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index 7ab47a84671f..30f9af590969 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -4245,6 +4245,24 @@ static const struct drm_i915_gem_object_ops i915_gem_object_ops = {
.pwrite = i915_gem_object_pwrite_gtt,
};
+static int i915_drm_gem_object_init(struct drm_device *dev,
+ struct drm_gem_object *obj,
+ size_t size)
+{
+ struct drm_i915_private *i915 = to_i915(dev);
+ struct file *filp;
+
+ drm_gem_private_object_init(dev, obj, size);
+
+ filp = i915_gemfs_file_setup(i915->gemfs_mnt, "i915 mm object", size);
+ if (IS_ERR(filp))
+ return PTR_ERR(filp);
+
+ obj->filp = filp;
+
+ return 0;
+}
+
struct drm_i915_gem_object *
i915_gem_object_create(struct drm_i915_private *dev_priv, u64 size)
{
@@ -4268,7 +4286,7 @@ i915_gem_object_create(struct drm_i915_private *dev_priv, u64 size)
if (obj == NULL)
return ERR_PTR(-ENOMEM);
- ret = drm_gem_object_init(&dev_priv->drm, &obj->base, size);
+ ret = i915_drm_gem_object_init(&dev_priv->drm, &obj->base, size);
if (ret)
goto fail;
@@ -4383,6 +4401,9 @@ static void __i915_gem_free_objects(struct drm_i915_private *i915,
drm_prime_gem_destroy(&obj->base, NULL);
reservation_object_fini(&obj->__builtin_resv);
+
+ if (obj->base.filp)
+ i915_gemfs_unlink(obj->base.filp);
drm_gem_object_release(&obj->base);
i915_gem_info_remove_obj(i915, obj->base.size);
@@ -4843,6 +4864,10 @@ i915_gem_load_init(struct drm_i915_private *dev_priv)
{
int err = -ENOMEM;
+ dev_priv->gemfs_mnt = i915_gemfs_create();
+ if (IS_ERR(dev_priv->gemfs_mnt))
+ return PTR_ERR(dev_priv->gemfs_mnt);
+
dev_priv->objects = KMEM_CACHE(drm_i915_gem_object, SLAB_HWCACHE_ALIGN);
if (!dev_priv->objects)
goto err_out;
@@ -4908,6 +4933,7 @@ i915_gem_load_init(struct drm_i915_private *dev_priv)
err_objects:
kmem_cache_destroy(dev_priv->objects);
err_out:
+ i915_gemfs_destroy(dev_priv->gemfs_mnt);
return err;
}
@@ -4930,6 +4956,8 @@ void i915_gem_load_cleanup(struct drm_i915_private *dev_priv)
/* And ensure that our DESTROY_BY_RCU slabs are truly destroyed */
rcu_barrier();
+
+ i915_gemfs_destroy(dev_priv->gemfs_mnt);
}
int i915_gem_freeze(struct drm_i915_private *dev_priv)
diff --git a/drivers/gpu/drm/i915/i915_gemfs.c b/drivers/gpu/drm/i915/i915_gemfs.c
new file mode 100644
index 000000000000..e1b2af1d9946
--- /dev/null
+++ b/drivers/gpu/drm/i915/i915_gemfs.c
@@ -0,0 +1,105 @@
+/*
+ * Copyright © 2017 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
+ *
+ */
+
+#include <linux/fs.h>
+#include <linux/file.h>
+#include <linux/mount.h>
+
+static const struct dentry_operations anon_ops = {
+ .d_dname = simple_dname
+};
+
+struct vfsmount *i915_gemfs_create(void)
+{
+ struct file_system_type *type;
+ struct vfsmount *gemfs_mnt;
+
+ type = get_fs_type("tmpfs");
+ if (!type)
+ return ERR_PTR(-EINVAL);
+
+ gemfs_mnt = kern_mount(type);
+
+ return gemfs_mnt;
+}
+
+void i915_gemfs_destroy(struct vfsmount *gemfs_mnt)
+{
+ kern_unmount(gemfs_mnt);
+}
+
+struct file *i915_gemfs_file_setup(struct vfsmount *gemfs_mnt,
+ const char *name, size_t size)
+{
+ struct super_block *sb = gemfs_mnt->mnt_sb;
+ struct inode *dir = d_inode(sb->s_root);
+ struct inode *inode;
+ struct path path;
+ struct qstr this;
+ struct file *res;
+ int ret;
+
+ if (size < 0 || size > MAX_LFS_FILESIZE)
+ return ERR_PTR(-EINVAL);
+
+ this.name = name;
+ this.len = strlen(name);
+ this.hash = 0;
+
+ path.mnt = mntget(gemfs_mnt);
+ path.dentry = d_alloc_pseudo(sb, &this);
+ if (!path.dentry) {
+ res = ERR_PTR(-ENOMEM);
+ goto put_path;
+ }
+ d_set_d_op(path.dentry, &anon_ops);
+
+ ret = dir->i_op->create(dir, path.dentry, S_IFREG | S_IRWXUGO, false);
+ if (ret) {
+ res = ERR_PTR(ret);
+ goto put_path;
+ }
+
+ inode = d_inode(path.dentry);
+ inode->i_size = size;
+
+ res = alloc_file(&path, FMODE_WRITE | FMODE_READ, inode->i_fop);
+ if (IS_ERR(res))
+ goto unlink;
+
+ return res;
+
+unlink:
+ dir->i_op->unlink(dir, path.dentry);
+put_path:
+ path_put(&path);
+ return res;
+}
+
+int i915_gemfs_unlink(struct file *filp)
+{
+ struct inode *dir = d_inode(filp->f_inode->i_sb->s_root);
+
+ return dir->i_op->unlink(dir, filp->f_path.dentry);
+}
diff --git a/drivers/gpu/drm/i915/selftests/mock_gem_device.c b/drivers/gpu/drm/i915/selftests/mock_gem_device.c
index 627e2aa09766..7f038ea15ef5 100644
--- a/drivers/gpu/drm/i915/selftests/mock_gem_device.c
+++ b/drivers/gpu/drm/i915/selftests/mock_gem_device.c
@@ -80,6 +80,8 @@ static void mock_device_release(struct drm_device *dev)
kmem_cache_destroy(i915->vmas);
kmem_cache_destroy(i915->objects);
+ i915_gemfs_destroy(i915->gemfs_mnt);
+
drm_dev_fini(&i915->drm);
put_device(&i915->drm.pdev->dev);
}
@@ -167,9 +169,15 @@ struct drm_i915_private *mock_gem_device(void)
i915->gt.awake = true;
+ i915->gemfs_mnt = i915_gemfs_create();
+ if (IS_ERR(i915->gemfs_mnt)) {
+ err = PTR_ERR(i915->gemfs_mnt);
+ goto err_wq;
+ }
+
i915->objects = KMEM_CACHE(mock_object, SLAB_HWCACHE_ALIGN);
if (!i915->objects)
- goto err_wq;
+ goto err_gemfs;
i915->vmas = KMEM_CACHE(i915_vma, SLAB_HWCACHE_ALIGN);
if (!i915->vmas)
@@ -227,6 +235,8 @@ struct drm_i915_private *mock_gem_device(void)
kmem_cache_destroy(i915->vmas);
err_objects:
kmem_cache_destroy(i915->objects);
+err_gemfs:
+ i915_gemfs_destroy(i915->gemfs_mnt);
err_wq:
destroy_workqueue(i915->wq);
put_device:
--
2.9.4
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^ permalink raw reply related [flat|nested] 30+ messages in thread* Re: [PATCH 01/15] drm/i915: really simple gemfs
2017-05-31 18:51 ` [PATCH 01/15] drm/i915: really simple gemfs Matthew Auld
@ 2017-05-31 19:16 ` Chris Wilson
2017-06-01 10:49 ` Joonas Lahtinen
1 sibling, 0 replies; 30+ messages in thread
From: Chris Wilson @ 2017-05-31 19:16 UTC (permalink / raw)
To: Matthew Auld; +Cc: intel-gfx
On Wed, May 31, 2017 at 07:51:56PM +0100, Matthew Auld wrote:
> Not a fully blown gemfs, just our very own tmpfs kernel mount. Doing so
> moves us away from the shmemfs shm_mnt, and gives us the much needed
> flexibility to do things like set our own mount options, namely huge=
> which should allow us to enable the use of transparent-huge-pages for
> our shmem backed objects.
After we get the kinks worked out, this should be in drm_gem.c With a
default mountpoint, it should present the same interface to the existing
users. But we will not be the only ones who will custom mount options.
Even for ttm who may only use shmemfs for swap, with the advent of fast
swapping for huge pages that will be win (if any improvement to swap
hell can be a win!).
Just food for thought, not the actual review.
-Chris
--
Chris Wilson, Intel Open Source Technology Centre
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 30+ messages in thread
* Re: [PATCH 01/15] drm/i915: really simple gemfs
2017-05-31 18:51 ` [PATCH 01/15] drm/i915: really simple gemfs Matthew Auld
2017-05-31 19:16 ` Chris Wilson
@ 2017-06-01 10:49 ` Joonas Lahtinen
2017-06-01 12:33 ` Matthew Auld
1 sibling, 1 reply; 30+ messages in thread
From: Joonas Lahtinen @ 2017-06-01 10:49 UTC (permalink / raw)
To: Matthew Auld, intel-gfx
On ke, 2017-05-31 at 19:51 +0100, Matthew Auld wrote:
> Not a fully blown gemfs, just our very own tmpfs kernel mount. Doing so
> moves us away from the shmemfs shm_mnt, and gives us the much needed
> flexibility to do things like set our own mount options, namely huge=
> which should allow us to enable the use of transparent-huge-pages for
> our shmem backed objects.
>
> Signed-off-by: Matthew Auld <matthew.auld@intel.com>
> Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
> Cc: Chris Wilson <chris@chris-wilson.co.uk>
<SNIP>
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -2227,6 +2227,9 @@ struct drm_i915_private {
> DECLARE_HASHTABLE(mm_structs, 7);
> struct mutex mm_lock;
>
> + /* Our tmpfs instance used for shmem backed objects */
> + struct vfsmount *gemfs_mnt;
"gemfs" might be good enough, should not cause any confusion?
> @@ -4169,4 +4172,14 @@ static inline bool i915_gem_object_is_coherent(struct drm_i915_gem_object *obj)
> HAS_LLC(to_i915(obj->base.dev)));
> }
>
> +/* i915_gemfs.c */
i915_gemfs.h please. Lets not bloat i915_drv.h more when effort is in
place to strip it down.
> +struct vfsmount *i915_gemfs_create(void);
Not "int gemfs_init(struct drm_i915_privat *i915)" and _fini?
I doubt we should be creating more of these.
> @@ -4268,7 +4286,7 @@ i915_gem_object_create(struct drm_i915_private *dev_priv, u64 size)
> if (obj == NULL)
> return ERR_PTR(-ENOMEM);
>
> - ret = drm_gem_object_init(&dev_priv->drm, &obj->base, size);
> + ret = i915_drm_gem_object_init(&dev_priv->drm, &obj->base, size);
> if (ret)
> goto fail;
As Chris mentioned, smells bit like we could be targeting DRM scope in
the future.
> @@ -4383,6 +4401,9 @@ static void __i915_gem_free_objects(struct drm_i915_private *i915,
> drm_prime_gem_destroy(&obj->base, NULL);
>
> reservation_object_fini(&obj->__builtin_resv);
> +
For code below, do drop a note here that we want to do part of
drm_gem_object_release's work in advance. Or rather than commenting,
make it explicitly clear by having i915_gem_object_release() with this
hunk of code.
> + if (obj->base.filp)
> + i915_gemfs_unlink(obj->base.filp);
> drm_gem_object_release(&obj->base);
> i915_gem_info_remove_obj(i915, obj->base.size);
>
> @@ -4843,6 +4864,10 @@ i915_gem_load_init(struct drm_i915_private *dev_priv)
> {
> int err = -ENOMEM;
>
> + dev_priv->gemfs_mnt = i915_gemfs_create();
> + if (IS_ERR(dev_priv->gemfs_mnt))
> + return PTR_ERR(dev_priv->gemfs_mnt);
err = i915_gemfs_init(dev_priv);
if (err)
return err;
> +
> dev_priv->objects = KMEM_CACHE(drm_i915_gem_object, SLAB_HWCACHE_ALIGN);
> if (!dev_priv->objects)
err = -ENOMEM;
goto err_gemfs;
> @@ -4930,6 +4956,8 @@ void i915_gem_load_cleanup(struct drm_i915_private *dev_priv)
>
> /* And ensure that our DESTROY_BY_RCU slabs are truly destroyed */
> rcu_barrier();
> +
> + i915_gemfs_destroy(dev_priv->gemfs_mnt);
i915_gemfs_fini();
> +struct file *i915_gemfs_file_setup(struct vfsmount *gemfs_mnt,
> + const char *name, size_t size)
> +{
<SNIP>
> +
> + inode = d_inode(path.dentry);
> + inode->i_size = size;
> +
> + res = alloc_file(&path, FMODE_WRITE | FMODE_READ, inode->i_fop);
shmem is passing their own fops, we don't need to? shmem_mmap seems to
have some transparent huge page code at least which would be missed,
no?
> + if (IS_ERR(res))
> + goto unlink;
> +
> + return res;
> +
> +unlink:
> + dir->i_op->unlink(dir, path.dentry);
> +put_path:
> + path_put(&path);
Might throw newline here.
Regards, Joonas
--
Joonas Lahtinen
Open Source Technology Center
Intel Corporation
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^ permalink raw reply [flat|nested] 30+ messages in thread* Re: [PATCH 01/15] drm/i915: really simple gemfs
2017-06-01 10:49 ` Joonas Lahtinen
@ 2017-06-01 12:33 ` Matthew Auld
0 siblings, 0 replies; 30+ messages in thread
From: Matthew Auld @ 2017-06-01 12:33 UTC (permalink / raw)
To: Joonas Lahtinen; +Cc: Intel Graphics Development, Matthew Auld
On 1 June 2017 at 11:49, Joonas Lahtinen
<joonas.lahtinen@linux.intel.com> wrote:
> On ke, 2017-05-31 at 19:51 +0100, Matthew Auld wrote:
>> Not a fully blown gemfs, just our very own tmpfs kernel mount. Doing so
>> moves us away from the shmemfs shm_mnt, and gives us the much needed
>> flexibility to do things like set our own mount options, namely huge=
>> which should allow us to enable the use of transparent-huge-pages for
>> our shmem backed objects.
>>
>> Signed-off-by: Matthew Auld <matthew.auld@intel.com>
>> Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
>> Cc: Chris Wilson <chris@chris-wilson.co.uk>
>
> <SNIP>
>
>> +++ b/drivers/gpu/drm/i915/i915_drv.h
>> @@ -2227,6 +2227,9 @@ struct drm_i915_private {
>> DECLARE_HASHTABLE(mm_structs, 7);
>> struct mutex mm_lock;
>>
>> + /* Our tmpfs instance used for shmem backed objects */
>> + struct vfsmount *gemfs_mnt;
>
> "gemfs" might be good enough, should not cause any confusion?
>
>> @@ -4169,4 +4172,14 @@ static inline bool i915_gem_object_is_coherent(struct drm_i915_gem_object *obj)
>> HAS_LLC(to_i915(obj->base.dev)));
>> }
>>
>> +/* i915_gemfs.c */
>
> i915_gemfs.h please. Lets not bloat i915_drv.h more when effort is in
> place to strip it down.
>
>> +struct vfsmount *i915_gemfs_create(void);
>
> Not "int gemfs_init(struct drm_i915_privat *i915)" and _fini?
>
> I doubt we should be creating more of these.
>
>> @@ -4268,7 +4286,7 @@ i915_gem_object_create(struct drm_i915_private *dev_priv, u64 size)
>> if (obj == NULL)
>> return ERR_PTR(-ENOMEM);
>>
>> - ret = drm_gem_object_init(&dev_priv->drm, &obj->base, size);
>> + ret = i915_drm_gem_object_init(&dev_priv->drm, &obj->base, size);
>> if (ret)
>> goto fail;
>
> As Chris mentioned, smells bit like we could be targeting DRM scope in
> the future.
>
>> @@ -4383,6 +4401,9 @@ static void __i915_gem_free_objects(struct drm_i915_private *i915,
>> drm_prime_gem_destroy(&obj->base, NULL);
>>
>> reservation_object_fini(&obj->__builtin_resv);
>> +
>
> For code below, do drop a note here that we want to do part of
> drm_gem_object_release's work in advance. Or rather than commenting,
> make it explicitly clear by having i915_gem_object_release() with this
> hunk of code.
>
>> + if (obj->base.filp)
>> + i915_gemfs_unlink(obj->base.filp);
>> drm_gem_object_release(&obj->base);
>> i915_gem_info_remove_obj(i915, obj->base.size);
>>
>> @@ -4843,6 +4864,10 @@ i915_gem_load_init(struct drm_i915_private *dev_priv)
>> {
>> int err = -ENOMEM;
>>
>> + dev_priv->gemfs_mnt = i915_gemfs_create();
>> + if (IS_ERR(dev_priv->gemfs_mnt))
>> + return PTR_ERR(dev_priv->gemfs_mnt);
>
> err = i915_gemfs_init(dev_priv);
> if (err)
> return err;
>
>> +
>> dev_priv->objects = KMEM_CACHE(drm_i915_gem_object, SLAB_HWCACHE_ALIGN);
>> if (!dev_priv->objects)
>
> err = -ENOMEM;
> goto err_gemfs;
>
>> @@ -4930,6 +4956,8 @@ void i915_gem_load_cleanup(struct drm_i915_private *dev_priv)
>>
>> /* And ensure that our DESTROY_BY_RCU slabs are truly destroyed */
>> rcu_barrier();
>> +
>> + i915_gemfs_destroy(dev_priv->gemfs_mnt);
>
> i915_gemfs_fini();
>
>> +struct file *i915_gemfs_file_setup(struct vfsmount *gemfs_mnt,
>> + const char *name, size_t size)
>> +{
>
> <SNIP>
>
>> +
>> + inode = d_inode(path.dentry);
>> + inode->i_size = size;
>> +
>> + res = alloc_file(&path, FMODE_WRITE | FMODE_READ, inode->i_fop);
>
> shmem is passing their own fops, we don't need to? shmem_mmap seems to
> have some transparent huge page code at least which would be missed,
> no?
We pass the same fops, since shmem_file_operations == inode->i_fop.
See shmem_get_inode.
I'll try to address the other comments, thanks.
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^ permalink raw reply [flat|nested] 30+ messages in thread
* [PATCH 02/15] drm/i915: enable THP for gemfs
2017-05-31 18:51 [PATCH 00/15] huge gtt pages Matthew Auld
2017-05-31 18:51 ` [PATCH 01/15] drm/i915: really simple gemfs Matthew Auld
@ 2017-05-31 18:51 ` Matthew Auld
2017-06-01 10:27 ` Joonas Lahtinen
2017-05-31 18:51 ` [PATCH 03/15] drm/i915: introduce page_size_mask to dev_info Matthew Auld
` (13 subsequent siblings)
15 siblings, 1 reply; 30+ messages in thread
From: Matthew Auld @ 2017-05-31 18:51 UTC (permalink / raw)
To: intel-gfx
Enable transparent-huge-pages through gemfs by mounting with
huge=within_size.
Signed-off-by: Matthew Auld <matthew.auld@intel.com>
Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
---
drivers/gpu/drm/i915/i915_gemfs.c | 23 +++++++++++++++++++++++
1 file changed, 23 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_gemfs.c b/drivers/gpu/drm/i915/i915_gemfs.c
index e1b2af1d9946..7b50ff97623e 100644
--- a/drivers/gpu/drm/i915/i915_gemfs.c
+++ b/drivers/gpu/drm/i915/i915_gemfs.c
@@ -25,6 +25,7 @@
#include <linux/fs.h>
#include <linux/file.h>
#include <linux/mount.h>
+#include <linux/pagemap.h>
static const struct dentry_operations anon_ops = {
.d_dname = simple_dname
@@ -41,6 +42,28 @@ struct vfsmount *i915_gemfs_create(void)
gemfs_mnt = kern_mount(type);
+#if defined(CONFIG_TRANSPARENT_HUGE_PAGECACHE)
+ if (!IS_ERR(gemfs_mnt) && has_transparent_hugepage()) {
+ struct super_block *sb = gemfs_mnt->mnt_sb;
+ char options[] = "huge=within_size";
+ int flags = 0;
+ int ret;
+
+ /* Idealy we would just pass the mount options when mounting,
+ * but for some reason shmem chooses not to parse the options
+ * for MS_KERNMOUNT, probably because shm_mnt is the only tmpfs
+ * kernel mount other than this, where the mount options aren't
+ * used. To workaround this we do a remount, which is fairly
+ * inexpensive, where we know the options are never igonored.
+ */
+ ret = sb->s_op->remount_fs(sb, &flags, options);
+ if (ret) {
+ kern_unmount(gemfs_mnt);
+ return ERR_PTR(ret);
+ }
+ }
+#endif
+
return gemfs_mnt;
}
--
2.9.4
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 30+ messages in thread* Re: [PATCH 02/15] drm/i915: enable THP for gemfs
2017-05-31 18:51 ` [PATCH 02/15] drm/i915: enable THP for gemfs Matthew Auld
@ 2017-06-01 10:27 ` Joonas Lahtinen
0 siblings, 0 replies; 30+ messages in thread
From: Joonas Lahtinen @ 2017-06-01 10:27 UTC (permalink / raw)
To: Matthew Auld, intel-gfx
On ke, 2017-05-31 at 19:51 +0100, Matthew Auld wrote:
> Enable transparent-huge-pages through gemfs by mounting with
> huge=within_size.
>
> Signed-off-by: Matthew Auld <matthew.auld@intel.com>
> Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
> Cc: Chris Wilson <chris@chris-wilson.co.uk>
<SNIP>
> @@ -41,6 +42,28 @@ struct vfsmount *i915_gemfs_create(void)
>
> gemfs_mnt = kern_mount(type);
>
> +#if defined(CONFIG_TRANSPARENT_HUGE_PAGECACHE)
> + if (!IS_ERR(gemfs_mnt) && has_transparent_hugepage()) {
> + struct super_block *sb = gemfs_mnt->mnt_sb;
> + char options[] = "huge=within_size";
> + int flags = 0;
> + int ret;
> +
> + /* Idealy we would just pass the mount options when mounting,
> + * but for some reason shmem chooses not to parse the options
> + * for MS_KERNMOUNT, probably because shm_mnt is the only tmpfs
> + * kernel mount other than this, where the mount options aren't
> + * used. To workaround this we do a remount, which is fairly
> + * inexpensive, where we know the options are never igonored.
> + */
> + ret = sb->s_op->remount_fs(sb, &flags, options);
This sounds like a bugfix to be sent.
Regards, Joonas
--
Joonas Lahtinen
Open Source Technology Center
Intel Corporation
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 30+ messages in thread
* [PATCH 03/15] drm/i915: introduce page_size_mask to dev_info
2017-05-31 18:51 [PATCH 00/15] huge gtt pages Matthew Auld
2017-05-31 18:51 ` [PATCH 01/15] drm/i915: really simple gemfs Matthew Auld
2017-05-31 18:51 ` [PATCH 02/15] drm/i915: enable THP for gemfs Matthew Auld
@ 2017-05-31 18:51 ` Matthew Auld
2017-05-31 19:19 ` Chris Wilson
2017-06-01 10:57 ` Joonas Lahtinen
2017-05-31 18:51 ` [PATCH 04/15] drm/i915: introduce gem object page_sizes Matthew Auld
` (12 subsequent siblings)
15 siblings, 2 replies; 30+ messages in thread
From: Matthew Auld @ 2017-05-31 18:51 UTC (permalink / raw)
To: intel-gfx
In preparation for huge gtt pages expose a page_size_mask as part of the
device info, to indicate the page sizes supported by the HW. Currently
only 4K is supported.
Signed-off-by: Matthew Auld <matthew.auld@intel.com>
Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
---
drivers/gpu/drm/i915/i915_drv.h | 1 +
drivers/gpu/drm/i915/i915_gem_gtt.h | 8 +++++++-
drivers/gpu/drm/i915/i915_pci.c | 21 +++++++++++++++++++++
drivers/gpu/drm/i915/selftests/mock_gem_device.c | 3 +++
4 files changed, 32 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index ca3196e2566f..8be48e5d8c1f 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -840,6 +840,7 @@ struct intel_device_info {
enum intel_platform platform;
u8 ring_mask; /* Rings supported by the HW */
u8 num_rings;
+ unsigned int page_size_mask; /* page sizes supported by the HW */
#define DEFINE_FLAG(name) u8 name:1
DEV_INFO_FOR_EACH_FLAG(DEFINE_FLAG);
#undef DEFINE_FLAG
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.h b/drivers/gpu/drm/i915/i915_gem_gtt.h
index fb15684c1d83..f8db231c28aa 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.h
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.h
@@ -42,7 +42,13 @@
#include "i915_gem_request.h"
#include "i915_selftest.h"
-#define I915_GTT_PAGE_SIZE 4096UL
+#define I915_GTT_PAGE_SIZE_4K BIT(12)
+#define I915_GTT_PAGE_SIZE_64K BIT(16)
+#define I915_GTT_PAGE_SIZE_2M BIT(21)
+#define I915_GTT_PAGE_SIZE_1G BIT(30)
+
+#define I915_GTT_PAGE_SIZE I915_GTT_PAGE_SIZE_4K
+
#define I915_GTT_MIN_ALIGNMENT I915_GTT_PAGE_SIZE
#define I915_FENCE_REG_NONE -1
diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index f80db2ccd92f..7caccb5bf963 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -56,6 +56,10 @@
.color = { .degamma_lut_size = 65, .gamma_lut_size = 257 }
/* Keep in gen based order, and chronological order within a gen */
+
+#define GEN_DEFAULT_PAGE_SIZES \
+ .page_size_mask = I915_GTT_PAGE_SIZE_4K
+
#define GEN2_FEATURES \
.gen = 2, .num_pipes = 1, \
.has_overlay = 1, .overlay_needs_physical = 1, \
@@ -64,6 +68,7 @@
.unfenced_needs_alignment = 1, \
.ring_mask = RENDER_RING, \
GEN_DEFAULT_PIPEOFFSETS, \
+ GEN_DEFAULT_PAGE_SIZES, \
CURSOR_OFFSETS
static const struct intel_device_info intel_i830_info = {
@@ -96,6 +101,7 @@ static const struct intel_device_info intel_i865g_info = {
.has_gmch_display = 1, \
.ring_mask = RENDER_RING, \
GEN_DEFAULT_PIPEOFFSETS, \
+ GEN_DEFAULT_PAGE_SIZES, \
CURSOR_OFFSETS
static const struct intel_device_info intel_i915g_info = {
@@ -158,6 +164,7 @@ static const struct intel_device_info intel_pineview_info = {
.has_gmch_display = 1, \
.ring_mask = RENDER_RING, \
GEN_DEFAULT_PIPEOFFSETS, \
+ GEN_DEFAULT_PAGE_SIZES, \
CURSOR_OFFSETS
static const struct intel_device_info intel_i965g_info = {
@@ -198,6 +205,7 @@ static const struct intel_device_info intel_gm45_info = {
.has_gmbus_irq = 1, \
.ring_mask = RENDER_RING | BSD_RING, \
GEN_DEFAULT_PIPEOFFSETS, \
+ GEN_DEFAULT_PAGE_SIZES, \
CURSOR_OFFSETS
static const struct intel_device_info intel_ironlake_d_info = {
@@ -222,6 +230,7 @@ static const struct intel_device_info intel_ironlake_m_info = {
.has_gmbus_irq = 1, \
.has_aliasing_ppgtt = 1, \
GEN_DEFAULT_PIPEOFFSETS, \
+ GEN_DEFAULT_PAGE_SIZES, \
CURSOR_OFFSETS
static const struct intel_device_info intel_sandybridge_d_info = {
@@ -247,6 +256,7 @@ static const struct intel_device_info intel_sandybridge_m_info = {
.has_aliasing_ppgtt = 1, \
.has_full_ppgtt = 1, \
GEN_DEFAULT_PIPEOFFSETS, \
+ GEN_DEFAULT_PAGE_SIZES, \
IVB_CURSOR_OFFSETS
static const struct intel_device_info intel_ivybridge_d_info = {
@@ -284,6 +294,7 @@ static const struct intel_device_info intel_valleyview_info = {
.has_full_ppgtt = 1,
.ring_mask = RENDER_RING | BSD_RING | BLT_RING,
.display_mmio_offset = VLV_DISPLAY_BASE,
+ GEN_DEFAULT_PAGE_SIZES,
GEN_DEFAULT_PIPEOFFSETS,
CURSOR_OFFSETS
};
@@ -308,6 +319,7 @@ static const struct intel_device_info intel_haswell_info = {
#define BDW_FEATURES \
HSW_FEATURES, \
BDW_COLORS, \
+ GEN_DEFAULT_PAGE_SIZES, \
.has_logical_ring_contexts = 1, \
.has_full_48bit_ppgtt = 1, \
.has_64bit_reloc = 1
@@ -342,13 +354,18 @@ static const struct intel_device_info intel_cherryview_info = {
.has_aliasing_ppgtt = 1,
.has_full_ppgtt = 1,
.display_mmio_offset = VLV_DISPLAY_BASE,
+ GEN_DEFAULT_PAGE_SIZES,
GEN_CHV_PIPEOFFSETS,
CURSOR_OFFSETS,
CHV_COLORS,
};
+#define GEN9_DEFAULT_PAGE_SIZES \
+ .page_size_mask = I915_GTT_PAGE_SIZE_4K
+
static const struct intel_device_info intel_skylake_info = {
BDW_FEATURES,
+ GEN_DEFAULT_PAGE_SIZES,
.platform = INTEL_SKYLAKE,
.gen = 9,
.has_csr = 1,
@@ -358,6 +375,7 @@ static const struct intel_device_info intel_skylake_info = {
static const struct intel_device_info intel_skylake_gt3_info = {
BDW_FEATURES,
+ GEN9_DEFAULT_PAGE_SIZES,
.platform = INTEL_SKYLAKE,
.gen = 9,
.has_csr = 1,
@@ -389,6 +407,7 @@ static const struct intel_device_info intel_skylake_gt3_info = {
.has_aliasing_ppgtt = 1, \
.has_full_ppgtt = 1, \
.has_full_48bit_ppgtt = 1, \
+ GEN9_DEFAULT_PAGE_SIZES, \
GEN_DEFAULT_PIPEOFFSETS, \
IVB_CURSOR_OFFSETS, \
BDW_COLORS
@@ -409,6 +428,7 @@ static const struct intel_device_info intel_geminilake_info = {
static const struct intel_device_info intel_kabylake_info = {
BDW_FEATURES,
+ GEN9_DEFAULT_PAGE_SIZES,
.platform = INTEL_KABYLAKE,
.gen = 9,
.has_csr = 1,
@@ -418,6 +438,7 @@ static const struct intel_device_info intel_kabylake_info = {
static const struct intel_device_info intel_kabylake_gt3_info = {
BDW_FEATURES,
+ GEN9_DEFAULT_PAGE_SIZES,
.platform = INTEL_KABYLAKE,
.gen = 9,
.has_csr = 1,
diff --git a/drivers/gpu/drm/i915/selftests/mock_gem_device.c b/drivers/gpu/drm/i915/selftests/mock_gem_device.c
index 7f038ea15ef5..bb12e6fe24ec 100644
--- a/drivers/gpu/drm/i915/selftests/mock_gem_device.c
+++ b/drivers/gpu/drm/i915/selftests/mock_gem_device.c
@@ -147,6 +147,9 @@ struct drm_i915_private *mock_gem_device(void)
mkwrite_device_info(i915)->gen = -1;
+ mkwrite_device_info(i915)->page_size_mask =
+ I915_GTT_PAGE_SIZE_4K;
+
spin_lock_init(&i915->mm.object_stat_lock);
mock_uncore_init(i915);
--
2.9.4
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 30+ messages in thread* Re: [PATCH 03/15] drm/i915: introduce page_size_mask to dev_info
2017-05-31 18:51 ` [PATCH 03/15] drm/i915: introduce page_size_mask to dev_info Matthew Auld
@ 2017-05-31 19:19 ` Chris Wilson
2017-06-01 10:57 ` Joonas Lahtinen
1 sibling, 0 replies; 30+ messages in thread
From: Chris Wilson @ 2017-05-31 19:19 UTC (permalink / raw)
To: Matthew Auld; +Cc: intel-gfx
On Wed, May 31, 2017 at 07:51:58PM +0100, Matthew Auld wrote:
> diff --git a/drivers/gpu/drm/i915/selftests/mock_gem_device.c b/drivers/gpu/drm/i915/selftests/mock_gem_device.c
> index 7f038ea15ef5..bb12e6fe24ec 100644
> --- a/drivers/gpu/drm/i915/selftests/mock_gem_device.c
> +++ b/drivers/gpu/drm/i915/selftests/mock_gem_device.c
> @@ -147,6 +147,9 @@ struct drm_i915_private *mock_gem_device(void)
>
> mkwrite_device_info(i915)->gen = -1;
>
> + mkwrite_device_info(i915)->page_size_mask =
> + I915_GTT_PAGE_SIZE_4K;
> +
The next person to add mock device_info details will be moving these to
a function. You have been warned.
-Chris
--
Chris Wilson, Intel Open Source Technology Centre
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 30+ messages in thread
* Re: [PATCH 03/15] drm/i915: introduce page_size_mask to dev_info
2017-05-31 18:51 ` [PATCH 03/15] drm/i915: introduce page_size_mask to dev_info Matthew Auld
2017-05-31 19:19 ` Chris Wilson
@ 2017-06-01 10:57 ` Joonas Lahtinen
2017-06-01 12:10 ` Jani Nikula
1 sibling, 1 reply; 30+ messages in thread
From: Joonas Lahtinen @ 2017-06-01 10:57 UTC (permalink / raw)
To: Matthew Auld, intel-gfx; +Cc: Jani Nikula
On ke, 2017-05-31 at 19:51 +0100, Matthew Auld wrote:
> In preparation for huge gtt pages expose a page_size_mask as part of the
> device info, to indicate the page sizes supported by the HW. Currently
> only 4K is supported.
>
> Signed-off-by: Matthew Auld <matthew.auld@intel.com>
> Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
> Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>
> Cc: Chris Wilson <chris@chris-wilson.co.uk>
<SNIP>
I don't quite get why there can't be more inheritance when declaring
these (Jani CC'd), but not related to this patch.
> /* Keep in gen based order, and chronological order within a gen */
> +
> +#define GEN_DEFAULT_PAGE_SIZES \
> + .page_size_mask = I915_GTT_PAGE_SIZE_4K
> +
> #define GEN2_FEATURES \
> .gen = 2, .num_pipes = 1, \
> .has_overlay = 1, .overlay_needs_physical = 1, \
> @@ -64,6 +68,7 @@
> .unfenced_needs_alignment = 1, \
> .ring_mask = RENDER_RING, \
> GEN_DEFAULT_PIPEOFFSETS, \
> + GEN_DEFAULT_PAGE_SIZES, \
> CURSOR_OFFSETS
>
> static const struct intel_device_info intel_i830_info = {
> @@ -96,6 +101,7 @@ static const struct intel_device_info intel_i865g_info = {
> .has_gmch_display = 1, \
> .ring_mask = RENDER_RING, \
> GEN_DEFAULT_PIPEOFFSETS, \
> + GEN_DEFAULT_PAGE_SIZES, \
> CURSOR_OFFSETS
>
> static const struct intel_device_info intel_i915g_info = {
> @@ -158,6 +164,7 @@ static const struct intel_device_info intel_pineview_info = {
> .has_gmch_display = 1, \
> .ring_mask = RENDER_RING, \
> GEN_DEFAULT_PIPEOFFSETS, \
> + GEN_DEFAULT_PAGE_SIZES, \
> CURSOR_OFFSETS
And goes on... Seems repetitive.
Reviewed-by: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Regards, Joonas
--
Joonas Lahtinen
Open Source Technology Center
Intel Corporation
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 30+ messages in thread* Re: [PATCH 03/15] drm/i915: introduce page_size_mask to dev_info
2017-06-01 10:57 ` Joonas Lahtinen
@ 2017-06-01 12:10 ` Jani Nikula
0 siblings, 0 replies; 30+ messages in thread
From: Jani Nikula @ 2017-06-01 12:10 UTC (permalink / raw)
To: Joonas Lahtinen, Matthew Auld, intel-gfx
On Thu, 01 Jun 2017, Joonas Lahtinen <joonas.lahtinen@linux.intel.com> wrote:
> On ke, 2017-05-31 at 19:51 +0100, Matthew Auld wrote:
>> In preparation for huge gtt pages expose a page_size_mask as part of the
>> device info, to indicate the page sizes supported by the HW. Currently
>> only 4K is supported.
>>
>> Signed-off-by: Matthew Auld <matthew.auld@intel.com>
>> Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
>> Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>
>> Cc: Chris Wilson <chris@chris-wilson.co.uk>
>
> <SNIP>
>
> I don't quite get why there can't be more inheritance when declaring
> these (Jani CC'd), but not related to this patch.
Yeah, could use more inheritance, but can also be follow-up. *shrug*
BR,
Jani.
>
>> /* Keep in gen based order, and chronological order within a gen */
>> +
>> +#define GEN_DEFAULT_PAGE_SIZES \
>> + .page_size_mask = I915_GTT_PAGE_SIZE_4K
>> +
>> #define GEN2_FEATURES \
>> .gen = 2, .num_pipes = 1, \
>> .has_overlay = 1, .overlay_needs_physical = 1, \
>> @@ -64,6 +68,7 @@
>> .unfenced_needs_alignment = 1, \
>> .ring_mask = RENDER_RING, \
>> GEN_DEFAULT_PIPEOFFSETS, \
>> + GEN_DEFAULT_PAGE_SIZES, \
>> CURSOR_OFFSETS
>>
>> static const struct intel_device_info intel_i830_info = {
>> @@ -96,6 +101,7 @@ static const struct intel_device_info intel_i865g_info = {
>> .has_gmch_display = 1, \
>> .ring_mask = RENDER_RING, \
>> GEN_DEFAULT_PIPEOFFSETS, \
>> + GEN_DEFAULT_PAGE_SIZES, \
>> CURSOR_OFFSETS
>>
>> static const struct intel_device_info intel_i915g_info = {
>> @@ -158,6 +164,7 @@ static const struct intel_device_info intel_pineview_info = {
>> .has_gmch_display = 1, \
>> .ring_mask = RENDER_RING, \
>> GEN_DEFAULT_PIPEOFFSETS, \
>> + GEN_DEFAULT_PAGE_SIZES, \
>> CURSOR_OFFSETS
>
> And goes on... Seems repetitive.
>
> Reviewed-by: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
>
> Regards, Joonas
--
Jani Nikula, Intel Open Source Technology Center
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 30+ messages in thread
* [PATCH 04/15] drm/i915: introduce gem object page_sizes
2017-05-31 18:51 [PATCH 00/15] huge gtt pages Matthew Auld
` (2 preceding siblings ...)
2017-05-31 18:51 ` [PATCH 03/15] drm/i915: introduce page_size_mask to dev_info Matthew Auld
@ 2017-05-31 18:51 ` Matthew Auld
2017-05-31 19:25 ` Chris Wilson
2017-06-01 9:49 ` Chris Wilson
2017-05-31 18:52 ` [PATCH 05/15] drm/i915: align the vma start to the largest gtt page size Matthew Auld
` (11 subsequent siblings)
15 siblings, 2 replies; 30+ messages in thread
From: Matthew Auld @ 2017-05-31 18:51 UTC (permalink / raw)
To: intel-gfx
We need to track the possible page sizes given the layout of the sg
table, in preparation for supporting huge gtt pages. Note that this does
in any way represent the real gtt page size usage.
Signed-off-by: Matthew Auld <matthew.auld@intel.com>
Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Daniel Vetter <daniel@ffwll.ch>
---
drivers/gpu/drm/i915/i915_drv.h | 2 ++
drivers/gpu/drm/i915/i915_gem.c | 38 +++++++++++++++++++++++++++++++++-
drivers/gpu/drm/i915/i915_gem_object.h | 5 +++++
3 files changed, 44 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 8be48e5d8c1f..e6d1e1df4454 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -2896,6 +2896,8 @@ intel_info(const struct drm_i915_private *dev_priv)
#define USES_PPGTT(dev_priv) (i915.enable_ppgtt)
#define USES_FULL_PPGTT(dev_priv) (i915.enable_ppgtt >= 2)
#define USES_FULL_48BIT_PPGTT(dev_priv) (i915.enable_ppgtt == 3)
+#define HAS_PAGE_SIZE(dev_priv, page_size) \
+ ((dev_priv)->info.page_size_mask & (page_size))
#define HAS_OVERLAY(dev_priv) ((dev_priv)->info.has_overlay)
#define OVERLAY_NEEDS_PHYSICAL(dev_priv) \
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index 30f9af590969..e8ebf39448a5 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -2294,6 +2294,8 @@ void __i915_gem_object_put_pages(struct drm_i915_gem_object *obj,
if (!IS_ERR(pages))
obj->ops->put_pages(obj, pages);
+ obj->mm.page_sizes.phys = obj->mm.page_sizes.sg = 0;
+
unlock:
mutex_unlock(&obj->mm.lock);
}
@@ -2473,6 +2475,7 @@ i915_gem_object_get_pages_gtt(struct drm_i915_gem_object *obj)
void __i915_gem_object_set_pages(struct drm_i915_gem_object *obj,
struct sg_table *pages)
{
+
lockdep_assert_held(&obj->mm.lock);
obj->mm.get_page.sg_pos = pages->sgl;
@@ -2516,6 +2519,13 @@ static int ____i915_gem_object_get_pages(struct drm_i915_gem_object *obj)
*/
int __i915_gem_object_get_pages(struct drm_i915_gem_object *obj)
{
+ struct drm_i915_private *i915 = to_i915(obj->base.dev);
+ unsigned long supported_page_sizes = INTEL_INFO(i915)->page_size_mask;
+ struct scatterlist *sg;
+ unsigned int sg_mask = 0;
+ unsigned int i;
+ unsigned int bit;
+ unsigned int max_page_size;
int err;
err = mutex_lock_interruptible(&obj->mm.lock);
@@ -2533,7 +2543,33 @@ int __i915_gem_object_get_pages(struct drm_i915_gem_object *obj)
unlock:
mutex_unlock(&obj->mm.lock);
- return err;
+
+ if (err)
+ return err;
+
+ for_each_sg(obj->mm.pages->sgl, sg, obj->mm.pages->nents, i)
+ sg_mask |= sg->length;
+
+ GEM_BUG_ON(!sg_mask);
+
+ obj->mm.page_sizes.phys = sg_mask;
+
+ obj->mm.page_sizes.sg = 0;
+
+ for_each_set_bit(bit, &supported_page_sizes, BITS_PER_LONG) {
+ if (obj->mm.page_sizes.phys & ~0u << bit)
+ obj->mm.page_sizes.sg |= BIT(bit);
+ }
+
+ max_page_size = BIT(fls64(obj->mm.page_sizes.sg)-1);
+
+ /* If were are actually dealing with a single page-size, mark it so */
+ if (IS_ALIGNED(obj->mm.page_sizes.phys, max_page_size))
+ obj->mm.page_sizes.sg = max_page_size;
+
+ GEM_BUG_ON(!HAS_PAGE_SIZE(i915, obj->mm.page_sizes.sg));
+
+ return 0;
}
/* The 'mapping' part of i915_gem_object_pin_map() below */
diff --git a/drivers/gpu/drm/i915/i915_gem_object.h b/drivers/gpu/drm/i915/i915_gem_object.h
index 35e1a27729dc..6db34eac9794 100644
--- a/drivers/gpu/drm/i915/i915_gem_object.h
+++ b/drivers/gpu/drm/i915/i915_gem_object.h
@@ -129,6 +129,11 @@ struct drm_i915_gem_object {
struct sg_table *pages;
void *mapping;
+ struct i915_page_sizes {
+ unsigned int phys;
+ unsigned int sg;
+ } page_sizes;
+
struct i915_gem_object_page_iter {
struct scatterlist *sg_pos;
unsigned int sg_idx; /* in pages, but 32bit eek! */
--
2.9.4
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 30+ messages in thread* Re: [PATCH 04/15] drm/i915: introduce gem object page_sizes
2017-05-31 18:51 ` [PATCH 04/15] drm/i915: introduce gem object page_sizes Matthew Auld
@ 2017-05-31 19:25 ` Chris Wilson
2017-06-01 9:49 ` Chris Wilson
1 sibling, 0 replies; 30+ messages in thread
From: Chris Wilson @ 2017-05-31 19:25 UTC (permalink / raw)
To: Matthew Auld; +Cc: intel-gfx
On Wed, May 31, 2017 at 07:51:59PM +0100, Matthew Auld wrote:
> err = mutex_lock_interruptible(&obj->mm.lock);
> @@ -2533,7 +2543,33 @@ int __i915_gem_object_get_pages(struct drm_i915_gem_object *obj)
>
> unlock:
> mutex_unlock(&obj->mm.lock);
> - return err;
> +
> + if (err)
> + return err;
> +
> + for_each_sg(obj->mm.pages->sgl, sg, obj->mm.pages->nents, i)
> + sg_mask |= sg->length;
This is the worst place to put a loop over sg. Not only is this
synchronous, but pages may not have been allocated yet. Using
set_pages was at least correct in that regard! The interface I will keep
nagging for is for each task to compute sg_mask as they populate the
scatterlist, and then they pass sg_mask to
__i915_gem_object_set_pages() alongside the pages.
Since this didn't fail BAT, that only means we do not have any userptr
tests there...
-Chris
--
Chris Wilson, Intel Open Source Technology Centre
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 30+ messages in thread
* Re: [PATCH 04/15] drm/i915: introduce gem object page_sizes
2017-05-31 18:51 ` [PATCH 04/15] drm/i915: introduce gem object page_sizes Matthew Auld
2017-05-31 19:25 ` Chris Wilson
@ 2017-06-01 9:49 ` Chris Wilson
1 sibling, 0 replies; 30+ messages in thread
From: Chris Wilson @ 2017-06-01 9:49 UTC (permalink / raw)
To: Matthew Auld; +Cc: intel-gfx
On Wed, May 31, 2017 at 07:51:59PM +0100, Matthew Auld wrote:
> + max_page_size = BIT(fls64(obj->mm.page_sizes.sg)-1);
> +
> + /* If were are actually dealing with a single page-size, mark it so */
> + if (IS_ALIGNED(obj->mm.page_sizes.phys, max_page_size))
> + obj->mm.page_sizes.sg = max_page_size;
Pardon?
If the physical page sizes is a multiple of the max sg->length (rounded
to GTT page sizes), only use the max?
page_sizes.sg will already express the smallest unit that can be used to
for the whole object (as well as the largest one that may be used
opportunistically).
The current kselftests that mix sg chunk sizes are ignorant of the large
pages sizes, it would be useful to add some that did mix huge pages.
-Chris
--
Chris Wilson, Intel Open Source Technology Centre
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 30+ messages in thread
* [PATCH 05/15] drm/i915: align the vma start to the largest gtt page size
2017-05-31 18:51 [PATCH 00/15] huge gtt pages Matthew Auld
` (3 preceding siblings ...)
2017-05-31 18:51 ` [PATCH 04/15] drm/i915: introduce gem object page_sizes Matthew Auld
@ 2017-05-31 18:52 ` Matthew Auld
2017-05-31 19:31 ` Chris Wilson
2017-05-31 18:52 ` [PATCH 06/15] drm/i915: align 64K objects to 2M Matthew Auld
` (10 subsequent siblings)
15 siblings, 1 reply; 30+ messages in thread
From: Matthew Auld @ 2017-05-31 18:52 UTC (permalink / raw)
To: intel-gfx
When inserting into a 48bit PPGTT we should the align the vma start
address to the required page size boundary, to guarantee we use said
page size in the gtt. If we are dealing with multiple page-sizes, we
can't guarantee anything and just align to the largest. For soft pinning
we don't force any alignment.
Signed-off-by: Matthew Auld <matthew.auld@intel.com>
Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
---
drivers/gpu/drm/i915/i915_vma.c | 12 ++++++++++++
1 file changed, 12 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_vma.c b/drivers/gpu/drm/i915/i915_vma.c
index 1aba47024656..c355ccb01872 100644
--- a/drivers/gpu/drm/i915/i915_vma.c
+++ b/drivers/gpu/drm/i915/i915_vma.c
@@ -485,6 +485,18 @@ i915_vma_insert(struct i915_vma *vma, u64 size, u64 alignment, u64 flags)
if (ret)
goto err_unpin;
} else {
+ if (i915_vm_is_48bit(vma->vm) &&
+ obj->mm.page_sizes.sg > I915_GTT_PAGE_SIZE) {
+ unsigned int page_alignment = obj->mm.page_sizes.sg;
+
+ /* Align to the largest and hope for the best */
+ if (!is_power_of_2(page_alignment))
+ page_alignment = BIT(fls64(page_alignment)-1);
+
+ alignment = max_t(typeof(alignment), alignment,
+ page_alignment);
+ }
+
ret = i915_gem_gtt_insert(vma->vm, &vma->node,
size, alignment, obj->cache_level,
start, end, flags);
--
2.9.4
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 30+ messages in thread* Re: [PATCH 05/15] drm/i915: align the vma start to the largest gtt page size
2017-05-31 18:52 ` [PATCH 05/15] drm/i915: align the vma start to the largest gtt page size Matthew Auld
@ 2017-05-31 19:31 ` Chris Wilson
0 siblings, 0 replies; 30+ messages in thread
From: Chris Wilson @ 2017-05-31 19:31 UTC (permalink / raw)
To: Matthew Auld; +Cc: intel-gfx
On Wed, May 31, 2017 at 07:52:00PM +0100, Matthew Auld wrote:
> When inserting into a 48bit PPGTT we should the align the vma start
> address to the required page size boundary, to guarantee we use said
> page size in the gtt. If we are dealing with multiple page-sizes, we
> can't guarantee anything and just align to the largest. For soft pinning
> we don't force any alignment.
>
> Signed-off-by: Matthew Auld <matthew.auld@intel.com>
> Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
> Cc: Chris Wilson <chris@chris-wilson.co.uk>
> ---
> drivers/gpu/drm/i915/i915_vma.c | 12 ++++++++++++
> 1 file changed, 12 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/i915_vma.c b/drivers/gpu/drm/i915/i915_vma.c
> index 1aba47024656..c355ccb01872 100644
> --- a/drivers/gpu/drm/i915/i915_vma.c
> +++ b/drivers/gpu/drm/i915/i915_vma.c
> @@ -485,6 +485,18 @@ i915_vma_insert(struct i915_vma *vma, u64 size, u64 alignment, u64 flags)
> if (ret)
> goto err_unpin;
> } else {
> + if (i915_vm_is_48bit(vma->vm) &&
I would use end > 4G here. As that encapsulates the i915_vm_is_48bit()
test and avoids us applying the extra padding to objects that must be
tightly packed into the low 32bits.
> + obj->mm.page_sizes.sg > I915_GTT_PAGE_SIZE) {
> + unsigned int page_alignment = obj->mm.page_sizes.sg;
> +
> + /* Align to the largest and hope for the best */
> + if (!is_power_of_2(page_alignment))
> + page_alignment = BIT(fls64(page_alignment)-1);
fls64() - 1 == ilog2()
BIT(ilog2()) == roundup_pow_of_two()
linux/log2.h is your friend.
> +
> + alignment = max_t(typeof(alignment), alignment,
> + page_alignment);
Make page_alignment be u64 and be happy.
-Chris
--
Chris Wilson, Intel Open Source Technology Centre
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 30+ messages in thread
* [PATCH 06/15] drm/i915: align 64K objects to 2M
2017-05-31 18:51 [PATCH 00/15] huge gtt pages Matthew Auld
` (4 preceding siblings ...)
2017-05-31 18:52 ` [PATCH 05/15] drm/i915: align the vma start to the largest gtt page size Matthew Auld
@ 2017-05-31 18:52 ` Matthew Auld
2017-06-01 9:55 ` Chris Wilson
2017-05-31 18:52 ` [PATCH 07/15] drm/i915: pass mm.gtt_page_sizes to ppgtt insert_entries Matthew Auld
` (9 subsequent siblings)
15 siblings, 1 reply; 30+ messages in thread
From: Matthew Auld @ 2017-05-31 18:52 UTC (permalink / raw)
To: intel-gfx
We can't mix 64K and 4K pte's in the same page-table, so for now we
align 64K objects to 2M to avoid any potential mixing. This is
potentially wasteful but in reality shouldn't be too bad since this only
applies to the virtual address space of a 48b PPGTT.
Suggested-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Matthew Auld <matthew.auld@intel.com>
Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
---
drivers/gpu/drm/i915/i915_vma.c | 18 ++++++++++++++++++
1 file changed, 18 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_vma.c b/drivers/gpu/drm/i915/i915_vma.c
index c355ccb01872..af950d92fa13 100644
--- a/drivers/gpu/drm/i915/i915_vma.c
+++ b/drivers/gpu/drm/i915/i915_vma.c
@@ -479,6 +479,15 @@ i915_vma_insert(struct i915_vma *vma, u64 size, u64 alignment, u64 flags)
goto err_unpin;
}
+ /* A current limitation in our implementation is that 64K
+ * objects must be aligned to 2M, and given that we can't
+ * enforce this for soft pinning, we need to fallback to normal
+ * pages if don't meet this restriction.
+ */
+ if (obj->mm.page_sizes.sg == I915_GTT_PAGE_SIZE_64K &&
+ !IS_ALIGNED(offset | size, I915_GTT_PAGE_SIZE_2M))
+ obj->mm.page_sizes.sg = I915_GTT_PAGE_SIZE;
+
ret = i915_gem_gtt_reserve(vma->vm, &vma->node,
size, offset, obj->cache_level,
flags);
@@ -493,6 +502,15 @@ i915_vma_insert(struct i915_vma *vma, u64 size, u64 alignment, u64 flags)
if (!is_power_of_2(page_alignment))
page_alignment = BIT(fls64(page_alignment)-1);
+ /* We can't mix 64K and 4K pte's in the same page-table (2M
+ * block), and so to avoid the ugliness and complexity of
+ * coloring we opt for just aligning 64K objects to 2M.
+ */
+ if (obj->mm.page_sizes.sg == I915_GTT_PAGE_SIZE_64K) {
+ page_alignment = I915_GTT_PAGE_SIZE_2M;
+ size = roundup(size, page_alignment);
+ }
+
alignment = max_t(typeof(alignment), alignment,
page_alignment);
}
--
2.9.4
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 30+ messages in thread* Re: [PATCH 06/15] drm/i915: align 64K objects to 2M
2017-05-31 18:52 ` [PATCH 06/15] drm/i915: align 64K objects to 2M Matthew Auld
@ 2017-06-01 9:55 ` Chris Wilson
0 siblings, 0 replies; 30+ messages in thread
From: Chris Wilson @ 2017-06-01 9:55 UTC (permalink / raw)
To: Matthew Auld; +Cc: intel-gfx
On Wed, May 31, 2017 at 07:52:01PM +0100, Matthew Auld wrote:
> We can't mix 64K and 4K pte's in the same page-table, so for now we
> align 64K objects to 2M to avoid any potential mixing. This is
> potentially wasteful but in reality shouldn't be too bad since this only
> applies to the virtual address space of a 48b PPGTT.
>
> Suggested-by: Chris Wilson <chris@chris-wilson.co.uk>
> Signed-off-by: Matthew Auld <matthew.auld@intel.com>
> Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
> ---
> drivers/gpu/drm/i915/i915_vma.c | 18 ++++++++++++++++++
> 1 file changed, 18 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/i915_vma.c b/drivers/gpu/drm/i915/i915_vma.c
> index c355ccb01872..af950d92fa13 100644
> --- a/drivers/gpu/drm/i915/i915_vma.c
> +++ b/drivers/gpu/drm/i915/i915_vma.c
> @@ -479,6 +479,15 @@ i915_vma_insert(struct i915_vma *vma, u64 size, u64 alignment, u64 flags)
> goto err_unpin;
> }
>
> + /* A current limitation in our implementation is that 64K
> + * objects must be aligned to 2M, and given that we can't
> + * enforce this for soft pinning, we need to fallback to normal
> + * pages if don't meet this restriction.
> + */
> + if (obj->mm.page_sizes.sg == I915_GTT_PAGE_SIZE_64K &&
page_sizes.sg > I915_GTT_PAGE_SIZE_4K.
> + !IS_ALIGNED(offset | size, I915_GTT_PAGE_SIZE_2M))
Abusing the semantics of PAGE_SIZE_2M. It just happens to be the value
you want, but it doesn't mean what you say.
> + obj->mm.page_sizes.sg = I915_GTT_PAGE_SIZE;
> +
> ret = i915_gem_gtt_reserve(vma->vm, &vma->node,
> size, offset, obj->cache_level,
> flags);
> @@ -493,6 +502,15 @@ i915_vma_insert(struct i915_vma *vma, u64 size, u64 alignment, u64 flags)
> if (!is_power_of_2(page_alignment))
> page_alignment = BIT(fls64(page_alignment)-1);
>
> + /* We can't mix 64K and 4K pte's in the same page-table (2M
> + * block), and so to avoid the ugliness and complexity of
> + * coloring we opt for just aligning 64K objects to 2M.
> + */
> + if (obj->mm.page_sizes.sg == I915_GTT_PAGE_SIZE_64K) {
page_sizes.sg & SIZE_64K or page_sizes.sg > SIZE_4K
Also refer to earlier discussion that this should be vma->page_sizes
here not obj.
> + page_alignment = I915_GTT_PAGE_SIZE_2M;
> + size = roundup(size, page_alignment);
round_up.
> + }
> +
> alignment = max_t(typeof(alignment), alignment,
> page_alignment);
> }
> --
> 2.9.4
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Chris Wilson, Intel Open Source Technology Centre
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 30+ messages in thread
* [PATCH 07/15] drm/i915: pass mm.gtt_page_sizes to ppgtt insert_entries
2017-05-31 18:51 [PATCH 00/15] huge gtt pages Matthew Auld
` (5 preceding siblings ...)
2017-05-31 18:52 ` [PATCH 06/15] drm/i915: align 64K objects to 2M Matthew Auld
@ 2017-05-31 18:52 ` Matthew Auld
2017-05-31 19:10 ` Chris Wilson
2017-05-31 18:52 ` [PATCH 08/15] drm/i915: enable IPS bit for 64K pages Matthew Auld
` (8 subsequent siblings)
15 siblings, 1 reply; 30+ messages in thread
From: Matthew Auld @ 2017-05-31 18:52 UTC (permalink / raw)
To: intel-gfx
In preparation for supporting huge-pages for the ppgtt, we need to know
the details of mm.page_sizes at insertion time, such that we can we can
easily determine the page sizes we are allowed to use. This is
especially true for 64K where we can't just arbitrarily use it, since we
require aligning/padding the vm space to 2M, which sometimes we can't
enforce.
Signed-off-by: Matthew Auld <matthew.auld@intel.com>
Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
---
drivers/gpu/drm/i915/i915_gem_gtt.c | 24 ++++++++++++++++--------
drivers/gpu/drm/i915/i915_gem_gtt.h | 3 +++
drivers/gpu/drm/i915/selftests/i915_gem_gtt.c | 3 ++-
drivers/gpu/drm/i915/selftests/mock_gtt.c | 1 +
4 files changed, 22 insertions(+), 9 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c
index 0c1008a2bbda..935656802f09 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -208,7 +208,8 @@ static int ppgtt_bind_vma(struct i915_vma *vma,
pte_flags |= PTE_READ_ONLY;
vma->vm->insert_entries(vma->vm, vma->pages, vma->node.start,
- cache_level, pte_flags);
+ &vma->obj->mm.page_sizes, cache_level,
+ pte_flags);
return 0;
}
@@ -909,6 +910,7 @@ gen8_ppgtt_insert_pte_entries(struct i915_hw_ppgtt *ppgtt,
static void gen8_ppgtt_insert_3lvl(struct i915_address_space *vm,
struct sg_table *pages,
u64 start,
+ struct i915_page_sizes *page_sizes,
enum i915_cache_level cache_level,
u32 unused)
{
@@ -927,6 +929,7 @@ static void gen8_ppgtt_insert_3lvl(struct i915_address_space *vm,
static void gen8_ppgtt_insert_4lvl(struct i915_address_space *vm,
struct sg_table *pages,
u64 start,
+ struct i915_page_sizes *page_sizes,
enum i915_cache_level cache_level,
u32 unused)
{
@@ -1623,6 +1626,7 @@ static void gen6_ppgtt_clear_range(struct i915_address_space *vm,
static void gen6_ppgtt_insert_entries(struct i915_address_space *vm,
struct sg_table *pages,
u64 start,
+ struct i915_page_sizes *page_sizes,
enum i915_cache_level cache_level,
u32 flags)
{
@@ -2092,6 +2096,7 @@ static void gen8_ggtt_insert_page(struct i915_address_space *vm,
static void gen8_ggtt_insert_entries(struct i915_address_space *vm,
struct sg_table *st,
u64 start,
+ struct i915_page_sizes *page_sizes,
enum i915_cache_level level,
u32 unused)
{
@@ -2139,6 +2144,7 @@ static void gen6_ggtt_insert_page(struct i915_address_space *vm,
static void gen6_ggtt_insert_entries(struct i915_address_space *vm,
struct sg_table *st,
u64 start,
+ struct i915_page_sizes *page_sizes,
enum i915_cache_level level,
u32 flags)
{
@@ -2238,7 +2244,7 @@ static int bxt_vtd_ggtt_insert_entries__cb(void *_arg)
{
struct insert_entries *arg = _arg;
- gen8_ggtt_insert_entries(arg->vm, arg->st, arg->start, arg->level, 0);
+ gen8_ggtt_insert_entries(arg->vm, arg->st, arg->start, 0, arg->level, 0);
bxt_vtd_ggtt_wa(arg->vm);
return 0;
@@ -2247,6 +2253,7 @@ static int bxt_vtd_ggtt_insert_entries__cb(void *_arg)
static void bxt_vtd_ggtt_insert_entries__BKL(struct i915_address_space *vm,
struct sg_table *st,
u64 start,
+ struct i915_page_sizes *page_sizes,
enum i915_cache_level level,
u32 unused)
{
@@ -2318,6 +2325,7 @@ static void i915_ggtt_insert_page(struct i915_address_space *vm,
static void i915_ggtt_insert_entries(struct i915_address_space *vm,
struct sg_table *pages,
u64 start,
+ struct i915_page_sizes *page_sizes,
enum i915_cache_level cache_level,
u32 unused)
{
@@ -2353,7 +2361,7 @@ static int ggtt_bind_vma(struct i915_vma *vma,
pte_flags |= PTE_READ_ONLY;
intel_runtime_pm_get(i915);
- vma->vm->insert_entries(vma->vm, vma->pages, vma->node.start,
+ vma->vm->insert_entries(vma->vm, vma->pages, vma->node.start, 0,
cache_level, pte_flags);
intel_runtime_pm_put(i915);
@@ -2407,16 +2415,16 @@ static int aliasing_gtt_bind_vma(struct i915_vma *vma,
goto err_pages;
}
- appgtt->base.insert_entries(&appgtt->base,
- vma->pages, vma->node.start,
+ appgtt->base.insert_entries(&appgtt->base, vma->pages,
+ vma->node.start,
+ &vma->obj->mm.page_sizes,
cache_level, pte_flags);
}
if (flags & I915_VMA_GLOBAL_BIND) {
intel_runtime_pm_get(i915);
- vma->vm->insert_entries(vma->vm,
- vma->pages, vma->node.start,
- cache_level, pte_flags);
+ vma->vm->insert_entries(vma->vm, vma->pages, vma->node.start,
+ 0, cache_level, pte_flags);
intel_runtime_pm_put(i915);
}
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.h b/drivers/gpu/drm/i915/i915_gem_gtt.h
index f8db231c28aa..d45729b9da0c 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.h
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.h
@@ -206,6 +206,8 @@ enum i915_cache_level;
struct i915_vma;
+struct i915_page_sizes;
+
struct i915_page_dma {
struct page *page;
union {
@@ -320,6 +322,7 @@ struct i915_address_space {
void (*insert_entries)(struct i915_address_space *vm,
struct sg_table *st,
u64 start,
+ struct i915_page_sizes *page_sizes,
enum i915_cache_level cache_level,
u32 flags);
void (*cleanup)(struct i915_address_space *vm);
diff --git a/drivers/gpu/drm/i915/selftests/i915_gem_gtt.c b/drivers/gpu/drm/i915/selftests/i915_gem_gtt.c
index 50710e3f1caa..81c0d6b87e68 100644
--- a/drivers/gpu/drm/i915/selftests/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/selftests/i915_gem_gtt.c
@@ -256,7 +256,8 @@ static int lowlevel_hole(struct drm_i915_private *i915,
break;
vm->insert_entries(vm, obj->mm.pages, addr,
- I915_CACHE_NONE, 0);
+ &obj->mm.page_sizes, I915_CACHE_NONE,
+ 0);
}
count = n;
diff --git a/drivers/gpu/drm/i915/selftests/mock_gtt.c b/drivers/gpu/drm/i915/selftests/mock_gtt.c
index a61309c7cb3e..4d594eaf0b53 100644
--- a/drivers/gpu/drm/i915/selftests/mock_gtt.c
+++ b/drivers/gpu/drm/i915/selftests/mock_gtt.c
@@ -35,6 +35,7 @@ static void mock_insert_page(struct i915_address_space *vm,
static void mock_insert_entries(struct i915_address_space *vm,
struct sg_table *st,
u64 start,
+ struct i915_page_sizes *page_sizes,
enum i915_cache_level level, u32 flags)
{
}
--
2.9.4
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^ permalink raw reply related [flat|nested] 30+ messages in thread* Re: [PATCH 07/15] drm/i915: pass mm.gtt_page_sizes to ppgtt insert_entries
2017-05-31 18:52 ` [PATCH 07/15] drm/i915: pass mm.gtt_page_sizes to ppgtt insert_entries Matthew Auld
@ 2017-05-31 19:10 ` Chris Wilson
0 siblings, 0 replies; 30+ messages in thread
From: Chris Wilson @ 2017-05-31 19:10 UTC (permalink / raw)
To: Matthew Auld; +Cc: intel-gfx
On Wed, May 31, 2017 at 07:52:02PM +0100, Matthew Auld wrote:
> In preparation for supporting huge-pages for the ppgtt, we need to know
> the details of mm.page_sizes at insertion time, such that we can we can
> easily determine the page sizes we are allowed to use. This is
> especially true for 64K where we can't just arbitrarily use it, since we
> require aligning/padding the vm space to 2M, which sometimes we can't
> enforce.
I haven't considered the implications yet, but this information should
be available on the vma. In principle, the intent here is to more or less
do vma->vm->insert_entries(vma, flags); Just wondering how practical it
will be to get the relevant bits into the vma. Looks doable at first
glance, and it prevent the issue of having multiple vma cloberring the
obj->mm.page_sizes.gtt.
-Chris
--
Chris Wilson, Intel Open Source Technology Centre
_______________________________________________
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^ permalink raw reply [flat|nested] 30+ messages in thread
* [PATCH 08/15] drm/i915: enable IPS bit for 64K pages
2017-05-31 18:51 [PATCH 00/15] huge gtt pages Matthew Auld
` (6 preceding siblings ...)
2017-05-31 18:52 ` [PATCH 07/15] drm/i915: pass mm.gtt_page_sizes to ppgtt insert_entries Matthew Auld
@ 2017-05-31 18:52 ` Matthew Auld
2017-05-31 18:52 ` [PATCH 09/15] drm/i915: disable GTT cache for 2M/1G pages Matthew Auld
` (7 subsequent siblings)
15 siblings, 0 replies; 30+ messages in thread
From: Matthew Auld @ 2017-05-31 18:52 UTC (permalink / raw)
To: intel-gfx
Before we can enable 64K pages through the IPS bit, we must first enable
it through MMIO, otherwise the page-walker will simply ignore it.
Signed-off-by: Matthew Auld <matthew.auld@intel.com>
Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
---
drivers/gpu/drm/i915/i915_gem.c | 11 +++++++++++
drivers/gpu/drm/i915/i915_reg.h | 3 +++
2 files changed, 14 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index e8ebf39448a5..d53e091e8b11 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -4738,6 +4738,17 @@ int i915_gem_init_hw(struct drm_i915_private *dev_priv)
}
}
+ /* To support 64K PTE's we need to first enable the use of the
+ * Intermediate-Page-Size(IPS) bit of the PDE field via some magical
+ * mmio, otherwise the page-walker will simply ignore the IPS bit. This
+ * shouldn't be needed after GEN10.
+ */
+ if (HAS_PAGE_SIZE(dev_priv, I915_GTT_PAGE_SIZE_64K) &&
+ INTEL_GEN(dev_priv) <= 10)
+ I915_WRITE(GEN8_GAMW_ECO_DEV_RW_IA,
+ I915_READ(GEN8_GAMW_ECO_DEV_RW_IA) |
+ GAMW_ECO_ENABLE_64K_IPS_FIELD);
+
i915_gem_init_swizzling(dev_priv);
/*
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 89888adb9af1..9b967101b9b2 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -1993,6 +1993,9 @@ enum skl_disp_power_wells {
#define GEN9_GAMT_ECO_REG_RW_IA _MMIO(0x4ab0)
#define GAMT_ECO_ENABLE_IN_PLACE_DECOMPRESS (1<<18)
+#define GEN8_GAMW_ECO_DEV_RW_IA _MMIO(0x4080)
+#define GAMW_ECO_ENABLE_64K_IPS_FIELD 0xF
+
#define GAMT_CHKN_BIT_REG _MMIO(0x4ab8)
#define GAMT_CHKN_DISABLE_DYNAMIC_CREDIT_SHARING (1<<28)
--
2.9.4
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^ permalink raw reply related [flat|nested] 30+ messages in thread* [PATCH 09/15] drm/i915: disable GTT cache for 2M/1G pages
2017-05-31 18:51 [PATCH 00/15] huge gtt pages Matthew Auld
` (7 preceding siblings ...)
2017-05-31 18:52 ` [PATCH 08/15] drm/i915: enable IPS bit for 64K pages Matthew Auld
@ 2017-05-31 18:52 ` Matthew Auld
2017-06-01 9:56 ` Chris Wilson
2017-05-31 18:52 ` [PATCH 10/15] drm/i915: support huge gtt pages for the 48b PPGTT Matthew Auld
` (6 subsequent siblings)
15 siblings, 1 reply; 30+ messages in thread
From: Matthew Auld @ 2017-05-31 18:52 UTC (permalink / raw)
To: intel-gfx
When SW enables the use of 2M/1G pages, it must disable the GTT cache.
Signed-off-by: Matthew Auld <matthew.auld@intel.com>
Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
---
drivers/gpu/drm/i915/intel_pm.c | 12 ++++++------
1 file changed, 6 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 936eef1634c7..496b64f65eb2 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -8195,10 +8195,10 @@ static void broadwell_init_clock_gating(struct drm_i915_private *dev_priv)
/*
* WaGttCachingOffByDefault:bdw
- * GTT cache may not work with big pages, so if those
- * are ever enabled GTT cache may need to be disabled.
+ * The GTT cache must be disabled if the system is planning to use
+ * 2M/1G pages.
*/
- I915_WRITE(HSW_GTT_CACHE_EN, GTT_CACHE_EN_ALL);
+ I915_WRITE(HSW_GTT_CACHE_EN, 0);
/* WaKVMNotificationOnConfigChange:bdw */
I915_WRITE(CHICKEN_PAR2_1, I915_READ(CHICKEN_PAR2_1)
@@ -8474,10 +8474,10 @@ static void cherryview_init_clock_gating(struct drm_i915_private *dev_priv)
gen8_set_l3sqc_credits(dev_priv, 38, 2);
/*
- * GTT cache may not work with big pages, so if those
- * are ever enabled GTT cache may need to be disabled.
+ * The GTT cache must be disabled if the system is planning to use
+ * 2M/1G pages.
*/
- I915_WRITE(HSW_GTT_CACHE_EN, GTT_CACHE_EN_ALL);
+ I915_WRITE(HSW_GTT_CACHE_EN, 0);
}
static void g4x_init_clock_gating(struct drm_i915_private *dev_priv)
--
2.9.4
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^ permalink raw reply related [flat|nested] 30+ messages in thread* Re: [PATCH 09/15] drm/i915: disable GTT cache for 2M/1G pages
2017-05-31 18:52 ` [PATCH 09/15] drm/i915: disable GTT cache for 2M/1G pages Matthew Auld
@ 2017-06-01 9:56 ` Chris Wilson
0 siblings, 0 replies; 30+ messages in thread
From: Chris Wilson @ 2017-06-01 9:56 UTC (permalink / raw)
To: Matthew Auld; +Cc: intel-gfx
On Wed, May 31, 2017 at 07:52:04PM +0100, Matthew Auld wrote:
> When SW enables the use of 2M/1G pages, it must disable the GTT cache.
>
> Signed-off-by: Matthew Auld <matthew.auld@intel.com>
> Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
> ---
> drivers/gpu/drm/i915/intel_pm.c | 12 ++++++------
> 1 file changed, 6 insertions(+), 6 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index 936eef1634c7..496b64f65eb2 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -8195,10 +8195,10 @@ static void broadwell_init_clock_gating(struct drm_i915_private *dev_priv)
>
> /*
> * WaGttCachingOffByDefault:bdw
> - * GTT cache may not work with big pages, so if those
> - * are ever enabled GTT cache may need to be disabled.
> + * The GTT cache must be disabled if the system is planning to use
> + * 2M/1G pages.
> */
> - I915_WRITE(HSW_GTT_CACHE_EN, GTT_CACHE_EN_ALL);
> + I915_WRITE(HSW_GTT_CACHE_EN, 0);
>
> /* WaKVMNotificationOnConfigChange:bdw */
> I915_WRITE(CHICKEN_PAR2_1, I915_READ(CHICKEN_PAR2_1)
> @@ -8474,10 +8474,10 @@ static void cherryview_init_clock_gating(struct drm_i915_private *dev_priv)
> gen8_set_l3sqc_credits(dev_priv, 38, 2);
>
> /*
> - * GTT cache may not work with big pages, so if those
> - * are ever enabled GTT cache may need to be disabled.
> + * The GTT cache must be disabled if the system is planning to use
> + * 2M/1G pages.
> */
Cherryview doesn't support 48bit ppgtt so isn't using huge pages.
-Chris
--
Chris Wilson, Intel Open Source Technology Centre
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^ permalink raw reply [flat|nested] 30+ messages in thread
* [PATCH 10/15] drm/i915: support huge gtt pages for the 48b PPGTT
2017-05-31 18:51 [PATCH 00/15] huge gtt pages Matthew Auld
` (8 preceding siblings ...)
2017-05-31 18:52 ` [PATCH 09/15] drm/i915: disable GTT cache for 2M/1G pages Matthew Auld
@ 2017-05-31 18:52 ` Matthew Auld
2017-05-31 18:52 ` [PATCH 11/15] drm/i915: accurate page size tracking for the ppgtt Matthew Auld
` (5 subsequent siblings)
15 siblings, 0 replies; 30+ messages in thread
From: Matthew Auld @ 2017-05-31 18:52 UTC (permalink / raw)
To: intel-gfx
Support inserting huge gtt pages into the 48b PPGTT, including
mixed-mode where we allow a mixture of gtt page sizes.
Signed-off-by: Matthew Auld <matthew.auld@intel.com>
Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Daniel Vetter <daniel@ffwll.ch>
---
drivers/gpu/drm/i915/i915_gem_gtt.c | 79 ++++++++++++++++++++++++++++++++++---
drivers/gpu/drm/i915/i915_gem_gtt.h | 5 +++
2 files changed, 79 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c
index 935656802f09..924aec4adf6d 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -934,17 +934,86 @@ static void gen8_ppgtt_insert_4lvl(struct i915_address_space *vm,
u32 unused)
{
struct i915_hw_ppgtt *ppgtt = i915_vm_to_ppgtt(vm);
+ struct gen8_insert_pte idx = gen8_insert_pte(start);
+ struct i915_page_directory_pointer **pdps = ppgtt->pml4.pdps;
+ struct i915_page_directory_pointer *pdp = pdps[idx.pml4e];
+ struct i915_page_directory *pd = pdp->page_directory[idx.pdpe];
+ struct i915_page_table *pt = pd->page_table[idx.pde];
+ gen8_pte_t *pdp_vaddr = kmap_atomic_px(pdp);
+ gen8_pte_t *pd_vaddr = kmap_atomic_px(pd);
+ gen8_pte_t *pt_vaddr = kmap_atomic_px(pt);
+ const gen8_pte_t pte_encode = gen8_pte_encode(0, cache_level);
struct sgt_dma iter = {
.sg = pages->sgl,
.dma = sg_dma_address(iter.sg),
.max = iter.dma + iter.sg->length,
};
- struct i915_page_directory_pointer **pdps = ppgtt->pml4.pdps;
- struct gen8_insert_pte idx = gen8_insert_pte(start);
- while (gen8_ppgtt_insert_pte_entries(ppgtt, pdps[idx.pml4e++], &iter,
- &idx, cache_level))
- GEM_BUG_ON(idx.pml4e >= GEN8_PML4ES_PER_PML4);
+ do {
+ unsigned int page_size;
+
+ pt_vaddr[idx.pte] = pte_encode | iter.dma;
+ page_size = I915_GTT_PAGE_SIZE;
+
+ if (!idx.pte && page_sizes->sg > I915_GTT_PAGE_SIZE) {
+ dma_addr_t remaining = iter.max - iter.dma;
+
+ if (unlikely(page_sizes->sg & I915_GTT_PAGE_SIZE_1G) &&
+ remaining >= I915_GTT_PAGE_SIZE_1G && !idx.pde) {
+ pdp_vaddr[idx.pdpe] = pte_encode | GEN8_PDPE_PS_1G | iter.dma;
+ page_size = I915_GTT_PAGE_SIZE_1G;
+ } else if (page_sizes->sg & I915_GTT_PAGE_SIZE_2M &&
+ remaining >= I915_GTT_PAGE_SIZE_2M) {
+ pd_vaddr[idx.pde] = pte_encode | GEN8_PDE_PS_2M | iter.dma;
+ page_size = I915_GTT_PAGE_SIZE_2M;
+ /* We don't support 64K in mixed mode for now */
+ } else if (page_sizes->sg == I915_GTT_PAGE_SIZE_64K) {
+ pd_vaddr[idx.pde] |= GEN8_PDE_IPS_64K;
+ }
+ }
+
+ start += page_size;
+ iter.dma += page_size;
+ if (iter.dma >= iter.max) {
+ iter.sg = __sg_next(iter.sg);
+ if (!iter.sg)
+ break;
+
+ iter.dma = sg_dma_address(iter.sg);
+ iter.max = iter.dma + iter.sg->length;
+ }
+
+ idx.pte = gen8_pte_index(start);
+ if (!idx.pte) {
+ idx.pde = gen8_pde_index(start);
+
+ if (!idx.pde) {
+ idx.pdpe = gen8_pdpe_index(start);
+
+ if (!idx.pdpe) {
+ GEM_BUG_ON(idx.pml4e >= GEN8_PML4ES_PER_PML4);
+ pdp = pdps[idx.pml4e++];
+
+ kunmap_atomic(pdp_vaddr);
+ pdp_vaddr = kmap_atomic_px(pdp);
+ }
+
+ pd = pdp->page_directory[idx.pdpe];
+
+ kunmap_atomic(pd_vaddr);
+ pd_vaddr = kmap_atomic_px(pd);
+ }
+
+ pt = pd->page_table[idx.pde];
+
+ kunmap_atomic(pt_vaddr);
+ pt_vaddr = kmap_atomic_px(pt);
+ }
+ } while (1);
+
+ kunmap_atomic(pt_vaddr);
+ kunmap_atomic(pd_vaddr);
+ kunmap_atomic(pdp_vaddr);
}
static void gen8_free_page_tables(struct i915_address_space *vm,
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.h b/drivers/gpu/drm/i915/i915_gem_gtt.h
index d45729b9da0c..0811859b3a55 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.h
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.h
@@ -149,6 +149,11 @@ typedef u64 gen8_ppgtt_pml4e_t;
#define GEN8_PPAT_ELLC_OVERRIDE (0<<2)
#define GEN8_PPAT(i, x) ((u64)(x) << ((i) * 8))
+#define GEN8_PDE_IPS_64K BIT(11)
+#define GEN8_PDE_PS_2M BIT(7)
+
+#define GEN8_PDPE_PS_1G BIT(7)
+
struct sg_table;
struct intel_rotation_info {
--
2.9.4
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^ permalink raw reply related [flat|nested] 30+ messages in thread* [PATCH 11/15] drm/i915: accurate page size tracking for the ppgtt
2017-05-31 18:51 [PATCH 00/15] huge gtt pages Matthew Auld
` (9 preceding siblings ...)
2017-05-31 18:52 ` [PATCH 10/15] drm/i915: support huge gtt pages for the 48b PPGTT Matthew Auld
@ 2017-05-31 18:52 ` Matthew Auld
2017-05-31 18:52 ` [PATCH 12/15] drm/i915/debugfs: include some gtt page size metrics Matthew Auld
` (4 subsequent siblings)
15 siblings, 0 replies; 30+ messages in thread
From: Matthew Auld @ 2017-05-31 18:52 UTC (permalink / raw)
To: intel-gfx
Now that we support multiple page sizes for the ppgtt, it would be
useful to track the real usage for debugging purposes.
Signed-off-by: Matthew Auld <matthew.auld@intel.com>
Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
---
drivers/gpu/drm/i915/i915_gem_gtt.c | 10 ++++++++++
drivers/gpu/drm/i915/i915_gem_object.h | 2 ++
drivers/gpu/drm/i915/selftests/i915_gem_gtt.c | 1 +
3 files changed, 13 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c
index 924aec4adf6d..84de1618594e 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -217,6 +217,8 @@ static int ppgtt_bind_vma(struct i915_vma *vma,
static void ppgtt_unbind_vma(struct i915_vma *vma)
{
vma->vm->clear_range(vma->vm, vma->node.start, vma->size);
+
+ vma->obj->mm.page_sizes.gtt = 0;
}
static gen8_pte_t gen8_pte_encode(dma_addr_t addr,
@@ -924,6 +926,8 @@ static void gen8_ppgtt_insert_3lvl(struct i915_address_space *vm,
gen8_ppgtt_insert_pte_entries(ppgtt, &ppgtt->pdp, &iter, &idx,
cache_level);
+
+ page_sizes->gtt = I915_GTT_PAGE_SIZE;
}
static void gen8_ppgtt_insert_4lvl(struct i915_address_space *vm,
@@ -972,6 +976,8 @@ static void gen8_ppgtt_insert_4lvl(struct i915_address_space *vm,
}
}
+ page_sizes->gtt |= page_size;
+
start += page_size;
iter.dma += page_size;
if (iter.dma >= iter.max) {
@@ -1731,6 +1737,8 @@ static void gen6_ppgtt_insert_entries(struct i915_address_space *vm,
}
} while (1);
kunmap_atomic(vaddr);
+
+ page_sizes->gtt = I915_GTT_PAGE_SIZE;
}
static int gen6_alloc_va_range(struct i915_address_space *vm,
@@ -2525,6 +2533,8 @@ static void aliasing_gtt_unbind_vma(struct i915_vma *vma)
struct i915_address_space *vm = &i915->mm.aliasing_ppgtt->base;
vm->clear_range(vm, vma->node.start, vma->size);
+
+ vma->obj->mm.page_sizes.gtt = 0;
}
}
diff --git a/drivers/gpu/drm/i915/i915_gem_object.h b/drivers/gpu/drm/i915/i915_gem_object.h
index 6db34eac9794..9b00947bf856 100644
--- a/drivers/gpu/drm/i915/i915_gem_object.h
+++ b/drivers/gpu/drm/i915/i915_gem_object.h
@@ -129,9 +129,11 @@ struct drm_i915_gem_object {
struct sg_table *pages;
void *mapping;
+ /* TODO: whack some of this into the error state */
struct i915_page_sizes {
unsigned int phys;
unsigned int sg;
+ unsigned int gtt;
} page_sizes;
struct i915_gem_object_page_iter {
diff --git a/drivers/gpu/drm/i915/selftests/i915_gem_gtt.c b/drivers/gpu/drm/i915/selftests/i915_gem_gtt.c
index 81c0d6b87e68..954f4140d902 100644
--- a/drivers/gpu/drm/i915/selftests/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/selftests/i915_gem_gtt.c
@@ -267,6 +267,7 @@ static int lowlevel_hole(struct drm_i915_private *i915,
GEM_BUG_ON(addr + BIT_ULL(size) > vm->total);
vm->clear_range(vm, addr, BIT_ULL(size));
+ obj->mm.page_sizes.gtt = 0;
}
i915_gem_object_unpin_pages(obj);
--
2.9.4
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^ permalink raw reply related [flat|nested] 30+ messages in thread* [PATCH 12/15] drm/i915/debugfs: include some gtt page size metrics
2017-05-31 18:51 [PATCH 00/15] huge gtt pages Matthew Auld
` (10 preceding siblings ...)
2017-05-31 18:52 ` [PATCH 11/15] drm/i915: accurate page size tracking for the ppgtt Matthew Auld
@ 2017-05-31 18:52 ` Matthew Auld
2017-05-31 18:52 ` [PATCH 13/15] drm/i915: enable platform support for 64K pages Matthew Auld
` (3 subsequent siblings)
15 siblings, 0 replies; 30+ messages in thread
From: Matthew Auld @ 2017-05-31 18:52 UTC (permalink / raw)
To: intel-gfx
Good to know, mostly for debugging purposes.
Signed-off-by: Matthew Auld <matthew.auld@intel.com>
Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
---
drivers/gpu/drm/i915/i915_debugfs.c | 40 ++++++++++++++++++++++++++++++++++---
1 file changed, 37 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
index 7e0816ccdc21..bdcbbd9635c5 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -117,6 +117,26 @@ static u64 i915_gem_obj_total_ggtt_size(struct drm_i915_gem_object *obj)
return size;
}
+static const char *stringify_page_sizes(unsigned int page_sizes)
+{
+ switch (page_sizes) {
+ case I915_GTT_PAGE_SIZE_4K:
+ return "4K";
+ case I915_GTT_PAGE_SIZE_64K:
+ return "64K";
+ case I915_GTT_PAGE_SIZE_2M:
+ return "2M";
+ case I915_GTT_PAGE_SIZE_1G:
+ return "1G";
+ default:
+ /* mixed-mode? */
+ if (page_sizes)
+ return "M";
+
+ return "";
+ }
+}
+
static void
describe_obj(struct seq_file *m, struct drm_i915_gem_object *obj)
{
@@ -128,7 +148,7 @@ describe_obj(struct seq_file *m, struct drm_i915_gem_object *obj)
lockdep_assert_held(&obj->base.dev->struct_mutex);
- seq_printf(m, "%pK: %c%c%c%c%c %8zdKiB %02x %02x %s%s%s",
+ seq_printf(m, "%pK: %c%c%c%c%c %8zdKiB %3s %02x %02x %s%s%s",
&obj->base,
get_active_flag(obj),
get_pin_flag(obj),
@@ -136,6 +156,7 @@ describe_obj(struct seq_file *m, struct drm_i915_gem_object *obj)
get_global_flag(obj),
get_pin_mapped_flag(obj),
obj->base.size / 1024,
+ stringify_page_sizes(obj->mm.page_sizes.gtt),
obj->base.read_domains,
obj->base.write_domain,
i915_cache_level_str(dev_priv, obj->cache_level),
@@ -399,8 +420,8 @@ static int i915_gem_object_info(struct seq_file *m, void *data)
struct drm_i915_private *dev_priv = node_to_i915(m->private);
struct drm_device *dev = &dev_priv->drm;
struct i915_ggtt *ggtt = &dev_priv->ggtt;
- u32 count, mapped_count, purgeable_count, dpy_count;
- u64 size, mapped_size, purgeable_size, dpy_size;
+ u32 count, mapped_count, purgeable_count, dpy_count, huge_count;
+ u64 size, mapped_size, purgeable_size, dpy_size, huge_size;
struct drm_i915_gem_object *obj;
struct drm_file *file;
int ret;
@@ -416,6 +437,7 @@ static int i915_gem_object_info(struct seq_file *m, void *data)
size = count = 0;
mapped_size = mapped_count = 0;
purgeable_size = purgeable_count = 0;
+ huge_size = huge_count = 0;
list_for_each_entry(obj, &dev_priv->mm.unbound_list, global_link) {
size += obj->base.size;
++count;
@@ -429,6 +451,11 @@ static int i915_gem_object_info(struct seq_file *m, void *data)
mapped_count++;
mapped_size += obj->base.size;
}
+
+ if (obj->mm.page_sizes.gtt > I915_GTT_PAGE_SIZE) {
+ huge_count++;
+ huge_size += obj->base.size;
+ }
}
seq_printf(m, "%u unbound objects, %llu bytes\n", count, size);
@@ -451,6 +478,11 @@ static int i915_gem_object_info(struct seq_file *m, void *data)
mapped_count++;
mapped_size += obj->base.size;
}
+
+ if (obj->mm.page_sizes.gtt > I915_GTT_PAGE_SIZE) {
+ huge_count++;
+ huge_size += obj->base.size;
+ }
}
seq_printf(m, "%u bound objects, %llu bytes\n",
count, size);
@@ -458,6 +490,8 @@ static int i915_gem_object_info(struct seq_file *m, void *data)
purgeable_count, purgeable_size);
seq_printf(m, "%u mapped objects, %llu bytes\n",
mapped_count, mapped_size);
+ seq_printf(m, "%u huge-paged objects, %llu bytes\n",
+ huge_count, huge_size);
seq_printf(m, "%u display objects (pinned), %llu bytes\n",
dpy_count, dpy_size);
--
2.9.4
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^ permalink raw reply related [flat|nested] 30+ messages in thread* [PATCH 13/15] drm/i915: enable platform support for 64K pages
2017-05-31 18:51 [PATCH 00/15] huge gtt pages Matthew Auld
` (11 preceding siblings ...)
2017-05-31 18:52 ` [PATCH 12/15] drm/i915/debugfs: include some gtt page size metrics Matthew Auld
@ 2017-05-31 18:52 ` Matthew Auld
2017-05-31 18:52 ` [PATCH 14/15] drm/i915: enable platform support for 2M pages Matthew Auld
` (2 subsequent siblings)
15 siblings, 0 replies; 30+ messages in thread
From: Matthew Auld @ 2017-05-31 18:52 UTC (permalink / raw)
To: intel-gfx
For gen9+ enable platform level support for 64K pages. Also enable for
mock testing.
Signed-off-by: Matthew Auld <matthew.auld@intel.com>
Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
---
drivers/gpu/drm/i915/i915_pci.c | 6 ++++--
drivers/gpu/drm/i915/selftests/mock_gem_device.c | 3 ++-
2 files changed, 6 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index 7caccb5bf963..0a6940c3841d 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -354,14 +354,16 @@ static const struct intel_device_info intel_cherryview_info = {
.has_aliasing_ppgtt = 1,
.has_full_ppgtt = 1,
.display_mmio_offset = VLV_DISPLAY_BASE,
- GEN_DEFAULT_PAGE_SIZES,
+ .page_size_mask = I915_GTT_PAGE_SIZE_4K |
+ I915_GTT_PAGE_SIZE_64K,
GEN_CHV_PIPEOFFSETS,
CURSOR_OFFSETS,
CHV_COLORS,
};
#define GEN9_DEFAULT_PAGE_SIZES \
- .page_size_mask = I915_GTT_PAGE_SIZE_4K
+ .page_size_mask = I915_GTT_PAGE_SIZE_4K | \
+ I915_GTT_PAGE_SIZE_64K
static const struct intel_device_info intel_skylake_info = {
BDW_FEATURES,
diff --git a/drivers/gpu/drm/i915/selftests/mock_gem_device.c b/drivers/gpu/drm/i915/selftests/mock_gem_device.c
index bb12e6fe24ec..14e5b11312a7 100644
--- a/drivers/gpu/drm/i915/selftests/mock_gem_device.c
+++ b/drivers/gpu/drm/i915/selftests/mock_gem_device.c
@@ -148,7 +148,8 @@ struct drm_i915_private *mock_gem_device(void)
mkwrite_device_info(i915)->gen = -1;
mkwrite_device_info(i915)->page_size_mask =
- I915_GTT_PAGE_SIZE_4K;
+ I915_GTT_PAGE_SIZE_4K |
+ I915_GTT_PAGE_SIZE_64K;
spin_lock_init(&i915->mm.object_stat_lock);
mock_uncore_init(i915);
--
2.9.4
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 30+ messages in thread* [PATCH 14/15] drm/i915: enable platform support for 2M pages
2017-05-31 18:51 [PATCH 00/15] huge gtt pages Matthew Auld
` (12 preceding siblings ...)
2017-05-31 18:52 ` [PATCH 13/15] drm/i915: enable platform support for 64K pages Matthew Auld
@ 2017-05-31 18:52 ` Matthew Auld
2017-05-31 18:52 ` [PATCH 15/15] drm/i915: enable platform support for 1G pages Matthew Auld
2017-05-31 19:11 ` ✓ Fi.CI.BAT: success for huge gtt pages Patchwork
15 siblings, 0 replies; 30+ messages in thread
From: Matthew Auld @ 2017-05-31 18:52 UTC (permalink / raw)
To: intel-gfx
For gen8+ enable platform level support for 2M pages. Also enable for
mock testing.
Signed-off-by: Matthew Auld <matthew.auld@intel.com>
Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
---
drivers/gpu/drm/i915/i915_pci.c | 9 ++++++---
drivers/gpu/drm/i915/selftests/mock_gem_device.c | 3 ++-
2 files changed, 8 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index 0a6940c3841d..452f061fd7b3 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -319,7 +319,8 @@ static const struct intel_device_info intel_haswell_info = {
#define BDW_FEATURES \
HSW_FEATURES, \
BDW_COLORS, \
- GEN_DEFAULT_PAGE_SIZES, \
+ .page_size_mask = I915_GTT_PAGE_SIZE_4K | \
+ I915_GTT_PAGE_SIZE_2M, \
.has_logical_ring_contexts = 1, \
.has_full_48bit_ppgtt = 1, \
.has_64bit_reloc = 1
@@ -355,7 +356,8 @@ static const struct intel_device_info intel_cherryview_info = {
.has_full_ppgtt = 1,
.display_mmio_offset = VLV_DISPLAY_BASE,
.page_size_mask = I915_GTT_PAGE_SIZE_4K |
- I915_GTT_PAGE_SIZE_64K,
+ I915_GTT_PAGE_SIZE_64K |
+ I915_GTT_PAGE_SIZE_2M,
GEN_CHV_PIPEOFFSETS,
CURSOR_OFFSETS,
CHV_COLORS,
@@ -363,7 +365,8 @@ static const struct intel_device_info intel_cherryview_info = {
#define GEN9_DEFAULT_PAGE_SIZES \
.page_size_mask = I915_GTT_PAGE_SIZE_4K | \
- I915_GTT_PAGE_SIZE_64K
+ I915_GTT_PAGE_SIZE_64K | \
+ I915_GTT_PAGE_SIZE_2M
static const struct intel_device_info intel_skylake_info = {
BDW_FEATURES,
diff --git a/drivers/gpu/drm/i915/selftests/mock_gem_device.c b/drivers/gpu/drm/i915/selftests/mock_gem_device.c
index 14e5b11312a7..97d7e84f9893 100644
--- a/drivers/gpu/drm/i915/selftests/mock_gem_device.c
+++ b/drivers/gpu/drm/i915/selftests/mock_gem_device.c
@@ -149,7 +149,8 @@ struct drm_i915_private *mock_gem_device(void)
mkwrite_device_info(i915)->page_size_mask =
I915_GTT_PAGE_SIZE_4K |
- I915_GTT_PAGE_SIZE_64K;
+ I915_GTT_PAGE_SIZE_64K |
+ I915_GTT_PAGE_SIZE_2M;
spin_lock_init(&i915->mm.object_stat_lock);
mock_uncore_init(i915);
--
2.9.4
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 30+ messages in thread* [PATCH 15/15] drm/i915: enable platform support for 1G pages
2017-05-31 18:51 [PATCH 00/15] huge gtt pages Matthew Auld
` (13 preceding siblings ...)
2017-05-31 18:52 ` [PATCH 14/15] drm/i915: enable platform support for 2M pages Matthew Auld
@ 2017-05-31 18:52 ` Matthew Auld
2017-05-31 19:11 ` ✓ Fi.CI.BAT: success for huge gtt pages Patchwork
15 siblings, 0 replies; 30+ messages in thread
From: Matthew Auld @ 2017-05-31 18:52 UTC (permalink / raw)
To: intel-gfx
For gen8+ enable platform level support for 1G pages. Also enable for
mock testing.
Signed-off-by: Matthew Auld <matthew.auld@intel.com>
Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
---
drivers/gpu/drm/i915/i915_pci.c | 9 ++++++---
drivers/gpu/drm/i915/selftests/mock_gem_device.c | 3 ++-
2 files changed, 8 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index 452f061fd7b3..68baefe6566c 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -320,7 +320,8 @@ static const struct intel_device_info intel_haswell_info = {
HSW_FEATURES, \
BDW_COLORS, \
.page_size_mask = I915_GTT_PAGE_SIZE_4K | \
- I915_GTT_PAGE_SIZE_2M, \
+ I915_GTT_PAGE_SIZE_2M | \
+ I915_GTT_PAGE_SIZE_1G, \
.has_logical_ring_contexts = 1, \
.has_full_48bit_ppgtt = 1, \
.has_64bit_reloc = 1
@@ -357,7 +358,8 @@ static const struct intel_device_info intel_cherryview_info = {
.display_mmio_offset = VLV_DISPLAY_BASE,
.page_size_mask = I915_GTT_PAGE_SIZE_4K |
I915_GTT_PAGE_SIZE_64K |
- I915_GTT_PAGE_SIZE_2M,
+ I915_GTT_PAGE_SIZE_2M |
+ I915_GTT_PAGE_SIZE_1G,
GEN_CHV_PIPEOFFSETS,
CURSOR_OFFSETS,
CHV_COLORS,
@@ -366,7 +368,8 @@ static const struct intel_device_info intel_cherryview_info = {
#define GEN9_DEFAULT_PAGE_SIZES \
.page_size_mask = I915_GTT_PAGE_SIZE_4K | \
I915_GTT_PAGE_SIZE_64K | \
- I915_GTT_PAGE_SIZE_2M
+ I915_GTT_PAGE_SIZE_2M | \
+ I915_GTT_PAGE_SIZE_1G
static const struct intel_device_info intel_skylake_info = {
BDW_FEATURES,
diff --git a/drivers/gpu/drm/i915/selftests/mock_gem_device.c b/drivers/gpu/drm/i915/selftests/mock_gem_device.c
index 97d7e84f9893..8d8068083597 100644
--- a/drivers/gpu/drm/i915/selftests/mock_gem_device.c
+++ b/drivers/gpu/drm/i915/selftests/mock_gem_device.c
@@ -150,7 +150,8 @@ struct drm_i915_private *mock_gem_device(void)
mkwrite_device_info(i915)->page_size_mask =
I915_GTT_PAGE_SIZE_4K |
I915_GTT_PAGE_SIZE_64K |
- I915_GTT_PAGE_SIZE_2M;
+ I915_GTT_PAGE_SIZE_2M |
+ I915_GTT_PAGE_SIZE_1G;
spin_lock_init(&i915->mm.object_stat_lock);
mock_uncore_init(i915);
--
2.9.4
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 30+ messages in thread* ✓ Fi.CI.BAT: success for huge gtt pages
2017-05-31 18:51 [PATCH 00/15] huge gtt pages Matthew Auld
` (14 preceding siblings ...)
2017-05-31 18:52 ` [PATCH 15/15] drm/i915: enable platform support for 1G pages Matthew Auld
@ 2017-05-31 19:11 ` Patchwork
15 siblings, 0 replies; 30+ messages in thread
From: Patchwork @ 2017-05-31 19:11 UTC (permalink / raw)
To: Matthew Auld; +Cc: intel-gfx
== Series Details ==
Series: huge gtt pages
URL : https://patchwork.freedesktop.org/series/25118/
State : success
== Summary ==
Series 25118v1 huge gtt pages
https://patchwork.freedesktop.org/api/1.0/series/25118/revisions/1/mbox/
fi-bdw-5557u total:278 pass:267 dwarn:0 dfail:0 fail:0 skip:11 time:446s
fi-bdw-gvtdvm total:278 pass:256 dwarn:8 dfail:0 fail:0 skip:14 time:438s
fi-bsw-n3050 total:278 pass:242 dwarn:0 dfail:0 fail:0 skip:36 time:568s
fi-bxt-j4205 total:278 pass:259 dwarn:0 dfail:0 fail:0 skip:19 time:494s
fi-byt-j1900 total:278 pass:254 dwarn:0 dfail:0 fail:0 skip:24 time:475s
fi-byt-n2820 total:278 pass:250 dwarn:0 dfail:0 fail:0 skip:28 time:473s
fi-hsw-4770 total:278 pass:262 dwarn:0 dfail:0 fail:0 skip:16 time:432s
fi-hsw-4770r total:278 pass:262 dwarn:0 dfail:0 fail:0 skip:16 time:412s
fi-ilk-650 total:278 pass:228 dwarn:0 dfail:0 fail:0 skip:50 time:412s
fi-ivb-3520m total:278 pass:260 dwarn:0 dfail:0 fail:0 skip:18 time:491s
fi-ivb-3770 total:278 pass:260 dwarn:0 dfail:0 fail:0 skip:18 time:462s
fi-kbl-7500u total:278 pass:255 dwarn:5 dfail:0 fail:0 skip:18 time:463s
fi-kbl-7560u total:278 pass:263 dwarn:5 dfail:0 fail:0 skip:10 time:566s
fi-skl-6260u total:278 pass:268 dwarn:0 dfail:0 fail:0 skip:10 time:452s
fi-skl-6700hq total:278 pass:239 dwarn:0 dfail:1 fail:17 skip:21 time:433s
fi-skl-6700k total:278 pass:256 dwarn:4 dfail:0 fail:0 skip:18 time:465s
fi-skl-6770hq total:278 pass:268 dwarn:0 dfail:0 fail:0 skip:10 time:489s
fi-skl-gvtdvm total:278 pass:265 dwarn:0 dfail:0 fail:0 skip:13 time:432s
fi-snb-2520m total:278 pass:250 dwarn:0 dfail:0 fail:0 skip:28 time:533s
fi-snb-2600 total:278 pass:249 dwarn:0 dfail:0 fail:0 skip:29 time:403s
593aae9587d79f8a823a36f4e6cc12e23b547d07 drm-tip: 2017y-05m-31d-14h-36m-16s UTC integration manifest
7f3e1da drm/i915: enable platform support for 1G pages
14bccb0 drm/i915: enable platform support for 2M pages
d4e64ea drm/i915: enable platform support for 64K pages
b31a68e drm/i915/debugfs: include some gtt page size metrics
4770028 drm/i915: accurate page size tracking for the ppgtt
2e4fbc8 drm/i915: support huge gtt pages for the 48b PPGTT
9e817e0 drm/i915: disable GTT cache for 2M/1G pages
f30b433 drm/i915: enable IPS bit for 64K pages
bfc2fa4 drm/i915: pass mm.gtt_page_sizes to ppgtt insert_entries
73ee6a0 drm/i915: align 64K objects to 2M
84d06ac drm/i915: align the vma start to the largest gtt page size
2fdf461 drm/i915: introduce gem object page_sizes
cfd5167 drm/i915: introduce page_size_mask to dev_info
79c3010 drm/i915: enable THP for gemfs
4738e84 drm/i915: really simple gemfs
== Logs ==
For more details see: https://intel-gfx-ci.01.org/CI/Patchwork_4847/
_______________________________________________
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^ permalink raw reply [flat|nested] 30+ messages in thread