From: Xiaoguang Chen <xiaoguang.chen@intel.com>
To: alex.williamson@redhat.com, kraxel@redhat.com,
chris@chris-wilson.co.uk, intel-gfx@lists.freedesktop.org,
linux-kernel@vger.kernel.org, zhenyuw@linux.intel.com,
zhiyuan.lv@intel.com, intel-gvt-dev@lists.freedesktop.org,
zhi.a.wang@intel.com, kevin.tian@intel.com
Cc: Xiaoguang Chen <xiaoguang.chen@intel.com>
Subject: [PATCH v9 2/7] drm/i915/gvt: OpRegion support for GVT-g
Date: Thu, 15 Jun 2017 16:00:06 +0800 [thread overview]
Message-ID: <1497513611-2814-3-git-send-email-xiaoguang.chen@intel.com> (raw)
In-Reply-To: <1497513611-2814-1-git-send-email-xiaoguang.chen@intel.com>
OpRegion is needed to support display related operation for
intel vgpu.
A vfio device region is added to intel vgpu to deliver the
host OpRegion information to user space so user space can
construct the OpRegion for vgpu.
Signed-off-by: Bing Niu <bing.niu@intel.com>
Signed-off-by: Xiaoguang Chen <xiaoguang.chen@intel.com>
---
drivers/gpu/drm/i915/gvt/hypercall.h | 1 +
drivers/gpu/drm/i915/gvt/kvmgt.c | 88 ++++++++++++++++++++++++++++++++++++
drivers/gpu/drm/i915/gvt/mpt.h | 15 ++++++
drivers/gpu/drm/i915/gvt/opregion.c | 26 ++++++++---
drivers/gpu/drm/i915/gvt/vgpu.c | 4 ++
5 files changed, 128 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/i915/gvt/hypercall.h b/drivers/gpu/drm/i915/gvt/hypercall.h
index df7f33a..32c345c 100644
--- a/drivers/gpu/drm/i915/gvt/hypercall.h
+++ b/drivers/gpu/drm/i915/gvt/hypercall.h
@@ -55,6 +55,7 @@ struct intel_gvt_mpt {
unsigned long mfn, unsigned int nr, bool map);
int (*set_trap_area)(unsigned long handle, u64 start, u64 end,
bool map);
+ int (*set_opregion)(void *vgpu);
};
extern struct intel_gvt_mpt xengt_mpt;
diff --git a/drivers/gpu/drm/i915/gvt/kvmgt.c b/drivers/gpu/drm/i915/gvt/kvmgt.c
index 3c6a02b..6b4652a 100644
--- a/drivers/gpu/drm/i915/gvt/kvmgt.c
+++ b/drivers/gpu/drm/i915/gvt/kvmgt.c
@@ -53,6 +53,8 @@ static const struct intel_gvt_ops *intel_gvt_ops;
#define VFIO_PCI_INDEX_TO_OFFSET(index) ((u64)(index) << VFIO_PCI_OFFSET_SHIFT)
#define VFIO_PCI_OFFSET_MASK (((u64)(1) << VFIO_PCI_OFFSET_SHIFT) - 1)
+#define OPREGION_SIGNATURE "IntelGraphicsMem"
+
struct vfio_region;
struct intel_vgpu_regops {
size_t (*rw)(struct intel_vgpu *vgpu, char *buf,
@@ -436,6 +438,91 @@ static void kvmgt_protect_table_del(struct kvmgt_guest_info *info,
}
}
+static size_t intel_vgpu_reg_rw_opregion(struct intel_vgpu *vgpu, char *buf,
+ size_t count, loff_t *ppos, bool iswrite)
+{
+ unsigned int i = VFIO_PCI_OFFSET_TO_INDEX(*ppos) -
+ VFIO_PCI_NUM_REGIONS;
+ void *base = vgpu->vdev.region[i].data;
+ loff_t pos = *ppos & VFIO_PCI_OFFSET_MASK;
+
+ if (pos >= vgpu->vdev.region[i].size || iswrite) {
+ gvt_vgpu_err("invalid op or offset for Intel vgpu OpRegion\n");
+ return -EINVAL;
+ }
+ count = min(count, (size_t)(vgpu->vdev.region[i].size - pos));
+ memcpy(buf, base + pos, count);
+
+ return count;
+}
+
+static void intel_vgpu_reg_release_opregion(struct intel_vgpu *vgpu,
+ struct vfio_region *region)
+{
+ memunmap(region->data);
+}
+
+static const struct intel_vgpu_regops intel_vgpu_regops_opregion = {
+ .rw = intel_vgpu_reg_rw_opregion,
+ .release = intel_vgpu_reg_release_opregion,
+};
+
+static int intel_vgpu_register_reg(struct intel_vgpu *vgpu,
+ unsigned int type, unsigned int subtype,
+ const struct intel_vgpu_regops *ops,
+ size_t size, u32 flags, void *data)
+{
+ struct vfio_region *region;
+
+ region = krealloc(vgpu->vdev.region,
+ (vgpu->vdev.num_regions + 1) * sizeof(*region),
+ GFP_KERNEL);
+ if (!region)
+ return -ENOMEM;
+
+ vgpu->vdev.region = region;
+ vgpu->vdev.region[vgpu->vdev.num_regions].type = type;
+ vgpu->vdev.region[vgpu->vdev.num_regions].subtype = subtype;
+ vgpu->vdev.region[vgpu->vdev.num_regions].ops = ops;
+ vgpu->vdev.region[vgpu->vdev.num_regions].size = size;
+ vgpu->vdev.region[vgpu->vdev.num_regions].flags = flags;
+ vgpu->vdev.region[vgpu->vdev.num_regions].data = data;
+ vgpu->vdev.num_regions++;
+
+ return 0;
+}
+
+static int kvmgt_set_opregion(void *p_vgpu)
+{
+ struct intel_vgpu *vgpu = (struct intel_vgpu *)p_vgpu;
+ unsigned int addr;
+ void *base;
+ int ret;
+
+ addr = vgpu->gvt->opregion.opregion_pa;
+ if (!addr || !(~addr))
+ return -ENODEV;
+
+ base = memremap(addr, OPREGION_SIZE, MEMREMAP_WB);
+ if (!base)
+ return -ENOMEM;
+
+ if (memcmp(base, OPREGION_SIGNATURE, 16)) {
+ memunmap(base);
+ return -EINVAL;
+ }
+
+ ret = intel_vgpu_register_reg(vgpu,
+ PCI_VENDOR_ID_INTEL | VFIO_REGION_TYPE_PCI_VENDOR_TYPE,
+ VFIO_REGION_SUBTYPE_INTEL_IGD_OPREGION,
+ &intel_vgpu_regops_opregion, OPREGION_SIZE,
+ VFIO_REGION_INFO_FLAG_READ, base);
+ if (ret)
+ memunmap(base);
+
+ return ret;
+}
+
static int intel_vgpu_create(struct kobject *kobj, struct mdev_device *mdev)
{
struct intel_vgpu *vgpu = NULL;
@@ -1524,6 +1611,7 @@ struct intel_gvt_mpt kvmgt_mpt = {
.read_gpa = kvmgt_read_gpa,
.write_gpa = kvmgt_write_gpa,
.gfn_to_mfn = kvmgt_gfn_to_pfn,
+ .set_opregion = kvmgt_set_opregion,
};
EXPORT_SYMBOL_GPL(kvmgt_mpt);
diff --git a/drivers/gpu/drm/i915/gvt/mpt.h b/drivers/gpu/drm/i915/gvt/mpt.h
index 4193536..ab71300 100644
--- a/drivers/gpu/drm/i915/gvt/mpt.h
+++ b/drivers/gpu/drm/i915/gvt/mpt.h
@@ -293,4 +293,19 @@ static inline int intel_gvt_hypervisor_set_trap_area(
return intel_gvt_host.mpt->set_trap_area(vgpu->handle, start, end, map);
}
+/**
+ * intel_gvt_hypervisor_set_opregion - Set opregion for guest
+ * @vgpu: a vGPU
+ *
+ * Returns:
+ * Zero on success, negative error code if failed.
+ */
+static inline int intel_gvt_hypervisor_set_opregion(struct intel_vgpu *vgpu)
+{
+ if (!intel_gvt_host.mpt->set_opregion)
+ return 0;
+
+ return intel_gvt_host.mpt->set_opregion(vgpu);
+}
+
#endif /* _GVT_MPT_H_ */
diff --git a/drivers/gpu/drm/i915/gvt/opregion.c b/drivers/gpu/drm/i915/gvt/opregion.c
index 3117991..04c0452 100644
--- a/drivers/gpu/drm/i915/gvt/opregion.c
+++ b/drivers/gpu/drm/i915/gvt/opregion.c
@@ -113,23 +113,37 @@ void intel_vgpu_clean_opregion(struct intel_vgpu *vgpu)
*/
int intel_vgpu_init_opregion(struct intel_vgpu *vgpu, u32 gpa)
{
- int ret;
+ int ret = 0;
+ unsigned long pfn;
gvt_dbg_core("vgpu%d: init vgpu opregion\n", vgpu->id);
- if (intel_gvt_host.hypervisor_type == INTEL_GVT_HYPERVISOR_XEN) {
+ switch (intel_gvt_host.hypervisor_type) {
+ case INTEL_GVT_HYPERVISOR_KVM:
+ pfn = intel_gvt_hypervisor_gfn_to_mfn(vgpu, gpa >> PAGE_SHIFT);
+ vgpu_opregion(vgpu)->va = memremap(pfn << PAGE_SHIFT,
+ INTEL_GVT_OPREGION_SIZE,
+ MEMREMAP_WB);
+ if (!vgpu_opregion(vgpu)->va) {
+ gvt_vgpu_err("failed to map guest opregion\n");
+ ret = -EFAULT;
+ }
+ break;
+ case INTEL_GVT_HYPERVISOR_XEN:
gvt_dbg_core("emulate opregion from kernel\n");
ret = init_vgpu_opregion(vgpu, gpa);
if (ret)
- return ret;
+ break;
ret = map_vgpu_opregion(vgpu, true);
- if (ret)
- return ret;
+ break;
+ default:
+ ret = -EINVAL;
+ gvt_vgpu_err("not supported hypervisor\n");
}
- return 0;
+ return ret;
}
/**
diff --git a/drivers/gpu/drm/i915/gvt/vgpu.c b/drivers/gpu/drm/i915/gvt/vgpu.c
index 6e3cbd8..8e1d504 100644
--- a/drivers/gpu/drm/i915/gvt/vgpu.c
+++ b/drivers/gpu/drm/i915/gvt/vgpu.c
@@ -383,6 +383,10 @@ static struct intel_vgpu *__intel_gvt_create_vgpu(struct intel_gvt *gvt,
if (ret)
goto out_clean_shadow_ctx;
+ ret = intel_gvt_hypervisor_set_opregion(vgpu);
+ if (ret)
+ goto out_clean_shadow_ctx;
+
mutex_unlock(&gvt->lock);
return vgpu;
--
2.7.4
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
next prev parent reply other threads:[~2017-06-15 8:00 UTC|newest]
Thread overview: 56+ messages / expand[flat|nested] mbox.gz Atom feed top
2017-06-15 8:00 [PATCH v9 0/7] drm/i915/gvt: Dma-buf support for GVT-g Xiaoguang Chen
2017-06-15 8:00 ` [PATCH v9 1/7] drm/i915/gvt: Extend the GVT-g architecture Xiaoguang Chen
2017-06-15 8:00 ` Xiaoguang Chen [this message]
2017-06-15 8:00 ` [PATCH v9 3/7] drm: Extend the drm format Xiaoguang Chen
2017-06-15 10:21 ` Ville Syrjälä
2017-06-20 9:01 ` [Intel-gfx] " Zhang, Tina
2017-06-15 8:00 ` [PATCH v9 4/7] drm/i915/gvt: Frame buffer decoder support for GVT-g Xiaoguang Chen
2017-06-15 8:00 ` [PATCH v9 5/7] vfio: Define vfio based dma-buf operations Xiaoguang Chen
2017-06-15 14:51 ` Kirti Wankhede
2017-06-15 16:00 ` Gerd Hoffmann
2017-06-15 20:38 ` Alex Williamson
2017-06-16 10:24 ` Gerd Hoffmann
2017-06-16 12:52 ` Alex Williamson
2017-06-16 13:32 ` Kirti Wankhede
2017-06-16 16:39 ` Alex Williamson
2017-06-16 18:28 ` Kirti Wankhede
2017-06-19 6:34 ` Gerd Hoffmann
2017-06-19 14:54 ` Alex Williamson
2017-06-20 8:35 ` Gerd Hoffmann
2017-06-20 13:55 ` Kirti Wankhede
2017-06-21 7:22 ` Gerd Hoffmann
2017-07-12 13:18 ` Kirti Wankhede
2017-07-14 9:58 ` Gerd Hoffmann
2017-06-19 6:38 ` Gerd Hoffmann
2017-06-19 14:55 ` Alex Williamson
2017-06-20 8:41 ` Zhang, Tina
2017-06-20 10:57 ` Gerd Hoffmann
2017-06-20 15:00 ` [Intel-gfx] " Alex Williamson
2017-06-20 17:07 ` Kirti Wankhede
2017-06-20 23:01 ` Zhang, Tina
2017-06-20 23:22 ` Alex Williamson
2017-06-21 9:20 ` Zhang, Tina
2017-06-21 11:03 ` [Intel-gfx] " Gerd Hoffmann
2017-06-21 18:59 ` Alex Williamson
2017-06-22 8:30 ` Gerd Hoffmann
2017-06-22 18:54 ` Alex Williamson
2017-06-23 7:26 ` Gerd Hoffmann
2017-06-23 7:49 ` [Intel-gfx] " Zhi Wang
2017-06-23 8:31 ` Gerd Hoffmann
2017-06-23 16:40 ` Alex Williamson
2017-06-23 17:15 ` Alex Williamson
2017-06-26 6:17 ` Gerd Hoffmann
2017-06-22 0:21 ` Zhang, Tina
2017-06-21 7:34 ` Gerd Hoffmann
2017-06-23 21:58 ` Zhang, Tina
2017-06-26 6:39 ` Gerd Hoffmann
2017-06-26 17:28 ` Alex Williamson
2017-06-27 6:12 ` Gerd Hoffmann
2017-06-28 12:48 ` Zhang, Tina
2017-06-29 6:41 ` Gerd Hoffmann
2017-06-29 8:39 ` Daniel Vetter
2017-07-04 0:47 ` Zhang, Tina
2017-06-20 13:35 ` Kirti Wankhede
2017-06-15 8:00 ` [PATCH v9 6/7] drm/i915/gvt: Dmabuf support for GVT-g Xiaoguang Chen
2017-06-15 8:00 ` [PATCH v9 7/7] drm/i915/gvt: Adding user interface for dma-buf Xiaoguang Chen
2017-06-15 8:03 ` ✗ Fi.CI.BAT: failure for drm/i915/gvt: dma-buf support for GVT-g (rev9) Patchwork
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=1497513611-2814-3-git-send-email-xiaoguang.chen@intel.com \
--to=xiaoguang.chen@intel.com \
--cc=alex.williamson@redhat.com \
--cc=chris@chris-wilson.co.uk \
--cc=intel-gfx@lists.freedesktop.org \
--cc=intel-gvt-dev@lists.freedesktop.org \
--cc=kevin.tian@intel.com \
--cc=kraxel@redhat.com \
--cc=linux-kernel@vger.kernel.org \
--cc=zhenyuw@linux.intel.com \
--cc=zhi.a.wang@intel.com \
--cc=zhiyuan.lv@intel.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).