[PATCH 1/3] drm/i915/cnl: Add allowed DP rates for Cannonlake.

[PATCH 1/3] drm/i915/cnl: Add allowed DP rates for Cannonlake.

[Rodrigo Vivi]

One warning is that in order to get DPLL Link rates
3240 and 4050 that allows 648000 and 810000 is that:
"Some SKUs may require elevated I/O voltage to support
this."

v2: Rebase on top of source_rates changes.

Cc: Clint Taylor <clinton.a.taylor@intel.com>
Cc: Mika Kahola <mika.kahola@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
---
 drivers/gpu/drm/i915/intel_dp.c | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 2d42d09..4355bdf 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -97,6 +97,9 @@ struct dp_link_dpll {
 				  324000, 432000, 540000 };
 static const int skl_rates[] = { 162000, 216000, 270000,
 				  324000, 432000, 540000 };
+static const int cnl_rates[] = { 162000, 216000, 270000,
+				 324000, 432000, 540000,
+				 648000, 810000 };
 static const int default_rates[] = { 162000, 270000, 540000 };
 
 /**
@@ -238,6 +241,9 @@ int intel_dp_max_lane_count(struct intel_dp *intel_dp)
 	if (IS_GEN9_LP(dev_priv)) {
 		source_rates = bxt_rates;
 		size = ARRAY_SIZE(bxt_rates);
+	} else if (IS_CANNONLAKE(dev_priv)) {
+		source_rates = cnl_rates;
+		size = ARRAY_SIZE(cnl_rates);
 	} else if (IS_GEN9_BC(dev_priv)) {
 		source_rates = skl_rates;
 		size = ARRAY_SIZE(skl_rates);
-- 
1.9.1

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[PATCH 2/3] drm/i915/cnl: Dump the right pll registers when dumping pipe config.

[Rodrigo Vivi]

Different from SKL we don't need ctrl1 and cfgcr2, but
we need to dump cfgcr0 amd cfgcr1 instead.

v2: rebase and commit message

Cc: Clint Taylor <clinton.a.taylor@intel.com>
Cc: Mika Kahola <mika.kahola@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
---
 drivers/gpu/drm/i915/intel_dpll_mgr.c | 11 ++++++++++-
 1 file changed, 10 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/intel_dpll_mgr.c b/drivers/gpu/drm/i915/intel_dpll_mgr.c
index 2f7b0e6..a2a3d93 100644
--- a/drivers/gpu/drm/i915/intel_dpll_mgr.c
+++ b/drivers/gpu/drm/i915/intel_dpll_mgr.c
@@ -2379,6 +2379,15 @@ static bool cnl_ddi_hdmi_pll_dividers(struct intel_crtc *crtc,
 	return pll;
 }
 
+static void cnl_dump_hw_state(struct drm_i915_private *dev_priv,
+			      struct intel_dpll_hw_state *hw_state)
+{
+	DRM_DEBUG_KMS("dpll_hw_state: "
+		      "cfgcr0: 0x%x, cfgcr1: 0x%x\n",
+		      hw_state->cfgcr0,
+		      hw_state->cfgcr1);
+}
+
 static const struct intel_shared_dpll_funcs cnl_ddi_pll_funcs = {
 	.enable = cnl_ddi_pll_enable,
 	.disable = cnl_ddi_pll_disable,
@@ -2395,7 +2404,7 @@ static bool cnl_ddi_hdmi_pll_dividers(struct intel_crtc *crtc,
 static const struct intel_dpll_mgr cnl_pll_mgr = {
 	.dpll_info = cnl_plls,
 	.get_dpll = cnl_get_dpll,
-	.dump_hw_state = skl_dump_hw_state,
+	.dump_hw_state = cnl_dump_hw_state,
 };
 
 /**
-- 
1.9.1

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[PATCH 3/3] drm/i915/cnl: Avoid old DDI translation functions on Cannonlake.

[Rodrigo Vivi]

Cannonlake uses a different swing voltage initalization
sequence scheme that doesn't require these old functions.

All other DDI, voltage swing and PLLs initialialization
and configuration are already in place for Cannonlake.
This patch only removes unecessary steps probably saving
us from some useless warnings.

Cc: Clint Taylor <clinton.a.taylor@intel.com>
Cc: Mika Kahola <mika.kahola@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
---
 drivers/gpu/drm/i915/intel_ddi.c | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
index 80e96f1..9e9bfbe 100644
--- a/drivers/gpu/drm/i915/intel_ddi.c
+++ b/drivers/gpu/drm/i915/intel_ddi.c
@@ -596,7 +596,7 @@ static int intel_ddi_hdmi_level(struct drm_i915_private *dev_priv, enum port por
 
 	hdmi_level = dev_priv->vbt.ddi_port_info[port].hdmi_level_shift;
 
-	if (IS_GEN9_LP(dev_priv))
+	if (IS_GEN9_LP(dev_priv) || INTEL_GEN(dev_priv) >= 10)
 		return hdmi_level;
 
 	if (IS_GEN9_BC(dev_priv)) {
@@ -688,7 +688,7 @@ static void intel_prepare_dp_ddi_buffers(struct intel_encoder *encoder)
 	enum port port = intel_ddi_get_encoder_port(encoder);
 	const struct ddi_buf_trans *ddi_translations;
 
-	if (IS_GEN9_LP(dev_priv))
+	if (IS_GEN9_LP(dev_priv) || INTEL_GEN(dev_priv) >= 10)
 		return;
 
 	switch (encoder->type) {
@@ -741,7 +741,7 @@ static void intel_prepare_hdmi_ddi_buffers(struct intel_encoder *encoder)
 	enum port port = intel_ddi_get_encoder_port(encoder);
 	const struct ddi_buf_trans *ddi_translations_hdmi;
 
-	if (IS_GEN9_LP(dev_priv))
+	if (IS_GEN9_LP(dev_priv) || INTEL_GEN(dev_priv) >= 10)
 		return;
 
 	hdmi_level = intel_ddi_hdmi_level(dev_priv, port);
-- 
1.9.1

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✓ Fi.CI.BAT: success for series starting with [1/3] drm/i915/cnl: Add allowed DP rates for Cannonlake.

[Patchwork]

== Series Details ==

Series: series starting with [1/3] drm/i915/cnl: Add allowed DP rates for Cannonlake.
URL   : https://patchwork.freedesktop.org/series/26952/
State : success

== Summary ==

Series 26952v1 Series without cover letter
https://patchwork.freedesktop.org/api/1.0/series/26952/revisions/1/mbox/

Test gem_exec_suspend:
        Subgroup basic-s4-devices:
                pass       -> DMESG-WARN (fi-kbl-7560u) fdo#100125
Test kms_force_connector_basic:
        Subgroup force-connector-state:
                skip       -> PASS       (fi-ivb-3520m) fdo#101048 +3
Test kms_pipe_crc_basic:
        Subgroup suspend-read-crc-pipe-c:
                pass       -> FAIL       (fi-skl-6700k) fdo#100367

fdo#100125 https://bugs.freedesktop.org/show_bug.cgi?id=100125
fdo#101048 https://bugs.freedesktop.org/show_bug.cgi?id=101048
fdo#100367 https://bugs.freedesktop.org/show_bug.cgi?id=100367

fi-bdw-5557u     total:279  pass:268  dwarn:0   dfail:0   fail:0   skip:11  time:438s
fi-bdw-gvtdvm    total:279  pass:265  dwarn:0   dfail:0   fail:0   skip:14  time:425s
fi-blb-e6850     total:279  pass:224  dwarn:1   dfail:0   fail:0   skip:54  time:355s
fi-bsw-n3050     total:279  pass:243  dwarn:0   dfail:0   fail:0   skip:36  time:530s
fi-bxt-j4205     total:279  pass:260  dwarn:0   dfail:0   fail:0   skip:19  time:512s
fi-byt-j1900     total:279  pass:255  dwarn:0   dfail:0   fail:0   skip:24  time:492s
fi-byt-n2820     total:279  pass:250  dwarn:1   dfail:0   fail:0   skip:28  time:481s
fi-glk-2a        total:279  pass:260  dwarn:0   dfail:0   fail:0   skip:19  time:593s
fi-hsw-4770      total:279  pass:263  dwarn:0   dfail:0   fail:0   skip:16  time:439s
fi-hsw-4770r     total:279  pass:263  dwarn:0   dfail:0   fail:0   skip:16  time:413s
fi-ilk-650       total:279  pass:229  dwarn:0   dfail:0   fail:0   skip:50  time:425s
fi-ivb-3520m     total:279  pass:261  dwarn:0   dfail:0   fail:0   skip:18  time:507s
fi-ivb-3770      total:279  pass:261  dwarn:0   dfail:0   fail:0   skip:18  time:478s
fi-kbl-7500u     total:279  pass:261  dwarn:0   dfail:0   fail:0   skip:18  time:459s
fi-kbl-7560u     total:279  pass:268  dwarn:1   dfail:0   fail:0   skip:10  time:572s
fi-kbl-r         total:279  pass:260  dwarn:1   dfail:0   fail:0   skip:18  time:579s
fi-pnv-d510      total:279  pass:221  dwarn:3   dfail:0   fail:0   skip:55  time:560s
fi-skl-6260u     total:279  pass:269  dwarn:0   dfail:0   fail:0   skip:10  time:454s
fi-skl-6700hq    total:279  pass:262  dwarn:0   dfail:0   fail:0   skip:17  time:591s
fi-skl-6700k     total:279  pass:256  dwarn:4   dfail:0   fail:1   skip:18  time:469s
fi-skl-6770hq    total:279  pass:269  dwarn:0   dfail:0   fail:0   skip:10  time:477s
fi-skl-gvtdvm    total:279  pass:266  dwarn:0   dfail:0   fail:0   skip:13  time:436s
fi-snb-2520m     total:279  pass:251  dwarn:0   dfail:0   fail:0   skip:28  time:542s
fi-snb-2600      total:279  pass:250  dwarn:0   dfail:0   fail:0   skip:29  time:404s

2132c198e6afd4ed75e89eee86c40c7def49c1dc drm-tip: 2017y-07m-06d-20h-24m-04s UTC integration manifest
7fa9ba8 drm/i915/cnl: Avoid old DDI translation functions on Cannonlake.
c7942ac drm/i915/cnl: Dump the right pll registers when dumping pipe config.
23b05f2 drm/i915/cnl: Add allowed DP rates for Cannonlake.

== Logs ==

For more details see: https://intel-gfx-ci.01.org/CI/Patchwork_5132/
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Re: [PATCH 1/3] drm/i915/cnl: Add allowed DP rates for Cannonlake.

[Rodrigo Vivi]

Clint or Mika, could you please review this patch and next 2 here?

I remember Clint telling me at some point that rates had possibly
change on spec but I checked here and I still see:
"eDP/DP link bit rates: 1.62, 2.16, 2.7, 3.24, 4.32, 5.4, 6.48*, 8.1* GHz"

Thanks in advance,
Rodrigo.

On Thu, Jul 6, 2017 at 1:54 PM, Rodrigo Vivi <rodrigo.vivi@intel.com> wrote:
> One warning is that in order to get DPLL Link rates
> 3240 and 4050 that allows 648000 and 810000 is that:
> "Some SKUs may require elevated I/O voltage to support
> this."
>
> v2: Rebase on top of source_rates changes.
>
> Cc: Clint Taylor <clinton.a.taylor@intel.com>
> Cc: Mika Kahola <mika.kahola@intel.com>
> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
> ---
>  drivers/gpu/drm/i915/intel_dp.c | 6 ++++++
>  1 file changed, 6 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> index 2d42d09..4355bdf 100644
> --- a/drivers/gpu/drm/i915/intel_dp.c
> +++ b/drivers/gpu/drm/i915/intel_dp.c
> @@ -97,6 +97,9 @@ struct dp_link_dpll {
>                                   324000, 432000, 540000 };
>  static const int skl_rates[] = { 162000, 216000, 270000,
>                                   324000, 432000, 540000 };
> +static const int cnl_rates[] = { 162000, 216000, 270000,
> +                                324000, 432000, 540000,
> +                                648000, 810000 };
>  static const int default_rates[] = { 162000, 270000, 540000 };
>
>  /**
> @@ -238,6 +241,9 @@ int intel_dp_max_lane_count(struct intel_dp *intel_dp)
>         if (IS_GEN9_LP(dev_priv)) {
>                 source_rates = bxt_rates;
>                 size = ARRAY_SIZE(bxt_rates);
> +       } else if (IS_CANNONLAKE(dev_priv)) {
> +               source_rates = cnl_rates;
> +               size = ARRAY_SIZE(cnl_rates);
>         } else if (IS_GEN9_BC(dev_priv)) {
>                 source_rates = skl_rates;
>                 size = ARRAY_SIZE(skl_rates);
> --
> 1.9.1
>
> _______________________________________________
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> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx



-- 
Rodrigo Vivi
Blog: http://blog.vivi.eng.br
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Re: [PATCH 1/3] drm/i915/cnl: Add allowed DP rates for Cannonlake.

[Mika Kahola]

On Thu, 2017-07-06 at 13:54 -0700, Rodrigo Vivi wrote:
> One warning is that in order to get DPLL Link rates
> 3240 and 4050 that allows 648000 and 810000 is that:
> "Some SKUs may require elevated I/O voltage to support
> this."
I also found a mention in BSpec 

"Frequencies over 5.4 GHz only supported on certain DDI ports and SKUs"

The only difference between SKUs that I spotted was related to DDI D
port speeds. If BSpec is correct, then we should somehow separate the
max port speeds for DDI D port.

> 
> v2: Rebase on top of source_rates changes.
> 
> Cc: Clint Taylor <clinton.a.taylor@intel.com>
> Cc: Mika Kahola <mika.kahola@intel.com>
> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
> ---
>  drivers/gpu/drm/i915/intel_dp.c | 6 ++++++
>  1 file changed, 6 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/intel_dp.c
> b/drivers/gpu/drm/i915/intel_dp.c
> index 2d42d09..4355bdf 100644
> --- a/drivers/gpu/drm/i915/intel_dp.c
> +++ b/drivers/gpu/drm/i915/intel_dp.c
> @@ -97,6 +97,9 @@ struct dp_link_dpll {
>  				  324000, 432000, 540000 };
>  static const int skl_rates[] = { 162000, 216000, 270000,
>  				  324000, 432000, 540000 };
> +static const int cnl_rates[] = { 162000, 216000, 270000,
> +				 324000, 432000, 540000,
> +				 648000, 810000 };
>  static const int default_rates[] = { 162000, 270000, 540000 };
>  
>  /**
> @@ -238,6 +241,9 @@ int intel_dp_max_lane_count(struct intel_dp
> *intel_dp)
>  	if (IS_GEN9_LP(dev_priv)) {
>  		source_rates = bxt_rates;
>  		size = ARRAY_SIZE(bxt_rates);
> +	} else if (IS_CANNONLAKE(dev_priv)) {
> +		source_rates = cnl_rates;
> +		size = ARRAY_SIZE(cnl_rates);
>  	} else if (IS_GEN9_BC(dev_priv)) {
>  		source_rates = skl_rates;
>  		size = ARRAY_SIZE(skl_rates);
-- 
Mika Kahola - Intel OTC

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Re: [PATCH 2/3] drm/i915/cnl: Dump the right pll registers when dumping pipe config.

[Mika Kahola]

On Thu, 2017-07-06 at 13:54 -0700, Rodrigo Vivi wrote:
> Different from SKL we don't need ctrl1 and cfgcr2, but
> we need to dump cfgcr0 amd cfgcr1 instead.

With minor typo fixed in commit message, this is

Reviewed-by: Mika Kahola <mika.kahola@intel.com>

> 
> v2: rebase and commit message
> 
> Cc: Clint Taylor <clinton.a.taylor@intel.com>
> Cc: Mika Kahola <mika.kahola@intel.com>
> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
> ---
>  drivers/gpu/drm/i915/intel_dpll_mgr.c | 11 ++++++++++-
>  1 file changed, 10 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_dpll_mgr.c
> b/drivers/gpu/drm/i915/intel_dpll_mgr.c
> index 2f7b0e6..a2a3d93 100644
> --- a/drivers/gpu/drm/i915/intel_dpll_mgr.c
> +++ b/drivers/gpu/drm/i915/intel_dpll_mgr.c
> @@ -2379,6 +2379,15 @@ static bool cnl_ddi_hdmi_pll_dividers(struct
> intel_crtc *crtc,
>  	return pll;
>  }
>  
> +static void cnl_dump_hw_state(struct drm_i915_private *dev_priv,
> +			      struct intel_dpll_hw_state *hw_state)
> +{
> +	DRM_DEBUG_KMS("dpll_hw_state: "
> +		      "cfgcr0: 0x%x, cfgcr1: 0x%x\n",
> +		      hw_state->cfgcr0,
> +		      hw_state->cfgcr1);
> +}
> +
>  static const struct intel_shared_dpll_funcs cnl_ddi_pll_funcs = {
>  	.enable = cnl_ddi_pll_enable,
>  	.disable = cnl_ddi_pll_disable,
> @@ -2395,7 +2404,7 @@ static bool cnl_ddi_hdmi_pll_dividers(struct
> intel_crtc *crtc,
>  static const struct intel_dpll_mgr cnl_pll_mgr = {
>  	.dpll_info = cnl_plls,
>  	.get_dpll = cnl_get_dpll,
> -	.dump_hw_state = skl_dump_hw_state,
> +	.dump_hw_state = cnl_dump_hw_state,
>  };
>  
>  /**
-- 
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[PATCH] drm/i915/cnl: Add allowed DP rates for Cannonlake.

[Rodrigo Vivi]

"Frequencies over 5.4 GHz only supported on certain
DDI ports and SKUs, and requires Vccio >= 0.95V."

More specifically, for current CNL SKUs available
(CNL-U and CNL-Y) we have:

DDI A - 5.4G eDP
DDI B - 8.1G DP
DDI C - 8.1G DP
DDI D - 5.4G DP

v2: Rebase on top of source_rates changes.
v3: Address the max 5.4 x 8.1 per DDI and also consider vccio.

Cc: Mika Kahola <mika.kahola@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
---
 drivers/gpu/drm/i915/intel_dp.c | 12 ++++++++++++
 1 file changed, 12 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 76c8a0bd17f9..ead37c449019 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -97,6 +97,9 @@ static const int bxt_rates[] = { 162000, 216000, 243000, 270000,
 				  324000, 432000, 540000 };
 static const int skl_rates[] = { 162000, 216000, 270000,
 				  324000, 432000, 540000 };
+static const int cnl_rates[] = { 162000, 216000, 270000,
+				 324000, 432000, 540000,
+				 648000, 810000 };
 static const int default_rates[] = { 162000, 270000, 540000 };
 
 /**
@@ -229,8 +232,10 @@ intel_dp_set_source_rates(struct intel_dp *intel_dp)
 {
 	struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
 	struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
+	enum port port = dig_port->port;
 	const int *source_rates;
 	int size;
+	u32 voltage;
 
 	/* This should only be done once */
 	WARN_ON(intel_dp->source_rates || intel_dp->num_source_rates);
@@ -238,6 +243,13 @@ intel_dp_set_source_rates(struct intel_dp *intel_dp)
 	if (IS_GEN9_LP(dev_priv)) {
 		source_rates = bxt_rates;
 		size = ARRAY_SIZE(bxt_rates);
+	} else if (IS_CANNONLAKE(dev_priv)) {
+		source_rates = cnl_rates;
+		size = ARRAY_SIZE(cnl_rates);
+		voltage = I915_READ(CNL_PORT_COMP_DW3) & VOLTAGE_INFO_MASK;
+		if (port == PORT_A || port == PORT_D ||
+		    voltage == VOLTAGE_INFO_0_85V)
+			size -= 2;
 	} else if (IS_GEN9_BC(dev_priv)) {
 		source_rates = skl_rates;
 		size = ARRAY_SIZE(skl_rates);
-- 
2.13.2

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Re: [PATCH] drm/i915/cnl: Add allowed DP rates for Cannonlake.

[Manasi Navare]

Verified this as per the Bspec and it looks good.

Manasi

On Thu, Aug 10, 2017 at 03:40:08PM -0700, Rodrigo Vivi wrote:
> "Frequencies over 5.4 GHz only supported on certain
> DDI ports and SKUs, and requires Vccio >= 0.95V."
> 
> More specifically, for current CNL SKUs available
> (CNL-U and CNL-Y) we have:
> 
> DDI A - 5.4G eDP
> DDI B - 8.1G DP
> DDI C - 8.1G DP
> DDI D - 5.4G DP
> 
> v2: Rebase on top of source_rates changes.
> v3: Address the max 5.4 x 8.1 per DDI and also consider vccio.
> 
> Cc: Mika Kahola <mika.kahola@intel.com>
> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
 Reviewed-by: Manasi Navare <manasi.d.navare@intel.com>
> ---
>  drivers/gpu/drm/i915/intel_dp.c | 12 ++++++++++++
>  1 file changed, 12 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> index 76c8a0bd17f9..ead37c449019 100644
> --- a/drivers/gpu/drm/i915/intel_dp.c
> +++ b/drivers/gpu/drm/i915/intel_dp.c
> @@ -97,6 +97,9 @@ static const int bxt_rates[] = { 162000, 216000, 243000, 270000,
>  				  324000, 432000, 540000 };
>  static const int skl_rates[] = { 162000, 216000, 270000,
>  				  324000, 432000, 540000 };
> +static const int cnl_rates[] = { 162000, 216000, 270000,
> +				 324000, 432000, 540000,
> +				 648000, 810000 };
>  static const int default_rates[] = { 162000, 270000, 540000 };
>  
>  /**
> @@ -229,8 +232,10 @@ intel_dp_set_source_rates(struct intel_dp *intel_dp)
>  {
>  	struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
>  	struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
> +	enum port port = dig_port->port;
>  	const int *source_rates;
>  	int size;
> +	u32 voltage;
>  
>  	/* This should only be done once */
>  	WARN_ON(intel_dp->source_rates || intel_dp->num_source_rates);
> @@ -238,6 +243,13 @@ intel_dp_set_source_rates(struct intel_dp *intel_dp)
>  	if (IS_GEN9_LP(dev_priv)) {
>  		source_rates = bxt_rates;
>  		size = ARRAY_SIZE(bxt_rates);
> +	} else if (IS_CANNONLAKE(dev_priv)) {
> +		source_rates = cnl_rates;
> +		size = ARRAY_SIZE(cnl_rates);
> +		voltage = I915_READ(CNL_PORT_COMP_DW3) & VOLTAGE_INFO_MASK;
> +		if (port == PORT_A || port == PORT_D ||
> +		    voltage == VOLTAGE_INFO_0_85V)
> +			size -= 2;
>  	} else if (IS_GEN9_BC(dev_priv)) {
>  		source_rates = skl_rates;
>  		size = ARRAY_SIZE(skl_rates);
> -- 
> 2.13.2
> 
> _______________________________________________
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> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
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✓ Fi.CI.BAT: success for series starting with drm/i915/cnl: Add allowed DP rates for Cannonlake. (rev2)

[Patchwork]

== Series Details ==

Series: series starting with drm/i915/cnl: Add allowed DP rates for Cannonlake. (rev2)
URL   : https://patchwork.freedesktop.org/series/26952/
State : success

== Summary ==

Series 26952v2 Series without cover letter
https://patchwork.freedesktop.org/api/1.0/series/26952/revisions/2/mbox/

Test kms_cursor_legacy:
        Subgroup basic-busy-flip-before-cursor-legacy:
                fail       -> PASS       (fi-snb-2600) fdo#100215

fdo#100215 https://bugs.freedesktop.org/show_bug.cgi?id=100215

fi-bdw-5557u     total:279  pass:268  dwarn:0   dfail:0   fail:0   skip:11  time:448s
fi-bdw-gvtdvm    total:279  pass:265  dwarn:0   dfail:0   fail:0   skip:14  time:433s
fi-blb-e6850     total:279  pass:224  dwarn:1   dfail:0   fail:0   skip:54  time:358s
fi-bsw-n3050     total:279  pass:243  dwarn:0   dfail:0   fail:0   skip:36  time:552s
fi-bxt-j4205     total:279  pass:260  dwarn:0   dfail:0   fail:0   skip:19  time:518s
fi-byt-j1900     total:279  pass:254  dwarn:1   dfail:0   fail:0   skip:24  time:526s
fi-glk-2a        total:279  pass:260  dwarn:0   dfail:0   fail:0   skip:19  time:604s
fi-hsw-4770      total:279  pass:263  dwarn:0   dfail:0   fail:0   skip:16  time:439s
fi-hsw-4770r     total:279  pass:263  dwarn:0   dfail:0   fail:0   skip:16  time:420s
fi-ilk-650       total:279  pass:229  dwarn:0   dfail:0   fail:0   skip:50  time:414s
fi-ivb-3520m     total:279  pass:261  dwarn:0   dfail:0   fail:0   skip:18  time:508s
fi-ivb-3770      total:279  pass:261  dwarn:0   dfail:0   fail:0   skip:18  time:479s
fi-kbl-7500u     total:279  pass:261  dwarn:0   dfail:0   fail:0   skip:18  time:474s
fi-kbl-7560u     total:279  pass:269  dwarn:0   dfail:0   fail:0   skip:10  time:589s
fi-kbl-r         total:279  pass:261  dwarn:0   dfail:0   fail:0   skip:18  time:595s
fi-pnv-d510      total:279  pass:223  dwarn:1   dfail:0   fail:0   skip:55  time:529s
fi-skl-6260u     total:279  pass:269  dwarn:0   dfail:0   fail:0   skip:10  time:464s
fi-skl-6700k     total:279  pass:261  dwarn:0   dfail:0   fail:0   skip:18  time:470s
fi-skl-6770hq    total:279  pass:269  dwarn:0   dfail:0   fail:0   skip:10  time:476s
fi-skl-gvtdvm    total:279  pass:266  dwarn:0   dfail:0   fail:0   skip:13  time:446s
fi-skl-x1585l    total:279  pass:268  dwarn:0   dfail:0   fail:0   skip:11  time:485s
fi-snb-2520m     total:279  pass:251  dwarn:0   dfail:0   fail:0   skip:28  time:549s
fi-snb-2600      total:279  pass:250  dwarn:0   dfail:0   fail:0   skip:29  time:409s

a8f0812284aa77e62aba1e4b430ac3bc090f43d0 drm-tip: 2017y-08m-11d-07h-22m-37s UTC integration manifest
9cda511c78ee drm/i915/cnl: Avoid old DDI translation functions on Cannonlake.
54daadd97d88 drm/i915/cnl: Dump the right pll registers when dumping pipe config.
75362f1ff342 drm/i915/cnl: Add allowed DP rates for Cannonlake.

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_5373/
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Re: [PATCH] drm/i915/cnl: Add allowed DP rates for Cannonlake.

[Rodrigo Vivi]

On Thu, Aug 10, 2017 at 5:19 PM, Manasi Navare
<manasi.d.navare@intel.com> wrote:
> Verified this as per the Bspec and it looks good.
>
> Manasi
>
> On Thu, Aug 10, 2017 at 03:40:08PM -0700, Rodrigo Vivi wrote:
>> "Frequencies over 5.4 GHz only supported on certain
>> DDI ports and SKUs, and requires Vccio >= 0.95V."
>>
>> More specifically, for current CNL SKUs available
>> (CNL-U and CNL-Y) we have:
>>
>> DDI A - 5.4G eDP
>> DDI B - 8.1G DP
>> DDI C - 8.1G DP
>> DDI D - 5.4G DP
>>
>> v2: Rebase on top of source_rates changes.
>> v3: Address the max 5.4 x 8.1 per DDI and also consider vccio.
>>
>> Cc: Mika Kahola <mika.kahola@intel.com>
>> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
>  Reviewed-by: Manasi Navare <manasi.d.navare@intel.com>

it is funny that patchwork continue to refuse to get your rv-b automatically...
probably a lack of blank lines before and/or after?  does anyone know
why that happens?

merge to dinq. thanks for the reviews.

>> ---
>>  drivers/gpu/drm/i915/intel_dp.c | 12 ++++++++++++
>>  1 file changed, 12 insertions(+)
>>
>> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
>> index 76c8a0bd17f9..ead37c449019 100644
>> --- a/drivers/gpu/drm/i915/intel_dp.c
>> +++ b/drivers/gpu/drm/i915/intel_dp.c
>> @@ -97,6 +97,9 @@ static const int bxt_rates[] = { 162000, 216000, 243000, 270000,
>>                                 324000, 432000, 540000 };
>>  static const int skl_rates[] = { 162000, 216000, 270000,
>>                                 324000, 432000, 540000 };
>> +static const int cnl_rates[] = { 162000, 216000, 270000,
>> +                              324000, 432000, 540000,
>> +                              648000, 810000 };
>>  static const int default_rates[] = { 162000, 270000, 540000 };
>>
>>  /**
>> @@ -229,8 +232,10 @@ intel_dp_set_source_rates(struct intel_dp *intel_dp)
>>  {
>>       struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
>>       struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
>> +     enum port port = dig_port->port;
>>       const int *source_rates;
>>       int size;
>> +     u32 voltage;
>>
>>       /* This should only be done once */
>>       WARN_ON(intel_dp->source_rates || intel_dp->num_source_rates);
>> @@ -238,6 +243,13 @@ intel_dp_set_source_rates(struct intel_dp *intel_dp)
>>       if (IS_GEN9_LP(dev_priv)) {
>>               source_rates = bxt_rates;
>>               size = ARRAY_SIZE(bxt_rates);
>> +     } else if (IS_CANNONLAKE(dev_priv)) {
>> +             source_rates = cnl_rates;
>> +             size = ARRAY_SIZE(cnl_rates);
>> +             voltage = I915_READ(CNL_PORT_COMP_DW3) & VOLTAGE_INFO_MASK;
>> +             if (port == PORT_A || port == PORT_D ||
>> +                 voltage == VOLTAGE_INFO_0_85V)
>> +                     size -= 2;
>>       } else if (IS_GEN9_BC(dev_priv)) {
>>               source_rates = skl_rates;
>>               size = ARRAY_SIZE(skl_rates);
>> --
>> 2.13.2
>>
>> _______________________________________________
>> Intel-gfx mailing list
>> Intel-gfx@lists.freedesktop.org
>> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx



-- 
Rodrigo Vivi
Blog: http://blog.vivi.eng.br
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Re: [PATCH 3/3] drm/i915/cnl: Avoid old DDI translation functions on Cannonlake.

[Mika Kahola]

On Thu, 2017-07-06 at 13:54 -0700, Rodrigo Vivi wrote:
> Cannonlake uses a different swing voltage initalization
> sequence scheme that doesn't require these old functions.
> 
> All other DDI, voltage swing and PLLs initialialization
> and configuration are already in place for Cannonlake.
> This patch only removes unecessary steps probably saving
> us from some useless warnings.
> 
> Cc: Clint Taylor <clinton.a.taylor@intel.com>
> Cc: Mika Kahola <mika.kahola@intel.com>
> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
> ---
>  drivers/gpu/drm/i915/intel_ddi.c | 6 +++---
>  1 file changed, 3 insertions(+), 3 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_ddi.c
> b/drivers/gpu/drm/i915/intel_ddi.c
> index 80e96f1..9e9bfbe 100644
> --- a/drivers/gpu/drm/i915/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/intel_ddi.c
> @@ -596,7 +596,7 @@ static int intel_ddi_hdmi_level(struct
> drm_i915_private *dev_priv, enum port por
>  
>  	hdmi_level = dev_priv-
> >vbt.ddi_port_info[port].hdmi_level_shift;
>  
> -	if (IS_GEN9_LP(dev_priv))
> +	if (IS_GEN9_LP(dev_priv) || INTEL_GEN(dev_priv) >= 10)
Can we assume that this holds always for GEN10 and above platforms?
 
>  		return hdmi_level;
>  
>  	if (IS_GEN9_BC(dev_priv)) {
> @@ -688,7 +688,7 @@ static void intel_prepare_dp_ddi_buffers(struct
> intel_encoder *encoder)
>  	enum port port = intel_ddi_get_encoder_port(encoder);
>  	const struct ddi_buf_trans *ddi_translations;
>  
> -	if (IS_GEN9_LP(dev_priv))
> +	if (IS_GEN9_LP(dev_priv) || INTEL_GEN(dev_priv) >= 10)
>  		return;
>  
>  	switch (encoder->type) {
> @@ -741,7 +741,7 @@ static void intel_prepare_hdmi_ddi_buffers(struct
> intel_encoder *encoder)
>  	enum port port = intel_ddi_get_encoder_port(encoder);
>  	const struct ddi_buf_trans *ddi_translations_hdmi;
>  
> -	if (IS_GEN9_LP(dev_priv))
> +	if (IS_GEN9_LP(dev_priv) || INTEL_GEN(dev_priv) >= 10)
>  		return;
>  
>  	hdmi_level = intel_ddi_hdmi_level(dev_priv, port);
-- 
Mika Kahola - Intel OTC

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Re: [PATCH 3/3] drm/i915/cnl: Avoid old DDI translation functions on Cannonlake.

[Vivi, Rodrigo]

On Thu, 2017-08-17 at 15:59 +0300, Mika Kahola wrote:
> On Thu, 2017-07-06 at 13:54 -0700, Rodrigo Vivi wrote:
> > Cannonlake uses a different swing voltage initalization
> > sequence scheme that doesn't require these old functions.
> > 
> > All other DDI, voltage swing and PLLs initialialization
> > and configuration are already in place for Cannonlake.
> > This patch only removes unecessary steps probably saving
> > us from some useless warnings.
> > 
> > Cc: Clint Taylor <clinton.a.taylor@intel.com>
> > Cc: Mika Kahola <mika.kahola@intel.com>
> > Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
> > ---
> >  drivers/gpu/drm/i915/intel_ddi.c | 6 +++---
> >  1 file changed, 3 insertions(+), 3 deletions(-)
> > 
> > diff --git a/drivers/gpu/drm/i915/intel_ddi.c
> > b/drivers/gpu/drm/i915/intel_ddi.c
> > index 80e96f1..9e9bfbe 100644
> > --- a/drivers/gpu/drm/i915/intel_ddi.c
> > +++ b/drivers/gpu/drm/i915/intel_ddi.c
> > @@ -596,7 +596,7 @@ static int intel_ddi_hdmi_level(struct
> > drm_i915_private *dev_priv, enum port por
> >  
> >  	hdmi_level = dev_priv-
> > >vbt.ddi_port_info[port].hdmi_level_shift;
> >  
> > -	if (IS_GEN9_LP(dev_priv))
> > +	if (IS_GEN9_LP(dev_priv) || INTEL_GEN(dev_priv) >= 10)
> Can we assume that this holds always for GEN10 and above platforms?

Hi Mika, thanks for looking, but please ignore this patch here.

I should have told earlier, sorry, but this patch should be replaced by:

https://patchwork.freedesktop.org/series/28883/

reviews and suggestions there are welcome...

Thanks,
Rodrigo.

>  
> >  		return hdmi_level;
> >  
> >  	if (IS_GEN9_BC(dev_priv)) {
> > @@ -688,7 +688,7 @@ static void intel_prepare_dp_ddi_buffers(struct
> > intel_encoder *encoder)
> >  	enum port port = intel_ddi_get_encoder_port(encoder);
> >  	const struct ddi_buf_trans *ddi_translations;
> >  
> > -	if (IS_GEN9_LP(dev_priv))
> > +	if (IS_GEN9_LP(dev_priv) || INTEL_GEN(dev_priv) >= 10)
> >  		return;
> >  
> >  	switch (encoder->type) {
> > @@ -741,7 +741,7 @@ static void intel_prepare_hdmi_ddi_buffers(struct
> > intel_encoder *encoder)
> >  	enum port port = intel_ddi_get_encoder_port(encoder);
> >  	const struct ddi_buf_trans *ddi_translations_hdmi;
> >  
> > -	if (IS_GEN9_LP(dev_priv))
> > +	if (IS_GEN9_LP(dev_priv) || INTEL_GEN(dev_priv) >= 10)
> >  		return;
> >  
> >  	hdmi_level = intel_ddi_hdmi_level(dev_priv, port);

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