Re: [PATCH 2/3] drm/i915/cnl: Dump the right pll registers when dumping pipe config.

[Mika Kahola <mika.kahola@intel.com>]

On Thu, 2017-07-06 at 13:54 -0700, Rodrigo Vivi wrote:
> Different from SKL we don't need ctrl1 and cfgcr2, but
> we need to dump cfgcr0 amd cfgcr1 instead.

With minor typo fixed in commit message, this is

Reviewed-by: Mika Kahola <mika.kahola@intel.com>

> 
> v2: rebase and commit message
> 
> Cc: Clint Taylor <clinton.a.taylor@intel.com>
> Cc: Mika Kahola <mika.kahola@intel.com>
> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
> ---
>  drivers/gpu/drm/i915/intel_dpll_mgr.c | 11 ++++++++++-
>  1 file changed, 10 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_dpll_mgr.c
> b/drivers/gpu/drm/i915/intel_dpll_mgr.c
> index 2f7b0e6..a2a3d93 100644
> --- a/drivers/gpu/drm/i915/intel_dpll_mgr.c
> +++ b/drivers/gpu/drm/i915/intel_dpll_mgr.c
> @@ -2379,6 +2379,15 @@ static bool cnl_ddi_hdmi_pll_dividers(struct
> intel_crtc *crtc,
>  	return pll;
>  }
>  
> +static void cnl_dump_hw_state(struct drm_i915_private *dev_priv,
> +			      struct intel_dpll_hw_state *hw_state)
> +{
> +	DRM_DEBUG_KMS("dpll_hw_state: "
> +		      "cfgcr0: 0x%x, cfgcr1: 0x%x\n",
> +		      hw_state->cfgcr0,
> +		      hw_state->cfgcr1);
> +}
> +
>  static const struct intel_shared_dpll_funcs cnl_ddi_pll_funcs = {
>  	.enable = cnl_ddi_pll_enable,
>  	.disable = cnl_ddi_pll_disable,
> @@ -2395,7 +2404,7 @@ static bool cnl_ddi_hdmi_pll_dividers(struct
> intel_crtc *crtc,
>  static const struct intel_dpll_mgr cnl_pll_mgr = {
>  	.dpll_info = cnl_plls,
>  	.get_dpll = cnl_get_dpll,
> -	.dump_hw_state = skl_dump_hw_state,
> +	.dump_hw_state = cnl_dump_hw_state,
>  };
>  
>  /**
-- 
Mika Kahola - Intel OTC

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