* [PATCH] drm/i915/cnl: WaFbcSkipSegments
@ 2017-08-29 23:08 Rodrigo Vivi
2017-08-29 23:59 ` ✓ Fi.CI.BAT: success for " Patchwork
` (6 more replies)
0 siblings, 7 replies; 17+ messages in thread
From: Rodrigo Vivi @ 2017-08-29 23:08 UTC (permalink / raw)
To: intel-gfx; +Cc: Paulo Zanoni, Rodrigo Vivi
Skip compressing 1 segment at the end of the frame,
avoid a pixel count mismatch nuke event when last active
pixel and dummy pixel has same color for Odd Plane
Width / Height.
Cc: Paulo Zanoni <paulo.r.zanoni@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
---
drivers/gpu/drm/i915/i915_reg.h | 2 ++
drivers/gpu/drm/i915/intel_pm.c | 4 ++++
2 files changed, 6 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index e2908ae34004..0072ef79bf34 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -2939,6 +2939,8 @@ enum i915_power_well_id {
#define ILK_DPFC_CHICKEN _MMIO(0x43224)
#define ILK_DPFC_DISABLE_DUMMY0 (1<<8)
#define ILK_DPFC_NUKE_ON_ANY_MODIFICATION (1<<23)
+#define CNL_SKIP_SEG_EN (1<<12)
+#define CNL_SKIP_SEG_COUNT (1<<10)
#define ILK_FBC_RT_BASE _MMIO(0x2128)
#define ILK_FBC_RT_VALID (1<<0)
#define SNB_FBC_FRONT_BUFFER (1<<1)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index d5ff0b9f999f..acf793256507 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -8283,6 +8283,10 @@ static void cannonlake_init_clock_gating(struct drm_i915_private *dev_priv)
I915_WRITE(SLICE_UNIT_LEVEL_CLKGATE,
I915_READ(SLICE_UNIT_LEVEL_CLKGATE) |
SARBUNIT_CLKGATE_DIS);
+
+ /* WaFbcSkipSegments:cnl */
+ I915_WRITE(ILK_DPFC_CHICKEN, I915_READ(ILK_DPFC_CHICKEN) |
+ CNL_SKIP_SEG_EN | CNL_SKIP_SEG_COUNT);
}
static void kabylake_init_clock_gating(struct drm_i915_private *dev_priv)
--
2.13.2
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^ permalink raw reply related [flat|nested] 17+ messages in thread* ✓ Fi.CI.BAT: success for drm/i915/cnl: WaFbcSkipSegments
2017-08-29 23:08 [PATCH] drm/i915/cnl: WaFbcSkipSegments Rodrigo Vivi
@ 2017-08-29 23:59 ` Patchwork
2017-08-30 3:40 ` ✗ Fi.CI.IGT: failure " Patchwork
` (5 subsequent siblings)
6 siblings, 0 replies; 17+ messages in thread
From: Patchwork @ 2017-08-29 23:59 UTC (permalink / raw)
To: Rodrigo Vivi; +Cc: intel-gfx
== Series Details ==
Series: drm/i915/cnl: WaFbcSkipSegments
URL : https://patchwork.freedesktop.org/series/29507/
State : success
== Summary ==
Series 29507v1 drm/i915/cnl: WaFbcSkipSegments
https://patchwork.freedesktop.org/api/1.0/series/29507/revisions/1/mbox/
Test gem_ringfill:
Subgroup basic-default-hang:
incomplete -> DMESG-WARN (fi-pnv-d510) fdo#101600
Test kms_cursor_legacy:
Subgroup basic-busy-flip-before-cursor-legacy:
pass -> FAIL (fi-snb-2600) fdo#100215
Test kms_flip:
Subgroup basic-flip-vs-modeset:
pass -> SKIP (fi-skl-x1585l) fdo#101781
Test kms_frontbuffer_tracking:
Subgroup basic:
dmesg-warn -> PASS (fi-bdw-5557u)
fdo#101600 https://bugs.freedesktop.org/show_bug.cgi?id=101600
fdo#100215 https://bugs.freedesktop.org/show_bug.cgi?id=100215
fdo#101781 https://bugs.freedesktop.org/show_bug.cgi?id=101781
fi-bdw-5557u total:279 pass:268 dwarn:0 dfail:0 fail:0 skip:11 time:454s
fi-bdw-gvtdvm total:279 pass:265 dwarn:0 dfail:0 fail:0 skip:14 time:448s
fi-blb-e6850 total:279 pass:224 dwarn:1 dfail:0 fail:0 skip:54 time:359s
fi-bsw-n3050 total:279 pass:243 dwarn:0 dfail:0 fail:0 skip:36 time:561s
fi-bwr-2160 total:279 pass:184 dwarn:0 dfail:0 fail:0 skip:95 time:252s
fi-bxt-j4205 total:279 pass:260 dwarn:0 dfail:0 fail:0 skip:19 time:522s
fi-byt-j1900 total:279 pass:254 dwarn:1 dfail:0 fail:0 skip:24 time:516s
fi-byt-n2820 total:279 pass:250 dwarn:1 dfail:0 fail:0 skip:28 time:519s
fi-elk-e7500 total:279 pass:230 dwarn:0 dfail:0 fail:0 skip:49 time:437s
fi-glk-2a total:279 pass:260 dwarn:0 dfail:0 fail:0 skip:19 time:610s
fi-hsw-4770 total:279 pass:263 dwarn:0 dfail:0 fail:0 skip:16 time:441s
fi-hsw-4770r total:279 pass:263 dwarn:0 dfail:0 fail:0 skip:16 time:430s
fi-ilk-650 total:279 pass:229 dwarn:0 dfail:0 fail:0 skip:50 time:427s
fi-ivb-3520m total:279 pass:261 dwarn:0 dfail:0 fail:0 skip:18 time:493s
fi-ivb-3770 total:279 pass:261 dwarn:0 dfail:0 fail:0 skip:18 time:472s
fi-kbl-7500u total:279 pass:261 dwarn:0 dfail:0 fail:0 skip:18 time:477s
fi-kbl-7560u total:279 pass:269 dwarn:0 dfail:0 fail:0 skip:10 time:600s
fi-kbl-r total:279 pass:261 dwarn:0 dfail:0 fail:0 skip:18 time:594s
fi-pnv-d510 total:279 pass:223 dwarn:1 dfail:0 fail:0 skip:55 time:519s
fi-skl-6260u total:279 pass:269 dwarn:0 dfail:0 fail:0 skip:10 time:472s
fi-skl-6770hq total:279 pass:269 dwarn:0 dfail:0 fail:0 skip:10 time:489s
fi-skl-gvtdvm total:279 pass:266 dwarn:0 dfail:0 fail:0 skip:13 time:444s
fi-skl-x1585l total:279 pass:268 dwarn:0 dfail:0 fail:0 skip:11 time:483s
fi-snb-2520m total:279 pass:251 dwarn:0 dfail:0 fail:0 skip:28 time:545s
fi-snb-2600 total:279 pass:249 dwarn:0 dfail:0 fail:1 skip:29 time:404s
fi-skl-6700k failed to connect after reboot
428ed27345fbf9be530d01ca6dc862eb5895db81 drm-tip: 2017y-08m-29d-17h-43m-11s UTC integration manifest
5b3a4809fc72 drm/i915/cnl: WaFbcSkipSegments
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_5532/
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^ permalink raw reply [flat|nested] 17+ messages in thread* ✗ Fi.CI.IGT: failure for drm/i915/cnl: WaFbcSkipSegments
2017-08-29 23:08 [PATCH] drm/i915/cnl: WaFbcSkipSegments Rodrigo Vivi
2017-08-29 23:59 ` ✓ Fi.CI.BAT: success for " Patchwork
@ 2017-08-30 3:40 ` Patchwork
2017-09-01 21:04 ` [PATCH] " Paulo Zanoni
` (4 subsequent siblings)
6 siblings, 0 replies; 17+ messages in thread
From: Patchwork @ 2017-08-30 3:40 UTC (permalink / raw)
To: Rodrigo Vivi; +Cc: intel-gfx
== Series Details ==
Series: drm/i915/cnl: WaFbcSkipSegments
URL : https://patchwork.freedesktop.org/series/29507/
State : failure
== Summary ==
Test kms_setmode:
Subgroup basic:
fail -> PASS (shard-hsw) fdo#99912
Test perf:
Subgroup polling:
pass -> FAIL (shard-hsw) fdo#102252
Test kms_flip:
Subgroup plain-flip-fb-recreate-interruptible:
pass -> FAIL (shard-hsw)
Test kms_cursor_legacy:
Subgroup short-flip-before-cursor-atomic-transitions-varying-size:
skip -> PASS (shard-hsw)
fdo#99912 https://bugs.freedesktop.org/show_bug.cgi?id=99912
fdo#102252 https://bugs.freedesktop.org/show_bug.cgi?id=102252
shard-hsw total:2230 pass:1229 dwarn:0 dfail:0 fail:19 skip:982 time:9540s
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_5532/shards.html
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^ permalink raw reply [flat|nested] 17+ messages in thread* Re: [PATCH] drm/i915/cnl: WaFbcSkipSegments
2017-08-29 23:08 [PATCH] drm/i915/cnl: WaFbcSkipSegments Rodrigo Vivi
2017-08-29 23:59 ` ✓ Fi.CI.BAT: success for " Patchwork
2017-08-30 3:40 ` ✗ Fi.CI.IGT: failure " Patchwork
@ 2017-09-01 21:04 ` Paulo Zanoni
2017-09-01 21:31 ` Rodrigo Vivi
2017-09-05 18:23 ` ✓ Fi.CI.BAT: success for drm/i915/cnl: WaFbcSkipSegments (rev3) Patchwork
` (3 subsequent siblings)
6 siblings, 1 reply; 17+ messages in thread
From: Paulo Zanoni @ 2017-09-01 21:04 UTC (permalink / raw)
To: Rodrigo Vivi, intel-gfx
Em Ter, 2017-08-29 às 16:08 -0700, Rodrigo Vivi escreveu:
> Skip compressing 1 segment at the end of the frame,
> avoid a pixel count mismatch nuke event when last active
> pixel and dummy pixel has same color for Odd Plane
> Width / Height.
>
> Cc: Paulo Zanoni <paulo.r.zanoni@intel.com>
> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
> ---
> drivers/gpu/drm/i915/i915_reg.h | 2 ++
> drivers/gpu/drm/i915/intel_pm.c | 4 ++++
> 2 files changed, 6 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h
> b/drivers/gpu/drm/i915/i915_reg.h
> index e2908ae34004..0072ef79bf34 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -2939,6 +2939,8 @@ enum i915_power_well_id {
> #define ILK_DPFC_CHICKEN _MMIO(0x43224)
> #define ILK_DPFC_DISABLE_DUMMY0 (1<<8)
> #define ILK_DPFC_NUKE_ON_ANY_MODIFICATION (1<<23)
> +#define CNL_SKIP_SEG_EN (1<<12)
> +#define CNL_SKIP_SEG_COUNT (1<<10)
#define CNL_SKIP_SEG_COUNT_MASK (3 << 10)
#define CNL_SKIP_SEG_COUNT(x) ((x) << 10)
Also, since you're going to submit v2 anyway, I wouldn't complain if
you drive-by fixed the definitions of ILK_DPFC_CHICKEN bits to use
spaces as documented in the beginning of the file. If we fix every time
we touch a reg, we may at some point be consistent :).
> #define ILK_FBC_RT_BASE _MMIO(0x2128)
> #define ILK_FBC_RT_VALID (1<<0)
> #define SNB_FBC_FRONT_BUFFER (1<<1)
> diff --git a/drivers/gpu/drm/i915/intel_pm.c
> b/drivers/gpu/drm/i915/intel_pm.c
> index d5ff0b9f999f..acf793256507 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -8283,6 +8283,10 @@ static void
> cannonlake_init_clock_gating(struct drm_i915_private *dev_priv)
> I915_WRITE(SLICE_UNIT_LEVEL_CLKGATE,
> I915_READ(SLICE_UNIT_LEVEL_CLKGATE) |
> SARBUNIT_CLKGATE_DIS);
> +
> + /* WaFbcSkipSegments:cnl */
Since this is also documented in BSpec but it doesn't include the WA
name, can you please also document that this is WA #1133 in this
comment? I'd do something like:
/* Display WA #1133: WaFbcSkipSegments:cnl,glk. */
Please notice that we also need to apply this WA for GLK.
> + I915_WRITE(ILK_DPFC_CHICKEN, I915_READ(ILK_DPFC_CHICKEN) |
> + CNL_SKIP_SEG_EN | CNL_SKIP_SEG_COUNT);
Need to clear bit 11 too.
val = READ();
val &= ~CNL_SKIP_SEG_COUNT_MASK;
val |= CNL_SKIP_SEG_EN | CNL_SKIP_SEG_COUNT(1);
> }
>
> static void kabylake_init_clock_gating(struct drm_i915_private
> *dev_priv)
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^ permalink raw reply [flat|nested] 17+ messages in thread* Re: [PATCH] drm/i915/cnl: WaFbcSkipSegments
2017-09-01 21:04 ` [PATCH] " Paulo Zanoni
@ 2017-09-01 21:31 ` Rodrigo Vivi
2017-09-04 18:05 ` Paulo Zanoni
0 siblings, 1 reply; 17+ messages in thread
From: Rodrigo Vivi @ 2017-09-01 21:31 UTC (permalink / raw)
To: Paulo Zanoni, Jani Nikula; +Cc: intel-gfx, Rodrigo Vivi
On Fri, Sep 1, 2017 at 2:04 PM, Paulo Zanoni <paulo.r.zanoni@intel.com> wrote:
> Em Ter, 2017-08-29 às 16:08 -0700, Rodrigo Vivi escreveu:
>> Skip compressing 1 segment at the end of the frame,
>> avoid a pixel count mismatch nuke event when last active
>> pixel and dummy pixel has same color for Odd Plane
>> Width / Height.
>>
>> Cc: Paulo Zanoni <paulo.r.zanoni@intel.com>
>> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
>> ---
>> drivers/gpu/drm/i915/i915_reg.h | 2 ++
>> drivers/gpu/drm/i915/intel_pm.c | 4 ++++
>> 2 files changed, 6 insertions(+)
>>
>> diff --git a/drivers/gpu/drm/i915/i915_reg.h
>> b/drivers/gpu/drm/i915/i915_reg.h
>> index e2908ae34004..0072ef79bf34 100644
>> --- a/drivers/gpu/drm/i915/i915_reg.h
>> +++ b/drivers/gpu/drm/i915/i915_reg.h
>> @@ -2939,6 +2939,8 @@ enum i915_power_well_id {
>> #define ILK_DPFC_CHICKEN _MMIO(0x43224)
>> #define ILK_DPFC_DISABLE_DUMMY0 (1<<8)
>> #define ILK_DPFC_NUKE_ON_ANY_MODIFICATION (1<<23)
>> +#define CNL_SKIP_SEG_EN (1<<12)
>> +#define CNL_SKIP_SEG_COUNT (1<<10)
>
> #define CNL_SKIP_SEG_COUNT_MASK (3 << 10)
> #define CNL_SKIP_SEG_COUNT(x) ((x) << 10)
By the definition we should add the SHIFT then as well?
Although we are not going to read ever?!
>
> Also, since you're going to submit v2 anyway, I wouldn't complain if
> you drive-by fixed the definitions of ILK_DPFC_CHICKEN bits to use
> spaces as documented in the beginning of the file. If we fix every time
> we touch a reg, we may at some point be consistent :).
Last patch I tried to fix the style on the same patch Jani nacked it.
So I wonder if we need a bit patch to fix all the style entirely.
>
>
>> #define ILK_FBC_RT_BASE _MMIO(0x2128)
>> #define ILK_FBC_RT_VALID (1<<0)
>> #define SNB_FBC_FRONT_BUFFER (1<<1)
>> diff --git a/drivers/gpu/drm/i915/intel_pm.c
>> b/drivers/gpu/drm/i915/intel_pm.c
>> index d5ff0b9f999f..acf793256507 100644
>> --- a/drivers/gpu/drm/i915/intel_pm.c
>> +++ b/drivers/gpu/drm/i915/intel_pm.c
>> @@ -8283,6 +8283,10 @@ static void
>> cannonlake_init_clock_gating(struct drm_i915_private *dev_priv)
>> I915_WRITE(SLICE_UNIT_LEVEL_CLKGATE,
>> I915_READ(SLICE_UNIT_LEVEL_CLKGATE) |
>> SARBUNIT_CLKGATE_DIS);
>> +
>> + /* WaFbcSkipSegments:cnl */
>
> Since this is also documented in BSpec but it doesn't include the WA
> name, can you please also document that this is WA #1133 in this
> comment? I'd do something like:
>
> /* Display WA #1133: WaFbcSkipSegments:cnl,glk. */
good idea!
>
> Please notice that we also need to apply this WA for GLK.
hm... indeed...
>
>
>> + I915_WRITE(ILK_DPFC_CHICKEN, I915_READ(ILK_DPFC_CHICKEN) |
>> + CNL_SKIP_SEG_EN | CNL_SKIP_SEG_COUNT);
>
> Need to clear bit 11 too.
ouch! yeap!
Thanks,
Rodrigo.
>
> val = READ();
> val &= ~CNL_SKIP_SEG_COUNT_MASK;
> val |= CNL_SKIP_SEG_EN | CNL_SKIP_SEG_COUNT(1);
>
>> }
>>
>> static void kabylake_init_clock_gating(struct drm_i915_private
>> *dev_priv)
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Rodrigo Vivi
Blog: http://blog.vivi.eng.br
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^ permalink raw reply [flat|nested] 17+ messages in thread* Re: [PATCH] drm/i915/cnl: WaFbcSkipSegments
2017-09-01 21:31 ` Rodrigo Vivi
@ 2017-09-04 18:05 ` Paulo Zanoni
2017-09-05 17:56 ` Rodrigo Vivi
0 siblings, 1 reply; 17+ messages in thread
From: Paulo Zanoni @ 2017-09-04 18:05 UTC (permalink / raw)
To: Rodrigo Vivi, Jani Nikula; +Cc: intel-gfx, Rodrigo Vivi
Em Sex, 2017-09-01 às 14:31 -0700, Rodrigo Vivi escreveu:
> On Fri, Sep 1, 2017 at 2:04 PM, Paulo Zanoni <paulo.r.zanoni@intel.co
> m> wrote:
> > Em Ter, 2017-08-29 às 16:08 -0700, Rodrigo Vivi escreveu:
> > > Skip compressing 1 segment at the end of the frame,
> > > avoid a pixel count mismatch nuke event when last active
> > > pixel and dummy pixel has same color for Odd Plane
> > > Width / Height.
> > >
> > > Cc: Paulo Zanoni <paulo.r.zanoni@intel.com>
> > > Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
> > > ---
> > > drivers/gpu/drm/i915/i915_reg.h | 2 ++
> > > drivers/gpu/drm/i915/intel_pm.c | 4 ++++
> > > 2 files changed, 6 insertions(+)
> > >
> > > diff --git a/drivers/gpu/drm/i915/i915_reg.h
> > > b/drivers/gpu/drm/i915/i915_reg.h
> > > index e2908ae34004..0072ef79bf34 100644
> > > --- a/drivers/gpu/drm/i915/i915_reg.h
> > > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > > @@ -2939,6 +2939,8 @@ enum i915_power_well_id {
> > > #define ILK_DPFC_CHICKEN _MMIO(0x43224)
> > > #define ILK_DPFC_DISABLE_DUMMY0 (1<<8)
> > > #define ILK_DPFC_NUKE_ON_ANY_MODIFICATION (1<<23)
> > > +#define CNL_SKIP_SEG_EN (1<<12)
> > > +#define CNL_SKIP_SEG_COUNT (1<<10)
> >
> > #define CNL_SKIP_SEG_COUNT_MASK (3 << 10)
> > #define CNL_SKIP_SEG_COUNT(x) ((x) << 10)
>
> By the definition we should add the SHIFT then as well?
> Although we are not going to read ever?!
I don't see the point in adding it if we're not using it. Most of the
times where we have the function-like macro we don't need _SHIFT, but
_MASK is needed due to the RMW.
>
> >
> > Also, since you're going to submit v2 anyway, I wouldn't complain
> > if
> > you drive-by fixed the definitions of ILK_DPFC_CHICKEN bits to use
> > spaces as documented in the beginning of the file. If we fix every
> > time
> > we touch a reg, we may at some point be consistent :).
>
> Last patch I tried to fix the style on the same patch Jani nacked it.
> So I wonder if we need a bit patch to fix all the style entirely.
I just gave a suggestion, fixing the spacing is not required in this
patch.
>
> >
> >
> > > #define ILK_FBC_RT_BASE _MMIO(0x2128)
> > > #define ILK_FBC_RT_VALID (1<<0)
> > > #define SNB_FBC_FRONT_BUFFER (1<<1)
> > > diff --git a/drivers/gpu/drm/i915/intel_pm.c
> > > b/drivers/gpu/drm/i915/intel_pm.c
> > > index d5ff0b9f999f..acf793256507 100644
> > > --- a/drivers/gpu/drm/i915/intel_pm.c
> > > +++ b/drivers/gpu/drm/i915/intel_pm.c
> > > @@ -8283,6 +8283,10 @@ static void
> > > cannonlake_init_clock_gating(struct drm_i915_private *dev_priv)
> > > I915_WRITE(SLICE_UNIT_LEVEL_CLKGATE,
> > > I915_READ(SLICE_UNIT_LEVEL_CLKGATE) |
> > > SARBUNIT_CLKGATE_DIS);
> > > +
> > > + /* WaFbcSkipSegments:cnl */
> >
> > Since this is also documented in BSpec but it doesn't include the
> > WA
> > name, can you please also document that this is WA #1133 in this
> > comment? I'd do something like:
> >
> > /* Display WA #1133: WaFbcSkipSegments:cnl,glk. */
>
> good idea!
>
> >
> > Please notice that we also need to apply this WA for GLK.
>
> hm... indeed...
> >
> >
> > > + I915_WRITE(ILK_DPFC_CHICKEN, I915_READ(ILK_DPFC_CHICKEN) |
> > > + CNL_SKIP_SEG_EN | CNL_SKIP_SEG_COUNT);
> >
> > Need to clear bit 11 too.
>
> ouch! yeap!
>
> Thanks,
> Rodrigo.
>
> >
> > val = READ();
> > val &= ~CNL_SKIP_SEG_COUNT_MASK;
> > val |= CNL_SKIP_SEG_EN | CNL_SKIP_SEG_COUNT(1);
> >
> > > }
> > >
> > > static void kabylake_init_clock_gating(struct drm_i915_private
> > > *dev_priv)
> >
> > _______________________________________________
> > Intel-gfx mailing list
> > Intel-gfx@lists.freedesktop.org
> > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
>
>
>
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^ permalink raw reply [flat|nested] 17+ messages in thread* [PATCH] drm/i915/cnl: WaFbcSkipSegments
2017-09-04 18:05 ` Paulo Zanoni
@ 2017-09-05 17:56 ` Rodrigo Vivi
2017-09-05 18:05 ` [PATCH] drm/i915: Display WA #1133 WaFbcSkipSegments:cnl, glk Rodrigo Vivi
0 siblings, 1 reply; 17+ messages in thread
From: Rodrigo Vivi @ 2017-09-05 17:56 UTC (permalink / raw)
To: intel-gfx; +Cc: Paulo Zanoni, Rodrigo Vivi
Skip compressing 1 segment at the end of the frame,
avoid a pixel count mismatch nuke event when last active
pixel and dummy pixel has same color for Odd Plane
Width / Height.
v2: Use function-like macro and also use mask to clean
to make sure bit 11 is 0. (Suggested by Paulo).
Cc: Paulo Zanoni <paulo.r.zanoni@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
---
drivers/gpu/drm/i915/i915_reg.h | 3 +++
drivers/gpu/drm/i915/intel_pm.c | 8 ++++++++
2 files changed, 11 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index c718c2f2eaeb..318a56ba1843 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -2940,6 +2940,9 @@ enum i915_power_well_id {
#define ILK_DPFC_CHICKEN _MMIO(0x43224)
#define ILK_DPFC_DISABLE_DUMMY0 (1<<8)
#define ILK_DPFC_NUKE_ON_ANY_MODIFICATION (1<<23)
+#define CNL_SKIP_SEG_EN (1<<12)
+#define CNL_SKIP_SEG_COUNT_MASK (3<<10)
+#define CNL_SKIP_SEG_COUNT(x) ((x)<<10)
#define ILK_FBC_RT_BASE _MMIO(0x2128)
#define ILK_FBC_RT_VALID (1<<0)
#define SNB_FBC_FRONT_BUFFER (1<<1)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index b0ba5a1018cd..405c39fa0332 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -8266,6 +8266,8 @@ static void gen8_set_l3sqc_credits(struct drm_i915_private *dev_priv,
static void cnl_init_clock_gating(struct drm_i915_private *dev_priv)
{
+ u32 val;
+
/* This is not an Wa. Enable for better image quality */
I915_WRITE(_3D_CHICKEN3,
_MASKED_BIT_ENABLE(_3D_CHICKEN3_AA_LINE_QUALITY_FIX_ENABLE));
@@ -8283,6 +8285,12 @@ static void cnl_init_clock_gating(struct drm_i915_private *dev_priv)
I915_WRITE(SLICE_UNIT_LEVEL_CLKGATE,
I915_READ(SLICE_UNIT_LEVEL_CLKGATE) |
SARBUNIT_CLKGATE_DIS);
+
+ /* WaFbcSkipSegments:cnl */
+ val = I915_READ(ILK_DPFC_CHICKEN);
+ val &= ~CNL_SKIP_SEG_COUNT_MASK;
+ val = CNL_SKIP_SEG_EN | CNL_SKIP_SEG_COUNT(1);
+ I915_WRITE(ILK_DPFC_CHICKEN, val);
}
static void kbl_init_clock_gating(struct drm_i915_private *dev_priv)
--
2.13.2
_______________________________________________
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^ permalink raw reply related [flat|nested] 17+ messages in thread* [PATCH] drm/i915: Display WA #1133 WaFbcSkipSegments:cnl, glk
2017-09-05 17:56 ` Rodrigo Vivi
@ 2017-09-05 18:05 ` Rodrigo Vivi
2017-09-05 18:59 ` Paulo Zanoni
0 siblings, 1 reply; 17+ messages in thread
From: Rodrigo Vivi @ 2017-09-05 18:05 UTC (permalink / raw)
To: intel-gfx; +Cc: Paulo Zanoni, Rodrigo Vivi
Skip compressing 1 segment at the end of the frame,
avoid a pixel count mismatch nuke event when last active
pixel and dummy pixel has same color for Odd Plane
Width / Height.
For both platforms Gemini Lake and Cannon Lake.
v2: Use function-like macro and also use mask to clean
to make sure bit 11 is 0. (Suggested by Paulo).
v3: Add Display WA notation and also apply for GLK.
Both Forgotten on v2.
Using "GLK_" prefix since GLK came before CNL.
Cc: Imre Deak <imre.deak@intel.com>
Cc: Paulo Zanoni <paulo.r.zanoni@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
---
drivers/gpu/drm/i915/i915_reg.h | 3 +++
drivers/gpu/drm/i915/intel_pm.c | 14 ++++++++++++++
2 files changed, 17 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index c718c2f2eaeb..fbf824b6e37a 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -2940,6 +2940,9 @@ enum i915_power_well_id {
#define ILK_DPFC_CHICKEN _MMIO(0x43224)
#define ILK_DPFC_DISABLE_DUMMY0 (1<<8)
#define ILK_DPFC_NUKE_ON_ANY_MODIFICATION (1<<23)
+#define GLK_SKIP_SEG_EN (1<<12)
+#define GLK_SKIP_SEG_COUNT_MASK (3<<10)
+#define GLK_SKIP_SEG_COUNT(x) ((x)<<10)
#define ILK_FBC_RT_BASE _MMIO(0x2128)
#define ILK_FBC_RT_VALID (1<<0)
#define SNB_FBC_FRONT_BUFFER (1<<1)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index b0ba5a1018cd..324011f40373 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -125,6 +125,7 @@ static void bxt_init_clock_gating(struct drm_i915_private *dev_priv)
static void glk_init_clock_gating(struct drm_i915_private *dev_priv)
{
+ u32 val;
gen9_init_clock_gating(dev_priv);
/*
@@ -144,6 +145,11 @@ static void glk_init_clock_gating(struct drm_i915_private *dev_priv)
I915_WRITE(CHICKEN_MISC_2, val);
}
+ /* Display WA #1133: WaFbcSkipSegments:glk */
+ val = I915_READ(ILK_DPFC_CHICKEN);
+ val &= ~GLK_SKIP_SEG_COUNT_MASK;
+ val = GLK_SKIP_SEG_EN | GLK_SKIP_SEG_COUNT(1);
+ I915_WRITE(ILK_DPFC_CHICKEN, val);
}
static void i915_pineview_get_mem_freq(struct drm_i915_private *dev_priv)
@@ -8266,6 +8272,8 @@ static void gen8_set_l3sqc_credits(struct drm_i915_private *dev_priv,
static void cnl_init_clock_gating(struct drm_i915_private *dev_priv)
{
+ u32 val;
+
/* This is not an Wa. Enable for better image quality */
I915_WRITE(_3D_CHICKEN3,
_MASKED_BIT_ENABLE(_3D_CHICKEN3_AA_LINE_QUALITY_FIX_ENABLE));
@@ -8283,6 +8291,12 @@ static void cnl_init_clock_gating(struct drm_i915_private *dev_priv)
I915_WRITE(SLICE_UNIT_LEVEL_CLKGATE,
I915_READ(SLICE_UNIT_LEVEL_CLKGATE) |
SARBUNIT_CLKGATE_DIS);
+
+ /* Display WA #1133: WaFbcSkipSegments:cnl */
+ val = I915_READ(ILK_DPFC_CHICKEN);
+ val &= ~GLK_SKIP_SEG_COUNT_MASK;
+ val = GLK_SKIP_SEG_EN | GLK_SKIP_SEG_COUNT(1);
+ I915_WRITE(ILK_DPFC_CHICKEN, val);
}
static void kbl_init_clock_gating(struct drm_i915_private *dev_priv)
--
2.13.2
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 17+ messages in thread* Re: [PATCH] drm/i915: Display WA #1133 WaFbcSkipSegments:cnl, glk
2017-09-05 18:05 ` [PATCH] drm/i915: Display WA #1133 WaFbcSkipSegments:cnl, glk Rodrigo Vivi
@ 2017-09-05 18:59 ` Paulo Zanoni
2017-09-05 19:07 ` Rodrigo Vivi
0 siblings, 1 reply; 17+ messages in thread
From: Paulo Zanoni @ 2017-09-05 18:59 UTC (permalink / raw)
To: Rodrigo Vivi, intel-gfx
Em Ter, 2017-09-05 às 11:05 -0700, Rodrigo Vivi escreveu:
> Skip compressing 1 segment at the end of the frame,
> avoid a pixel count mismatch nuke event when last active
> pixel and dummy pixel has same color for Odd Plane
> Width / Height.
>
> For both platforms Gemini Lake and Cannon Lake.
>
> v2: Use function-like macro and also use mask to clean
> to make sure bit 11 is 0. (Suggested by Paulo).
> v3: Add Display WA notation and also apply for GLK.
> Both Forgotten on v2.
> Using "GLK_" prefix since GLK came before CNL.
>
> Cc: Imre Deak <imre.deak@intel.com>
> Cc: Paulo Zanoni <paulo.r.zanoni@intel.com>
> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
> ---
> drivers/gpu/drm/i915/i915_reg.h | 3 +++
> drivers/gpu/drm/i915/intel_pm.c | 14 ++++++++++++++
> 2 files changed, 17 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h
> b/drivers/gpu/drm/i915/i915_reg.h
> index c718c2f2eaeb..fbf824b6e37a 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -2940,6 +2940,9 @@ enum i915_power_well_id {
> #define ILK_DPFC_CHICKEN _MMIO(0x43224)
> #define ILK_DPFC_DISABLE_DUMMY0 (1<<8)
> #define ILK_DPFC_NUKE_ON_ANY_MODIFICATION (1<<23)
> +#define GLK_SKIP_SEG_EN (1<<12)
> +#define GLK_SKIP_SEG_COUNT_MASK (3<<10)
> +#define GLK_SKIP_SEG_COUNT(x) ((x)<<10)
> #define ILK_FBC_RT_BASE _MMIO(0x2128)
> #define ILK_FBC_RT_VALID (1<<0)
> #define SNB_FBC_FRONT_BUFFER (1<<1)
> diff --git a/drivers/gpu/drm/i915/intel_pm.c
> b/drivers/gpu/drm/i915/intel_pm.c
> index b0ba5a1018cd..324011f40373 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -125,6 +125,7 @@ static void bxt_init_clock_gating(struct
> drm_i915_private *dev_priv)
>
> static void glk_init_clock_gating(struct drm_i915_private *dev_priv)
> {
> + u32 val;
> gen9_init_clock_gating(dev_priv);
>
> /*
> @@ -144,6 +145,11 @@ static void glk_init_clock_gating(struct
> drm_i915_private *dev_priv)
> I915_WRITE(CHICKEN_MISC_2, val);
> }
>
> + /* Display WA #1133: WaFbcSkipSegments:glk */
> + val = I915_READ(ILK_DPFC_CHICKEN);
> + val &= ~GLK_SKIP_SEG_COUNT_MASK;
> + val = GLK_SKIP_SEG_EN | GLK_SKIP_SEG_COUNT(1);
s/=/|=/
> + I915_WRITE(ILK_DPFC_CHICKEN, val);
> }
>
> static void i915_pineview_get_mem_freq(struct drm_i915_private
> *dev_priv)
> @@ -8266,6 +8272,8 @@ static void gen8_set_l3sqc_credits(struct
> drm_i915_private *dev_priv,
>
> static void cnl_init_clock_gating(struct drm_i915_private *dev_priv)
> {
> + u32 val;
> +
> /* This is not an Wa. Enable for better image quality */
> I915_WRITE(_3D_CHICKEN3,
> _MASKED_BIT_ENABLE(_3D_CHICKEN3_AA_LINE_QUALITY_F
> IX_ENABLE));
> @@ -8283,6 +8291,12 @@ static void cnl_init_clock_gating(struct
> drm_i915_private *dev_priv)
> I915_WRITE(SLICE_UNIT_LEVEL_CLKGATE,
> I915_READ(SLICE_UNIT_LEVEL_CLKGATE) |
> SARBUNIT_CLKGATE_DIS);
> +
> + /* Display WA #1133: WaFbcSkipSegments:cnl */
> + val = I915_READ(ILK_DPFC_CHICKEN);
> + val &= ~GLK_SKIP_SEG_COUNT_MASK;
> + val = GLK_SKIP_SEG_EN | GLK_SKIP_SEG_COUNT(1);
Same here.
> + I915_WRITE(ILK_DPFC_CHICKEN, val);
> }
>
> static void kbl_init_clock_gating(struct drm_i915_private *dev_priv)
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 17+ messages in thread* [PATCH] drm/i915: Display WA #1133 WaFbcSkipSegments:cnl, glk
2017-09-05 18:59 ` Paulo Zanoni
@ 2017-09-05 19:07 ` Rodrigo Vivi
2017-09-05 19:16 ` Paulo Zanoni
0 siblings, 1 reply; 17+ messages in thread
From: Rodrigo Vivi @ 2017-09-05 19:07 UTC (permalink / raw)
To: intel-gfx; +Cc: Paulo Zanoni, Rodrigo Vivi
Skip compressing 1 segment at the end of the frame,
avoid a pixel count mismatch nuke event when last active
pixel and dummy pixel has same color for Odd Plane
Width / Height.
For both platforms Gemini Lake and Cannon Lake.
v2: Use function-like macro and also use mask to clean
to make sure bit 11 is 0. (Suggested by Paulo).
v3: Add Display WA notation and also apply for GLK.
Both Forgotten on v2.
Using "GLK_" prefix since GLK came before CNL.
v4: Forgot to "|=" when moving directly macro to masked
val. (Noticed by Paulo.)
Cc: Imre Deak <imre.deak@intel.com>
Cc: Paulo Zanoni <paulo.r.zanoni@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
---
drivers/gpu/drm/i915/i915_reg.h | 3 +++
drivers/gpu/drm/i915/intel_pm.c | 14 ++++++++++++++
2 files changed, 17 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index c718c2f2eaeb..fbf824b6e37a 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -2940,6 +2940,9 @@ enum i915_power_well_id {
#define ILK_DPFC_CHICKEN _MMIO(0x43224)
#define ILK_DPFC_DISABLE_DUMMY0 (1<<8)
#define ILK_DPFC_NUKE_ON_ANY_MODIFICATION (1<<23)
+#define GLK_SKIP_SEG_EN (1<<12)
+#define GLK_SKIP_SEG_COUNT_MASK (3<<10)
+#define GLK_SKIP_SEG_COUNT(x) ((x)<<10)
#define ILK_FBC_RT_BASE _MMIO(0x2128)
#define ILK_FBC_RT_VALID (1<<0)
#define SNB_FBC_FRONT_BUFFER (1<<1)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index b0ba5a1018cd..6abad2048b23 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -125,6 +125,7 @@ static void bxt_init_clock_gating(struct drm_i915_private *dev_priv)
static void glk_init_clock_gating(struct drm_i915_private *dev_priv)
{
+ u32 val;
gen9_init_clock_gating(dev_priv);
/*
@@ -144,6 +145,11 @@ static void glk_init_clock_gating(struct drm_i915_private *dev_priv)
I915_WRITE(CHICKEN_MISC_2, val);
}
+ /* Display WA #1133: WaFbcSkipSegments:glk */
+ val = I915_READ(ILK_DPFC_CHICKEN);
+ val &= ~GLK_SKIP_SEG_COUNT_MASK;
+ val |= GLK_SKIP_SEG_EN | GLK_SKIP_SEG_COUNT(1);
+ I915_WRITE(ILK_DPFC_CHICKEN, val);
}
static void i915_pineview_get_mem_freq(struct drm_i915_private *dev_priv)
@@ -8266,6 +8272,8 @@ static void gen8_set_l3sqc_credits(struct drm_i915_private *dev_priv,
static void cnl_init_clock_gating(struct drm_i915_private *dev_priv)
{
+ u32 val;
+
/* This is not an Wa. Enable for better image quality */
I915_WRITE(_3D_CHICKEN3,
_MASKED_BIT_ENABLE(_3D_CHICKEN3_AA_LINE_QUALITY_FIX_ENABLE));
@@ -8283,6 +8291,12 @@ static void cnl_init_clock_gating(struct drm_i915_private *dev_priv)
I915_WRITE(SLICE_UNIT_LEVEL_CLKGATE,
I915_READ(SLICE_UNIT_LEVEL_CLKGATE) |
SARBUNIT_CLKGATE_DIS);
+
+ /* Display WA #1133: WaFbcSkipSegments:cnl */
+ val = I915_READ(ILK_DPFC_CHICKEN);
+ val &= ~GLK_SKIP_SEG_COUNT_MASK;
+ val |= GLK_SKIP_SEG_EN | GLK_SKIP_SEG_COUNT(1);
+ I915_WRITE(ILK_DPFC_CHICKEN, val);
}
static void kbl_init_clock_gating(struct drm_i915_private *dev_priv)
--
2.13.2
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 17+ messages in thread* Re: [PATCH] drm/i915: Display WA #1133 WaFbcSkipSegments:cnl, glk
2017-09-05 19:07 ` Rodrigo Vivi
@ 2017-09-05 19:16 ` Paulo Zanoni
0 siblings, 0 replies; 17+ messages in thread
From: Paulo Zanoni @ 2017-09-05 19:16 UTC (permalink / raw)
To: Rodrigo Vivi, intel-gfx
Em Ter, 2017-09-05 às 12:07 -0700, Rodrigo Vivi escreveu:
> Skip compressing 1 segment at the end of the frame,
> avoid a pixel count mismatch nuke event when last active
> pixel and dummy pixel has same color for Odd Plane
> Width / Height.
>
> For both platforms Gemini Lake and Cannon Lake.
>
> v2: Use function-like macro and also use mask to clean
> to make sure bit 11 is 0. (Suggested by Paulo).
> v3: Add Display WA notation and also apply for GLK.
> Both Forgotten on v2.
> Using "GLK_" prefix since GLK came before CNL.
> v4: Forgot to "|=" when moving directly macro to masked
> val. (Noticed by Paulo.)
Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
>
> Cc: Imre Deak <imre.deak@intel.com>
> Cc: Paulo Zanoni <paulo.r.zanoni@intel.com>
> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
> ---
> drivers/gpu/drm/i915/i915_reg.h | 3 +++
> drivers/gpu/drm/i915/intel_pm.c | 14 ++++++++++++++
> 2 files changed, 17 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h
> b/drivers/gpu/drm/i915/i915_reg.h
> index c718c2f2eaeb..fbf824b6e37a 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -2940,6 +2940,9 @@ enum i915_power_well_id {
> #define ILK_DPFC_CHICKEN _MMIO(0x43224)
> #define ILK_DPFC_DISABLE_DUMMY0 (1<<8)
> #define ILK_DPFC_NUKE_ON_ANY_MODIFICATION (1<<23)
> +#define GLK_SKIP_SEG_EN (1<<12)
> +#define GLK_SKIP_SEG_COUNT_MASK (3<<10)
> +#define GLK_SKIP_SEG_COUNT(x) ((x)<<10)
> #define ILK_FBC_RT_BASE _MMIO(0x2128)
> #define ILK_FBC_RT_VALID (1<<0)
> #define SNB_FBC_FRONT_BUFFER (1<<1)
> diff --git a/drivers/gpu/drm/i915/intel_pm.c
> b/drivers/gpu/drm/i915/intel_pm.c
> index b0ba5a1018cd..6abad2048b23 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -125,6 +125,7 @@ static void bxt_init_clock_gating(struct
> drm_i915_private *dev_priv)
>
> static void glk_init_clock_gating(struct drm_i915_private *dev_priv)
> {
> + u32 val;
> gen9_init_clock_gating(dev_priv);
>
> /*
> @@ -144,6 +145,11 @@ static void glk_init_clock_gating(struct
> drm_i915_private *dev_priv)
> I915_WRITE(CHICKEN_MISC_2, val);
> }
>
> + /* Display WA #1133: WaFbcSkipSegments:glk */
> + val = I915_READ(ILK_DPFC_CHICKEN);
> + val &= ~GLK_SKIP_SEG_COUNT_MASK;
> + val |= GLK_SKIP_SEG_EN | GLK_SKIP_SEG_COUNT(1);
> + I915_WRITE(ILK_DPFC_CHICKEN, val);
> }
>
> static void i915_pineview_get_mem_freq(struct drm_i915_private
> *dev_priv)
> @@ -8266,6 +8272,8 @@ static void gen8_set_l3sqc_credits(struct
> drm_i915_private *dev_priv,
>
> static void cnl_init_clock_gating(struct drm_i915_private *dev_priv)
> {
> + u32 val;
> +
> /* This is not an Wa. Enable for better image quality */
> I915_WRITE(_3D_CHICKEN3,
> _MASKED_BIT_ENABLE(_3D_CHICKEN3_AA_LINE_QUALITY_F
> IX_ENABLE));
> @@ -8283,6 +8291,12 @@ static void cnl_init_clock_gating(struct
> drm_i915_private *dev_priv)
> I915_WRITE(SLICE_UNIT_LEVEL_CLKGATE,
> I915_READ(SLICE_UNIT_LEVEL_CLKGATE) |
> SARBUNIT_CLKGATE_DIS);
> +
> + /* Display WA #1133: WaFbcSkipSegments:cnl */
> + val = I915_READ(ILK_DPFC_CHICKEN);
> + val &= ~GLK_SKIP_SEG_COUNT_MASK;
> + val |= GLK_SKIP_SEG_EN | GLK_SKIP_SEG_COUNT(1);
> + I915_WRITE(ILK_DPFC_CHICKEN, val);
> }
>
> static void kbl_init_clock_gating(struct drm_i915_private *dev_priv)
_______________________________________________
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 17+ messages in thread
* ✓ Fi.CI.BAT: success for drm/i915/cnl: WaFbcSkipSegments (rev3)
2017-08-29 23:08 [PATCH] drm/i915/cnl: WaFbcSkipSegments Rodrigo Vivi
` (2 preceding siblings ...)
2017-09-01 21:04 ` [PATCH] " Paulo Zanoni
@ 2017-09-05 18:23 ` Patchwork
2017-09-05 19:26 ` ✓ Fi.CI.BAT: success for drm/i915/cnl: WaFbcSkipSegments (rev4) Patchwork
` (2 subsequent siblings)
6 siblings, 0 replies; 17+ messages in thread
From: Patchwork @ 2017-09-05 18:23 UTC (permalink / raw)
To: Rodrigo Vivi; +Cc: intel-gfx
== Series Details ==
Series: drm/i915/cnl: WaFbcSkipSegments (rev3)
URL : https://patchwork.freedesktop.org/series/29507/
State : success
== Summary ==
Series 29507v3 drm/i915/cnl: WaFbcSkipSegments
https://patchwork.freedesktop.org/api/1.0/series/29507/revisions/3/mbox/
Test kms_cursor_legacy:
Subgroup basic-busy-flip-before-cursor-legacy:
fail -> PASS (fi-snb-2600) fdo#100215
Test kms_flip:
Subgroup basic-flip-vs-modeset:
skip -> PASS (fi-skl-x1585l) fdo#101781
fdo#100215 https://bugs.freedesktop.org/show_bug.cgi?id=100215
fdo#101781 https://bugs.freedesktop.org/show_bug.cgi?id=101781
fi-bdw-5557u total:289 pass:268 dwarn:0 dfail:0 fail:0 skip:21 time:456s
fi-bdw-gvtdvm total:289 pass:265 dwarn:0 dfail:0 fail:0 skip:24 time:444s
fi-blb-e6850 total:289 pass:224 dwarn:1 dfail:0 fail:0 skip:64 time:359s
fi-bsw-n3050 total:289 pass:243 dwarn:0 dfail:0 fail:0 skip:46 time:565s
fi-bwr-2160 total:289 pass:184 dwarn:0 dfail:0 fail:0 skip:105 time:257s
fi-bxt-j4205 total:289 pass:260 dwarn:0 dfail:0 fail:0 skip:29 time:526s
fi-byt-j1900 total:289 pass:254 dwarn:1 dfail:0 fail:0 skip:34 time:522s
fi-byt-n2820 total:289 pass:250 dwarn:1 dfail:0 fail:0 skip:38 time:510s
fi-cfl-s total:289 pass:250 dwarn:4 dfail:0 fail:0 skip:35 time:463s
fi-elk-e7500 total:289 pass:230 dwarn:0 dfail:0 fail:0 skip:59 time:437s
fi-glk-2a total:289 pass:260 dwarn:0 dfail:0 fail:0 skip:29 time:607s
fi-hsw-4770 total:289 pass:263 dwarn:0 dfail:0 fail:0 skip:26 time:446s
fi-hsw-4770r total:289 pass:263 dwarn:0 dfail:0 fail:0 skip:26 time:425s
fi-ilk-650 total:289 pass:229 dwarn:0 dfail:0 fail:0 skip:60 time:424s
fi-ivb-3520m total:289 pass:261 dwarn:0 dfail:0 fail:0 skip:28 time:514s
fi-ivb-3770 total:289 pass:261 dwarn:0 dfail:0 fail:0 skip:28 time:471s
fi-kbl-7500u total:289 pass:264 dwarn:1 dfail:0 fail:0 skip:24 time:517s
fi-kbl-7560u total:289 pass:270 dwarn:0 dfail:0 fail:0 skip:19 time:602s
fi-kbl-r total:289 pass:262 dwarn:0 dfail:0 fail:0 skip:27 time:602s
fi-pnv-d510 total:289 pass:223 dwarn:1 dfail:0 fail:0 skip:65 time:532s
fi-skl-6260u total:289 pass:269 dwarn:0 dfail:0 fail:0 skip:20 time:470s
fi-skl-6700k total:289 pass:265 dwarn:0 dfail:0 fail:0 skip:24 time:538s
fi-skl-6770hq total:289 pass:269 dwarn:0 dfail:0 fail:0 skip:20 time:520s
fi-skl-gvtdvm total:289 pass:266 dwarn:0 dfail:0 fail:0 skip:23 time:449s
fi-skl-x1585l total:289 pass:269 dwarn:0 dfail:0 fail:0 skip:20 time:517s
fi-snb-2520m total:289 pass:251 dwarn:0 dfail:0 fail:0 skip:38 time:555s
fi-snb-2600 total:289 pass:249 dwarn:0 dfail:0 fail:1 skip:39 time:405s
9c31136737acb5254b63947aabda3449097416fe drm-tip: 2017y-09m-05d-17h-38m-59s UTC integration manifest
a12878fda92e drm/i915: Display WA #1133 WaFbcSkipSegments:cnl, glk
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_5584/
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 17+ messages in thread* ✓ Fi.CI.BAT: success for drm/i915/cnl: WaFbcSkipSegments (rev4)
2017-08-29 23:08 [PATCH] drm/i915/cnl: WaFbcSkipSegments Rodrigo Vivi
` (3 preceding siblings ...)
2017-09-05 18:23 ` ✓ Fi.CI.BAT: success for drm/i915/cnl: WaFbcSkipSegments (rev3) Patchwork
@ 2017-09-05 19:26 ` Patchwork
2017-09-05 20:43 ` ✗ Fi.CI.IGT: warning for drm/i915/cnl: WaFbcSkipSegments (rev3) Patchwork
2017-09-05 22:19 ` ✗ Fi.CI.IGT: failure for drm/i915/cnl: WaFbcSkipSegments (rev4) Patchwork
6 siblings, 0 replies; 17+ messages in thread
From: Patchwork @ 2017-09-05 19:26 UTC (permalink / raw)
To: Rodrigo Vivi; +Cc: intel-gfx
== Series Details ==
Series: drm/i915/cnl: WaFbcSkipSegments (rev4)
URL : https://patchwork.freedesktop.org/series/29507/
State : success
== Summary ==
Series 29507v4 drm/i915/cnl: WaFbcSkipSegments
https://patchwork.freedesktop.org/api/1.0/series/29507/revisions/4/mbox/
Test kms_cursor_legacy:
Subgroup basic-busy-flip-before-cursor-atomic:
pass -> FAIL (fi-snb-2600) fdo#100215
Test kms_flip:
Subgroup basic-flip-vs-modeset:
skip -> PASS (fi-skl-x1585l) fdo#101781
skip -> PASS (fi-cfl-s)
Test kms_pipe_crc_basic:
Subgroup suspend-read-crc-pipe-b:
pass -> DMESG-WARN (fi-byt-n2820) fdo#101705
Test drv_module_reload:
Subgroup basic-reload-inject:
dmesg-fail -> DMESG-WARN (fi-cfl-s) k.org#196765
fdo#100215 https://bugs.freedesktop.org/show_bug.cgi?id=100215
fdo#101781 https://bugs.freedesktop.org/show_bug.cgi?id=101781
fdo#101705 https://bugs.freedesktop.org/show_bug.cgi?id=101705
k.org#196765 https://bugzilla.kernel.org/show_bug.cgi?id=196765
fi-bdw-5557u total:289 pass:268 dwarn:0 dfail:0 fail:0 skip:21 time:459s
fi-bdw-gvtdvm total:289 pass:265 dwarn:0 dfail:0 fail:0 skip:24 time:441s
fi-blb-e6850 total:289 pass:224 dwarn:1 dfail:0 fail:0 skip:64 time:362s
fi-bsw-n3050 total:289 pass:243 dwarn:0 dfail:0 fail:0 skip:46 time:550s
fi-bwr-2160 total:289 pass:184 dwarn:0 dfail:0 fail:0 skip:105 time:255s
fi-bxt-j4205 total:289 pass:260 dwarn:0 dfail:0 fail:0 skip:29 time:525s
fi-byt-j1900 total:289 pass:254 dwarn:1 dfail:0 fail:0 skip:34 time:520s
fi-byt-n2820 total:289 pass:250 dwarn:1 dfail:0 fail:0 skip:38 time:511s
fi-cfl-s total:289 pass:250 dwarn:4 dfail:0 fail:0 skip:35 time:460s
fi-elk-e7500 total:289 pass:230 dwarn:0 dfail:0 fail:0 skip:59 time:438s
fi-glk-2a total:289 pass:260 dwarn:0 dfail:0 fail:0 skip:29 time:613s
fi-hsw-4770 total:289 pass:263 dwarn:0 dfail:0 fail:0 skip:26 time:445s
fi-hsw-4770r total:289 pass:263 dwarn:0 dfail:0 fail:0 skip:26 time:429s
fi-ilk-650 total:289 pass:229 dwarn:0 dfail:0 fail:0 skip:60 time:433s
fi-ivb-3520m total:289 pass:261 dwarn:0 dfail:0 fail:0 skip:28 time:501s
fi-ivb-3770 total:289 pass:261 dwarn:0 dfail:0 fail:0 skip:28 time:473s
fi-kbl-7500u total:289 pass:264 dwarn:1 dfail:0 fail:0 skip:24 time:517s
fi-kbl-7560u total:289 pass:270 dwarn:0 dfail:0 fail:0 skip:19 time:602s
fi-kbl-r total:289 pass:262 dwarn:0 dfail:0 fail:0 skip:27 time:599s
fi-pnv-d510 total:289 pass:223 dwarn:1 dfail:0 fail:0 skip:65 time:536s
fi-skl-6260u total:289 pass:269 dwarn:0 dfail:0 fail:0 skip:20 time:474s
fi-skl-6700k total:289 pass:265 dwarn:0 dfail:0 fail:0 skip:24 time:542s
fi-skl-6770hq total:289 pass:269 dwarn:0 dfail:0 fail:0 skip:20 time:515s
fi-skl-gvtdvm total:289 pass:266 dwarn:0 dfail:0 fail:0 skip:23 time:448s
fi-skl-x1585l total:289 pass:269 dwarn:0 dfail:0 fail:0 skip:20 time:511s
fi-snb-2520m total:289 pass:251 dwarn:0 dfail:0 fail:0 skip:38 time:555s
fi-snb-2600 total:289 pass:249 dwarn:0 dfail:0 fail:1 skip:39 time:402s
3b8f5b73f918f7aba4569b155bbd87e258f21c81 drm-tip: 2017y-09m-05d-18h-24m-26s UTC integration manifest
74545751f756 drm/i915: Display WA #1133 WaFbcSkipSegments:cnl, glk
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_5586/
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 17+ messages in thread* ✗ Fi.CI.IGT: warning for drm/i915/cnl: WaFbcSkipSegments (rev3)
2017-08-29 23:08 [PATCH] drm/i915/cnl: WaFbcSkipSegments Rodrigo Vivi
` (4 preceding siblings ...)
2017-09-05 19:26 ` ✓ Fi.CI.BAT: success for drm/i915/cnl: WaFbcSkipSegments (rev4) Patchwork
@ 2017-09-05 20:43 ` Patchwork
2017-09-05 22:19 ` ✗ Fi.CI.IGT: failure for drm/i915/cnl: WaFbcSkipSegments (rev4) Patchwork
6 siblings, 0 replies; 17+ messages in thread
From: Patchwork @ 2017-09-05 20:43 UTC (permalink / raw)
To: Rodrigo Vivi; +Cc: intel-gfx
== Series Details ==
Series: drm/i915/cnl: WaFbcSkipSegments (rev3)
URL : https://patchwork.freedesktop.org/series/29507/
State : warning
== Summary ==
Test kms_frontbuffer_tracking:
Subgroup fbc-rgb101010-draw-mmap-gtt:
pass -> SKIP (shard-hsw)
Subgroup fbc-1p-primscrn-spr-indfb-draw-mmap-gtt:
pass -> SKIP (shard-hsw)
Subgroup fbc-1p-offscren-pri-shrfb-draw-render:
pass -> SKIP (shard-hsw)
Test kms_cursor_legacy:
Subgroup cursor-vs-flip-toggle:
pass -> SKIP (shard-hsw)
Test kms_plane:
Subgroup plane-position-hole-dpms-pipe-B-planes:
pass -> SKIP (shard-hsw)
shard-hsw total:2265 pass:1229 dwarn:0 dfail:0 fail:15 skip:1021 time:9567s
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_5584/shards.html
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 17+ messages in thread* ✗ Fi.CI.IGT: failure for drm/i915/cnl: WaFbcSkipSegments (rev4)
2017-08-29 23:08 [PATCH] drm/i915/cnl: WaFbcSkipSegments Rodrigo Vivi
` (5 preceding siblings ...)
2017-09-05 20:43 ` ✗ Fi.CI.IGT: warning for drm/i915/cnl: WaFbcSkipSegments (rev3) Patchwork
@ 2017-09-05 22:19 ` Patchwork
6 siblings, 0 replies; 17+ messages in thread
From: Patchwork @ 2017-09-05 22:19 UTC (permalink / raw)
To: Rodrigo Vivi; +Cc: intel-gfx
== Series Details ==
Series: drm/i915/cnl: WaFbcSkipSegments (rev4)
URL : https://patchwork.freedesktop.org/series/29507/
State : failure
== Summary ==
Test gem_exec_store:
Subgroup basic-render:
pass -> FAIL (shard-hsw)
shard-hsw total:2265 pass:1231 dwarn:0 dfail:0 fail:18 skip:1016 time:9626s
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_5586/shards.html
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 17+ messages in thread
[parent not found: <Message-id: <1504638961.2824.38.camel@intel.com>]
* [PATCH] drm/i915: Display WA #1133 WaFbcSkipSegments:cnl, glk
[not found] <Message-id: <1504638961.2824.38.camel@intel.com>
@ 2017-09-05 19:30 ` Rodrigo Vivi
2017-09-06 20:43 ` Rodrigo Vivi
0 siblings, 1 reply; 17+ messages in thread
From: Rodrigo Vivi @ 2017-09-05 19:30 UTC (permalink / raw)
To: intel-gfx; +Cc: Paulo Zanoni, Rodrigo Vivi
Skip compressing 1 segment at the end of the frame,
avoid a pixel count mismatch nuke event when last active
pixel and dummy pixel has same color for Odd Plane
Width / Height.
For both platforms Gemini Lake and Cannon Lake.
v2: Use function-like macro and also use mask to clean
to make sure bit 11 is 0. (Suggested by Paulo).
v3: Add Display WA notation and also apply for GLK.
Both Forgotten on v2.
Using "GLK_" prefix since GLK came before CNL.
v4: Forgot to "|=" when moving directly macro to masked
val. (Noticed by Paulo.)
v5: Rebased on top of 0a46ddd57c9e ("drm/i915/cnp: Wa 1181:
Fix Backlight issue")
Cc: Imre Deak <imre.deak@intel.com>
Cc: Paulo Zanoni <paulo.r.zanoni@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
---
drivers/gpu/drm/i915/i915_reg.h | 3 +++
drivers/gpu/drm/i915/intel_pm.c | 13 +++++++++++++
2 files changed, 16 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 5651081ff789..1878c4967529 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -2940,6 +2940,9 @@ enum i915_power_well_id {
#define ILK_DPFC_CHICKEN _MMIO(0x43224)
#define ILK_DPFC_DISABLE_DUMMY0 (1<<8)
#define ILK_DPFC_NUKE_ON_ANY_MODIFICATION (1<<23)
+#define GLK_SKIP_SEG_EN (1<<12)
+#define GLK_SKIP_SEG_COUNT_MASK (3<<10)
+#define GLK_SKIP_SEG_COUNT(x) ((x)<<10)
#define ILK_FBC_RT_BASE _MMIO(0x2128)
#define ILK_FBC_RT_VALID (1<<0)
#define SNB_FBC_FRONT_BUFFER (1<<1)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index f5d77b131b58..0201816a4229 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -125,6 +125,7 @@ static void bxt_init_clock_gating(struct drm_i915_private *dev_priv)
static void glk_init_clock_gating(struct drm_i915_private *dev_priv)
{
+ u32 val;
gen9_init_clock_gating(dev_priv);
/*
@@ -144,6 +145,11 @@ static void glk_init_clock_gating(struct drm_i915_private *dev_priv)
I915_WRITE(CHICKEN_MISC_2, val);
}
+ /* Display WA #1133: WaFbcSkipSegments:glk */
+ val = I915_READ(ILK_DPFC_CHICKEN);
+ val &= ~GLK_SKIP_SEG_COUNT_MASK;
+ val |= GLK_SKIP_SEG_EN | GLK_SKIP_SEG_COUNT(1);
+ I915_WRITE(ILK_DPFC_CHICKEN, val);
}
static void i915_pineview_get_mem_freq(struct drm_i915_private *dev_priv)
@@ -8275,6 +8281,7 @@ static void cnp_init_clock_gating(struct drm_i915_private *dev_priv)
static void cnl_init_clock_gating(struct drm_i915_private *dev_priv)
{
+ u32 val;
cnp_init_clock_gating(dev_priv);
/* This is not an Wa. Enable for better image quality */
@@ -8294,6 +8301,12 @@ static void cnl_init_clock_gating(struct drm_i915_private *dev_priv)
I915_WRITE(SLICE_UNIT_LEVEL_CLKGATE,
I915_READ(SLICE_UNIT_LEVEL_CLKGATE) |
SARBUNIT_CLKGATE_DIS);
+
+ /* Display WA #1133: WaFbcSkipSegments:cnl */
+ val = I915_READ(ILK_DPFC_CHICKEN);
+ val &= ~GLK_SKIP_SEG_COUNT_MASK;
+ val |= GLK_SKIP_SEG_EN | GLK_SKIP_SEG_COUNT(1);
+ I915_WRITE(ILK_DPFC_CHICKEN, val);
}
static void cfl_init_clock_gating(struct drm_i915_private *dev_priv)
--
2.13.2
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 17+ messages in thread* Re: [PATCH] drm/i915: Display WA #1133 WaFbcSkipSegments:cnl, glk
2017-09-05 19:30 ` [PATCH] drm/i915: Display WA #1133 WaFbcSkipSegments:cnl, glk Rodrigo Vivi
@ 2017-09-06 20:43 ` Rodrigo Vivi
0 siblings, 0 replies; 17+ messages in thread
From: Rodrigo Vivi @ 2017-09-06 20:43 UTC (permalink / raw)
To: intel-gfx; +Cc: Paulo Zanoni
On Tue, Sep 05, 2017 at 12:30:13PM -0700, Rodrigo Vivi wrote:
> Skip compressing 1 segment at the end of the frame,
> avoid a pixel count mismatch nuke event when last active
> pixel and dummy pixel has same color for Odd Plane
> Width / Height.
>
> For both platforms Gemini Lake and Cannon Lake.
>
> v2: Use function-like macro and also use mask to clean
> to make sure bit 11 is 0. (Suggested by Paulo).
> v3: Add Display WA notation and also apply for GLK.
> Both Forgotten on v2.
> Using "GLK_" prefix since GLK came before CNL.
> v4: Forgot to "|=" when moving directly macro to masked
> val. (Noticed by Paulo.)
> v5: Rebased on top of 0a46ddd57c9e ("drm/i915/cnp: Wa 1181:
> Fix Backlight issue")
>
> Cc: Imre Deak <imre.deak@intel.com>
> Cc: Paulo Zanoni <paulo.r.zanoni@intel.com>
> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
> Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
merge to dinq. thanks for the review.
> ---
> drivers/gpu/drm/i915/i915_reg.h | 3 +++
> drivers/gpu/drm/i915/intel_pm.c | 13 +++++++++++++
> 2 files changed, 16 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 5651081ff789..1878c4967529 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -2940,6 +2940,9 @@ enum i915_power_well_id {
> #define ILK_DPFC_CHICKEN _MMIO(0x43224)
> #define ILK_DPFC_DISABLE_DUMMY0 (1<<8)
> #define ILK_DPFC_NUKE_ON_ANY_MODIFICATION (1<<23)
> +#define GLK_SKIP_SEG_EN (1<<12)
> +#define GLK_SKIP_SEG_COUNT_MASK (3<<10)
> +#define GLK_SKIP_SEG_COUNT(x) ((x)<<10)
> #define ILK_FBC_RT_BASE _MMIO(0x2128)
> #define ILK_FBC_RT_VALID (1<<0)
> #define SNB_FBC_FRONT_BUFFER (1<<1)
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index f5d77b131b58..0201816a4229 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -125,6 +125,7 @@ static void bxt_init_clock_gating(struct drm_i915_private *dev_priv)
>
> static void glk_init_clock_gating(struct drm_i915_private *dev_priv)
> {
> + u32 val;
> gen9_init_clock_gating(dev_priv);
>
> /*
> @@ -144,6 +145,11 @@ static void glk_init_clock_gating(struct drm_i915_private *dev_priv)
> I915_WRITE(CHICKEN_MISC_2, val);
> }
>
> + /* Display WA #1133: WaFbcSkipSegments:glk */
> + val = I915_READ(ILK_DPFC_CHICKEN);
> + val &= ~GLK_SKIP_SEG_COUNT_MASK;
> + val |= GLK_SKIP_SEG_EN | GLK_SKIP_SEG_COUNT(1);
> + I915_WRITE(ILK_DPFC_CHICKEN, val);
> }
>
> static void i915_pineview_get_mem_freq(struct drm_i915_private *dev_priv)
> @@ -8275,6 +8281,7 @@ static void cnp_init_clock_gating(struct drm_i915_private *dev_priv)
>
> static void cnl_init_clock_gating(struct drm_i915_private *dev_priv)
> {
> + u32 val;
> cnp_init_clock_gating(dev_priv);
>
> /* This is not an Wa. Enable for better image quality */
> @@ -8294,6 +8301,12 @@ static void cnl_init_clock_gating(struct drm_i915_private *dev_priv)
> I915_WRITE(SLICE_UNIT_LEVEL_CLKGATE,
> I915_READ(SLICE_UNIT_LEVEL_CLKGATE) |
> SARBUNIT_CLKGATE_DIS);
> +
> + /* Display WA #1133: WaFbcSkipSegments:cnl */
> + val = I915_READ(ILK_DPFC_CHICKEN);
> + val &= ~GLK_SKIP_SEG_COUNT_MASK;
> + val |= GLK_SKIP_SEG_EN | GLK_SKIP_SEG_COUNT(1);
> + I915_WRITE(ILK_DPFC_CHICKEN, val);
> }
>
> static void cfl_init_clock_gating(struct drm_i915_private *dev_priv)
> --
> 2.13.2
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 17+ messages in thread
end of thread, other threads:[~2017-09-06 20:43 UTC | newest]
Thread overview: 17+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2017-08-29 23:08 [PATCH] drm/i915/cnl: WaFbcSkipSegments Rodrigo Vivi
2017-08-29 23:59 ` ✓ Fi.CI.BAT: success for " Patchwork
2017-08-30 3:40 ` ✗ Fi.CI.IGT: failure " Patchwork
2017-09-01 21:04 ` [PATCH] " Paulo Zanoni
2017-09-01 21:31 ` Rodrigo Vivi
2017-09-04 18:05 ` Paulo Zanoni
2017-09-05 17:56 ` Rodrigo Vivi
2017-09-05 18:05 ` [PATCH] drm/i915: Display WA #1133 WaFbcSkipSegments:cnl, glk Rodrigo Vivi
2017-09-05 18:59 ` Paulo Zanoni
2017-09-05 19:07 ` Rodrigo Vivi
2017-09-05 19:16 ` Paulo Zanoni
2017-09-05 18:23 ` ✓ Fi.CI.BAT: success for drm/i915/cnl: WaFbcSkipSegments (rev3) Patchwork
2017-09-05 19:26 ` ✓ Fi.CI.BAT: success for drm/i915/cnl: WaFbcSkipSegments (rev4) Patchwork
2017-09-05 20:43 ` ✗ Fi.CI.IGT: warning for drm/i915/cnl: WaFbcSkipSegments (rev3) Patchwork
2017-09-05 22:19 ` ✗ Fi.CI.IGT: failure for drm/i915/cnl: WaFbcSkipSegments (rev4) Patchwork
[not found] <Message-id: <1504638961.2824.38.camel@intel.com>
2017-09-05 19:30 ` [PATCH] drm/i915: Display WA #1133 WaFbcSkipSegments:cnl, glk Rodrigo Vivi
2017-09-06 20:43 ` Rodrigo Vivi
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