[PATCH 00/20] Add support for GuC-based SLPC

[PATCH 00/20] Add support for GuC-based SLPC

[Sagar Arun Kamble]

SLPC (Single Loop Power Controller) is a replacement for some host-based
power management features. The SLPC implementation runs in GuC firmware.
This series has been tested with SKL/APL/KBL GuC firmware v9 and v10
which are yet to be released on 01.org.

The graphics power management features in SLPC are called GTPERF,
BALANCER, and DCC.
1. GTPERF is a combination of DFPS (Dynamic FPS) and Turbo. DFPS adjusts
requested graphics frequency to maintain target framerate. Turbo adjusts
requested graphics frequency to maintain target GT busyness.
2. BALANCER adjusts balance between power budgets for IA and GT in power
limited scenarios.
3. DCC (Duty Cycle Control) adjusts requested graphics frequency and stalls
guc-scheduler to maintain actual graphics frequency in efficient range.

This series activates GTPERF Turbo and BALANCER in GuC SLPC.
Patch to enable SLPC by default on platforms having support is removed
from this series as there are following new changes to be added in future
before we enable GuC/SLPC by default:
1. Link waitboost with SLPC.
2. Handle CPG as part of SLPC.
3. IA p-state logic update with GuC submission.

In order to enable CI/PnP testing of SLPC and to avoid frequent
rebase, this series should be safe for merge with feature in disabled
state.

v2: Addressed review comments on v1. Removed patch to enable SLPC by
    default.

v3: Addressed WARNING in igt@drv_module_reload_basic flagged by trybot BAT.
    Added change for sanitizing GT PM during reset. Added separate patch
    for sysfs interface to know HW requested frequency. Also, earlier
    patches did not go as series hence were not correctly picked up by BAT.

v4: Changes to multiple patches. CI BAT is passing. Performance run on SKL
    GT2 done and shows perf at parity with Host Turbo. For BXT, SLPC
    improves performance when GuC is enabled compared to Host Turbo.
    This series keeps only support of 9.18 firmware for better readability.
    If needed, other SLPC interfaces for different GuC version will be
    added later.

v5: This series incorporates feedback from code reviews on earlier series
    and adds following new changes:
	1. More changes for separation of RPS and RC6 handling for Gen9.
	2. Tied up SLPC enabling with GuC load/GuC submission sequence.
	3. SLPC structures are defined explicitly for event input/output.
	4. Definition of SLPC parameter control and task control functions
	   agnostic to the underlying param definitions as they might
	   change with GuC versions and prepared helpers for common tasks.
	5. Transition of i915 overrides done through host to guc events
	   to shared data and single reset event.
	6. Handling SLPC status post reset through shared memory.
	7. Derived helpers for setting frequency limits.
	8. Removed sysfs interface to know RPNSWREQ as it is available in
	   debugfs interface i915_frequency_info.
	9. Simple igt test to verify SLPC configuration by i915 in various
	   driver scenarios is prepared.

v6: This series adds following new changes:
	1. Updated intel_guc_send for SLPC to receive output data from GuC.
	2. Added task overrides and min frequency overrides in intel_slpc_init.
	   min frequency is set to Rpe.
	3. New debugfs interface added to set/unset/read SLPC parameters
	   other than tasks and frequencies. SLPC reset post parameter update
	   added.
	4. SLPC parameters persist as part of i915-GuC shared data hence not
	   overriding frequency limits while re-enabling SLPC.
	5. Other minor fixes to clear pm_rps_events, clflush the shared data.

v7: This series adds following new changes:
	1. Reordered patches. SLPC communication interfaces (structures and
	   functions) are pulled into patches earlier in the series.
	2. Eliminated dependency on i915.enable_slpc at various functions where
	   rps_enabled is available.
	3. s/i915_ggtt_offset/guc_ggtt_offset and sanitization of parameter
	   in intel_uc_sanitize_options.

v8: Activated Balancer. Changed prototype of SLPC functions to accept
    struct intel_slpc as parameter instead of drm_i915_private.

VIZ-6889, VIZ-6890

Cc: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Daniel Vetter <daniel.vetter@intel.com>
Cc: Beuchat, Marc <marc.beuchat@intel.com>
Cc: Radoslaw Szwichtenberg <radoslaw.szwichtenberg@intel.com>
Cc: Jeff McGee <jeff.mcgee@intel.com>
Cc: Arkadiusz Hiler <arkadiusz.hiler@intel.com>
Cc: Oscar Mateo <oscar.mateo@intel.com>
Cc: Michał Winiarski <michal.winiarski@intel.com>

Sagar Arun Kamble (11):
  drm/i915/debugfs: Create generic string tokenize function and update
    CRC control parsing
  drm/i915/gen9+: Separate RPS and RC6 handling
  drm/i915/slpc: Lay out SLPC init/enable/disable/cleanup helpers
  drm/i915/slpc: Add SLPC communication interfaces
  drm/i915/slpc: Allocate/Release/Initialize SLPC shared data
  drm/i915/slpc: Add parameter set/unset/get, task control/status
    functions
  drm/i915/slpc: Send RESET event to enable SLPC
  drm/i915/slpc: Add support for min/max frequency control
  drm/i915/slpc: Add debugfs support to read/write/revert the parameters
  drm/i915/slpc: Add SLPC banner to RPS debugfs interfaces.
  drm/i915/slpc: Add Kabylake SLPC support

Tom O'Rourke (9):
  drm/i915/slpc: Add has_slpc capability flag
  drm/i915/slpc: Add enable_slpc module parameter
  drm/i915/slpc: Sanitize GuC version
  drm/i915/slpc: Enable SLPC in GuC if supported
  drm/i915/slpc: Send SHUTDOWN event
  drm/i915/slpc: Add enable/disable controls for SLPC tasks
  drm/i915/slpc: Add i915_slpc_info to debugfs
  drm/i915/slpc: Add SKL SLPC Support
  drm/i915/slpc: Add Broxton SLPC support

 drivers/gpu/drm/i915/Makefile           |   1 +
 drivers/gpu/drm/i915/i915_debugfs.c     | 243 +++++++-
 drivers/gpu/drm/i915/i915_drv.c         |  11 +-
 drivers/gpu/drm/i915/i915_drv.h         |  24 +-
 drivers/gpu/drm/i915/i915_irq.c         |   5 +
 drivers/gpu/drm/i915/i915_params.c      |   6 +
 drivers/gpu/drm/i915/i915_params.h      |   1 +
 drivers/gpu/drm/i915/i915_pci.c         |   3 +
 drivers/gpu/drm/i915/i915_sysfs.c       |  36 +-
 drivers/gpu/drm/i915/intel_csr.c        |  15 +-
 drivers/gpu/drm/i915/intel_drv.h        |   1 +
 drivers/gpu/drm/i915/intel_guc.c        |  26 +-
 drivers/gpu/drm/i915/intel_guc.h        |   6 +
 drivers/gpu/drm/i915/intel_guc_loader.c |  18 +
 drivers/gpu/drm/i915/intel_pipe_crc.c   |  88 +--
 drivers/gpu/drm/i915/intel_pm.c         | 117 +++-
 drivers/gpu/drm/i915/intel_slpc.c       | 985 ++++++++++++++++++++++++++++++++
 drivers/gpu/drm/i915/intel_slpc.h       | 274 +++++++++
 drivers/gpu/drm/i915/intel_uc.c         |  39 ++
 drivers/gpu/drm/i915/intel_uc_common.h  |   2 +
 20 files changed, 1806 insertions(+), 95 deletions(-)
 create mode 100644 drivers/gpu/drm/i915/intel_slpc.c
 create mode 100644 drivers/gpu/drm/i915/intel_slpc.h

-- 
1.9.1

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[PATCH 01/20] drm/i915/debugfs: Create generic string tokenize function and update CRC control parsing

[Sagar Arun Kamble]

Input string parsing used in CRC control parameter parsing is generic
and can be reused for other debugfs interfaces. Hence name it as
buffer_tokenize instead of tieing to display_crc. Also fix the function
desciption for CRC control parsing that was misplaced at tokenize function.

Cc: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Signed-off-by: Sagar Arun Kamble <sagar.a.kamble@intel.com>
---
 drivers/gpu/drm/i915/i915_drv.h       |  1 +
 drivers/gpu/drm/i915/intel_pipe_crc.c | 88 +++++++++++++++++------------------
 2 files changed, 45 insertions(+), 44 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 570e71e..db684dc 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -3801,6 +3801,7 @@ u32 i915_gem_fence_alignment(struct drm_i915_private *dev_priv, u32 size,
 int i915_debugfs_register(struct drm_i915_private *dev_priv);
 int i915_debugfs_connector_add(struct drm_connector *connector);
 void intel_display_crc_init(struct drm_i915_private *dev_priv);
+int buffer_tokenize(char *buf, char *words[], int max_words);
 #else
 static inline int i915_debugfs_register(struct drm_i915_private *dev_priv) {return 0;}
 static inline int i915_debugfs_connector_add(struct drm_connector *connector)
diff --git a/drivers/gpu/drm/i915/intel_pipe_crc.c b/drivers/gpu/drm/i915/intel_pipe_crc.c
index 96043a5..2e312b8 100644
--- a/drivers/gpu/drm/i915/intel_pipe_crc.c
+++ b/drivers/gpu/drm/i915/intel_pipe_crc.c
@@ -710,49 +710,6 @@ static int pipe_crc_set_source(struct drm_i915_private *dev_priv,
 	return ret;
 }
 
-/*
- * Parse pipe CRC command strings:
- *   command: wsp* object wsp+ name wsp+ source wsp*
- *   object: 'pipe'
- *   name: (A | B | C)
- *   source: (none | plane1 | plane2 | pf)
- *   wsp: (#0x20 | #0x9 | #0xA)+
- *
- * eg.:
- *  "pipe A plane1"  ->  Start CRC computations on plane1 of pipe A
- *  "pipe A none"    ->  Stop CRC
- */
-static int display_crc_ctl_tokenize(char *buf, char *words[], int max_words)
-{
-	int n_words = 0;
-
-	while (*buf) {
-		char *end;
-
-		/* skip leading white space */
-		buf = skip_spaces(buf);
-		if (!*buf)
-			break;	/* end of buffer */
-
-		/* find end of word */
-		for (end = buf; *end && !isspace(*end); end++)
-			;
-
-		if (n_words == max_words) {
-			DRM_DEBUG_DRIVER("too many words, allowed <= %d\n",
-					 max_words);
-			return -EINVAL;	/* ran out of words[] before bytes */
-		}
-
-		if (*end)
-			*end++ = '\0';
-		words[n_words++] = buf;
-		buf = end;
-	}
-
-	return n_words;
-}
-
 enum intel_pipe_crc_object {
 	PIPE_CRC_OBJECT_PIPE,
 };
@@ -806,6 +763,49 @@ static int display_crc_ctl_parse_pipe(const char *buf, enum pipe *pipe)
 	return -EINVAL;
 }
 
+int buffer_tokenize(char *buf, char *words[], int max_words)
+{
+	int n_words = 0;
+
+	while (*buf) {
+		char *end;
+
+		/* skip leading white space */
+		buf = skip_spaces(buf);
+		if (!*buf)
+			break;	/* end of buffer */
+
+		/* find end of word */
+		for (end = buf; *end && !isspace(*end); end++)
+			;
+
+		if (n_words == max_words) {
+			DRM_DEBUG_DRIVER("too many words, allowed <= %d\n",
+					 max_words);
+			return -EINVAL;	/* ran out of words[] before bytes */
+		}
+
+		if (*end)
+			*end++ = '\0';
+		words[n_words++] = buf;
+		buf = end;
+	}
+
+	return n_words;
+}
+
+/*
+ * Parse pipe CRC command strings:
+ *   command: wsp* object wsp+ name wsp+ source wsp*
+ *   object: 'pipe'
+ *   name: (A | B | C)
+ *   source: (none | plane1 | plane2 | pf)
+ *   wsp: (#0x20 | #0x9 | #0xA)+
+ *
+ * eg.:
+ *  "pipe A plane1"  ->  Start CRC computations on plane1 of pipe A
+ *  "pipe A none"    ->  Stop CRC
+ */
 static int display_crc_ctl_parse(struct drm_i915_private *dev_priv,
 				 char *buf, size_t len)
 {
@@ -816,7 +816,7 @@ static int display_crc_ctl_parse(struct drm_i915_private *dev_priv,
 	enum intel_pipe_crc_object object;
 	enum intel_pipe_crc_source source;
 
-	n_words = display_crc_ctl_tokenize(buf, words, N_WORDS);
+	n_words = buffer_tokenize(buf, words, N_WORDS);
 	if (n_words != N_WORDS) {
 		DRM_DEBUG_DRIVER("tokenize failed, a command is %d words\n",
 				 N_WORDS);
-- 
1.9.1

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[PATCH 02/20] drm/i915/gen9+: Separate RPS and RC6 handling

[Sagar Arun Kamble]

With GuC based SLPC, frequency control will be moved to GuC and Host will
continue to control RC6 and Ring frequency setup. SLPC can be enabled in
the GuC setup path and can happen in parallel in GuC with other i915 setup.
Hence we can do away with deferred RPS enabling. This needs separate
handling of RPS, RC6 and ring frequencies in driver flows. We can still use
the *gt_powersave routines with separate status variables of RPS, RC6 and
SLPC. With this patch, RC6 and ring frequencies setup(if applicable) can be
tracked through rps.rc6_enabled and RPS through rps.rps_enabled.
Also, Active RPS check in suspend flow is needed for platforms with RC6
and RPS enabling/disabling coupled together. RPM suspend depends only on
RC6 though. Hence Active RPS check is done only for non-Gen9 platforms.

v2: Changing parameter to dev_priv for IS_GEN9 and HAS_RUNTIME_PM and line
    spacing changes. (David)
    and commit message update for checkpatch issues.

v3: Rebase.

v4: Commit message update.

v5: Updated intel_enable_gt_powersave and intel_disable_gt_powersave
    routines with separated RPS and RC6 handling and rebase. Commit message
    update.(Sagar)

v6: Added comments at the definition of rc6_enabled.

v7: s/rps.enabled/rps.rps_enabled. With gen9 preproduction RPS disabling
    changes removed, updating rps_enabled in enable/disable_gt_powersave.
    Added checks for rc6_enabled and rps_enabled for gen9+ platforms.

Signed-off-by: Sagar Arun Kamble <sagar.a.kamble@intel.com>
---
 drivers/gpu/drm/i915/i915_debugfs.c |  4 +-
 drivers/gpu/drm/i915/i915_drv.c     |  9 +++-
 drivers/gpu/drm/i915/i915_drv.h     |  9 +++-
 drivers/gpu/drm/i915/intel_pm.c     | 88 ++++++++++++++++++++++++++-----------
 4 files changed, 80 insertions(+), 30 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
index 48572b1..b3fb7350 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -2252,7 +2252,7 @@ static int i915_rps_boost_info(struct seq_file *m, void *data)
 	struct drm_device *dev = &dev_priv->drm;
 	struct drm_file *file;
 
-	seq_printf(m, "RPS enabled? %d\n", dev_priv->rps.enabled);
+	seq_printf(m, "RPS enabled? %d\n", dev_priv->rps.rps_enabled);
 	seq_printf(m, "GPU busy? %s [%d requests]\n",
 		   yesno(dev_priv->gt.awake), dev_priv->gt.active_requests);
 	seq_printf(m, "CPU waiting? %d\n", count_irq_waiters(dev_priv));
@@ -2288,7 +2288,7 @@ static int i915_rps_boost_info(struct seq_file *m, void *data)
 	mutex_unlock(&dev->filelist_mutex);
 
 	if (INTEL_GEN(dev_priv) >= 6 &&
-	    dev_priv->rps.enabled &&
+	    dev_priv->rps.rps_enabled &&
 	    dev_priv->gt.active_requests) {
 		u32 rpup, rpupei;
 		u32 rpdown, rpdownei;
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index b6cc2fe..54ccd13 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -2468,9 +2468,16 @@ static int intel_runtime_suspend(struct device *kdev)
 	struct drm_i915_private *dev_priv = to_i915(dev);
 	int ret;
 
-	if (WARN_ON_ONCE(!(dev_priv->rps.enabled && intel_enable_rc6())))
+	if (WARN_ON_ONCE(!intel_enable_rc6()))
 		return -ENODEV;
 
+	if (INTEL_GEN(dev_priv) >= 9) {
+		if (WARN_ON_ONCE(!dev_priv->rps.rc6_enabled))
+			return -ENODEV;
+	} else if (WARN_ON_ONCE(!dev_priv->rps.rps_enabled)) {
+		return -ENODEV;
+	}
+
 	if (WARN_ON_ONCE(!HAS_RUNTIME_PM(dev_priv)))
 		return -ENODEV;
 
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index db684dc..57fe045 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1336,7 +1336,12 @@ struct intel_gen6_power_mgmt {
 	int last_adj;
 	enum { LOW_POWER, BETWEEN, HIGH_POWER } power;
 
-	bool enabled;
+	/*
+	 * For platforms prior to Gen9, RPS and RC6 status is tracked through
+	 * "rps_enabled". For Gen9+, RC6 is tracked through "rc6_enabled".
+	 */
+	bool rps_enabled;
+	bool rc6_enabled;
 	struct delayed_work autoenable_work;
 	atomic_t num_waiters;
 	atomic_t boosts;
@@ -2376,7 +2381,7 @@ struct drm_i915_private {
 	/* Cannot be determined by PCIID. You must always read a register. */
 	u32 edram_cap;
 
-	/* gen6+ rps state */
+	/* gen6+ rps/rc6 state */
 	struct intel_gen6_power_mgmt rps;
 
 	/* ilk-only ips/rps state. Everything in here is protected by the global
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index b0ba5a1..a1b32e1 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -6118,7 +6118,7 @@ static void vlv_set_rps_idle(struct drm_i915_private *dev_priv)
 void gen6_rps_busy(struct drm_i915_private *dev_priv)
 {
 	mutex_lock(&dev_priv->rps.hw_lock);
-	if (dev_priv->rps.enabled) {
+	if (dev_priv->rps.rps_enabled) {
 		u8 freq;
 
 		if (dev_priv->pm_rps_events & GEN6_PM_RP_UP_EI_EXPIRED)
@@ -6153,7 +6153,7 @@ void gen6_rps_idle(struct drm_i915_private *dev_priv)
 	gen6_disable_rps_interrupts(dev_priv);
 
 	mutex_lock(&dev_priv->rps.hw_lock);
-	if (dev_priv->rps.enabled) {
+	if (dev_priv->rps.rps_enabled) {
 		if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
 			vlv_set_rps_idle(dev_priv);
 		else
@@ -6175,7 +6175,7 @@ void gen6_rps_boost(struct drm_i915_gem_request *rq,
 	/* This is intentionally racy! We peek at the state here, then
 	 * validate inside the RPS worker.
 	 */
-	if (!i915->rps.enabled)
+	if (!i915->rps.rps_enabled)
 		return;
 
 	boost = false;
@@ -6203,7 +6203,7 @@ int intel_set_rps(struct drm_i915_private *dev_priv, u8 val)
 	GEM_BUG_ON(val > dev_priv->rps.max_freq);
 	GEM_BUG_ON(val < dev_priv->rps.min_freq);
 
-	if (!dev_priv->rps.enabled) {
+	if (!dev_priv->rps.rps_enabled) {
 		dev_priv->rps.cur_freq = val;
 		return 0;
 	}
@@ -6220,6 +6220,8 @@ static void gen9_disable_rc6(struct drm_i915_private *dev_priv)
 {
 	I915_WRITE(GEN6_RC_CONTROL, 0);
 	I915_WRITE(GEN9_PG_ENABLE, 0);
+
+	dev_priv->rps.rc6_enabled = false;
 }
 
 static void gen9_disable_rps(struct drm_i915_private *dev_priv)
@@ -6507,6 +6509,8 @@ static void gen9_enable_rc6(struct drm_i915_private *dev_priv)
 		I915_WRITE(GEN9_PG_ENABLE, (rc6_mask & GEN6_RC_CTL_RC6_ENABLE) ?
 				(GEN9_RENDER_PG_ENABLE | GEN9_MEDIA_PG_ENABLE) : 0);
 
+	dev_priv->rps.rc6_enabled = true;
+
 	intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
 }
 
@@ -7808,21 +7812,23 @@ void intel_suspend_gt_powersave(struct drm_i915_private *dev_priv)
 
 void intel_sanitize_gt_powersave(struct drm_i915_private *dev_priv)
 {
-	dev_priv->rps.enabled = true; /* force disabling */
+	dev_priv->rps.rps_enabled = true; /* force disabling */
+	dev_priv->rps.rc6_enabled = true;
 	intel_disable_gt_powersave(dev_priv);
 
 	gen6_reset_rps_interrupts(dev_priv);
 }
 
-void intel_disable_gt_powersave(struct drm_i915_private *dev_priv)
+/*
+ * This function disables RPS and RC6 for platforms prior to GEN9 and
+ * disables only RPS for GEN9+.
+ */
+void __intel_disable_gt_powersave(struct drm_i915_private *dev_priv)
 {
-	if (!READ_ONCE(dev_priv->rps.enabled))
+	if (!READ_ONCE(dev_priv->rps.rps_enabled))
 		return;
 
-	mutex_lock(&dev_priv->rps.hw_lock);
-
 	if (INTEL_GEN(dev_priv) >= 9) {
-		gen9_disable_rc6(dev_priv);
 		gen9_disable_rps(dev_priv);
 	} else if (IS_CHERRYVIEW(dev_priv)) {
 		cherryview_disable_rps(dev_priv);
@@ -7834,33 +7840,40 @@ void intel_disable_gt_powersave(struct drm_i915_private *dev_priv)
 		ironlake_disable_drps(dev_priv);
 	}
 
-	dev_priv->rps.enabled = false;
+	dev_priv->rps.rps_enabled = false;
+}
+
+void intel_disable_gt_powersave(struct drm_i915_private *dev_priv)
+{
+	mutex_lock(&dev_priv->rps.hw_lock);
+
+	if (INTEL_GEN(dev_priv) >= 9) {
+		if (READ_ONCE(dev_priv->rps.rc6_enabled))
+			gen9_disable_rc6(dev_priv);
+	}
+	__intel_disable_gt_powersave(dev_priv);
+
 	mutex_unlock(&dev_priv->rps.hw_lock);
 }
 
-void intel_enable_gt_powersave(struct drm_i915_private *dev_priv)
+/*
+ * This function enables RPS and RC6 for platforms prior to GEN9 and
+ * enables only RPS for GEN9+.
+ */
+void __intel_enable_gt_powersave(struct drm_i915_private *dev_priv)
 {
 	/* We shouldn't be disabling as we submit, so this should be less
 	 * racy than it appears!
 	 */
-	if (READ_ONCE(dev_priv->rps.enabled))
+	if (READ_ONCE(dev_priv->rps.rps_enabled))
 		return;
 
-	/* Powersaving is controlled by the host when inside a VM */
-	if (intel_vgpu_active(dev_priv))
-		return;
-
-	mutex_lock(&dev_priv->rps.hw_lock);
-
 	if (IS_CHERRYVIEW(dev_priv)) {
 		cherryview_enable_rps(dev_priv);
 	} else if (IS_VALLEYVIEW(dev_priv)) {
 		valleyview_enable_rps(dev_priv);
 	} else if (INTEL_GEN(dev_priv) >= 9) {
-		gen9_enable_rc6(dev_priv);
 		gen9_enable_rps(dev_priv);
-		if (IS_GEN9_BC(dev_priv) || IS_CANNONLAKE(dev_priv))
-			gen6_update_ring_freq(dev_priv);
 	} else if (IS_BROADWELL(dev_priv)) {
 		gen8_enable_rps(dev_priv);
 		gen6_update_ring_freq(dev_priv);
@@ -7878,10 +7891,35 @@ void intel_enable_gt_powersave(struct drm_i915_private *dev_priv)
 	WARN_ON(dev_priv->rps.efficient_freq < dev_priv->rps.min_freq);
 	WARN_ON(dev_priv->rps.efficient_freq > dev_priv->rps.max_freq);
 
-	dev_priv->rps.enabled = true;
+	dev_priv->rps.rps_enabled = true;
+}
+
+void intel_enable_gt_powersave(struct drm_i915_private *dev_priv)
+{
+	/* Powersaving is controlled by the host when inside a VM */
+	if (intel_vgpu_active(dev_priv))
+		return;
+
+	mutex_lock(&dev_priv->rps.hw_lock);
+
+	if (INTEL_GEN(dev_priv) >= 9) {
+		if (!READ_ONCE(dev_priv->rps.rc6_enabled))
+			gen9_enable_rc6(dev_priv);
+		if (IS_GEN9_BC(dev_priv) || IS_CANNONLAKE(dev_priv))
+			gen6_update_ring_freq(dev_priv);
+	}
+	__intel_enable_gt_powersave(dev_priv);
+
 	mutex_unlock(&dev_priv->rps.hw_lock);
 }
 
+#define GT_POWERSAVE_ENABLED(dev_priv) \
+	(((INTEL_GEN(dev_priv) >= 9) && \
+		(READ_ONCE(dev_priv->rps.rps_enabled) && \
+		 READ_ONCE(dev_priv->rps.rc6_enabled))) || \
+	 ((INTEL_GEN(dev_priv) < 9) && \
+		READ_ONCE(dev_priv->rps.rps_enabled)))
+
 static void __intel_autoenable_gt_powersave(struct work_struct *work)
 {
 	struct drm_i915_private *dev_priv =
@@ -7889,7 +7927,7 @@ static void __intel_autoenable_gt_powersave(struct work_struct *work)
 	struct intel_engine_cs *rcs;
 	struct drm_i915_gem_request *req;
 
-	if (READ_ONCE(dev_priv->rps.enabled))
+	if (GT_POWERSAVE_ENABLED(dev_priv))
 		goto out;
 
 	rcs = dev_priv->engine[RCS];
@@ -7919,7 +7957,7 @@ static void __intel_autoenable_gt_powersave(struct work_struct *work)
 
 void intel_autoenable_gt_powersave(struct drm_i915_private *dev_priv)
 {
-	if (READ_ONCE(dev_priv->rps.enabled))
+	if (GT_POWERSAVE_ENABLED(dev_priv))
 		return;
 
 	if (IS_IRONLAKE_M(dev_priv)) {
-- 
1.9.1

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[PATCH 03/20] drm/i915/slpc: Add has_slpc capability flag

[Sagar Arun Kamble]

From: Tom O'Rourke <Tom.O'Rourke@intel.com>

Add has_slpc capablity flag to indicate GuC firmware
supports single loop power control (SLPC).  SLPC is
a replacement for some host-based power management
features.

v1: fix whitespace (Sagar)

Reviewed-by: David Weinehall <david.weinehall@linux.intel.com>
Signed-off-by: Tom O'Rourke <Tom.O'Rourke@intel.com>
Signed-off-by: Sagar Arun Kamble <sagar.a.kamble@intel.com>
---
 drivers/gpu/drm/i915/i915_drv.h | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 57fe045..5822d1f 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -793,6 +793,7 @@ struct intel_csr {
 	func(has_rc6p); \
 	func(has_resource_streamer); \
 	func(has_runtime_pm); \
+	func(has_slpc); \
 	func(has_snoop); \
 	func(unfenced_needs_alignment); \
 	func(cursor_needs_physical); \
@@ -3105,6 +3106,7 @@ static inline struct scatterlist *__sg_next(struct scatterlist *sg)
 #define HAS_GUC_UCODE(dev_priv)	(HAS_GUC(dev_priv))
 #define HAS_GUC_SCHED(dev_priv)	(HAS_GUC(dev_priv))
 #define HAS_HUC_UCODE(dev_priv)	(HAS_GUC(dev_priv))
+#define HAS_SLPC(dev_priv)	((dev_priv)->info.has_slpc)
 
 #define HAS_RESOURCE_STREAMER(dev_priv) ((dev_priv)->info.has_resource_streamer)
 
-- 
1.9.1

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[PATCH 04/20] drm/i915/slpc: Add enable_slpc module parameter

[Sagar Arun Kamble]

From: Tom O'Rourke <Tom.O'Rourke@intel.com>

i915.enable_slpc is used to override the default for slpc usage.
The expected values are -1=auto, 0=disabled [default], 1=enabled.

Sanitize i915.enable_slpc to either 0 or 1 based on HAS_SLPC() and
GuC load and submission options.

v1: Add early call to sanitize enable_slpc in intel_guc_ucode_init
    Remove sanitize enable_slpc call before firmware version check
    is performed. (ChrisW)
    Version check is added in next patch and that will be done as
    part of slpc_enable_sanitize function in the next patch. (Sagar)
    Updated slpc option sanitize function call for platforms without
    GuC support. This was caught by CI BAT.

v2: Changed parameter to dev_priv for HAS_SLPC macro. (David)
    Code indentation based on checkpatch.

v3: Rebase.

v4: Moved sanitization of SLPC option post GuC load.

v5: Removed function intel_slpc_enabled. Planning to rely only on
    kernel parameter. Moved sanitization prior to GuC load to use the
    parameter during SLPC state setup during to GuC load. (Sagar)

v6: Commit message update. Rebase.

v7: Moved SLPC option sanitization to intel_uc_sanitize_options.

Suggested-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Signed-off-by: Tom O'Rourke <Tom.O'Rourke@intel.com>
Signed-off-by: Sagar Arun Kamble <sagar.a.kamble@intel.com>
---
 drivers/gpu/drm/i915/i915_params.c |  6 ++++++
 drivers/gpu/drm/i915/i915_params.h |  1 +
 drivers/gpu/drm/i915/intel_uc.c    | 13 +++++++++++++
 3 files changed, 20 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_params.c b/drivers/gpu/drm/i915/i915_params.c
index 8ab003d..be365b4 100644
--- a/drivers/gpu/drm/i915/i915_params.c
+++ b/drivers/gpu/drm/i915/i915_params.c
@@ -36,6 +36,7 @@ struct i915_params i915 __read_mostly = {
 	.enable_dc = -1,
 	.enable_fbc = -1,
 	.enable_execlists = -1,
+	.enable_slpc = 0,
 	.enable_hangcheck = true,
 	.enable_ppgtt = -1,
 	.enable_psr = -1,
@@ -146,6 +147,11 @@ struct i915_params i915 __read_mostly = {
 	"Override execlists usage. "
 	"(-1=auto [default], 0=disabled, 1=enabled)");
 
+module_param_named_unsafe(enable_slpc, i915.enable_slpc, int, 0400);
+MODULE_PARM_DESC(enable_slpc,
+	"Override single-loop-power-controller (slpc) usage. "
+	"(-1=auto, 0=disabled [default], 1=enabled)");
+
 module_param_named_unsafe(enable_psr, i915.enable_psr, int, 0600);
 MODULE_PARM_DESC(enable_psr, "Enable PSR "
 		 "(0=disabled, 1=enabled - link mode chosen per-platform, 2=force link-standby mode, 3=force link-off mode) "
diff --git a/drivers/gpu/drm/i915/i915_params.h b/drivers/gpu/drm/i915/i915_params.h
index ac84470..d5c7bfb 100644
--- a/drivers/gpu/drm/i915/i915_params.h
+++ b/drivers/gpu/drm/i915/i915_params.h
@@ -41,6 +41,7 @@
 	func(int, enable_ppgtt); \
 	func(int, enable_execlists); \
 	func(int, enable_psr); \
+	func(int, enable_slpc); \
 	func(int, disable_power_well); \
 	func(int, enable_ips); \
 	func(int, invert_brightness); \
diff --git a/drivers/gpu/drm/i915/intel_uc.c b/drivers/gpu/drm/i915/intel_uc.c
index 9216c73..70d11c2 100644
--- a/drivers/gpu/drm/i915/intel_uc.c
+++ b/drivers/gpu/drm/i915/intel_uc.c
@@ -68,6 +68,7 @@ void intel_uc_sanitize_options(struct drm_i915_private *dev_priv)
 
 		i915.enable_guc_loading = 0;
 		i915.enable_guc_submission = 0;
+		i915.enable_slpc = 0;
 		return;
 	}
 
@@ -91,6 +92,18 @@ void intel_uc_sanitize_options(struct drm_i915_private *dev_priv)
 	/* A negative value means "use platform default" */
 	if (i915.enable_guc_submission < 0)
 		i915.enable_guc_submission = HAS_GUC_SCHED(dev_priv);
+
+	/* slpc requires hardware support and compatible firmware */
+	if (!HAS_SLPC(dev_priv))
+		i915.enable_slpc = 0;
+
+	/* slpc requires guc loaded */
+	if (!i915.enable_guc_loading)
+		i915.enable_slpc = 0;
+
+	/* slpc requires guc submission */
+	if (!i915.enable_guc_submission)
+		i915.enable_slpc = 0;
 }
 
 void intel_uc_init_early(struct drm_i915_private *dev_priv)
-- 
1.9.1

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[PATCH 05/20] drm/i915/slpc: Sanitize GuC version

[Sagar Arun Kamble]

From: Tom O'Rourke <Tom.O'Rourke@intel.com>

The SLPC interface is dependent on GuC version.
Only GuC versions known to be compatible are supported here.

SLPC with GuC firmware v9 is supported with this series.

v1: Updated with modified sanitize_slpc_option in earlier patch.

v2-v3: Rebase.

v4: Updated support for GuC firmware v9.

v5: Commit subject updated.

v6: Commit subject and message update. Add support condition as >=v9.

v7: Sanitizing GuC version in intel_uc_init_fw for SLPC compatibility.
    Added info. print for needed version and pointer to 01.org.

v8: s/FIRMWARE_URL/I915_FIRMWARE_URL, Macro added for SLPC required GuC
    Major version and rearrangement for sanitization. (MichalW, Joonas)

v9: Checking major_ver_found to sanitize SLPC option enable_slpc post
    fetching the firmware as with Custom firmware loaded through
    guc_firmware_path parameter, major_ver_wanted are cleared. (Lukasz)

Signed-off-by: Tom O'Rourke <Tom.O'Rourke@intel.com>
Signed-off-by: Sagar Arun Kamble <sagar.a.kamble@intel.com>
---
 drivers/gpu/drm/i915/intel_csr.c        | 15 ++++++---------
 drivers/gpu/drm/i915/intel_guc.h        |  1 +
 drivers/gpu/drm/i915/intel_guc_loader.c | 15 +++++++++++++++
 drivers/gpu/drm/i915/intel_uc.c         |  1 +
 drivers/gpu/drm/i915/intel_uc_common.h  |  2 ++
 5 files changed, 25 insertions(+), 9 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_csr.c b/drivers/gpu/drm/i915/intel_csr.c
index 965988f..56c56f5 100644
--- a/drivers/gpu/drm/i915/intel_csr.c
+++ b/drivers/gpu/drm/i915/intel_csr.c
@@ -52,11 +52,6 @@
 MODULE_FIRMWARE(I915_CSR_BXT);
 #define BXT_CSR_VERSION_REQUIRED	CSR_VERSION(1, 7)
 
-#define FIRMWARE_URL  "https://01.org/linuxgraphics/downloads/firmware"
-
-
-
-
 #define CSR_MAX_FW_SIZE			0x2FFF
 #define CSR_DEFAULT_FW_OFFSET		0xFFFFFFFF
 
@@ -309,11 +304,12 @@ static uint32_t *parse_csr_fw(struct drm_i915_private *dev_priv,
 
 	if (csr->version != required_version) {
 		DRM_INFO("Refusing to load DMC firmware v%u.%u,"
-			 " please use v%u.%u [" FIRMWARE_URL "].\n",
+			 " please use v%u.%u [%s].\n",
 			 CSR_VERSION_MAJOR(csr->version),
 			 CSR_VERSION_MINOR(csr->version),
 			 CSR_VERSION_MAJOR(required_version),
-			 CSR_VERSION_MINOR(required_version));
+			 CSR_VERSION_MINOR(required_version),
+			 I915_FIRMWARE_URL);
 		return NULL;
 	}
 
@@ -420,8 +416,9 @@ static void csr_load_work_fn(struct work_struct *work)
 	} else {
 		dev_notice(dev_priv->drm.dev,
 			   "Failed to load DMC firmware"
-			   " [" FIRMWARE_URL "],"
-			   " disabling runtime power management.\n");
+			   " [%s],"
+			   " disabling runtime power management.\n",
+			   I915_FIRMWARE_URL);
 	}
 
 	release_firmware(fw);
diff --git a/drivers/gpu/drm/i915/intel_guc.h b/drivers/gpu/drm/i915/intel_guc.h
index 1b3305f..e77ce1f 100644
--- a/drivers/gpu/drm/i915/intel_guc.h
+++ b/drivers/gpu/drm/i915/intel_guc.h
@@ -186,6 +186,7 @@ static inline void intel_guc_notify(struct intel_guc *guc)
 int intel_guc_select_fw(struct intel_guc *guc);
 int intel_guc_init_hw(struct intel_guc *guc);
 u32 intel_guc_wopcm_size(struct drm_i915_private *dev_priv);
+void intel_guc_fetch_sanitize_options(struct intel_guc *guc);
 
 /* i915_guc_submission.c */
 int i915_guc_submission_init(struct drm_i915_private *dev_priv);
diff --git a/drivers/gpu/drm/i915/intel_guc_loader.c b/drivers/gpu/drm/i915/intel_guc_loader.c
index d2b027c..1c3a242 100644
--- a/drivers/gpu/drm/i915/intel_guc_loader.c
+++ b/drivers/gpu/drm/i915/intel_guc_loader.c
@@ -63,6 +63,8 @@
 #define GLK_FW_MAJOR 10
 #define GLK_FW_MINOR 56
 
+#define I915_SLPC_REQUIRED_GUC_MAJOR 9
+
 #define GUC_FW_PATH(platform, major, minor) \
        "i915/" __stringify(platform) "_guc_ver" __stringify(major) "_" __stringify(minor) ".bin"
 
@@ -426,3 +428,16 @@ int intel_guc_select_fw(struct intel_guc *guc)
 
 	return 0;
 }
+
+void intel_guc_fetch_sanitize_options(struct intel_guc *guc)
+{
+	if (guc->fw.major_ver_found <
+			I915_SLPC_REQUIRED_GUC_MAJOR) {
+		DRM_INFO("SLPC not supported with GuC firmware"
+			 " v%u, please use v%u+ [%s].\n",
+			 guc->fw.major_ver_found,
+			 I915_SLPC_REQUIRED_GUC_MAJOR,
+			 I915_FIRMWARE_URL);
+		i915.enable_slpc = 0;
+	}
+}
diff --git a/drivers/gpu/drm/i915/intel_uc.c b/drivers/gpu/drm/i915/intel_uc.c
index 70d11c2..19a2847 100644
--- a/drivers/gpu/drm/i915/intel_uc.c
+++ b/drivers/gpu/drm/i915/intel_uc.c
@@ -195,6 +195,7 @@ static void fetch_uc_fw(struct drm_i915_private *dev_priv,
 		}
 		uc_fw->major_ver_found = css->guc.sw_version >> 16;
 		uc_fw->minor_ver_found = css->guc.sw_version & 0xFFFF;
+		intel_guc_fetch_sanitize_options(&dev_priv->guc);
 		break;
 
 	case INTEL_UC_FW_TYPE_HUC:
diff --git a/drivers/gpu/drm/i915/intel_uc_common.h b/drivers/gpu/drm/i915/intel_uc_common.h
index c6e873d..4564ca0 100644
--- a/drivers/gpu/drm/i915/intel_uc_common.h
+++ b/drivers/gpu/drm/i915/intel_uc_common.h
@@ -24,6 +24,8 @@
 #ifndef _INTEL_UC_COMMON_H_
 #define _INTEL_UC_COMMON_H_
 
+#define I915_FIRMWARE_URL  "https://01.org/linuxgraphics/intel-linux-graphics-firmwares"
+
 enum intel_uc_fw_status {
 	INTEL_UC_FIRMWARE_FAIL = -1,
 	INTEL_UC_FIRMWARE_NONE = 0,
-- 
1.9.1

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[PATCH 06/20] drm/i915/slpc: Lay out SLPC init/enable/disable/cleanup helpers

[Sagar Arun Kamble]

SLPC operates based on parameters setup in shared data between
i915 and GuC SLPC. This is to be created/initialized in intel_slpc_init.
>From then onwards i915 can control the SLPC operations by Enabling,
Disabling complete SLPC or changing SLPC parameters. During cleanup
SLPC shared data has to be freed.
With this patch on platforms with SLPC support we call intel_slpc_*()
functions from GuC setup functions and do not use Host rps functions.
With SLPC, intel_enable_gt_powersave will only handle RC6 and ring
frequencies. In the later patch intel_init_gt_powersave will check
if SLPC has started running through shared data and update initial
state that i915 needs like frequency limits.

v1: Return void instead of ignored error code (Paulo)
    enable/disable RC6 in SLPC flows (Sagar)
    replace HAS_SLPC() use with intel_slpc_enabled()
	or intel_slpc_active() (Paulo)
    Fix for renaming gen9_disable_rps to gen9_disable_rc6 in
    "drm/i915/bxt: Explicitly clear the Turbo control register"
    Defer RC6 and SLPC enabling to intel_gen6_powersave_work. (Sagar)
    Performance drop with SLPC was happening as ring frequency table
    was not programmed when SLPC was enabled. This patch programs ring
    frequency table with SLPC. Initial reset of SLPC is based on kernel
    parameter as planning to add slpc state in intel_slpc_active. Cleanup
    is also based on kernel parameter as SLPC gets disabled in
    disable/suspend.(Sagar)

v2: Usage of INTEL_GEN instead of INTEL_INFO->gen (David)
    Checkpatch update.

v3: Rebase

v4: Removed reset functions to comply with *_gt_powersave routines.
    (Sagar)

v5: Removed intel_slpc_active. Relying on slpc.active for control flows
    that are based on SLPC active status in GuC. State setup/cleanup needed
    for SLPC is handled using kernel parameter i915.enable_slpc. Moved SLPC
    init and enabling to GuC enable path as SLPC in GuC can start doing the
    setup post GuC init. Commit message update. (Sagar)

v6: Rearranged function definitions.

v7: Makefile rearrangement. Reducing usage of i915.enable_slpc and relying
    mostly on rps.rps_enabled to bypass Host RPS flows. Commit message
    update.

v8: Changed parameters for SLPC functions to struct intel_slpc*.

Signed-off-by: Tom O'Rourke <Tom.O'Rourke@intel.com>
Signed-off-by: Sagar Arun Kamble <sagar.a.kamble@intel.com>
---
 drivers/gpu/drm/i915/Makefile     |  1 +
 drivers/gpu/drm/i915/i915_drv.h   | 12 +++++++++++
 drivers/gpu/drm/i915/i915_irq.c   |  5 +++++
 drivers/gpu/drm/i915/intel_guc.c  |  5 +++++
 drivers/gpu/drm/i915/intel_guc.h  |  3 +++
 drivers/gpu/drm/i915/intel_pm.c   | 23 ++++++++++++++++++---
 drivers/gpu/drm/i915/intel_slpc.c | 42 +++++++++++++++++++++++++++++++++++++++
 drivers/gpu/drm/i915/intel_slpc.h | 37 ++++++++++++++++++++++++++++++++++
 drivers/gpu/drm/i915/intel_uc.c   | 25 +++++++++++++++++++++++
 9 files changed, 150 insertions(+), 3 deletions(-)
 create mode 100644 drivers/gpu/drm/i915/intel_slpc.c
 create mode 100644 drivers/gpu/drm/i915/intel_slpc.h

diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index efc5b30..98b4a9a 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -64,6 +64,7 @@ i915-y += intel_uc.o \
 	  intel_guc_log.o \
 	  intel_guc_loader.o \
 	  intel_huc.o \
+	  intel_slpc.o \
 	  i915_guc_submission.o
 
 # autogenerated null render state
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 5822d1f..64ba847 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -2710,6 +2710,18 @@ static inline struct drm_i915_private *guc_to_i915(struct intel_guc *guc)
 	return container_of(guc, struct drm_i915_private, guc);
 }
 
+static inline struct intel_guc *slpc_to_guc(struct intel_slpc *slpc)
+{
+	return container_of(slpc, struct intel_guc, slpc);
+}
+
+static inline struct drm_i915_private *slpc_to_i915(struct intel_slpc *slpc)
+{
+	struct intel_guc *guc = slpc_to_guc(slpc);
+
+	return guc_to_i915(guc);
+}
+
 static inline struct drm_i915_private *huc_to_i915(struct intel_huc *huc)
 {
 	return container_of(huc, struct drm_i915_private, huc);
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 5d391e6..0ff070f 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -2620,6 +2620,11 @@ static void i915_reset_device(struct drm_i915_private *dev_priv)
 		set_bit(I915_RESET_HANDOFF, &dev_priv->gpu_error.flags);
 		wake_up_all(&dev_priv->gpu_error.wait_queue);
 
+		/*
+		 * TODO: Enable SLPC with TDR indication to SLPC in case of
+		 * Engine Reset.
+		 */
+
 		/* Wait for anyone holding the lock to wakeup, without
 		 * blocking indefinitely on struct_mutex.
 		 */
diff --git a/drivers/gpu/drm/i915/intel_guc.c b/drivers/gpu/drm/i915/intel_guc.c
index da81c37..a9e7cb0 100644
--- a/drivers/gpu/drm/i915/intel_guc.c
+++ b/drivers/gpu/drm/i915/intel_guc.c
@@ -349,6 +349,11 @@ void intel_guc_fini(struct intel_guc *guc)
 	struct drm_i915_private *dev_priv = guc_to_i915(guc);
 	struct drm_device *dev = &dev_priv->drm;
 
+	if (i915.enable_slpc) {
+		if (dev_priv->guc.slpc.active)
+			intel_slpc_disable(&dev_priv->guc.slpc);
+	}
+
 	if (i915.enable_guc_submission) {
 		mutex_lock(&dev->struct_mutex);
 		i915_guc_submission_disable(dev_priv);
diff --git a/drivers/gpu/drm/i915/intel_guc.h b/drivers/gpu/drm/i915/intel_guc.h
index e77ce1f..dd94f92 100644
--- a/drivers/gpu/drm/i915/intel_guc.h
+++ b/drivers/gpu/drm/i915/intel_guc.h
@@ -29,6 +29,7 @@
 #include "intel_ringbuffer.h"
 #include "intel_guc_ct.h"
 #include "i915_vma.h"
+#include "intel_slpc.h"
 
 struct drm_i915_gem_request;
 
@@ -136,6 +137,8 @@ struct intel_guc {
 		enum forcewake_domains fw_domains;
 	} send_regs;
 
+	struct intel_slpc slpc;
+
 	/* To serialize the intel_guc_send actions */
 	struct mutex send_mutex;
 
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index a1b32e1..2452e2d 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -6117,6 +6117,9 @@ static void vlv_set_rps_idle(struct drm_i915_private *dev_priv)
 
 void gen6_rps_busy(struct drm_i915_private *dev_priv)
 {
+	if (!dev_priv->rps.rps_enabled)
+		return;
+
 	mutex_lock(&dev_priv->rps.hw_lock);
 	if (dev_priv->rps.rps_enabled) {
 		u8 freq;
@@ -6145,6 +6148,9 @@ void gen6_rps_busy(struct drm_i915_private *dev_priv)
 
 void gen6_rps_idle(struct drm_i915_private *dev_priv)
 {
+	if (!dev_priv->rps.rps_enabled)
+		return;
+
 	/* Flush our bottom-half so that it does not race with us
 	 * setting the idle frequency and so that it is bounded by
 	 * our rpm wakeref. And then disable the interrupts to stop any
@@ -7808,6 +7814,12 @@ void intel_suspend_gt_powersave(struct drm_i915_private *dev_priv)
 		intel_runtime_pm_put(dev_priv);
 
 	/* gen6_rps_idle() will be called later to disable interrupts */
+
+	if (dev_priv->guc.slpc.active) {
+		intel_runtime_pm_get(dev_priv);
+		intel_slpc_disable(&dev_priv->guc.slpc);
+		intel_runtime_pm_put(dev_priv);
+	}
 }
 
 void intel_sanitize_gt_powersave(struct drm_i915_private *dev_priv)
@@ -7908,15 +7920,20 @@ void intel_enable_gt_powersave(struct drm_i915_private *dev_priv)
 		if (IS_GEN9_BC(dev_priv) || IS_CANNONLAKE(dev_priv))
 			gen6_update_ring_freq(dev_priv);
 	}
-	__intel_enable_gt_powersave(dev_priv);
+
+	if (!i915.enable_slpc)
+		__intel_enable_gt_powersave(dev_priv);
 
 	mutex_unlock(&dev_priv->rps.hw_lock);
 }
 
 #define GT_POWERSAVE_ENABLED(dev_priv) \
 	(((INTEL_GEN(dev_priv) >= 9) && \
-		(READ_ONCE(dev_priv->rps.rps_enabled) && \
-		 READ_ONCE(dev_priv->rps.rc6_enabled))) || \
+		((!i915.enable_slpc && \
+		  READ_ONCE(dev_priv->rps.rps_enabled) && \
+		  READ_ONCE(dev_priv->rps.rc6_enabled)) || \
+		 (i915.enable_slpc && \
+		  READ_ONCE(dev_priv->rps.rc6_enabled)))) || \
 	 ((INTEL_GEN(dev_priv) < 9) && \
 		READ_ONCE(dev_priv->rps.rps_enabled)))
 
diff --git a/drivers/gpu/drm/i915/intel_slpc.c b/drivers/gpu/drm/i915/intel_slpc.c
new file mode 100644
index 0000000..06abda5
--- /dev/null
+++ b/drivers/gpu/drm/i915/intel_slpc.c
@@ -0,0 +1,42 @@
+/*
+ * Copyright © 2017 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
+ *
+ */
+#include <linux/firmware.h>
+#include "i915_drv.h"
+#include "intel_uc.h"
+
+void intel_slpc_init(struct intel_slpc *slpc)
+{
+}
+
+void intel_slpc_cleanup(struct intel_slpc *slpc)
+{
+}
+
+void intel_slpc_enable(struct intel_slpc *slpc)
+{
+}
+
+void intel_slpc_disable(struct intel_slpc *slpc)
+{
+}
diff --git a/drivers/gpu/drm/i915/intel_slpc.h b/drivers/gpu/drm/i915/intel_slpc.h
new file mode 100644
index 0000000..1a93719
--- /dev/null
+++ b/drivers/gpu/drm/i915/intel_slpc.h
@@ -0,0 +1,37 @@
+/*
+ * Copyright © 2017 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
+ *
+ */
+#ifndef _INTEL_SLPC_H_
+#define _INTEL_SLPC_H_
+
+struct intel_slpc {
+	bool active;
+};
+
+/* intel_slpc.c */
+void intel_slpc_init(struct intel_slpc *slpc);
+void intel_slpc_cleanup(struct intel_slpc *slpc);
+void intel_slpc_enable(struct intel_slpc *slpc);
+void intel_slpc_disable(struct intel_slpc *slpc);
+
+#endif
diff --git a/drivers/gpu/drm/i915/intel_uc.c b/drivers/gpu/drm/i915/intel_uc.c
index 19a2847..bd23d69 100644
--- a/drivers/gpu/drm/i915/intel_uc.c
+++ b/drivers/gpu/drm/i915/intel_uc.c
@@ -302,6 +302,9 @@ int intel_uc_init_hw(struct drm_i915_private *dev_priv)
 		ret = i915_guc_submission_init(dev_priv);
 		if (ret)
 			goto err_guc;
+
+		if (i915.enable_slpc)
+			intel_slpc_init(&dev_priv->guc.slpc);
 	}
 
 	/* init WOPCM */
@@ -345,6 +348,17 @@ int intel_uc_init_hw(struct drm_i915_private *dev_priv)
 		goto err_log_capture;
 
 	intel_huc_auth(huc);
+
+	/*
+	 * SLPC is enabled by setting up the shared data structure and
+	 * sending reset event to GuC SLPC. Initial data is setup in
+	 * intel_slpc_init. Here we send the reset event. SLPC enabling
+	 * in GuC can happen in parallel in GuC with other initialization
+	 * being done in i915.
+	 */
+	if (i915.enable_slpc)
+		intel_slpc_enable(&dev_priv->guc.slpc);
+
 	if (i915.enable_guc_submission) {
 		if (i915.guc_log_level >= 0)
 			gen9_enable_guc_interrupts(dev_priv);
@@ -374,6 +388,12 @@ int intel_uc_init_hw(struct drm_i915_private *dev_priv)
 	if (i915.enable_guc_submission)
 		i915_guc_submission_fini(dev_priv);
 err_guc:
+	if (i915.enable_slpc) {
+		if (dev_priv->guc.slpc.active)
+			intel_slpc_disable(&dev_priv->guc.slpc);
+		intel_slpc_cleanup(&dev_priv->guc.slpc);
+	}
+
 	i915_ggtt_disable_guc(dev_priv);
 
 	DRM_ERROR("GuC init failed\n");
@@ -390,6 +410,8 @@ int intel_uc_init_hw(struct drm_i915_private *dev_priv)
 	i915.enable_guc_loading = 0;
 	DRM_NOTE("GuC firmware loading disabled\n");
 
+	i915.enable_slpc = 0;
+
 	return ret;
 }
 
@@ -407,4 +429,7 @@ void intel_uc_cleanup_hw(struct drm_i915_private *dev_priv)
 
 	if (i915.enable_guc_submission)
 		i915_guc_submission_fini(dev_priv);
+
+	if (i915.enable_slpc)
+		intel_slpc_cleanup(&dev_priv->guc.slpc);
 }
-- 
1.9.1

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[PATCH 07/20] drm/i915/slpc: Enable SLPC in GuC if supported

[Sagar Arun Kamble]

From: Tom O'Rourke <Tom.O'Rourke@intel.com>

If slpc enabled, then add enable SLPC flag to guc
control parameter during guc load.

v1: Use intel_slpc_enabled() (Paulo)

v2-v4: Rebase.

v5: Changed intel_slpc_enabled() to i915.enable_slpc. (Sagar)

Signed-off-by: Tom O'Rourke <Tom.O'Rourke@intel.com>
Signed-off-by: Sagar Arun Kamble <sagar.a.kamble@intel.com>
---
 drivers/gpu/drm/i915/intel_guc_loader.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_guc_loader.c b/drivers/gpu/drm/i915/intel_guc_loader.c
index 1c3a242..7a5ea10 100644
--- a/drivers/gpu/drm/i915/intel_guc_loader.c
+++ b/drivers/gpu/drm/i915/intel_guc_loader.c
@@ -131,6 +131,9 @@ static void guc_params_init(struct drm_i915_private *dev_priv)
 	params[GUC_CTL_FEATURE] |= GUC_CTL_DISABLE_SCHEDULER |
 			GUC_CTL_VCS2_ENABLED;
 
+	if (i915.enable_slpc)
+		params[GUC_CTL_FEATURE] |= GUC_CTL_ENABLE_SLPC;
+
 	params[GUC_CTL_LOG_PARAMS] = guc->log.flags;
 
 	if (i915.guc_log_level >= 0) {
-- 
1.9.1

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[PATCH 08/20] drm/i915/slpc: Add SLPC communication interfaces

[Sagar Arun Kamble]

Communication with SLPC is via Host to GuC interrupt through
shared data and parameters. This patch defines the structure of
shared data, parameters, data structure to be passed as input and
received as output from SLPC. This patch also defines the events
to be sent as input and status values output by GuC on processing
SLPC events. SLPC shared data has details of SKU type, Slice count,
IA Perf MSR values, SLPC state, Power source/plan, SLPC tasks status.
Parameters allow overriding task control, frequency range etc.

v1: fix whitespace (Sagar)

v2-v3: Rebase.

v4: Updated with GuC firmware v9.

v5: Added definition of input and output data structures for SLPC
events. Updated commit message.

v6: Removed definition of host2guc_slpc. Will be added in the next
patch that uses it. Commit subject update. Rebase.

v7: Added definition of SLPC_RESET_FLAG_TDR_OCCURRED to be sent
throgh SLPC reset in case of engine reset. Moved all Host/SLPC
interfaces from later patches to this patch. Commit message update.

Signed-off-by: Tom O'Rourke <Tom.O'Rourke@intel.com>
Signed-off-by: Sagar Arun Kamble <sagar.a.kamble@intel.com>
---
 drivers/gpu/drm/i915/intel_slpc.c |  39 +++++++
 drivers/gpu/drm/i915/intel_slpc.h | 207 ++++++++++++++++++++++++++++++++++++++
 2 files changed, 246 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_slpc.c b/drivers/gpu/drm/i915/intel_slpc.c
index 06abda5..a3db63c 100644
--- a/drivers/gpu/drm/i915/intel_slpc.c
+++ b/drivers/gpu/drm/i915/intel_slpc.c
@@ -25,6 +25,45 @@
 #include "i915_drv.h"
 #include "intel_uc.h"
 
+struct slpc_param slpc_paramlist[SLPC_MAX_PARAM] = {
+	{SLPC_PARAM_TASK_ENABLE_GTPERF, "Enable task GTPERF"},
+	{SLPC_PARAM_TASK_DISABLE_GTPERF, "Disable task GTPERF"},
+	{SLPC_PARAM_TASK_ENABLE_BALANCER, "Enable task BALANCER"},
+	{SLPC_PARAM_TASK_DISABLE_BALANCER, "Disable task BALANCER"},
+	{SLPC_PARAM_TASK_ENABLE_DCC, "Enable task DCC"},
+	{SLPC_PARAM_TASK_DISABLE_DCC, "Disable task DCC"},
+	{SLPC_PARAM_GLOBAL_MIN_GT_UNSLICE_FREQ_MHZ,
+				"Minimum GT frequency request for unslice"},
+	{SLPC_PARAM_GLOBAL_MAX_GT_UNSLICE_FREQ_MHZ,
+				"Maximum GT frequency request for unslice"},
+	{SLPC_PARAM_GLOBAL_MIN_GT_SLICE_FREQ_MHZ,
+				"Minimum GT frequency request for slice"},
+	{SLPC_PARAM_GLOBAL_MAX_GT_SLICE_FREQ_MHZ,
+				"Maximum GT frequency request for slice"},
+	{SLPC_PARAM_GTPERF_THRESHOLD_MAX_FPS,
+				"If non-zero, algorithm will slow down "
+				"frame-based applications to this frame-rate"},
+	{SLPC_PARAM_GLOBAL_DISABLE_GT_FREQ_MANAGEMENT,
+				"Lock GT frequency request to RPe"},
+	{SLPC_PARAM_GTPERF_ENABLE_FRAMERATE_STALLING,
+				"Set to TRUE to enable slowing framerate"},
+	{SLPC_PARAM_GLOBAL_DISABLE_RC6_MODE_CHANGE,
+				"Prevent from changing the RC mode"},
+	{SLPC_PARAM_GLOBAL_OC_UNSLICE_FREQ_MHZ,
+				"Override fused value of unslice RP0"},
+	{SLPC_PARAM_GLOBAL_OC_SLICE_FREQ_MHZ,
+				"Override fused value of slice RP0"},
+	{SLPC_PARAM_GLOBAL_ENABLE_IA_GT_BALANCING,
+				"TRUE means enable Intelligent Bias Control"},
+	{SLPC_PARAM_GLOBAL_ENABLE_ADAPTIVE_BURST_TURBO,
+				"TRUE = enable eval mode when transitioning "
+				"from idle to active."},
+	{SLPC_PARAM_GLOBAL_ENABLE_EVAL_MODE,
+				"FALSE = disable eval mode completely"},
+	{SLPC_PARAM_GLOBAL_ENABLE_BALANCER_IN_NON_GAMING_MODE,
+				"Enable IBC when non-Gaming Mode is enabled"}
+};
+
 void intel_slpc_init(struct intel_slpc *slpc)
 {
 }
diff --git a/drivers/gpu/drm/i915/intel_slpc.h b/drivers/gpu/drm/i915/intel_slpc.h
index 1a93719..c6836b6 100644
--- a/drivers/gpu/drm/i915/intel_slpc.h
+++ b/drivers/gpu/drm/i915/intel_slpc.h
@@ -28,6 +28,213 @@ struct intel_slpc {
 	bool active;
 };
 
+enum slpc_status {
+	SLPC_STATUS_OK = 0,
+	SLPC_STATUS_ERROR = 1,
+	SLPC_STATUS_ILLEGAL_COMMAND = 2,
+	SLPC_STATUS_INVALID_ARGS = 3,
+	SLPC_STATUS_INVALID_PARAMS = 4,
+	SLPC_STATUS_INVALID_DATA = 5,
+	SLPC_STATUS_OUT_OF_RANGE = 6,
+	SLPC_STATUS_NOT_SUPPORTED = 7,
+	SLPC_STATUS_NOT_IMPLEMENTED = 8,
+	SLPC_STATUS_NO_DATA = 9,
+	SLPC_STATUS_EVENT_NOT_REGISTERED = 10,
+	SLPC_STATUS_REGISTER_LOCKED = 11,
+	SLPC_STATUS_TEMPORARILY_UNAVAILABLE = 12,
+	SLPC_STATUS_VALUE_ALREADY_SET = 13,
+	SLPC_STATUS_VALUE_ALREADY_UNSET = 14,
+	SLPC_STATUS_VALUE_NOT_CHANGED = 15,
+	SLPC_STATUS_MEMIO_ERROR = 16,
+	SLPC_STATUS_EVENT_QUEUED_REQ_DPC = 17,
+	SLPC_STATUS_EVENT_QUEUED_NOREQ_DPC = 18,
+	SLPC_STATUS_NO_EVENT_QUEUED = 19,
+	SLPC_STATUS_OUT_OF_SPACE = 20,
+	SLPC_STATUS_TIMEOUT = 21,
+	SLPC_STATUS_NO_LOCK = 22,
+};
+
+enum slpc_event_id {
+	SLPC_EVENT_RESET = 0,
+	SLPC_EVENT_SHUTDOWN = 1,
+	SLPC_EVENT_PLATFORM_INFO_CHANGE = 2,
+	SLPC_EVENT_DISPLAY_MODE_CHANGE = 3,
+	SLPC_EVENT_FLIP_COMPLETE = 4,
+	SLPC_EVENT_QUERY_TASK_STATE = 5,
+	SLPC_EVENT_PARAMETER_SET = 6,
+	SLPC_EVENT_PARAMETER_UNSET = 7,
+};
+
+enum slpc_param_id {
+	SLPC_PARAM_TASK_ENABLE_GTPERF = 0,
+	SLPC_PARAM_TASK_DISABLE_GTPERF = 1,
+	SLPC_PARAM_TASK_ENABLE_BALANCER = 2,
+	SLPC_PARAM_TASK_DISABLE_BALANCER = 3,
+	SLPC_PARAM_TASK_ENABLE_DCC = 4,
+	SLPC_PARAM_TASK_DISABLE_DCC = 5,
+	SLPC_PARAM_GLOBAL_MIN_GT_UNSLICE_FREQ_MHZ = 6,
+	SLPC_PARAM_GLOBAL_MAX_GT_UNSLICE_FREQ_MHZ = 7,
+	SLPC_PARAM_GLOBAL_MIN_GT_SLICE_FREQ_MHZ = 8,
+	SLPC_PARAM_GLOBAL_MAX_GT_SLICE_FREQ_MHZ = 9,
+	SLPC_PARAM_GTPERF_THRESHOLD_MAX_FPS = 10,
+	SLPC_PARAM_GLOBAL_DISABLE_GT_FREQ_MANAGEMENT = 11,
+	SLPC_PARAM_GTPERF_ENABLE_FRAMERATE_STALLING = 12,
+	SLPC_PARAM_GLOBAL_DISABLE_RC6_MODE_CHANGE = 13,
+	SLPC_PARAM_GLOBAL_OC_UNSLICE_FREQ_MHZ = 14,
+	SLPC_PARAM_GLOBAL_OC_SLICE_FREQ_MHZ = 15,
+	SLPC_PARAM_GLOBAL_ENABLE_IA_GT_BALANCING = 16,
+	SLPC_PARAM_GLOBAL_ENABLE_ADAPTIVE_BURST_TURBO = 17,
+	SLPC_PARAM_GLOBAL_ENABLE_EVAL_MODE = 18,
+	SLPC_PARAM_GLOBAL_ENABLE_BALANCER_IN_NON_GAMING_MODE = 19,
+	SLPC_MAX_PARAM,
+	SLPC_KMD_MAX_PARAM = 32,
+};
+
+enum slpc_platform_sku {
+	SLPC_PLATFORM_SKU_UNDEFINED = 0,
+	SLPC_PLATFORM_SKU_ULX = 1,
+	SLPC_PLATFORM_SKU_ULT = 2,
+	SLPC_PLATFORM_SKU_T = 3,
+	SLPC_PLATFORM_SKU_MOBL = 4,
+	SLPC_PLATFORM_SKU_DT = 5,
+	SLPC_PLATFORM_SKU_UNKNOWN = 6,
+};
+
+enum slpc_power_source {
+	SLPC_POWER_SOURCE_UNDEFINED = 0,
+	SLPC_POWER_SOURCE_AC = 1,
+	SLPC_POWER_SOURCE_DC = 2,
+	SLPC_POWER_SOURCE_UNKNOWN = 3,
+};
+
+enum slpc_power_plan {
+	SLPC_POWER_PLAN_UNDEFINED = 0,
+	SLPC_POWER_PLAN_BATTERY_SAVER = 1,
+	SLPC_POWER_PLAN_BALANCED = 2,
+	SLPC_POWER_PLAN_PERFORMANCE = 3,
+	SLPC_POWER_PLAN_UNKNOWN = 4,
+};
+
+struct slpc_platform_info {
+	u8 platform_sku;
+	u8 slice_count;
+	u8 reserved;
+	u8 power_plan_source;
+	u8 P0_freq;
+	u8 P1_freq;
+	u8 Pe_freq;
+	u8 Pn_freq;
+	u32 reserved1;
+	u32 reserved2;
+} __packed;
+
+enum slpc_global_state {
+	SLPC_GLOBAL_STATE_NOT_RUNNING = 0,
+	SLPC_GLOBAL_STATE_INITIALIZING = 1,
+	SLPC_GLOBAL_STATE_RESETTING = 2,
+	SLPC_GLOBAL_STATE_RUNNING = 3,
+	SLPC_GLOBAL_STATE_SHUTTING_DOWN = 4,
+	SLPC_GLOBAL_STATE_ERROR = 5
+};
+
+struct slpc_task_state_data {
+	union {
+		u32 bitfield1;
+		struct {
+			u32 gtperf_task_active:1;
+			u32 gtperf_stall_possible:1;
+			u32 gtperf_gaming_mode:1;
+			u32 gtperf_target_fps:8;
+			u32 dcc_task_active:1;
+			u32 in_dcc:1;
+			u32 in_dct:1;
+			u32 freq_switch_active:1;
+			u32 ibc_enabled:1;
+			u32 ibc_active:1;
+			u32 pg1_enabled:1;
+			u32 pg1_active:1;
+			u32 reserved:13;
+		};
+	};
+	union {
+		u32 bitfield2;
+		struct {
+			u32 max_unslice_freq:8;
+			u32 min_unslice_freq:8;
+			u32 max_slice_freq:8;
+			u32 min_slice_freq:8;
+		};
+	};
+} __packed;
+
+#define SLPC_MAX_OVERRIDE_PARAMETERS 192
+#define SLPC_OVERRIDE_BITFIELD_SIZE ((SLPC_MAX_OVERRIDE_PARAMETERS + 31) / 32)
+
+struct slpc_shared_data {
+	u32 reserved;
+	u32 shared_data_size;
+	u32 global_state;
+	struct slpc_platform_info platform_info;
+	struct slpc_task_state_data task_state_data;
+	u32 override_parameters_set_bits[SLPC_OVERRIDE_BITFIELD_SIZE];
+	u32 override_parameters_values[SLPC_MAX_OVERRIDE_PARAMETERS];
+} __packed;
+
+enum slpc_reset_flags {
+	SLPC_RESET_FLAG_TDR_OCCURRED
+};
+
+#define SLPC_EVENT_MAX_INPUT_ARGS  7
+#define SLPC_EVENT_MAX_OUTPUT_ARGS 1
+
+union slpc_event_input_header {
+	u32 value;
+	struct {
+		u32 num_args:8;
+		u32 event_id:8;
+	};
+};
+
+struct slpc_event_input {
+	u32 h2g_action_id;
+	union slpc_event_input_header header;
+	u32 args[SLPC_EVENT_MAX_INPUT_ARGS];
+} __packed;
+
+union slpc_event_output_header {
+	u32 value;
+	struct {
+		u32 num_args:8;
+		u32 event_id:8;
+		u32 status:16;
+	};
+};
+
+struct slpc_event_output {
+	u32 reserved;
+	union slpc_event_output_header header;
+	u32 args[SLPC_EVENT_MAX_OUTPUT_ARGS];
+} __packed;
+
+#define SLPC_EVENT(id, argc)	((u32) (id) << 8 | (argc))
+#define SLPC_POWER_PLAN_SOURCE(plan, source) ((plan) | ((source) << 6))
+#define SLPC_POWER_PLAN(plan_source) ((plan_source) & 0x3F)
+#define SLPC_POWER_SOURCE(plan_source) ((plan_source) >> 6)
+
+/* Structures for exposing parameter details to user. */
+#define MAX_PARAM_DESCRIPTION_SIZE	160
+struct slpc_param {
+	enum slpc_param_id id;
+	char description[MAX_PARAM_DESCRIPTION_SIZE];
+};
+
+extern struct slpc_param slpc_paramlist[];
+
+#define SLPC_PARAM_TASK_DEFAULT  0
+#define SLPC_PARAM_TASK_ENABLED  1
+#define SLPC_PARAM_TASK_DISABLED 2
+#define SLPC_PARAM_TASK_UNKNOWN  3
+
 /* intel_slpc.c */
 void intel_slpc_init(struct intel_slpc *slpc);
 void intel_slpc_cleanup(struct intel_slpc *slpc);
-- 
1.9.1

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[PATCH 09/20] drm/i915/slpc: Allocate/Release/Initialize SLPC shared data

[Sagar Arun Kamble]

Populate SLPC shared data with required default values for
Slice count, Power source/plan, IA Perf MSRs.

v1: Update for SLPC interface version 2015.2.4
    intel_slpc_active() returns 1 if slpc initialized (Paulo)
    change default host_os to "Windows"
    Spelling fixes (Sagar Kamble and Nick Hoath)
    Added WARN for checking if upper 32bits of GTT offset
    of shared object are zero. (ChrisW)
    Changed function call from gem_allocate/release_guc_obj to
    i915_guc_allocate/release_gem_obj. (Sagar)
    Updated commit message and moved POWER_PLAN and POWER_SOURCE
    definition from later patch. (Akash)
    Add struct_mutex locking while allocating/releasing slpc shared
    object. This was caught by CI BAT. Adding SLPC state variable
    to determine if it is active as it not just dependent on shared
    data setup.
    Rebase with guc_allocate_vma related changes.

v2: WARN_ON for platform_sku validity and space changes.(David)
    Checkpatch update.

v3: Fixing WARNING in igt@drv_module_reload_basic found in trybot BAT
    with SLPC Enabled.

v4: Updated support for GuC v9. s/slice_total/hweight8(slice_mask)/(Dave).

v5: SLPC vma mapping changes and removed explicit type conversions.(Chris).
    s/freq_unslice_max|min/unslice__max|min_freq.

v6: Commit message update. s/msr_value/val for reuse later.

v7: Set default values for tasks and min frequency parameters.
    Moved initialization with allocation of data so that post GuC load
    earlier parameters persist.

v8: Added check for SLPC status during cleanup of shared data. SLPC
    disabling is asynchronous and should complete within 10us.

v9: Enabling Balancer task in SLPC.

Signed-off-by: Tom O'Rourke <Tom.O'Rourke@intel.com>
Signed-off-by: Sagar Arun Kamble <sagar.a.kamble@intel.com>
---
 drivers/gpu/drm/i915/intel_drv.h  |   1 +
 drivers/gpu/drm/i915/intel_pm.c   |   2 +-
 drivers/gpu/drm/i915/intel_slpc.c | 167 ++++++++++++++++++++++++++++++++++++++
 drivers/gpu/drm/i915/intel_slpc.h |   1 +
 4 files changed, 170 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 3292221..4633f19 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -1866,6 +1866,7 @@ bool chv_phy_powergate_ch(struct drm_i915_private *dev_priv, enum dpio_phy phy,
 void gen6_rps_idle(struct drm_i915_private *dev_priv);
 void gen6_rps_boost(struct drm_i915_gem_request *rq,
 		    struct intel_rps_client *rps);
+void gen6_init_rps_frequencies(struct drm_i915_private *dev_priv);
 void g4x_wm_get_hw_state(struct drm_device *dev);
 void vlv_wm_get_hw_state(struct drm_device *dev);
 void ilk_wm_get_hw_state(struct drm_device *dev);
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 2452e2d..c6494a9 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -6378,7 +6378,7 @@ int sanitize_rc6_option(struct drm_i915_private *dev_priv, int enable_rc6)
 	return INTEL_RC6_ENABLE;
 }
 
-static void gen6_init_rps_frequencies(struct drm_i915_private *dev_priv)
+void gen6_init_rps_frequencies(struct drm_i915_private *dev_priv)
 {
 	/* All of these values are in units of 50MHz */
 
diff --git a/drivers/gpu/drm/i915/intel_slpc.c b/drivers/gpu/drm/i915/intel_slpc.c
index a3db63c..818b9bc 100644
--- a/drivers/gpu/drm/i915/intel_slpc.c
+++ b/drivers/gpu/drm/i915/intel_slpc.c
@@ -22,6 +22,7 @@
  *
  */
 #include <linux/firmware.h>
+#include <asm/msr-index.h>
 #include "i915_drv.h"
 #include "intel_uc.h"
 
@@ -64,12 +65,178 @@ struct slpc_param slpc_paramlist[SLPC_MAX_PARAM] = {
 				"Enable IBC when non-Gaming Mode is enabled"}
 };
 
+static unsigned int slpc_get_platform_sku(struct drm_i915_private *dev_priv)
+{
+	enum slpc_platform_sku platform_sku;
+
+	if (IS_SKL_ULX(dev_priv))
+		platform_sku = SLPC_PLATFORM_SKU_ULX;
+	else if (IS_SKL_ULT(dev_priv))
+		platform_sku = SLPC_PLATFORM_SKU_ULT;
+	else
+		platform_sku = SLPC_PLATFORM_SKU_DT;
+
+	WARN_ON(platform_sku > 0xFF);
+
+	return platform_sku;
+}
+
+static unsigned int slpc_get_slice_count(struct drm_i915_private *dev_priv)
+{
+	unsigned int slice_count = 1;
+
+	if (IS_SKYLAKE(dev_priv))
+		slice_count = hweight8(INTEL_INFO(dev_priv)->sseu.slice_mask);
+
+	return slice_count;
+}
+
+void slpc_mem_set_param(struct slpc_shared_data *data,
+			      u32 id,
+			      u32 value)
+{
+	data->override_parameters_set_bits[id >> 5]
+						|= (1 << (id % 32));
+	data->override_parameters_values[id] = value;
+}
+
+void slpc_mem_unset_param(struct slpc_shared_data *data,
+				u32 id)
+{
+	data->override_parameters_set_bits[id >> 5]
+						&= (~(1 << (id % 32)));
+	data->override_parameters_values[id] = 0;
+}
+
+int slpc_mem_task_control(struct slpc_shared_data *data, u64 val,
+			  u32 enable_id, u32 disable_id)
+{
+	int ret = 0;
+
+	if (val == SLPC_PARAM_TASK_DEFAULT) {
+		/* set default */
+		slpc_mem_unset_param(data, enable_id);
+		slpc_mem_unset_param(data, disable_id);
+	} else if (val == SLPC_PARAM_TASK_ENABLED) {
+		/* set enable */
+		slpc_mem_set_param(data, enable_id, 1);
+		slpc_mem_unset_param(data, disable_id);
+	} else if (val == SLPC_PARAM_TASK_DISABLED) {
+		/* set disable */
+		slpc_mem_set_param(data, disable_id, 1);
+		slpc_mem_unset_param(data, enable_id);
+	} else {
+		ret = -EINVAL;
+	}
+
+	return ret;
+}
+
+static void slpc_shared_data_init(struct intel_slpc *slpc)
+{
+	struct drm_i915_private *dev_priv = slpc_to_i915(slpc);
+	struct page *page;
+	struct slpc_shared_data *data;
+	u64 val;
+
+	page = i915_vma_first_page(slpc->vma);
+	data = kmap_atomic(page);
+
+	memset(data, 0, sizeof(struct slpc_shared_data));
+
+	data->shared_data_size = sizeof(struct slpc_shared_data);
+	data->global_state = SLPC_GLOBAL_STATE_NOT_RUNNING;
+	data->platform_info.platform_sku =
+				slpc_get_platform_sku(dev_priv);
+	data->platform_info.slice_count =
+				slpc_get_slice_count(dev_priv);
+	data->platform_info.power_plan_source =
+		SLPC_POWER_PLAN_SOURCE(SLPC_POWER_PLAN_BALANCED,
+					    SLPC_POWER_SOURCE_AC);
+	rdmsrl(MSR_TURBO_RATIO_LIMIT, val);
+	data->platform_info.P0_freq = val;
+	rdmsrl(MSR_PLATFORM_INFO, val);
+	data->platform_info.P1_freq = val >> 8;
+	data->platform_info.Pe_freq = val >> 40;
+	data->platform_info.Pn_freq = val >> 48;
+
+	/* Enable only GTPERF task, Disable others */
+	val = SLPC_PARAM_TASK_ENABLED;
+	slpc_mem_task_control(data, val,
+			      SLPC_PARAM_TASK_ENABLE_GTPERF,
+			      SLPC_PARAM_TASK_DISABLE_GTPERF);
+
+	slpc_mem_task_control(data, val,
+			      SLPC_PARAM_TASK_ENABLE_BALANCER,
+			      SLPC_PARAM_TASK_DISABLE_BALANCER);
+
+	val = SLPC_PARAM_TASK_DISABLED;
+	slpc_mem_task_control(data, val,
+			      SLPC_PARAM_TASK_ENABLE_DCC,
+			      SLPC_PARAM_TASK_DISABLE_DCC);
+
+	slpc_mem_set_param(data, SLPC_PARAM_GTPERF_THRESHOLD_MAX_FPS, 0);
+
+	slpc_mem_set_param(data, SLPC_PARAM_GTPERF_ENABLE_FRAMERATE_STALLING,
+			   0);
+
+	slpc_mem_set_param(data, SLPC_PARAM_GLOBAL_ENABLE_IA_GT_BALANCING,
+			   1);
+
+	slpc_mem_set_param(data,
+			   SLPC_PARAM_GLOBAL_ENABLE_ADAPTIVE_BURST_TURBO,
+			   0);
+
+	slpc_mem_set_param(data, SLPC_PARAM_GLOBAL_ENABLE_EVAL_MODE, 0);
+
+	slpc_mem_set_param(data,
+			   SLPC_PARAM_GLOBAL_ENABLE_BALANCER_IN_NON_GAMING_MODE,
+			   1);
+
+	slpc_mem_set_param(data,
+			   SLPC_PARAM_GLOBAL_MIN_GT_UNSLICE_FREQ_MHZ,
+			   intel_gpu_freq(dev_priv,
+				dev_priv->rps.efficient_freq));
+	slpc_mem_set_param(data,
+			   SLPC_PARAM_GLOBAL_MIN_GT_SLICE_FREQ_MHZ,
+			   intel_gpu_freq(dev_priv,
+				dev_priv->rps.efficient_freq));
+
+	kunmap_atomic(data);
+}
+
 void intel_slpc_init(struct intel_slpc *slpc)
 {
+	struct intel_guc *guc = slpc_to_guc(slpc);
+	struct drm_i915_private *dev_priv = slpc_to_i915(slpc);
+	struct i915_vma *vma;
+
+	slpc->active = false;
+
+	mutex_lock(&dev_priv->rps.hw_lock);
+	gen6_init_rps_frequencies(dev_priv);
+	mutex_unlock(&dev_priv->rps.hw_lock);
+
+	/* Allocate shared data structure */
+	vma = slpc->vma;
+	if (!vma) {
+		vma = intel_guc_allocate_vma(guc,
+			       PAGE_ALIGN(sizeof(struct slpc_shared_data)));
+		if (IS_ERR(vma)) {
+			DRM_ERROR("slpc_shared_data allocation failed\n");
+			i915.enable_slpc = 0;
+			return;
+		}
+
+		slpc->vma = vma;
+		slpc_shared_data_init(slpc);
+	}
 }
 
 void intel_slpc_cleanup(struct intel_slpc *slpc)
 {
+	/* Release shared data structure */
+	i915_vma_unpin_and_release(&slpc->vma);
 }
 
 void intel_slpc_enable(struct intel_slpc *slpc)
diff --git a/drivers/gpu/drm/i915/intel_slpc.h b/drivers/gpu/drm/i915/intel_slpc.h
index c6836b6..c894b05 100644
--- a/drivers/gpu/drm/i915/intel_slpc.h
+++ b/drivers/gpu/drm/i915/intel_slpc.h
@@ -26,6 +26,7 @@
 
 struct intel_slpc {
 	bool active;
+	struct i915_vma *vma;
 };
 
 enum slpc_status {
-- 
1.9.1

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

[PATCH 10/20] drm/i915/slpc: Add parameter set/unset/get, task control/status functions

[Sagar Arun Kamble]

SLPC behavior can be changed through set of parameters.
These parameters can be updated and queried from i915 though
Host to GuC SLPC events. This patch adds parameter update
events for setting/unsetting/getting parameters. SLPC has
various tasks for controlling different controls. This patch
adds functions to control and query the task status.

v1: Use host2guc_slpc
    update slcp_param_id enum values for SLPC 2015.2.4
    return void instead of ignored error code (Paulo)

v2: Checkpatch update.

v3: Rebase.

v4: Updated with GuC firmware v9.

v5: Updated input structure to host2guc_slpc. Added functions
    to update only parameters in the SLPC shared memory. This
    will allow to setup shared data with all parameters and send
    single event to SLPC take them into effect. Commit message
    update. (Sagar)

v6: Rearranged helpers to use them in slpc_shared_data_init.
    Added definition of SLPC_KMD_MAX_PARAM.

v7: Added definition of host2guc_slpc with rearrangement of patches.
    Added task control/status functions.

v8: Rebase w.r.t s/intel_guc_send/intel_guc_send_mmio.

Signed-off-by: Tom O'Rourke <Tom.O'Rourke@intel.com>
Signed-off-by: Sagar Arun Kamble <sagar.a.kamble@intel.com>
---
 drivers/gpu/drm/i915/intel_guc.c  |  21 ++++-
 drivers/gpu/drm/i915/intel_guc.h  |   2 +
 drivers/gpu/drm/i915/intel_slpc.c | 185 ++++++++++++++++++++++++++++++++++++++
 drivers/gpu/drm/i915/intel_slpc.h |   8 ++
 4 files changed, 215 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/intel_guc.c b/drivers/gpu/drm/i915/intel_guc.c
index a9e7cb0..c26bef0 100644
--- a/drivers/gpu/drm/i915/intel_guc.c
+++ b/drivers/gpu/drm/i915/intel_guc.c
@@ -75,9 +75,11 @@ void intel_guc_init_send_regs(struct intel_guc *guc)
 /*
  * This function implements the MMIO based host to GuC interface.
  */
-int intel_guc_send_mmio(struct intel_guc *guc, const u32 *action, u32 len)
+int __intel_guc_send_mmio(struct intel_guc *guc, const u32 *action, u32 len,
+			  u32 *output)
 {
 	struct drm_i915_private *dev_priv = guc_to_i915(guc);
+	union slpc_event_output_header header;
 	u32 status;
 	int i;
 	int ret;
@@ -123,12 +125,29 @@ int intel_guc_send_mmio(struct intel_guc *guc, const u32 *action, u32 len)
 			 action[0], ret, status, I915_READ(SOFT_SCRATCH(15)));
 	}
 
+	/*
+	 * Output data from Host to GuC SLPC actions is populated in scratch
+	 * registers SOFT_SCRATCH(1) to SOFT_SCRATCH(14) based on event.
+	 * Currently only SLPC action status in GuC is meaningful as Host
+	 * can query only overridden parameters and that are fetched from
+	 * Host-GuC SLPC shared data.
+	 */
+	if (output && !ret) {
+		output[0] = header.value = I915_READ(SOFT_SCRATCH(1));
+		ret = header.status;
+	}
+
 	intel_uncore_forcewake_put(dev_priv, guc->send_regs.fw_domains);
 	mutex_unlock(&guc->send_mutex);
 
 	return ret;
 }
 
+int intel_guc_send_mmio(struct intel_guc *guc, const u32 *action, u32 len)
+{
+	return __intel_guc_send_mmio(guc, action, len, NULL);
+}
+
 int intel_guc_sample_forcewake(struct intel_guc *guc)
 {
 	struct drm_i915_private *dev_priv = guc_to_i915(guc);
diff --git a/drivers/gpu/drm/i915/intel_guc.h b/drivers/gpu/drm/i915/intel_guc.h
index dd94f92..f798c86 100644
--- a/drivers/gpu/drm/i915/intel_guc.h
+++ b/drivers/gpu/drm/i915/intel_guc.h
@@ -163,6 +163,8 @@ static inline u32 guc_ggtt_offset(struct i915_vma *vma)
 int intel_guc_sample_forcewake(struct intel_guc *guc);
 void intel_guc_init_send_regs(struct intel_guc *guc);
 int intel_guc_send_nop(struct intel_guc *guc, const u32 *action, u32 len);
+int __intel_guc_send_mmio(struct intel_guc *guc, const u32 *action, u32 len,
+			  u32 *output);
 int intel_guc_send_mmio(struct intel_guc *guc, const u32 *action, u32 len);
 void intel_guc_auth_huc(struct intel_guc *guc, struct intel_uc_fw *huc_fw);
 int intel_guc_enable_communication(struct intel_guc *guc);
diff --git a/drivers/gpu/drm/i915/intel_slpc.c b/drivers/gpu/drm/i915/intel_slpc.c
index 818b9bc..3b376ff 100644
--- a/drivers/gpu/drm/i915/intel_slpc.c
+++ b/drivers/gpu/drm/i915/intel_slpc.c
@@ -132,6 +132,191 @@ int slpc_mem_task_control(struct slpc_shared_data *data, u64 val,
 	return ret;
 }
 
+static void host2guc_slpc(struct intel_slpc *slpc,
+			  struct slpc_event_input *input, u32 len)
+{
+	struct intel_guc *guc = slpc_to_guc(slpc);
+	u32 *data;
+	u32 output[SLPC_EVENT_MAX_OUTPUT_ARGS];
+	int ret = 0;
+
+	/*
+	 * We have only 15 scratch registers for communication.
+	 * the first we will use for the event ID in input and
+	 * output data. Event processing status will be present
+	 * in SOFT_SCRATCH(1) register.
+	 */
+	BUILD_BUG_ON(SLPC_EVENT_MAX_INPUT_ARGS > 14);
+	BUILD_BUG_ON(SLPC_EVENT_MAX_OUTPUT_ARGS < 1);
+	BUILD_BUG_ON(SLPC_EVENT_MAX_OUTPUT_ARGS > 14);
+
+	data = (u32 *) input;
+	data[0] = INTEL_GUC_ACTION_SLPC_REQUEST;
+	ret = __intel_guc_send_mmio(guc, data, len, output);
+
+	if (ret)
+		DRM_ERROR("event 0x%x status %d\n",
+			  ((output[0] & 0xFF00) >> 8), ret);
+}
+
+static void host2guc_slpc_set_param(struct intel_slpc *slpc,
+				    u32 id, u32 value)
+{
+	struct slpc_event_input data = {0};
+
+	data.header.value = SLPC_EVENT(SLPC_EVENT_PARAMETER_SET, 2);
+	data.args[0] = id;
+	data.args[1] = value;
+
+	host2guc_slpc(slpc, &data, 4);
+}
+
+static void host2guc_slpc_unset_param(struct intel_slpc *slpc,
+				      u32 id)
+{
+	struct slpc_event_input data = {0};
+
+	data.header.value = SLPC_EVENT(SLPC_EVENT_PARAMETER_UNSET, 1);
+	data.args[0] = id;
+
+	host2guc_slpc(slpc, &data, 3);
+}
+
+void intel_slpc_set_param(struct intel_slpc *slpc,
+			  u32 id,
+			  u32 value)
+{
+	struct page *page;
+	struct slpc_shared_data *data = NULL;
+
+	WARN_ON(id >= SLPC_MAX_PARAM);
+
+	if (!slpc->vma)
+		return;
+
+	page = i915_vma_first_page(slpc->vma);
+	data = kmap_atomic(page);
+	slpc_mem_set_param(data, id, value);
+	kunmap_atomic(data);
+
+	host2guc_slpc_set_param(slpc, id, value);
+}
+
+void intel_slpc_unset_param(struct intel_slpc *slpc,
+			    u32 id)
+{
+	struct page *page;
+	struct slpc_shared_data *data = NULL;
+
+	WARN_ON(id >= SLPC_MAX_PARAM);
+
+	if (!slpc->vma)
+		return;
+
+	page = i915_vma_first_page(slpc->vma);
+	data = kmap_atomic(page);
+	slpc_mem_unset_param(data, id);
+	kunmap_atomic(data);
+
+	host2guc_slpc_unset_param(slpc, id);
+}
+
+void intel_slpc_get_param(struct intel_slpc *slpc,
+			  u32 id,
+			  int *overriding, u32 *value)
+{
+	struct page *page;
+	struct slpc_shared_data *data = NULL;
+	u32 bits;
+
+	WARN_ON(id >= SLPC_MAX_PARAM);
+
+	if (!slpc->vma)
+		return;
+
+	page = i915_vma_first_page(slpc->vma);
+	data = kmap_atomic(page);
+	if (overriding) {
+		bits = data->override_parameters_set_bits[id >> 5];
+		*overriding = (0 != (bits & (1 << (id % 32))));
+	}
+	if (value)
+		*value = data->override_parameters_values[id];
+
+	kunmap_atomic(data);
+}
+
+int intel_slpc_task_control(struct intel_slpc *slpc, u64 val,
+			    u32 enable_id, u32 disable_id)
+{
+	struct drm_i915_private *dev_priv = slpc_to_i915(slpc);
+	int ret = 0;
+
+	if (!slpc->active)
+		return -ENODEV;
+
+	intel_runtime_pm_get(dev_priv);
+
+	if (val == SLPC_PARAM_TASK_DEFAULT) {
+		/* set default */
+		intel_slpc_unset_param(slpc, enable_id);
+		intel_slpc_unset_param(slpc, disable_id);
+	} else if (val == SLPC_PARAM_TASK_ENABLED) {
+		/* set enable */
+		intel_slpc_set_param(slpc, enable_id, 1);
+		intel_slpc_unset_param(slpc, disable_id);
+	} else if (val == SLPC_PARAM_TASK_DISABLED) {
+		/* set disable */
+		intel_slpc_set_param(slpc, disable_id, 1);
+		intel_slpc_unset_param(slpc, enable_id);
+	} else {
+		ret = -EINVAL;
+	}
+
+	intel_slpc_enable(slpc);
+	intel_runtime_pm_put(dev_priv);
+
+	return ret;
+}
+
+int intel_slpc_task_status(struct intel_slpc *slpc, u64 *val,
+			   u32 enable_id, u32 disable_id)
+{
+	int override_enable, override_disable;
+	u32 value_enable, value_disable;
+	int ret = 0;
+
+	if (!slpc->active) {
+		ret = -ENODEV;
+	} else if (val) {
+		intel_slpc_get_param(slpc, enable_id, &override_enable,
+				     &value_enable);
+		intel_slpc_get_param(slpc, disable_id, &override_disable,
+				     &value_disable);
+
+		/*
+		 * Set the output value:
+		 * 0: default
+		 * 1: enabled
+		 * 2: disabled
+		 * 3: unknown (should not happen)
+		 */
+		if (override_disable && (value_disable == 1))
+			*val = SLPC_PARAM_TASK_DISABLED;
+		else if (override_enable && (value_enable == 1))
+			*val = SLPC_PARAM_TASK_ENABLED;
+		else if (!override_enable && !override_disable)
+			*val = SLPC_PARAM_TASK_DEFAULT;
+		else
+			*val = SLPC_PARAM_TASK_UNKNOWN;
+
+	} else {
+		ret = -EINVAL;
+	}
+
+	return ret;
+}
+
 static void slpc_shared_data_init(struct intel_slpc *slpc)
 {
 	struct drm_i915_private *dev_priv = slpc_to_i915(slpc);
diff --git a/drivers/gpu/drm/i915/intel_slpc.h b/drivers/gpu/drm/i915/intel_slpc.h
index c894b05..fd639c1 100644
--- a/drivers/gpu/drm/i915/intel_slpc.h
+++ b/drivers/gpu/drm/i915/intel_slpc.h
@@ -237,6 +237,14 @@ struct slpc_param {
 #define SLPC_PARAM_TASK_UNKNOWN  3
 
 /* intel_slpc.c */
+void intel_slpc_set_param(struct intel_slpc *slpc, u32 id, u32 value);
+void intel_slpc_unset_param(struct intel_slpc *slpc, u32 id);
+void intel_slpc_get_param(struct intel_slpc *slpc, u32 id,
+			  int *overriding, u32 *value);
+int intel_slpc_task_control(struct intel_slpc *slpc, u64 val,
+			    u32 enable_id, u32 disable_id);
+int intel_slpc_task_status(struct intel_slpc *slpc, u64 *val,
+			   u32 enable_id, u32 disable_id);
 void intel_slpc_init(struct intel_slpc *slpc);
 void intel_slpc_cleanup(struct intel_slpc *slpc);
 void intel_slpc_enable(struct intel_slpc *slpc);
-- 
1.9.1

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[PATCH 11/20] drm/i915/slpc: Send RESET event to enable SLPC

[Sagar Arun Kamble]

Send host2guc SLPC reset event to GuC post GuC load.
Post this, i915 can ascertain if SLPC has started running successfully
through shared data. This check is done during intel_init_gt_powersave.
This allows to get initial configuration setup by SLPC and if needed
move to Host RPS if SLPC runs into issues.

v1: Extract host2guc_slpc to handle slpc status code
    coding style changes (Paulo)
    Removed WARN_ON for checking msb of gtt address of
    shared gem obj. (ChrisW)
    host2guc_action to i915_guc_action change.(Sagar)
    Updating SLPC enabled status. (Sagar)

v2: Commit message update. (David)

v3: Rebase.

v4: Added DRM_INFO message when SLPC is enabled.

v5: Updated patch as host2guc_slpc is moved to earlier patch.
    SLPC activation status message put after checking the
    state from shared data during intel_init_gt_powersave.

v6: Added definition of host2guc_slpc and clflush the shared data only
    for required size. Setting state to NOT_RUNNING before sending RESET
    event. Output data for SLPC actions is to be retrieved during
    intel_guc_send with lock protection so created wrapper
    __intel_guc_send that outputs GuC output data if needed. Clearing
    pm_rps_events on confirming SLPC RUNNING status so that even if
    host touches any of the PM registers by mistake it should not have
    any effect. (Sagar)

v7: Added save/restore_default_rps as Uncore sanitize will clear the
    RP_CONTROL setup by BIOS. s/i915_ggtt_offset/guc_ggtt_offset.

Signed-off-by: Tom O'Rourke <Tom.O'Rourke@intel.com>
Signed-off-by: Sagar Arun Kamble <sagar.a.kamble@intel.com>
---
 drivers/gpu/drm/i915/i915_drv.c   |   2 +
 drivers/gpu/drm/i915/intel_pm.c   |  10 +++
 drivers/gpu/drm/i915/intel_slpc.c | 133 ++++++++++++++++++++++++++++++++++++++
 drivers/gpu/drm/i915/intel_slpc.h |   7 ++
 4 files changed, 152 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 54ccd13..576351e 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -1071,6 +1071,8 @@ static int i915_driver_init_hw(struct drm_i915_private *dev_priv)
 
 	intel_sanitize_options(dev_priv);
 
+	intel_slpc_save_default_rps(&dev_priv->guc.slpc);
+
 	ret = i915_ggtt_probe_hw(dev_priv);
 	if (ret)
 		return ret;
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index c6494a9..71fdbf9 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -7741,6 +7741,16 @@ void intel_init_gt_powersave(struct drm_i915_private *dev_priv)
 		intel_runtime_pm_get(dev_priv);
 	}
 
+	if (i915.enable_slpc) {
+		dev_priv->guc.slpc.active =
+			intel_slpc_get_status(&dev_priv->guc.slpc);
+		if (!dev_priv->guc.slpc.active) {
+			i915.enable_slpc = 0;
+			intel_sanitize_gt_powersave(dev_priv);
+		} else
+			dev_priv->pm_rps_events = 0;
+	}
+
 	mutex_lock(&dev_priv->drm.struct_mutex);
 	mutex_lock(&dev_priv->rps.hw_lock);
 
diff --git a/drivers/gpu/drm/i915/intel_slpc.c b/drivers/gpu/drm/i915/intel_slpc.c
index 3b376ff..49643d3 100644
--- a/drivers/gpu/drm/i915/intel_slpc.c
+++ b/drivers/gpu/drm/i915/intel_slpc.c
@@ -390,6 +390,127 @@ static void slpc_shared_data_init(struct intel_slpc *slpc)
 	kunmap_atomic(data);
 }
 
+static void host2guc_slpc_reset(struct intel_slpc *slpc)
+{
+	struct slpc_event_input data = {0};
+	u32 shared_data_gtt_offset = guc_ggtt_offset(slpc->vma);
+
+	data.header.value = SLPC_EVENT(SLPC_EVENT_RESET, 2);
+	data.args[0] = shared_data_gtt_offset;
+	data.args[1] = 0;
+
+	host2guc_slpc(slpc, &data, 4);
+}
+
+static void host2guc_slpc_query_task_state(struct intel_slpc *slpc)
+{
+	struct slpc_event_input data = {0};
+	u32 shared_data_gtt_offset = guc_ggtt_offset(slpc->vma);
+
+	data.header.value = SLPC_EVENT(SLPC_EVENT_QUERY_TASK_STATE, 2);
+	data.args[0] = shared_data_gtt_offset;
+	data.args[1] = 0;
+
+	host2guc_slpc(slpc, &data, 4);
+}
+
+void intel_slpc_query_task_state(struct intel_slpc *slpc)
+{
+	if (slpc->active)
+		host2guc_slpc_query_task_state(slpc);
+}
+
+/*
+ * This function will reads the state updates from GuC SLPC into shared data
+ * by invoking H2G action. Returns current state of GuC SLPC.
+ */
+void intel_slpc_read_shared_data(struct intel_slpc *slpc,
+				 struct slpc_shared_data *data)
+{
+	struct page *page;
+	void *pv = NULL;
+
+	intel_slpc_query_task_state(slpc);
+
+	page = i915_vma_first_page(slpc->vma);
+	pv = kmap_atomic(page);
+
+	drm_clflush_virt_range(pv, sizeof(struct slpc_shared_data));
+	memcpy(data, pv, sizeof(struct slpc_shared_data));
+
+	kunmap_atomic(pv);
+}
+
+const char *intel_slpc_get_state_str(enum slpc_global_state state)
+{
+	if (state == SLPC_GLOBAL_STATE_NOT_RUNNING)
+		return "not running";
+	else if (state == SLPC_GLOBAL_STATE_INITIALIZING)
+		return "initializing";
+	else if (state == SLPC_GLOBAL_STATE_RESETTING)
+		return "resetting";
+	else if (state == SLPC_GLOBAL_STATE_RUNNING)
+		return "running";
+	else if (state == SLPC_GLOBAL_STATE_SHUTTING_DOWN)
+		return "shutting down";
+	else if (state == SLPC_GLOBAL_STATE_ERROR)
+		return "error";
+	else
+		return "unknown";
+}
+
+bool intel_slpc_get_status(struct intel_slpc *slpc)
+{
+	struct slpc_shared_data data;
+	bool ret = false;
+
+	intel_slpc_read_shared_data(slpc, &data);
+	DRM_INFO("SLPC state: %s\n",
+		 intel_slpc_get_state_str(data.global_state));
+
+	switch (data.global_state) {
+	case SLPC_GLOBAL_STATE_RUNNING:
+		/* Capture required state from SLPC here */
+		ret = true;
+		break;
+	case SLPC_GLOBAL_STATE_ERROR:
+		DRM_ERROR("SLPC in error state.\n");
+		break;
+	case SLPC_GLOBAL_STATE_RESETTING:
+		/*
+		 * SLPC enabling in GuC should be completing fast.
+		 * If SLPC is taking time to initialize (unlikely as we are
+		 * sending reset event during GuC load itself).
+		 * TODO: Need to wait till state changes to RUNNING.
+		 */
+		ret = true;
+		DRM_ERROR("SLPC not running yet.!!!");
+		break;
+	default:
+		break;
+	}
+	return ret;
+}
+
+/*
+ * Uncore sanitize clears RPS state in Host GTPM flows set by BIOS, Save the
+ * initial BIOS programmed RPS state that is needed by SLPC and not set by SLPC.
+ * Set this state while enabling SLPC.
+ */
+void intel_slpc_save_default_rps(struct intel_slpc *slpc)
+{
+	struct drm_i915_private *dev_priv = slpc_to_i915(slpc);
+
+	slpc->rp_control = I915_READ(GEN6_RP_CONTROL);
+}
+
+static void intel_slpc_restore_default_rps(struct intel_slpc *slpc)
+{
+	struct drm_i915_private *dev_priv = slpc_to_i915(slpc);
+
+	I915_WRITE(GEN6_RP_CONTROL, slpc->rp_control);
+}
+
 void intel_slpc_init(struct intel_slpc *slpc)
 {
 	struct intel_guc *guc = slpc_to_guc(slpc);
@@ -426,6 +547,18 @@ void intel_slpc_cleanup(struct intel_slpc *slpc)
 
 void intel_slpc_enable(struct intel_slpc *slpc)
 {
+	struct page *page;
+	struct slpc_shared_data *data;
+
+	intel_slpc_restore_default_rps(slpc);
+
+	page = i915_vma_first_page(slpc->vma);
+	data = kmap_atomic(page);
+	data->global_state = SLPC_GLOBAL_STATE_NOT_RUNNING;
+	kunmap_atomic(data);
+
+	host2guc_slpc_reset(slpc);
+	slpc->active = true;
 }
 
 void intel_slpc_disable(struct intel_slpc *slpc)
diff --git a/drivers/gpu/drm/i915/intel_slpc.h b/drivers/gpu/drm/i915/intel_slpc.h
index fd639c1..a01f9e5 100644
--- a/drivers/gpu/drm/i915/intel_slpc.h
+++ b/drivers/gpu/drm/i915/intel_slpc.h
@@ -27,6 +27,8 @@
 struct intel_slpc {
 	bool active;
 	struct i915_vma *vma;
+
+	u32 rp_control;
 };
 
 enum slpc_status {
@@ -245,6 +247,11 @@ int intel_slpc_task_control(struct intel_slpc *slpc, u64 val,
 			    u32 enable_id, u32 disable_id);
 int intel_slpc_task_status(struct intel_slpc *slpc, u64 *val,
 			   u32 enable_id, u32 disable_id);
+void intel_slpc_read_shared_data(struct intel_slpc *slpc,
+				 struct slpc_shared_data *data);
+const char *intel_slpc_get_state_str(enum slpc_global_state state);
+bool intel_slpc_get_status(struct intel_slpc *slpc);
+void intel_slpc_save_default_rps(struct intel_slpc *slpc);
 void intel_slpc_init(struct intel_slpc *slpc);
 void intel_slpc_cleanup(struct intel_slpc *slpc);
 void intel_slpc_enable(struct intel_slpc *slpc);
-- 
1.9.1

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[PATCH 12/20] drm/i915/slpc: Send SHUTDOWN event

[Sagar Arun Kamble]

From: Tom O'Rourke <Tom.O'Rourke@intel.com>

Send SLPC shutdown event during disable, suspend, and reset
operations. Sending shutdown event while already shutdown
is OK.

v1: Return void instead of ignored error code (Paulo)
    Removed WARN_ON for checking msb of gtt address of
    shared gem obj. (ChrisW)
    Added SLPC state update during disable, suspend and reset.
    Changed semantics of reset. It is supposed to just disable. (Sagar)

v2-v4: Rebase.

v5: Updated the input data structure. (Sagar)

v6: Rebase.

v7: s/i915_ggtt_offset/guc_ggtt_offset.

Signed-off-by: Tom O'Rourke <Tom.O'Rourke@intel.com>
Signed-off-by: Sagar Arun Kamble <sagar.a.kamble@intel.com>
---
 drivers/gpu/drm/i915/intel_slpc.c | 21 +++++++++++++++++++++
 1 file changed, 21 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_slpc.c b/drivers/gpu/drm/i915/intel_slpc.c
index 49643d3..b8a8437 100644
--- a/drivers/gpu/drm/i915/intel_slpc.c
+++ b/drivers/gpu/drm/i915/intel_slpc.c
@@ -414,6 +414,18 @@ static void host2guc_slpc_query_task_state(struct intel_slpc *slpc)
 	host2guc_slpc(slpc, &data, 4);
 }
 
+static void host2guc_slpc_shutdown(struct intel_slpc *slpc)
+{
+	struct slpc_event_input data = {0};
+	u32 shared_data_gtt_offset = guc_ggtt_offset(slpc->vma);
+
+	data.header.value = SLPC_EVENT(SLPC_EVENT_SHUTDOWN, 2);
+	data.args[0] = shared_data_gtt_offset;
+	data.args[1] = 0;
+
+	host2guc_slpc(slpc, &data, 4);
+}
+
 void intel_slpc_query_task_state(struct intel_slpc *slpc)
 {
 	if (slpc->active)
@@ -563,4 +575,13 @@ void intel_slpc_enable(struct intel_slpc *slpc)
 
 void intel_slpc_disable(struct intel_slpc *slpc)
 {
+	struct slpc_shared_data data;
+
+	host2guc_slpc_shutdown(slpc);
+
+	/* Ensure SLPC is not running prior to releasing Shared data */
+	intel_slpc_read_shared_data(slpc, &data);
+	WARN_ON(data.global_state != SLPC_GLOBAL_STATE_NOT_RUNNING);
+
+	slpc->active = false;
 }
-- 
1.9.1

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[PATCH 13/20] drm/i915/slpc: Add support for min/max frequency control

[Sagar Arun Kamble]

Update sysfs and debugfs functions to set SLPC
parameters when setting max/min frequency.

v1: Update for SLPC 2015.2.4 (params for both slice and unslice)
    Replace HAS_SLPC with intel_slpc_active() (Paulo)

v2-v4: Rebase.

v5: Removed typecasting the frequency values to u32. (Chris)
    Changed intel_slpc_active to guc.slpc.enabled. Carved out
    SLPC helpers to set min and max frequencies.

v6: Rebase. Doing explicit SLPC reset on setting frequency to start sane
    and covered with RPM get/put. Caching SLPC limits post enabling first.

Signed-off-by: Tom O'Rourke <Tom.O'Rourke@intel.com>
Signed-off-by: Sagar Arun Kamble <sagar.a.kamble@intel.com>
---
 drivers/gpu/drm/i915/i915_debugfs.c | 46 +++++++++++++++++++++++++++---
 drivers/gpu/drm/i915/i915_sysfs.c   | 36 ++++++++++++++++++++----
 drivers/gpu/drm/i915/intel_slpc.c   | 56 +++++++++++++++++++++++++++++++++++++
 drivers/gpu/drm/i915/intel_slpc.h   |  5 ++++
 4 files changed, 133 insertions(+), 10 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
index b3fb7350..2606554 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -4336,7 +4336,12 @@ static ssize_t cur_wm_latency_write(struct file *file, const char __user *ubuf,
 	if (INTEL_GEN(dev_priv) < 6)
 		return -ENODEV;
 
-	*val = intel_gpu_freq(dev_priv, dev_priv->rps.max_freq_softlimit);
+	if (dev_priv->guc.slpc.active)
+		*val = intel_gpu_freq(dev_priv,
+				      dev_priv->guc.slpc.max_unslice_freq);
+	else
+		*val = intel_gpu_freq(dev_priv,
+				      dev_priv->rps.max_freq_softlimit);
 	return 0;
 }
 
@@ -4352,20 +4357,32 @@ static ssize_t cur_wm_latency_write(struct file *file, const char __user *ubuf,
 
 	DRM_DEBUG_DRIVER("Manually setting max freq to %llu\n", val);
 
+	intel_runtime_pm_get(dev_priv);
+
 	ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
-	if (ret)
+	if (ret) {
+		intel_runtime_pm_put(dev_priv);
 		return ret;
+	}
 
 	/*
 	 * Turbo will still be enabled, but won't go above the set value.
 	 */
 	val = intel_freq_opcode(dev_priv, val);
 
+	if (dev_priv->guc.slpc.active) {
+		ret = intel_slpc_max_freq_set(&dev_priv->guc.slpc, val);
+		mutex_unlock(&dev_priv->rps.hw_lock);
+		intel_runtime_pm_put(dev_priv);
+		return ret;
+	}
+
 	hw_max = dev_priv->rps.max_freq;
 	hw_min = dev_priv->rps.min_freq;
 
 	if (val < hw_min || val > hw_max || val < dev_priv->rps.min_freq_softlimit) {
 		mutex_unlock(&dev_priv->rps.hw_lock);
+		intel_runtime_pm_put(dev_priv);
 		return -EINVAL;
 	}
 
@@ -4376,6 +4393,8 @@ static ssize_t cur_wm_latency_write(struct file *file, const char __user *ubuf,
 
 	mutex_unlock(&dev_priv->rps.hw_lock);
 
+	intel_runtime_pm_put(dev_priv);
+
 	return 0;
 }
 
@@ -4391,7 +4410,12 @@ static ssize_t cur_wm_latency_write(struct file *file, const char __user *ubuf,
 	if (INTEL_GEN(dev_priv) < 6)
 		return -ENODEV;
 
-	*val = intel_gpu_freq(dev_priv, dev_priv->rps.min_freq_softlimit);
+	if (dev_priv->guc.slpc.active)
+		*val = intel_gpu_freq(dev_priv,
+				      dev_priv->guc.slpc.min_unslice_freq);
+	else
+		*val = intel_gpu_freq(dev_priv,
+				      dev_priv->rps.min_freq_softlimit);
 	return 0;
 }
 
@@ -4407,21 +4431,33 @@ static ssize_t cur_wm_latency_write(struct file *file, const char __user *ubuf,
 
 	DRM_DEBUG_DRIVER("Manually setting min freq to %llu\n", val);
 
+	intel_runtime_pm_get(dev_priv);
+
 	ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
-	if (ret)
+	if (ret) {
+		intel_runtime_pm_put(dev_priv);
 		return ret;
+	}
 
 	/*
 	 * Turbo will still be enabled, but won't go below the set value.
 	 */
 	val = intel_freq_opcode(dev_priv, val);
 
+	if (dev_priv->guc.slpc.active) {
+		ret = intel_slpc_min_freq_set(&dev_priv->guc.slpc, val);
+		mutex_unlock(&dev_priv->rps.hw_lock);
+		intel_runtime_pm_put(dev_priv);
+		return ret;
+	}
+
 	hw_max = dev_priv->rps.max_freq;
 	hw_min = dev_priv->rps.min_freq;
 
 	if (val < hw_min ||
 	    val > hw_max || val > dev_priv->rps.max_freq_softlimit) {
 		mutex_unlock(&dev_priv->rps.hw_lock);
+		intel_runtime_pm_put(dev_priv);
 		return -EINVAL;
 	}
 
@@ -4432,6 +4468,8 @@ static ssize_t cur_wm_latency_write(struct file *file, const char __user *ubuf,
 
 	mutex_unlock(&dev_priv->rps.hw_lock);
 
+	intel_runtime_pm_put(dev_priv);
+
 	return 0;
 }
 
diff --git a/drivers/gpu/drm/i915/i915_sysfs.c b/drivers/gpu/drm/i915/i915_sysfs.c
index d61c872..b510f2f 100644
--- a/drivers/gpu/drm/i915/i915_sysfs.c
+++ b/drivers/gpu/drm/i915/i915_sysfs.c
@@ -325,9 +325,14 @@ static ssize_t gt_max_freq_mhz_show(struct device *kdev, struct device_attribute
 {
 	struct drm_i915_private *dev_priv = kdev_minor_to_i915(kdev);
 
-	return snprintf(buf, PAGE_SIZE, "%d\n",
-			intel_gpu_freq(dev_priv,
-				       dev_priv->rps.max_freq_softlimit));
+	if (dev_priv->guc.slpc.active)
+		return snprintf(buf, PAGE_SIZE, "%d\n",
+				intel_gpu_freq(dev_priv,
+					dev_priv->guc.slpc.max_unslice_freq));
+	else
+		return snprintf(buf, PAGE_SIZE, "%d\n",
+				intel_gpu_freq(dev_priv,
+					dev_priv->rps.max_freq_softlimit));
 }
 
 static ssize_t gt_max_freq_mhz_store(struct device *kdev,
@@ -348,6 +353,13 @@ static ssize_t gt_max_freq_mhz_store(struct device *kdev,
 
 	val = intel_freq_opcode(dev_priv, val);
 
+	if (dev_priv->guc.slpc.active) {
+		ret = intel_slpc_max_freq_set(&dev_priv->guc.slpc, val);
+		mutex_unlock(&dev_priv->rps.hw_lock);
+		intel_runtime_pm_put(dev_priv);
+		return ret ? ret : count;
+	}
+
 	if (val < dev_priv->rps.min_freq ||
 	    val > dev_priv->rps.max_freq ||
 	    val < dev_priv->rps.min_freq_softlimit) {
@@ -382,9 +394,14 @@ static ssize_t gt_min_freq_mhz_show(struct device *kdev, struct device_attribute
 {
 	struct drm_i915_private *dev_priv = kdev_minor_to_i915(kdev);
 
-	return snprintf(buf, PAGE_SIZE, "%d\n",
-			intel_gpu_freq(dev_priv,
-				       dev_priv->rps.min_freq_softlimit));
+	if (dev_priv->guc.slpc.active)
+		return snprintf(buf, PAGE_SIZE, "%d\n",
+				intel_gpu_freq(dev_priv,
+					dev_priv->guc.slpc.min_unslice_freq));
+	else
+		return snprintf(buf, PAGE_SIZE, "%d\n",
+				intel_gpu_freq(dev_priv,
+					dev_priv->rps.min_freq_softlimit));
 }
 
 static ssize_t gt_min_freq_mhz_store(struct device *kdev,
@@ -405,6 +422,13 @@ static ssize_t gt_min_freq_mhz_store(struct device *kdev,
 
 	val = intel_freq_opcode(dev_priv, val);
 
+	if (dev_priv->guc.slpc.active) {
+		ret = intel_slpc_min_freq_set(&dev_priv->guc.slpc, val);
+		mutex_unlock(&dev_priv->rps.hw_lock);
+		intel_runtime_pm_put(dev_priv);
+		return ret ? ret : count;
+	}
+
 	if (val < dev_priv->rps.min_freq ||
 	    val > dev_priv->rps.max_freq ||
 	    val > dev_priv->rps.max_freq_softlimit) {
diff --git a/drivers/gpu/drm/i915/intel_slpc.c b/drivers/gpu/drm/i915/intel_slpc.c
index b8a8437..43767c9 100644
--- a/drivers/gpu/drm/i915/intel_slpc.c
+++ b/drivers/gpu/drm/i915/intel_slpc.c
@@ -483,6 +483,10 @@ bool intel_slpc_get_status(struct intel_slpc *slpc)
 	switch (data.global_state) {
 	case SLPC_GLOBAL_STATE_RUNNING:
 		/* Capture required state from SLPC here */
+		slpc->max_unslice_freq = data.task_state_data.max_unslice_freq *
+					 GEN9_FREQ_SCALER;
+		slpc->min_unslice_freq = data.task_state_data.min_unslice_freq *
+					 GEN9_FREQ_SCALER;
 		ret = true;
 		break;
 	case SLPC_GLOBAL_STATE_ERROR:
@@ -523,6 +527,58 @@ static void intel_slpc_restore_default_rps(struct intel_slpc *slpc)
 	I915_WRITE(GEN6_RP_CONTROL, slpc->rp_control);
 }
 
+/*
+ * TODO: Add separate interfaces to set Max/Min Slice frequency.
+ * Since currently both slice and unslice are configured to same
+ * frequencies these unified interface relying on Unslice frequencies
+ * should be sufficient. These functions take frequency opcode as input.
+ */
+int intel_slpc_max_freq_set(struct intel_slpc *slpc, u32 val)
+{
+	struct drm_i915_private *dev_priv = slpc_to_i915(slpc);
+
+	if (val < dev_priv->rps.min_freq ||
+	    val > dev_priv->rps.max_freq ||
+	    val < slpc->min_unslice_freq)
+		return -EINVAL;
+
+	intel_slpc_set_param(slpc,
+			     SLPC_PARAM_GLOBAL_MAX_GT_UNSLICE_FREQ_MHZ,
+			     intel_gpu_freq(dev_priv, val));
+	intel_slpc_set_param(slpc,
+			     SLPC_PARAM_GLOBAL_MAX_GT_SLICE_FREQ_MHZ,
+			     intel_gpu_freq(dev_priv, val));
+
+	intel_slpc_enable(slpc);
+
+	slpc->max_unslice_freq = val;
+
+	return 0;
+}
+
+int intel_slpc_min_freq_set(struct intel_slpc *slpc, u32 val)
+{
+	struct drm_i915_private *dev_priv = slpc_to_i915(slpc);
+
+	if (val < dev_priv->rps.min_freq ||
+	    val > dev_priv->rps.max_freq ||
+	    val > slpc->max_unslice_freq)
+		return -EINVAL;
+
+	intel_slpc_set_param(slpc,
+			     SLPC_PARAM_GLOBAL_MIN_GT_UNSLICE_FREQ_MHZ,
+			     intel_gpu_freq(dev_priv, val));
+	intel_slpc_set_param(slpc,
+			     SLPC_PARAM_GLOBAL_MIN_GT_SLICE_FREQ_MHZ,
+			     intel_gpu_freq(dev_priv, val));
+
+	intel_slpc_enable(slpc);
+
+	slpc->min_unslice_freq = val;
+
+	return 0;
+}
+
 void intel_slpc_init(struct intel_slpc *slpc)
 {
 	struct intel_guc *guc = slpc_to_guc(slpc);
diff --git a/drivers/gpu/drm/i915/intel_slpc.h b/drivers/gpu/drm/i915/intel_slpc.h
index a01f9e5..a5132d4 100644
--- a/drivers/gpu/drm/i915/intel_slpc.h
+++ b/drivers/gpu/drm/i915/intel_slpc.h
@@ -29,6 +29,9 @@ struct intel_slpc {
 	struct i915_vma *vma;
 
 	u32 rp_control;
+	/* i915 cached SLPC frequency limits */
+	u32 min_unslice_freq;
+	u32 max_unslice_freq;
 };
 
 enum slpc_status {
@@ -252,6 +255,8 @@ void intel_slpc_read_shared_data(struct intel_slpc *slpc,
 const char *intel_slpc_get_state_str(enum slpc_global_state state);
 bool intel_slpc_get_status(struct intel_slpc *slpc);
 void intel_slpc_save_default_rps(struct intel_slpc *slpc);
+int intel_slpc_max_freq_set(struct intel_slpc *slpc, u32 val);
+int intel_slpc_min_freq_set(struct intel_slpc *slpc, u32 val);
 void intel_slpc_init(struct intel_slpc *slpc);
 void intel_slpc_cleanup(struct intel_slpc *slpc);
 void intel_slpc_enable(struct intel_slpc *slpc);
-- 
1.9.1

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[PATCH 14/20] drm/i915/slpc: Add debugfs support to read/write/revert the parameters

[Sagar Arun Kamble]

This patch adds two debugfs interfaces:
1. i915_slpc_paramlist: List of all parameters that Host can configure.
   Currently listing id and description of each.
2. i915_slpc_param_ctl: This allows to change the parameters. Syntax is:
   echo "write <id> <value>" > i915_slpc_param_ctl.
   echo "read <id>" > i915_slpc_param_ctl; cat i915_slpc_param_ctl
   revert allows to set to default SLPC internal values. Syntax is:
   echo "revert <id>" > i915_slpc_param_ctl.

Added support to set/read parameters and unset the parameters which will
revert them to default SLPC internal values. Also added RPM ref. cover
around set/unset calls. Explicit SLPC reset is needed on setting/unsetting
some of the parameters.

Signed-off-by: Sagar Arun Kamble <sagar.a.kamble@intel.com>
---
 drivers/gpu/drm/i915/i915_debugfs.c |  19 +++++
 drivers/gpu/drm/i915/intel_slpc.c   | 158 ++++++++++++++++++++++++++++++++++++
 drivers/gpu/drm/i915/intel_slpc.h   |   6 ++
 3 files changed, 183 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
index 2606554..91edc2f 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -2359,6 +2359,23 @@ static int i915_huc_load_status_info(struct seq_file *m, void *data)
 	return 0;
 }
 
+static int i915_slpc_paramlist_info(struct seq_file *m, void *data)
+{
+	struct drm_i915_private *dev_priv = node_to_i915(m->private);
+	int i;
+
+	if (!dev_priv->guc.slpc.active) {
+		seq_puts(m, "SLPC not active\n");
+		return 0;
+	}
+
+	seq_puts(m, "Param id\tParam description\n");
+	for (i = 0; i < SLPC_MAX_PARAM; i++)
+		seq_printf(m, "%8d\t%s\n", slpc_paramlist[i].id,
+					   slpc_paramlist[i].description);
+	return 0;
+}
+
 static int i915_guc_load_status_info(struct seq_file *m, void *data)
 {
 	struct drm_i915_private *dev_priv = node_to_i915(m->private);
@@ -4833,6 +4850,7 @@ static int i915_hpd_storm_ctl_open(struct inode *inode, struct file *file)
 	{"i915_guc_load_err_log_dump", i915_guc_log_dump, 0, (void *)1},
 	{"i915_guc_stage_pool", i915_guc_stage_pool, 0},
 	{"i915_huc_load_status", i915_huc_load_status_info, 0},
+	{"i915_slpc_paramlist", i915_slpc_paramlist_info, 0},
 	{"i915_frequency_info", i915_frequency_info, 0},
 	{"i915_hangcheck_info", i915_hangcheck_info, 0},
 	{"i915_reset_info", i915_reset_info, 0},
@@ -4896,6 +4914,7 @@ static int i915_hpd_storm_ctl_open(struct inode *inode, struct file *file)
 	{"i915_dp_test_type", &i915_displayport_test_type_fops},
 	{"i915_dp_test_active", &i915_displayport_test_active_fops},
 	{"i915_guc_log_control", &i915_guc_log_control_fops},
+	{"i915_slpc_param_ctl", &i915_slpc_param_ctl_fops},
 	{"i915_hpd_storm_ctl", &i915_hpd_storm_ctl_fops}
 };
 
diff --git a/drivers/gpu/drm/i915/intel_slpc.c b/drivers/gpu/drm/i915/intel_slpc.c
index 43767c9..7410e2d 100644
--- a/drivers/gpu/drm/i915/intel_slpc.c
+++ b/drivers/gpu/drm/i915/intel_slpc.c
@@ -25,6 +25,8 @@
 #include <asm/msr-index.h>
 #include "i915_drv.h"
 #include "intel_uc.h"
+#include <linux/seq_file.h>
+#include <linux/debugfs.h>
 
 struct slpc_param slpc_paramlist[SLPC_MAX_PARAM] = {
 	{SLPC_PARAM_TASK_ENABLE_GTPERF, "Enable task GTPERF"},
@@ -641,3 +643,159 @@ void intel_slpc_disable(struct intel_slpc *slpc)
 
 	slpc->active = false;
 }
+
+static int slpc_param_ctl_show(struct seq_file *m, void *data)
+{
+	struct drm_i915_private *dev_priv = m->private;
+	struct intel_slpc *slpc = &dev_priv->guc.slpc;
+
+	if (!slpc->active) {
+		seq_puts(m, "SLPC not active\n");
+		return 0;
+	}
+
+	seq_printf(m, "%s=%u, override=%s\n",
+			slpc_paramlist[slpc->debug_param_id].description,
+			slpc->debug_param_value,
+			yesno(!!slpc->debug_param_override));
+
+	return 0;
+}
+
+static int slpc_param_ctl_open(struct inode *inode, struct file *file)
+{
+	return single_open(file, slpc_param_ctl_show, inode->i_private);
+}
+
+static const char *read_token = "read", *write_token = "write",
+		  *revert_token = "revert";
+
+/*
+ * Parse SLPC parameter control strings: (Similar to Pipe CRC handling)
+ *   command: wsp* op wsp+ param id wsp+ [value] wsp*
+ *   op: "read"/"write"/"revert"
+ *   param id: slpc_param_id
+ *   value: u32 value
+ *   wsp: (#0x20 | #0x9 | #0xA)+
+ *
+ * eg.:
+ *  "read 0"		-> read SLPC_PARAM_TASK_ENABLE_GTPERF
+ *  "write 7 500"	-> set SLPC_PARAM_GLOBAL_MIN_GT_SLICE_FREQ_MHZ to 500MHz
+ *  "revert 7"		-> revert SLPC_PARAM_GLOBAL_MIN_GT_SLICE_FREQ_MHZ to
+ *			   default value.
+ */
+static int slpc_param_ctl_parse(char *buf, size_t len, char **op,
+				u32 *id, u32 *value)
+{
+#define MAX_WORDS 3
+	int n_words;
+	char *words[MAX_WORDS];
+	ssize_t ret;
+
+	n_words = buffer_tokenize(buf, words, MAX_WORDS);
+	if (!(n_words == 3) && !(n_words == 2)) {
+		DRM_DEBUG_DRIVER("tokenize failed, a command is %d words\n",
+				 MAX_WORDS);
+		return -EINVAL;
+	}
+
+	if (strcmp(words[0], read_token) && strcmp(words[0], write_token) &&
+	    strcmp(words[0], revert_token)) {
+		DRM_DEBUG_DRIVER("unknown operation\n");
+		return -EINVAL;
+	}
+
+	*op = words[0];
+
+	ret = kstrtou32(words[1], 0, id);
+	if (ret)
+		return ret;
+
+	if (n_words == 3) {
+		ret = kstrtou32(words[2], 0, value);
+		if (ret)
+			return ret;
+	}
+
+	return 0;
+}
+
+static ssize_t slpc_param_ctl_write(struct file *file, const char __user *ubuf,
+				     size_t len, loff_t *offp)
+{
+	struct seq_file *m = file->private_data;
+	struct drm_i915_private *dev_priv = m->private;
+	struct intel_slpc *slpc = &dev_priv->guc.slpc;
+	char *tmpbuf, *op = NULL;
+	u32 id, value;
+	int ret;
+
+	if (len == 0)
+		return 0;
+
+	if (len > 40) {
+		DRM_DEBUG_DRIVER("expected <40 chars into slpc_param_ctl\n");
+		return -E2BIG;
+	}
+
+	tmpbuf = kmalloc(len + 1, GFP_KERNEL);
+	if (!tmpbuf)
+		return -ENOMEM;
+
+	if (copy_from_user(tmpbuf, ubuf, len)) {
+		ret = -EFAULT;
+		goto out;
+	}
+	tmpbuf[len] = '\0';
+
+	ret = slpc_param_ctl_parse(tmpbuf, len, &op, &id, &value);
+
+	if (id >= SLPC_MAX_PARAM) {
+		ret = -EINVAL;
+		goto out;
+	}
+
+	if (!strcmp(op, read_token)) {
+		intel_slpc_get_param(slpc, id,
+				     &slpc->debug_param_override,
+				     &slpc->debug_param_value);
+		slpc->debug_param_id = id;
+	} else if (!strcmp(op, write_token) || !strcmp(op, revert_token)) {
+		if ((id >= SLPC_PARAM_TASK_ENABLE_GTPERF) &&
+		    (id <= SLPC_PARAM_TASK_DISABLE_DCC)) {
+			DRM_DEBUG_DRIVER("Tasks are not controlled by "
+					 "this interface\n");
+			ret = -EINVAL;
+			goto out;
+		}
+
+		/*
+		 * After updating parameters, RESET event has to be sent to GuC
+		 * SLPC for ensuring parameters take effect.
+		 */
+		intel_runtime_pm_get(dev_priv);
+		if (!strcmp(op, write_token))
+			intel_slpc_set_param(slpc, id, value);
+		else if (!strcmp(op, revert_token))
+			intel_slpc_unset_param(slpc, id);
+		intel_slpc_enable(slpc);
+		intel_runtime_pm_put(dev_priv);
+	}
+
+out:
+	kfree(tmpbuf);
+	if (ret < 0)
+		return ret;
+
+	*offp += len;
+	return len;
+}
+
+const struct file_operations i915_slpc_param_ctl_fops = {
+	.owner = THIS_MODULE,
+	.open = slpc_param_ctl_open,
+	.read = seq_read,
+	.llseek = seq_lseek,
+	.release = single_release,
+	.write = slpc_param_ctl_write
+};
diff --git a/drivers/gpu/drm/i915/intel_slpc.h b/drivers/gpu/drm/i915/intel_slpc.h
index a5132d4..d2d7448 100644
--- a/drivers/gpu/drm/i915/intel_slpc.h
+++ b/drivers/gpu/drm/i915/intel_slpc.h
@@ -32,6 +32,10 @@ struct intel_slpc {
 	/* i915 cached SLPC frequency limits */
 	u32 min_unslice_freq;
 	u32 max_unslice_freq;
+
+	u32 debug_param_id;
+	u32 debug_param_value;
+	u32 debug_param_override;
 };
 
 enum slpc_status {
@@ -241,6 +245,8 @@ struct slpc_param {
 #define SLPC_PARAM_TASK_DISABLED 2
 #define SLPC_PARAM_TASK_UNKNOWN  3
 
+extern const struct file_operations i915_slpc_param_ctl_fops;
+
 /* intel_slpc.c */
 void intel_slpc_set_param(struct intel_slpc *slpc, u32 id, u32 value);
 void intel_slpc_unset_param(struct intel_slpc *slpc, u32 id);
-- 
1.9.1

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[PATCH 15/20] drm/i915/slpc: Add enable/disable controls for SLPC tasks

[Sagar Arun Kamble]

From: Tom O'Rourke <Tom.O'Rourke@intel.com>

Adds debugfs hooks for enabling/disabling each SLPC task.

The enable/disable debugfs files are
i915_slpc_gtperf, i915_slpc_balancer, and i915_slpc_dcc.

Each of these can take the values:
"default", "enabled", or "disabled"

v1: update for SLPC v2015.2.4
    dfps and turbo merged and renamed "gtperf"
    ibc split out and renamed "balancer"
    Avoid magic numbers (Jon Bloomfield)

v2-v3: Rebase.

v5: Moved slpc_enable_disable_set and slpc_enable_disable_get to
    intel_slpc.c. s/slpc_enable_disable_get/intel_slpc_task_status
    and s/slpc_enable_disable_set/intel_slpc_task_control. Prepared
    separate functions to update the task status only in the SLPC
    shared memory. Passing dev_priv as parameter.

v6: Rebase. s/slpc_param_show|write/slpc_task_param_show|write.
    Moved functions to intel_slpc.c. RPM Get/Put added before setting
    parameters and sending RESET event explicitly. (Sagar)

Signed-off-by: Tom O'Rourke <Tom.O'Rourke@intel.com>
Signed-off-by: Sagar Arun Kamble <sagar.a.kamble@intel.com>
---
 drivers/gpu/drm/i915/i915_debugfs.c |   3 +
 drivers/gpu/drm/i915/intel_slpc.c   | 184 ++++++++++++++++++++++++++++++++++++
 drivers/gpu/drm/i915/intel_slpc.h   |   3 +
 3 files changed, 190 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
index 91edc2f..8d0d094 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -4894,6 +4894,9 @@ static int i915_hpd_storm_ctl_open(struct inode *inode, struct file *file)
 	const struct file_operations *fops;
 } i915_debugfs_files[] = {
 	{"i915_wedged", &i915_wedged_fops},
+	{"i915_slpc_gtperf", &i915_slpc_gtperf_fops},
+	{"i915_slpc_balancer", &i915_slpc_balancer_fops},
+	{"i915_slpc_dcc", &i915_slpc_dcc_fops},
 	{"i915_max_freq", &i915_max_freq_fops},
 	{"i915_min_freq", &i915_min_freq_fops},
 	{"i915_cache_sharing", &i915_cache_sharing_fops},
diff --git a/drivers/gpu/drm/i915/intel_slpc.c b/drivers/gpu/drm/i915/intel_slpc.c
index 7410e2d..093d670 100644
--- a/drivers/gpu/drm/i915/intel_slpc.c
+++ b/drivers/gpu/drm/i915/intel_slpc.c
@@ -799,3 +799,187 @@ static ssize_t slpc_param_ctl_write(struct file *file, const char __user *ubuf,
 	.release = single_release,
 	.write = slpc_param_ctl_write
 };
+
+static void slpc_task_param_show(struct seq_file *m, u32 enable_id,
+				 u32 disable_id)
+{
+	struct drm_i915_private *dev_priv = m->private;
+	const char *status;
+	u64 val;
+	int ret;
+
+	ret = intel_slpc_task_status(&dev_priv->guc.slpc, &val,
+				     enable_id, disable_id);
+
+	if (ret) {
+		seq_printf(m, "error %d\n", ret);
+	} else {
+		switch (val) {
+		case SLPC_PARAM_TASK_DEFAULT:
+			status = "default\n";
+			break;
+
+		case SLPC_PARAM_TASK_ENABLED:
+			status = "enabled\n";
+			break;
+
+		case SLPC_PARAM_TASK_DISABLED:
+			status = "disabled\n";
+			break;
+
+		default:
+			status = "unknown\n";
+			break;
+		}
+
+		seq_puts(m, status);
+	}
+}
+
+static int slpc_task_param_write(struct seq_file *m, const char __user *ubuf,
+			    size_t len, u32 enable_id, u32 disable_id)
+{
+	struct drm_i915_private *dev_priv = m->private;
+	u64 val;
+	int ret = 0;
+	char buf[10];
+
+	if (len >= sizeof(buf))
+		ret = -EINVAL;
+	else if (copy_from_user(buf, ubuf, len))
+		ret = -EFAULT;
+	else
+		buf[len] = '\0';
+
+	if (!ret) {
+		if (!strncmp(buf, "default", 7))
+			val = SLPC_PARAM_TASK_DEFAULT;
+		else if (!strncmp(buf, "enabled", 7))
+			val = SLPC_PARAM_TASK_ENABLED;
+		else if (!strncmp(buf, "disabled", 8))
+			val = SLPC_PARAM_TASK_DISABLED;
+		else
+			ret = -EINVAL;
+	}
+
+	if (!ret)
+		ret = intel_slpc_task_control(&dev_priv->guc.slpc, val,
+					      enable_id, disable_id);
+
+	return ret;
+}
+
+static int slpc_gtperf_show(struct seq_file *m, void *data)
+{
+	slpc_task_param_show(m, SLPC_PARAM_TASK_ENABLE_GTPERF,
+			SLPC_PARAM_TASK_DISABLE_GTPERF);
+
+	return 0;
+}
+
+static int slpc_gtperf_open(struct inode *inode, struct file *file)
+{
+	struct drm_i915_private *dev_priv = inode->i_private;
+
+	return single_open(file, slpc_gtperf_show, dev_priv);
+}
+
+static ssize_t slpc_gtperf_write(struct file *file, const char __user *ubuf,
+			      size_t len, loff_t *offp)
+{
+	struct seq_file *m = file->private_data;
+	int ret = 0;
+
+	ret = slpc_task_param_write(m, ubuf, len, SLPC_PARAM_TASK_ENABLE_GTPERF,
+			       SLPC_PARAM_TASK_DISABLE_GTPERF);
+	if (ret)
+		return ret;
+
+	return len;
+}
+
+const struct file_operations i915_slpc_gtperf_fops = {
+	.owner	 = THIS_MODULE,
+	.open	 = slpc_gtperf_open,
+	.release = single_release,
+	.read	 = seq_read,
+	.write	 = slpc_gtperf_write,
+	.llseek	 = seq_lseek
+};
+
+static int slpc_balancer_show(struct seq_file *m, void *data)
+{
+	slpc_task_param_show(m, SLPC_PARAM_TASK_ENABLE_BALANCER,
+			SLPC_PARAM_TASK_DISABLE_BALANCER);
+
+	return 0;
+}
+
+static int slpc_balancer_open(struct inode *inode, struct file *file)
+{
+	struct drm_i915_private *dev_priv = inode->i_private;
+
+	return single_open(file, slpc_balancer_show, dev_priv);
+}
+
+static ssize_t slpc_balancer_write(struct file *file, const char __user *ubuf,
+			      size_t len, loff_t *offp)
+{
+	struct seq_file *m = file->private_data;
+	int ret = 0;
+
+	ret = slpc_task_param_write(m, ubuf, len,
+				SLPC_PARAM_TASK_ENABLE_BALANCER,
+				SLPC_PARAM_TASK_DISABLE_BALANCER);
+	if (ret)
+		return ret;
+
+	return len;
+}
+
+const struct file_operations i915_slpc_balancer_fops = {
+	.owner	 = THIS_MODULE,
+	.open	 = slpc_balancer_open,
+	.release = single_release,
+	.read	 = seq_read,
+	.write	 = slpc_balancer_write,
+	.llseek	 = seq_lseek
+};
+
+static int slpc_dcc_show(struct seq_file *m, void *data)
+{
+	slpc_task_param_show(m, SLPC_PARAM_TASK_ENABLE_DCC,
+			SLPC_PARAM_TASK_DISABLE_DCC);
+
+	return 0;
+}
+
+static int slpc_dcc_open(struct inode *inode, struct file *file)
+{
+	struct drm_i915_private *dev_priv = inode->i_private;
+
+	return single_open(file, slpc_dcc_show, dev_priv);
+}
+
+static ssize_t slpc_dcc_write(struct file *file, const char __user *ubuf,
+			      size_t len, loff_t *offp)
+{
+	struct seq_file *m = file->private_data;
+	int ret = 0;
+
+	ret = slpc_task_param_write(m, ubuf, len, SLPC_PARAM_TASK_ENABLE_DCC,
+			       SLPC_PARAM_TASK_DISABLE_DCC);
+	if (ret)
+		return ret;
+
+	return len;
+}
+
+const struct file_operations i915_slpc_dcc_fops = {
+	.owner	 = THIS_MODULE,
+	.open	 = slpc_dcc_open,
+	.release = single_release,
+	.read	 = seq_read,
+	.write	 = slpc_dcc_write,
+	.llseek	 = seq_lseek
+};
diff --git a/drivers/gpu/drm/i915/intel_slpc.h b/drivers/gpu/drm/i915/intel_slpc.h
index d2d7448..796822b 100644
--- a/drivers/gpu/drm/i915/intel_slpc.h
+++ b/drivers/gpu/drm/i915/intel_slpc.h
@@ -246,6 +246,9 @@ struct slpc_param {
 #define SLPC_PARAM_TASK_UNKNOWN  3
 
 extern const struct file_operations i915_slpc_param_ctl_fops;
+extern const struct file_operations i915_slpc_gtperf_fops;
+extern const struct file_operations i915_slpc_balancer_fops;
+extern const struct file_operations i915_slpc_dcc_fops;
 
 /* intel_slpc.c */
 void intel_slpc_set_param(struct intel_slpc *slpc, u32 id, u32 value);
-- 
1.9.1

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[PATCH 16/20] drm/i915/slpc: Add i915_slpc_info to debugfs

[Sagar Arun Kamble]

From: Tom O'Rourke <Tom.O'Rourke@intel.com>

i915_slpc_info shows the contents of SLPC shared data
parsed into text format.

v1: Reformat slpc info (Radek)
    squashed query task state info
    in slpc info, kunmap before seq_print (Paulo)
    return void instead of ignored return value (Paulo)
    Avoid magic numbers and use local variables (Jon Bloomfield)
    Removed WARN_ON for checking msb of gtt address of
    shared gem obj. (ChrisW)
    Moved definition of power plan and power source to earlier
    patch in the series.
    drm/i915/slpc: Allocate/Release/Initialize SLPC shared data
    (Akash)

v2-v3: Rebase.

v4: Updated with GuC firmware v9.

v5: Updated host2guc_slpc_query_task_state with struct slpc_input_event
    structure. Removed unnecessary checks of vma from i915_slpc_info.
    Created helpers for reading the SLPC shared data and string form of
    SLPC state. (Sagar)

Signed-off-by: Tom O'Rourke <Tom.O'Rourke@intel.com>
Signed-off-by: Sagar Arun Kamble <sagar.a.kamble@intel.com>
---
 drivers/gpu/drm/i915/i915_debugfs.c | 165 ++++++++++++++++++++++++++++++++++++
 1 file changed, 165 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
index 8d0d094..8439ec2 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -1022,6 +1022,170 @@ static int i915_error_state_open(struct inode *inode, struct file *file)
 			NULL, i915_next_seqno_set,
 			"0x%llx\n");
 
+static int i915_slpc_info(struct seq_file *m, void *unused)
+{
+	struct drm_i915_private *dev_priv = node_to_i915(m->private);
+	int i, value;
+	struct slpc_shared_data data;
+	enum slpc_global_state global_state;
+	enum slpc_platform_sku platform_sku;
+	struct slpc_task_state_data *task_data;
+	enum slpc_power_plan power_plan;
+	enum slpc_power_source power_source;
+
+	if (!dev_priv->guc.slpc.active)
+		return -ENODEV;
+
+	intel_runtime_pm_get(dev_priv);
+	mutex_lock(&dev_priv->rps.hw_lock);
+
+	intel_slpc_read_shared_data(&dev_priv->guc.slpc, &data);
+
+	mutex_unlock(&dev_priv->rps.hw_lock);
+	intel_runtime_pm_put(dev_priv);
+
+	seq_printf(m, "shared data size: %d\n", data.shared_data_size);
+
+	global_state = (enum slpc_global_state) data.global_state;
+	seq_printf(m, "global state: %d (", global_state);
+	seq_printf(m, "%s)\n", intel_slpc_get_state_str(global_state));
+
+	platform_sku = (enum slpc_platform_sku)
+			data.platform_info.platform_sku;
+	seq_printf(m, "sku: %d (", platform_sku);
+	switch (platform_sku) {
+	case SLPC_PLATFORM_SKU_UNDEFINED:
+		seq_puts(m, "undefined)\n");
+		break;
+	case SLPC_PLATFORM_SKU_ULX:
+		seq_puts(m, "ULX)\n");
+		break;
+	case SLPC_PLATFORM_SKU_ULT:
+		seq_puts(m, "ULT)\n");
+		break;
+	case SLPC_PLATFORM_SKU_T:
+		seq_puts(m, "T)\n");
+		break;
+	case SLPC_PLATFORM_SKU_MOBL:
+		seq_puts(m, "Mobile)\n");
+		break;
+	case SLPC_PLATFORM_SKU_DT:
+		seq_puts(m, "DT)\n");
+		break;
+	case SLPC_PLATFORM_SKU_UNKNOWN:
+	default:
+		seq_puts(m, "unknown)\n");
+		break;
+	}
+	seq_printf(m, "slice count: %d\n",
+		   data.platform_info.slice_count);
+
+	seq_printf(m, "power plan/source: 0x%x\n\tplan:\t",
+		   data.platform_info.power_plan_source);
+	power_plan = (enum slpc_power_plan) SLPC_POWER_PLAN(
+				data.platform_info.power_plan_source);
+	power_source = (enum slpc_power_source) SLPC_POWER_SOURCE(
+				data.platform_info.power_plan_source);
+	switch (power_plan) {
+	case SLPC_POWER_PLAN_UNDEFINED:
+		seq_puts(m, "undefined");
+		break;
+	case SLPC_POWER_PLAN_BATTERY_SAVER:
+		seq_puts(m, "battery saver");
+		break;
+	case SLPC_POWER_PLAN_BALANCED:
+		seq_puts(m, "balanced");
+		break;
+	case SLPC_POWER_PLAN_PERFORMANCE:
+		seq_puts(m, "performance");
+		break;
+	case SLPC_POWER_PLAN_UNKNOWN:
+	default:
+		seq_puts(m, "unknown");
+		break;
+	}
+	seq_puts(m, "\n\tsource:\t");
+	switch (power_source) {
+	case SLPC_POWER_SOURCE_UNDEFINED:
+		seq_puts(m, "undefined\n");
+		break;
+	case SLPC_POWER_SOURCE_AC:
+		seq_puts(m, "AC\n");
+		break;
+	case SLPC_POWER_SOURCE_DC:
+		seq_puts(m, "DC\n");
+		break;
+	case SLPC_POWER_SOURCE_UNKNOWN:
+	default:
+		seq_puts(m, "unknown\n");
+		break;
+	}
+
+	seq_printf(m, "IA frequency (MHz):\n\tP0: %d\n\tP1: %d\n\tPe: %d\n\tPn: %d\n",
+		   data.platform_info.P0_freq * 50,
+		   data.platform_info.P1_freq * 50,
+		   data.platform_info.Pe_freq * 50,
+		   data.platform_info.Pn_freq * 50);
+
+	task_data = &data.task_state_data;
+	seq_printf(m, "task state data: 0x%08x 0x%08x\n",
+		   task_data->bitfield1, task_data->bitfield2);
+
+	seq_printf(m, "\tgtperf task active: %s\n",
+		   yesno(task_data->gtperf_task_active));
+	seq_printf(m, "\tgtperf stall possible: %s\n",
+		   yesno(task_data->gtperf_stall_possible));
+	seq_printf(m, "\tgtperf gaming mode: %s\n",
+		   yesno(task_data->gtperf_gaming_mode));
+	seq_printf(m, "\tgtperf target fps: %d\n",
+		   task_data->gtperf_target_fps);
+
+	seq_printf(m, "\tdcc task active: %s\n",
+		   yesno(task_data->dcc_task_active));
+	seq_printf(m, "\tin dcc: %s\n",
+		   yesno(task_data->in_dcc));
+	seq_printf(m, "\tin dct: %s\n",
+		   yesno(task_data->in_dct));
+	seq_printf(m, "\tfreq switch active: %s\n",
+		   yesno(task_data->freq_switch_active));
+
+	seq_printf(m, "\tibc enabled: %s\n",
+		   yesno(task_data->ibc_enabled));
+	seq_printf(m, "\tibc active: %s\n",
+		   yesno(task_data->ibc_active));
+	seq_printf(m, "\tpg1 enabled: %s\n",
+		   yesno(task_data->pg1_enabled));
+	seq_printf(m, "\tpg1 active: %s\n",
+		   yesno(task_data->pg1_active));
+
+	seq_printf(m, "\tunslice max freq: %dMHz\n",
+		   intel_gpu_freq(dev_priv,
+			task_data->max_unslice_freq * GEN9_FREQ_SCALER));
+	seq_printf(m, "\tunslice min freq: %dMHz\n",
+		   intel_gpu_freq(dev_priv,
+			task_data->min_unslice_freq * GEN9_FREQ_SCALER));
+	seq_printf(m, "\tslice max freq: %dMHz\n",
+		   intel_gpu_freq(dev_priv,
+			task_data->max_slice_freq * GEN9_FREQ_SCALER));
+	seq_printf(m, "\tslice min freq: %dMHz\n",
+		   intel_gpu_freq(dev_priv,
+			task_data->min_slice_freq * GEN9_FREQ_SCALER));
+
+	seq_puts(m, "override parameter bitfield\n");
+	for (i = 0; i < SLPC_OVERRIDE_BITFIELD_SIZE; i++)
+		seq_printf(m, "%d: 0x%08x\n", i,
+			   data.override_parameters_set_bits[i]);
+
+	seq_puts(m, "override parameters (only non-zero shown)\n");
+	for (i = 0; i < SLPC_MAX_OVERRIDE_PARAMETERS; i++) {
+		value = data.override_parameters_values[i];
+		if (value)
+			seq_printf(m, "%d: 0x%8x\n", i, value);
+	}
+
+	return 0;
+}
+
 static int i915_frequency_info(struct seq_file *m, void *unused)
 {
 	struct drm_i915_private *dev_priv = node_to_i915(m->private);
@@ -4851,6 +5015,7 @@ static int i915_hpd_storm_ctl_open(struct inode *inode, struct file *file)
 	{"i915_guc_stage_pool", i915_guc_stage_pool, 0},
 	{"i915_huc_load_status", i915_huc_load_status_info, 0},
 	{"i915_slpc_paramlist", i915_slpc_paramlist_info, 0},
+	{"i915_slpc_info", i915_slpc_info, 0},
 	{"i915_frequency_info", i915_frequency_info, 0},
 	{"i915_hangcheck_info", i915_hangcheck_info, 0},
 	{"i915_reset_info", i915_reset_info, 0},
-- 
1.9.1

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[PATCH 17/20] drm/i915/slpc: Add SLPC banner to RPS debugfs interfaces.

[Sagar Arun Kamble]

When SLPC is controlling frequency requests, RPS state related to
autotuning is no longer valid. Make user aware through banner
upfront. Value read from register RPNSWREQ likely has the frequency
requested last by GuC SLPC.

v1: Replace HAS_SLPC with intel_slpc_active (Paulo)
    Avoid magic numbers (Nick)
    Use a function for repeated code (Jon)

v2: Add "SLPC Active" to i915_frequency_info output and
    don't update cur_freq as it is driver internal request. (Chris)

v3: Removing sysfs interface gt_req_freq_mhz out of this patch
    for proper division of functionality. (Sagar)

v4: idle_freq, boost_freq are also not used with SLPC.

v5: Added SLPC banner to i915_rps_boost_info and keep printing
    driver internal values. (Chris)

v6: Commit message update.

Signed-off-by: Tom O'Rourke <Tom.O'Rourke@intel.com>
Signed-off-by: Sagar Arun Kamble <sagar.a.kamble@intel.com>
---
 drivers/gpu/drm/i915/i915_debugfs.c | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
index 8439ec2..3dc8832 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -1193,6 +1193,9 @@ static int i915_frequency_info(struct seq_file *m, void *unused)
 
 	intel_runtime_pm_get(dev_priv);
 
+	if (dev_priv->guc.slpc.active)
+		seq_puts(m, "SLPC Active\n");
+
 	if (IS_GEN5(dev_priv)) {
 		u16 rgvswctl = I915_READ16(MEMSWCTL);
 		u16 rgvstat = I915_READ16(MEMSTAT_ILK);
@@ -2416,6 +2419,9 @@ static int i915_rps_boost_info(struct seq_file *m, void *data)
 	struct drm_device *dev = &dev_priv->drm;
 	struct drm_file *file;
 
+	if (dev_priv->guc.slpc.active)
+		seq_puts(m, "SLPC Active\n");
+
 	seq_printf(m, "RPS enabled? %d\n", dev_priv->rps.rps_enabled);
 	seq_printf(m, "GPU busy? %s [%d requests]\n",
 		   yesno(dev_priv->gt.awake), dev_priv->gt.active_requests);
-- 
1.9.1

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[PATCH 18/20] drm/i915/slpc: Add SKL SLPC Support

[Sagar Arun Kamble]

From: Tom O'Rourke <Tom.O'Rourke@intel.com>

This patch adds has_slpc to skylake info.

The SLPC interface has changed and could continue to
change. Only GuC versions known to be compatible are
supported here.

On Skylake, GuC firmware v6 is supported.  Other
platforms and versions can be added here later.

v1: Move slpc_version_check to intel_guc_ucode_init.
    fix whitespace (Sagar)
    Moved version check to different patch as has_slpc
    should not be updated based on it. Instead module parameter
    should be updated based on version check. (Sagar)
    Added support to skylake_gt3 as well. (Sagar)

Reviewed-by: David Weinehall <david.weinehall@linux.intel.com>
Signed-off-by: Tom O'Rourke <Tom.O'Rourke@intel.com>
Signed-off-by: Sagar Arun Kamble <sagar.a.kamble@intel.com>
---
 drivers/gpu/drm/i915/i915_pci.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index a1e6b69..0ceb5b2 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -356,6 +356,7 @@
 	.platform = INTEL_SKYLAKE, \
 	.has_csr = 1, \
 	.has_guc = 1, \
+	.has_slpc = 1, \
 	.ddb_size = 896
 
 static const struct intel_device_info intel_skylake_info = {
-- 
1.9.1

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[PATCH 19/20] drm/i915/slpc: Add Broxton SLPC support

[Sagar Arun Kamble]

From: Tom O'Rourke <Tom.O'Rourke@intel.com>

Adds has_slpc to broxton info and adds broxton firmware version check
to sanitize_slpc_option.

v1: Adjusted slpc version check for major version 8.
    Added message if version mismatch happens for easier debug. (Sagar)

v2-v3: Rebase.

v4: Commit message update.

v5: Rebase. Updated check in sanitize_slpc_option.

Signed-off-by: Tom O'Rourke <Tom.O'Rourke@intel.com>
Signed-off-by: Sagar Arun Kamble <sagar.a.kamble@intel.com>
---
 drivers/gpu/drm/i915/i915_pci.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index 0ceb5b2..37d76d9 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -397,6 +397,7 @@
 
 static const struct intel_device_info intel_broxton_info = {
 	GEN9_LP_FEATURES,
+	.has_slpc = 1,
 	.platform = INTEL_BROXTON,
 	.ddb_size = 512,
 };
-- 
1.9.1

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[PATCH 20/20] drm/i915/slpc: Add Kabylake SLPC support

[Sagar Arun Kamble]

Adds has_slpc to kabylake info and adds kabylake firmware version check
to sanitize_slpc_option.

Signed-off-by: Sagar Arun Kamble <sagar.a.kamble@intel.com>
---
 drivers/gpu/drm/i915/i915_pci.c   | 1 +
 drivers/gpu/drm/i915/intel_slpc.c | 4 ++--
 2 files changed, 3 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index 37d76d9..bb71f01 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -415,6 +415,7 @@
 	.platform = INTEL_KABYLAKE, \
 	.has_csr = 1, \
 	.has_guc = 1, \
+	.has_slpc = 1, \
 	.ddb_size = 896
 
 static const struct intel_device_info intel_kabylake_info = {
diff --git a/drivers/gpu/drm/i915/intel_slpc.c b/drivers/gpu/drm/i915/intel_slpc.c
index 093d670..8ccdb4c 100644
--- a/drivers/gpu/drm/i915/intel_slpc.c
+++ b/drivers/gpu/drm/i915/intel_slpc.c
@@ -71,9 +71,9 @@ static unsigned int slpc_get_platform_sku(struct drm_i915_private *dev_priv)
 {
 	enum slpc_platform_sku platform_sku;
 
-	if (IS_SKL_ULX(dev_priv))
+	if (IS_SKL_ULX(dev_priv) || IS_KBL_ULX(dev_priv))
 		platform_sku = SLPC_PLATFORM_SKU_ULX;
-	else if (IS_SKL_ULT(dev_priv))
+	else if (IS_SKL_ULT(dev_priv) || IS_KBL_ULT(dev_priv))
 		platform_sku = SLPC_PLATFORM_SKU_ULT;
 	else
 		platform_sku = SLPC_PLATFORM_SKU_DT;
-- 
1.9.1

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Re: [PATCH 01/20] drm/i915/debugfs: Create generic string tokenize function and update CRC control parsing

[Szwichtenberg, Radoslaw]

On Fri, 2017-09-01 at 12:55 +0530, Sagar Arun Kamble wrote:
> Input string parsing used in CRC control parameter parsing is generic
> and can be reused for other debugfs interfaces. Hence name it as
> buffer_tokenize instead of tieing to display_crc. Also fix the function
s/tieing/tying ?
> desciption for CRC control parsing that was misplaced at tokenize function.
s/desciption/description
> 
> Cc: Tomeu Vizoso <tomeu.vizoso@collabora.com>
> Signed-off-by: Sagar Arun Kamble <sagar.a.kamble@intel.com>
Don't you think we could try to review and merge this change as separate commit
and not part of this series?

Some spelling mistakes, otherwise LGTM
Acked-by: Radoslaw Szwichtenberg <radoslaw.szwichtenberg@intel.com>

-Radek
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Re: [PATCH 02/20] drm/i915/gen9+: Separate RPS and RC6 handling

[Szwichtenberg, Radoslaw]

On Fri, 2017-09-01 at 12:55 +0530, Sagar Arun Kamble wrote:
> With GuC based SLPC, frequency control will be moved to GuC and Host will
> continue to control RC6 and Ring frequency setup. SLPC can be enabled in
> the GuC setup path and can happen in parallel in GuC with other i915 setup.
> Hence we can do away with deferred RPS enabling. This needs separate
> handling of RPS, RC6 and ring frequencies in driver flows. We can still use
> the *gt_powersave routines with separate status variables of RPS, RC6 and
> SLPC. With this patch, RC6 and ring frequencies setup(if applicable) can be
> tracked through rps.rc6_enabled and RPS through rps.rps_enabled.
> Also, Active RPS check in suspend flow is needed for platforms with RC6
> and RPS enabling/disabling coupled together. RPM suspend depends only on
> RC6 though. Hence Active RPS check is done only for non-Gen9 platforms.
> 
> v2: Changing parameter to dev_priv for IS_GEN9 and HAS_RUNTIME_PM and line
>     spacing changes. (David)
>     and commit message update for checkpatch issues.
> 
> v3: Rebase.
> 
> v4: Commit message update.
> 
> v5: Updated intel_enable_gt_powersave and intel_disable_gt_powersave
>     routines with separated RPS and RC6 handling and rebase. Commit message
>     update.(Sagar)
> 
> v6: Added comments at the definition of rc6_enabled.
> 
> v7: s/rps.enabled/rps.rps_enabled. With gen9 preproduction RPS disabling
>     changes removed, updating rps_enabled in enable/disable_gt_powersave.
>     Added checks for rc6_enabled and rps_enabled for gen9+ platforms.
> 
> Signed-off-by: Sagar Arun Kamble <sagar.a.kamble@intel.com>
Reviewed-by: Radoslaw Szwichtenberg <radoslaw.szwichtenberg@intel.com>
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Re: [PATCH 02/20] drm/i915/gen9+: Separate RPS and RC6 handling

[Chris Wilson]

Quoting Sagar Arun Kamble (2017-09-01 08:25:05)
> +/*
> + * This function enables RPS and RC6 for platforms prior to GEN9 and
> + * enables only RPS for GEN9+.
> + */
> +void __intel_enable_gt_powersave(struct drm_i915_private *dev_priv)
>  {
>         /* We shouldn't be disabling as we submit, so this should be less
>          * racy than it appears!
>          */
> -       if (READ_ONCE(dev_priv->rps.enabled))
> +       if (READ_ONCE(dev_priv->rps.rps_enabled))
>                 return;
>  
> -       /* Powersaving is controlled by the host when inside a VM */
> -       if (intel_vgpu_active(dev_priv))
> -               return;
> -
> -       mutex_lock(&dev_priv->rps.hw_lock);
> -
>         if (IS_CHERRYVIEW(dev_priv)) {
>                 cherryview_enable_rps(dev_priv);
>         } else if (IS_VALLEYVIEW(dev_priv)) {
>                 valleyview_enable_rps(dev_priv);
>         } else if (INTEL_GEN(dev_priv) >= 9) {
> -               gen9_enable_rc6(dev_priv);
>                 gen9_enable_rps(dev_priv);
> -               if (IS_GEN9_BC(dev_priv) || IS_CANNONLAKE(dev_priv))
> -                       gen6_update_ring_freq(dev_priv);
>         } else if (IS_BROADWELL(dev_priv)) {
>                 gen8_enable_rps(dev_priv);
>                 gen6_update_ring_freq(dev_priv);
> @@ -7878,10 +7891,35 @@ void intel_enable_gt_powersave(struct drm_i915_private *dev_priv)
>         WARN_ON(dev_priv->rps.efficient_freq < dev_priv->rps.min_freq);
>         WARN_ON(dev_priv->rps.efficient_freq > dev_priv->rps.max_freq);
>  
> -       dev_priv->rps.enabled = true;
> +       dev_priv->rps.rps_enabled = true;
> +}
> +
> +void intel_enable_gt_powersave(struct drm_i915_private *dev_priv)
> +{
> +       /* Powersaving is controlled by the host when inside a VM */
> +       if (intel_vgpu_active(dev_priv))
> +               return;
> +
> +       mutex_lock(&dev_priv->rps.hw_lock);
> +
> +       if (INTEL_GEN(dev_priv) >= 9) {
> +               if (!READ_ONCE(dev_priv->rps.rc6_enabled))
> +                       gen9_enable_rc6(dev_priv);
> +               if (IS_GEN9_BC(dev_priv) || IS_CANNONLAKE(dev_priv))
> +                       gen6_update_ring_freq(dev_priv);
> +       }
> +       __intel_enable_gt_powersave(dev_priv);
> +
>         mutex_unlock(&dev_priv->rps.hw_lock);
>  }

Ok, still nowhere close to being separate. Let's see if I can find the
patches I had to start making rc6 separate from rps.
-Chris
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Re: [PATCH 00/20] Add support for GuC-based SLPC

[Szwichtenberg, Radoslaw]

On Fri, 2017-09-01 at 12:55 +0530, Sagar Arun Kamble wrote:
> SLPC (Single Loop Power Controller) is a replacement for some host-based
> power management features. The SLPC implementation runs in GuC firmware.
> This series has been tested with SKL/APL/KBL GuC firmware v9 and v10
> which are yet to be released on 01.org.
> 
> The graphics power management features in SLPC are called GTPERF,
> BALANCER, and DCC.
> 1. GTPERF is a combination of DFPS (Dynamic FPS) and Turbo. DFPS adjusts
> requested graphics frequency to maintain target framerate. Turbo adjusts
> requested graphics frequency to maintain target GT busyness.
> 2. BALANCER adjusts balance between power budgets for IA and GT in power
> limited scenarios.
> 3. DCC (Duty Cycle Control) adjusts requested graphics frequency and stalls
> guc-scheduler to maintain actual graphics frequency in efficient range.
> 
> This series activates GTPERF Turbo and BALANCER in GuC SLPC.
> Patch to enable SLPC by default on platforms having support is removed
> from this series as there are following new changes to be added in future
> before we enable GuC/SLPC by default:
> 1. Link waitboost with SLPC.
> 2. Handle CPG as part of SLPC.
> 3. IA p-state logic update with GuC submission.
> 
> In order to enable CI/PnP testing of SLPC and to avoid frequent
> rebase, this series should be safe for merge with feature in disabled
> state.
> 
> v2: Addressed review comments on v1. Removed patch to enable SLPC by
>     default.
> 
> v3: Addressed WARNING in igt@drv_module_reload_basic flagged by trybot BAT.
>     Added change for sanitizing GT PM during reset. Added separate patch
>     for sysfs interface to know HW requested frequency. Also, earlier
>     patches did not go as series hence were not correctly picked up by BAT.
> 
> v4: Changes to multiple patches. CI BAT is passing. Performance run on SKL
>     GT2 done and shows perf at parity with Host Turbo. For BXT, SLPC
>     improves performance when GuC is enabled compared to Host Turbo.
>     This series keeps only support of 9.18 firmware for better readability.
>     If needed, other SLPC interfaces for different GuC version will be
>     added later.
> 
> v5: This series incorporates feedback from code reviews on earlier series
>     and adds following new changes:
> 	1. More changes for separation of RPS and RC6 handling for Gen9.
> 	2. Tied up SLPC enabling with GuC load/GuC submission sequence.
> 	3. SLPC structures are defined explicitly for event input/output.
> 	4. Definition of SLPC parameter control and task control functions
> 	   agnostic to the underlying param definitions as they might
> 	   change with GuC versions and prepared helpers for common tasks.
> 	5. Transition of i915 overrides done through host to guc events
> 	   to shared data and single reset event.
> 	6. Handling SLPC status post reset through shared memory.
> 	7. Derived helpers for setting frequency limits.
> 	8. Removed sysfs interface to know RPNSWREQ as it is available in
> 	   debugfs interface i915_frequency_info.
> 	9. Simple igt test to verify SLPC configuration by i915 in various
> 	   driver scenarios is prepared.
> 
> v6: This series adds following new changes:
> 	1. Updated intel_guc_send for SLPC to receive output data from GuC.
> 	2. Added task overrides and min frequency overrides in intel_slpc_init.
> 	   min frequency is set to Rpe.
> 	3. New debugfs interface added to set/unset/read SLPC parameters
> 	   other than tasks and frequencies. SLPC reset post parameter update
> 	   added.
> 	4. SLPC parameters persist as part of i915-GuC shared data hence not
> 	   overriding frequency limits while re-enabling SLPC.
> 	5. Other minor fixes to clear pm_rps_events, clflush the shared data.
> 
> v7: This series adds following new changes:
> 	1. Reordered patches. SLPC communication interfaces (structures and
> 	   functions) are pulled into patches earlier in the series.
> 	2. Eliminated dependency on i915.enable_slpc at various functions where
> 	   rps_enabled is available.
> 	3. s/i915_ggtt_offset/guc_ggtt_offset and sanitization of parameter
> 	   in intel_uc_sanitize_options.
> 
> v8: Activated Balancer. Changed prototype of SLPC functions to accept
>     struct intel_slpc as parameter instead of drm_i915_private.
> 
> VIZ-6889, VIZ-6890
> 
> Cc: Chris Wilson <chris@chris-wilson.co.uk>
> Cc: Daniel Vetter <daniel.vetter@intel.com>
> Cc: Beuchat, Marc <marc.beuchat@intel.com>
> Cc: Radoslaw Szwichtenberg <radoslaw.szwichtenberg@intel.com>
> Cc: Jeff McGee <jeff.mcgee@intel.com>
> Cc: Arkadiusz Hiler <arkadiusz.hiler@intel.com>
> Cc: Oscar Mateo <oscar.mateo@intel.com>
> Cc: Michał Winiarski <michal.winiarski@intel.com>

I did enable SLPC on my machine and looks like everything is working fine. I
will be spending more time reviewing whole series and also running some tests on
my KBL to see if there are no functional problems.

-Radek
Acked-by: Radoslaw Szwichtenberg <radoslaw.szwichtenberg@intel.com>
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Re: [PATCH 00/20] Add support for GuC-based SLPC

[Joonas Lahtinen]

On Tue, 2017-09-12 at 08:39 +0000, Szwichtenberg, Radoslaw wrote:
> On Fri, 2017-09-01 at 12:55 +0530, Sagar Arun Kamble wrote:
> > SLPC (Single Loop Power Controller) is a replacement for some host-based
> > power management features. The SLPC implementation runs in GuC firmware.
> > This series has been tested with SKL/APL/KBL GuC firmware v9 and v10
> > which are yet to be released on 01.org.
> > 
> > The graphics power management features in SLPC are called GTPERF,
> > BALANCER, and DCC.
> > 1. GTPERF is a combination of DFPS (Dynamic FPS) and Turbo. DFPS adjusts
> > requested graphics frequency to maintain target framerate. Turbo adjusts
> > requested graphics frequency to maintain target GT busyness.
> > 2. BALANCER adjusts balance between power budgets for IA and GT in power
> > limited scenarios.
> > 3. DCC (Duty Cycle Control) adjusts requested graphics frequency and stalls
> > guc-scheduler to maintain actual graphics frequency in efficient range.
> > 
> > This series activates GTPERF Turbo and BALANCER in GuC SLPC.
> > Patch to enable SLPC by default on platforms having support is removed
> > from this series as there are following new changes to be added in future
> > before we enable GuC/SLPC by default:
> > 1. Link waitboost with SLPC.
> > 2. Handle CPG as part of SLPC.
> > 3. IA p-state logic update with GuC submission.
> > 
> > In order to enable CI/PnP testing of SLPC and to avoid frequent
> > rebase, this series should be safe for merge with feature in disabled
> > state.
> > 
> > v2: Addressed review comments on v1. Removed patch to enable SLPC by
> >     default.
> > 
> > v3: Addressed WARNING in igt@drv_module_reload_basic flagged by trybot BAT.
> >     Added change for sanitizing GT PM during reset. Added separate patch
> >     for sysfs interface to know HW requested frequency. Also, earlier
> >     patches did not go as series hence were not correctly picked up by BAT.
> > 
> > v4: Changes to multiple patches. CI BAT is passing. Performance run on SKL
> >     GT2 done and shows perf at parity with Host Turbo. For BXT, SLPC
> >     improves performance when GuC is enabled compared to Host Turbo.
> >     This series keeps only support of 9.18 firmware for better readability.
> >     If needed, other SLPC interfaces for different GuC version will be
> >     added later.
> > 
> > v5: This series incorporates feedback from code reviews on earlier series
> >     and adds following new changes:
> > 	1. More changes for separation of RPS and RC6 handling for Gen9.
> > 	2. Tied up SLPC enabling with GuC load/GuC submission sequence.
> > 	3. SLPC structures are defined explicitly for event input/output.
> > 	4. Definition of SLPC parameter control and task control functions
> > 	   agnostic to the underlying param definitions as they might
> > 	   change with GuC versions and prepared helpers for common tasks.
> > 	5. Transition of i915 overrides done through host to guc events
> > 	   to shared data and single reset event.
> > 	6. Handling SLPC status post reset through shared memory.
> > 	7. Derived helpers for setting frequency limits.
> > 	8. Removed sysfs interface to know RPNSWREQ as it is available in
> > 	   debugfs interface i915_frequency_info.
> > 	9. Simple igt test to verify SLPC configuration by i915 in various
> > 	   driver scenarios is prepared.
> > 
> > v6: This series adds following new changes:
> > 	1. Updated intel_guc_send for SLPC to receive output data from GuC.
> > 	2. Added task overrides and min frequency overrides in intel_slpc_init.
> > 	   min frequency is set to Rpe.
> > 	3. New debugfs interface added to set/unset/read SLPC parameters
> > 	   other than tasks and frequencies. SLPC reset post parameter update
> > 	   added.
> > 	4. SLPC parameters persist as part of i915-GuC shared data hence not
> > 	   overriding frequency limits while re-enabling SLPC.
> > 	5. Other minor fixes to clear pm_rps_events, clflush the shared data.
> > 
> > v7: This series adds following new changes:
> > 	1. Reordered patches. SLPC communication interfaces (structures and
> > 	   functions) are pulled into patches earlier in the series.
> > 	2. Eliminated dependency on i915.enable_slpc at various functions where
> > 	   rps_enabled is available.
> > 	3. s/i915_ggtt_offset/guc_ggtt_offset and sanitization of parameter
> > 	   in intel_uc_sanitize_options.
> > 
> > v8: Activated Balancer. Changed prototype of SLPC functions to accept
> >     struct intel_slpc as parameter instead of drm_i915_private.
> > 
> > VIZ-6889, VIZ-6890
> > 
> > Cc: Chris Wilson <chris@chris-wilson.co.uk>
> > Cc: Daniel Vetter <daniel.vetter@intel.com>
> > Cc: Beuchat, Marc <marc.beuchat@intel.com>
> > Cc: Radoslaw Szwichtenberg <radoslaw.szwichtenberg@intel.com>
> > Cc: Jeff McGee <jeff.mcgee@intel.com>
> > Cc: Arkadiusz Hiler <arkadiusz.hiler@intel.com>
> > Cc: Oscar Mateo <oscar.mateo@intel.com>
> > Cc: Michał Winiarski <michal.winiarski@intel.com>
> 
> I did enable SLPC on my machine and looks like everything is working fine. I
> will be spending more time reviewing whole series and also running some tests on
> my KBL to see if there are no functional problems.

This would be more of a "Tested-by:" than "Acked-by:".

Regards, Joonas

> -Radek
> Acked-by: Radoslaw Szwichtenberg <radoslaw.szwichtenberg@intel.com>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
-- 
Joonas Lahtinen
Open Source Technology Center
Intel Corporation
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Re: [PATCH 00/20] Add support for GuC-based SLPC

[Kamble, Sagar A]

On 9/19/2017 4:00 PM, Joonas Lahtinen wrote:
> On Tue, 2017-09-12 at 08:39 +0000, Szwichtenberg, Radoslaw wrote:
>> On Fri, 2017-09-01 at 12:55 +0530, Sagar Arun Kamble wrote:
>>> SLPC (Single Loop Power Controller) is a replacement for some host-based
>>> power management features. The SLPC implementation runs in GuC firmware.
>>> This series has been tested with SKL/APL/KBL GuC firmware v9 and v10
>>> which are yet to be released on 01.org.
>>>
>>> The graphics power management features in SLPC are called GTPERF,
>>> BALANCER, and DCC.
>>> 1. GTPERF is a combination of DFPS (Dynamic FPS) and Turbo. DFPS adjusts
>>> requested graphics frequency to maintain target framerate. Turbo adjusts
>>> requested graphics frequency to maintain target GT busyness.
>>> 2. BALANCER adjusts balance between power budgets for IA and GT in power
>>> limited scenarios.
>>> 3. DCC (Duty Cycle Control) adjusts requested graphics frequency and stalls
>>> guc-scheduler to maintain actual graphics frequency in efficient range.
>>>
>>> This series activates GTPERF Turbo and BALANCER in GuC SLPC.
>>> Patch to enable SLPC by default on platforms having support is removed
>>> from this series as there are following new changes to be added in future
>>> before we enable GuC/SLPC by default:
>>> 1. Link waitboost with SLPC.
>>> 2. Handle CPG as part of SLPC.
>>> 3. IA p-state logic update with GuC submission.
>>>
>>> In order to enable CI/PnP testing of SLPC and to avoid frequent
>>> rebase, this series should be safe for merge with feature in disabled
>>> state.
>>>
>>> v2: Addressed review comments on v1. Removed patch to enable SLPC by
>>>      default.
>>>
>>> v3: Addressed WARNING in igt@drv_module_reload_basic flagged by trybot BAT.
>>>      Added change for sanitizing GT PM during reset. Added separate patch
>>>      for sysfs interface to know HW requested frequency. Also, earlier
>>>      patches did not go as series hence were not correctly picked up by BAT.
>>>
>>> v4: Changes to multiple patches. CI BAT is passing. Performance run on SKL
>>>      GT2 done and shows perf at parity with Host Turbo. For BXT, SLPC
>>>      improves performance when GuC is enabled compared to Host Turbo.
>>>      This series keeps only support of 9.18 firmware for better readability.
>>>      If needed, other SLPC interfaces for different GuC version will be
>>>      added later.
>>>
>>> v5: This series incorporates feedback from code reviews on earlier series
>>>      and adds following new changes:
>>> 	1. More changes for separation of RPS and RC6 handling for Gen9.
>>> 	2. Tied up SLPC enabling with GuC load/GuC submission sequence.
>>> 	3. SLPC structures are defined explicitly for event input/output.
>>> 	4. Definition of SLPC parameter control and task control functions
>>> 	   agnostic to the underlying param definitions as they might
>>> 	   change with GuC versions and prepared helpers for common tasks.
>>> 	5. Transition of i915 overrides done through host to guc events
>>> 	   to shared data and single reset event.
>>> 	6. Handling SLPC status post reset through shared memory.
>>> 	7. Derived helpers for setting frequency limits.
>>> 	8. Removed sysfs interface to know RPNSWREQ as it is available in
>>> 	   debugfs interface i915_frequency_info.
>>> 	9. Simple igt test to verify SLPC configuration by i915 in various
>>> 	   driver scenarios is prepared.
>>>
>>> v6: This series adds following new changes:
>>> 	1. Updated intel_guc_send for SLPC to receive output data from GuC.
>>> 	2. Added task overrides and min frequency overrides in intel_slpc_init.
>>> 	   min frequency is set to Rpe.
>>> 	3. New debugfs interface added to set/unset/read SLPC parameters
>>> 	   other than tasks and frequencies. SLPC reset post parameter update
>>> 	   added.
>>> 	4. SLPC parameters persist as part of i915-GuC shared data hence not
>>> 	   overriding frequency limits while re-enabling SLPC.
>>> 	5. Other minor fixes to clear pm_rps_events, clflush the shared data.
>>>
>>> v7: This series adds following new changes:
>>> 	1. Reordered patches. SLPC communication interfaces (structures and
>>> 	   functions) are pulled into patches earlier in the series.
>>> 	2. Eliminated dependency on i915.enable_slpc at various functions where
>>> 	   rps_enabled is available.
>>> 	3. s/i915_ggtt_offset/guc_ggtt_offset and sanitization of parameter
>>> 	   in intel_uc_sanitize_options.
>>>
>>> v8: Activated Balancer. Changed prototype of SLPC functions to accept
>>>      struct intel_slpc as parameter instead of drm_i915_private.
>>>
>>> VIZ-6889, VIZ-6890
>>>
>>> Cc: Chris Wilson <chris@chris-wilson.co.uk>
>>> Cc: Daniel Vetter <daniel.vetter@intel.com>
>>> Cc: Beuchat, Marc <marc.beuchat@intel.com>
>>> Cc: Radoslaw Szwichtenberg <radoslaw.szwichtenberg@intel.com>
>>> Cc: Jeff McGee <jeff.mcgee@intel.com>
>>> Cc: Arkadiusz Hiler <arkadiusz.hiler@intel.com>
>>> Cc: Oscar Mateo <oscar.mateo@intel.com>
>>> Cc: Michał Winiarski <michal.winiarski@intel.com>
>> I did enable SLPC on my machine and looks like everything is working fine. I
>> will be spending more time reviewing whole series and also running some tests on
>> my KBL to see if there are no functional problems.
> This would be more of a "Tested-by:" than "Acked-by:".
>
> Regards, Joonas
Thanks Radek, Joonas.
Will update this in the next series.
>
>> -Radek
>> Acked-by: Radoslaw Szwichtenberg <radoslaw.szwichtenberg@intel.com>
>> _______________________________________________
>> Intel-gfx mailing list
>> Intel-gfx@lists.freedesktop.org
>> https://lists.freedesktop.org/mailman/listinfo/intel-gfx

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