[PATCH] drm/i915: Disable DMC powersaving during GT operations

[PATCH] drm/i915: Disable DMC powersaving during GT operations

[Chris Wilson]

The DMC typifies the worst example of firmware: it overrides system
behaviour and is fubar. When no displays are active, the DMC appears to
continually toggle its control register trying to change display power
states. This in turn has the side effect of slowing down the GT by a few
orders of magntidue, making headless operations intolerably slow.

This seems to affect all machines with dmc (so a byproduct of the dmc
code itself being shared) and severely limits throughput on the CI bxt
and triggers the watchdog for incomplete tests.

Altenative suggestion is to blacklist all DMC firmware until it is
fixed.

References: https://bugs.freedesktop.org/show_bug.cgi?id=100572
Testcase: igt/gem_exec_nop/headless
Suggested-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Cc: Imre Deak <imre.deak@intel.com>
---
 drivers/gpu/drm/i915/i915_gem.c         | 3 +++
 drivers/gpu/drm/i915/i915_gem_request.c | 3 +++
 2 files changed, 6 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index ba72a4bdaa78..e3236c1d44f0 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -3331,6 +3331,9 @@ i915_gem_idle_work_handler(struct work_struct *work)
 	intel_engines_mark_idle(dev_priv);
 	i915_gem_timelines_mark_idle(dev_priv);
 
+	if (dev_priv->csr.dmc_payload)
+		intel_display_power_put(dev_priv, POWER_DOMAIN_MODESET);
+
 	GEM_BUG_ON(!dev_priv->gt.awake);
 	dev_priv->gt.awake = false;
 	rearm_hangcheck = false;
diff --git a/drivers/gpu/drm/i915/i915_gem_request.c b/drivers/gpu/drm/i915/i915_gem_request.c
index 813a3b546d6e..3c8ebdb5b0b4 100644
--- a/drivers/gpu/drm/i915/i915_gem_request.c
+++ b/drivers/gpu/drm/i915/i915_gem_request.c
@@ -254,6 +254,9 @@ static void mark_busy(struct drm_i915_private *i915)
 	intel_runtime_pm_get_noresume(i915);
 	i915->gt.awake = true;
 
+	if (i915->csr.dmc_payload)
+		intel_display_power_get(i915, POWER_DOMAIN_MODESET);
+
 	intel_enable_gt_powersave(i915);
 	i915_update_gfx_val(i915);
 	if (INTEL_GEN(i915) >= 6)
-- 
2.14.1

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Re: [PATCH] drm/i915: Disable DMC powersaving during GT operations

[Tvrtko Ursulin]

On 12/09/2017 13:37, Chris Wilson wrote:
> The DMC typifies the worst example of firmware: it overrides system
> behaviour and is fubar. When no displays are active, the DMC appears to
> continually toggle its control register trying to change display power
> states. This in turn has the side effect of slowing down the GT by a few
> orders of magntidue, making headless operations intolerably slow.
> 
> This seems to affect all machines with dmc (so a byproduct of the dmc
> code itself being shared) and severely limits throughput on the CI bxt
> and triggers the watchdog for incomplete tests.
> 
> Altenative suggestion is to blacklist all DMC firmware until it is
> fixed.

I've sent this as https://patchwork.freedesktop.org/patch/154942/ some 
time ago. You asked for a long code comment back then. :)

Anyway, I don't mind we merge one of the two since it is taking an 
eternity to get this fixes in the firmware. So:

Reviewed-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>

Regards,

Tvrtko

> References: https://bugs.freedesktop.org/show_bug.cgi?id=100572
> Testcase: igt/gem_exec_nop/headless
> Suggested-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
> Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
> Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
> Cc: Imre Deak <imre.deak@intel.com>
> ---
>   drivers/gpu/drm/i915/i915_gem.c         | 3 +++
>   drivers/gpu/drm/i915/i915_gem_request.c | 3 +++
>   2 files changed, 6 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
> index ba72a4bdaa78..e3236c1d44f0 100644
> --- a/drivers/gpu/drm/i915/i915_gem.c
> +++ b/drivers/gpu/drm/i915/i915_gem.c
> @@ -3331,6 +3331,9 @@ i915_gem_idle_work_handler(struct work_struct *work)
>   	intel_engines_mark_idle(dev_priv);
>   	i915_gem_timelines_mark_idle(dev_priv);
>   
> +	if (dev_priv->csr.dmc_payload)
> +		intel_display_power_put(dev_priv, POWER_DOMAIN_MODESET);
> +
>   	GEM_BUG_ON(!dev_priv->gt.awake);
>   	dev_priv->gt.awake = false;
>   	rearm_hangcheck = false;
> diff --git a/drivers/gpu/drm/i915/i915_gem_request.c b/drivers/gpu/drm/i915/i915_gem_request.c
> index 813a3b546d6e..3c8ebdb5b0b4 100644
> --- a/drivers/gpu/drm/i915/i915_gem_request.c
> +++ b/drivers/gpu/drm/i915/i915_gem_request.c
> @@ -254,6 +254,9 @@ static void mark_busy(struct drm_i915_private *i915)
>   	intel_runtime_pm_get_noresume(i915);
>   	i915->gt.awake = true;
>   
> +	if (i915->csr.dmc_payload)
> +		intel_display_power_get(i915, POWER_DOMAIN_MODESET);
> +
>   	intel_enable_gt_powersave(i915);
>   	i915_update_gfx_val(i915);
>   	if (INTEL_GEN(i915) >= 6)
> 
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Re: [PATCH] drm/i915: Disable DMC powersaving during GT operations

[Chris Wilson]

Quoting Chris Wilson (2017-09-12 13:37:32)
> diff --git a/drivers/gpu/drm/i915/i915_gem_request.c b/drivers/gpu/drm/i915/i915_gem_request.c
> index 813a3b546d6e..3c8ebdb5b0b4 100644
> --- a/drivers/gpu/drm/i915/i915_gem_request.c
> +++ b/drivers/gpu/drm/i915/i915_gem_request.c
> @@ -254,6 +254,9 @@ static void mark_busy(struct drm_i915_private *i915)
>         intel_runtime_pm_get_noresume(i915);
>         i915->gt.awake = true;
>  

/*
 * The DMC doesn't behave well when it is active (i.e the system is
 * idle). It continually tries to toggle DC_STATE_EN causing a
 * severe slow down of the rest of the system (severe enough to trigger
 * watchdogs and reboot the machine under CI testing).
 *
 * Known affected firmware:
 * - skl_dmc_ver1_26.bin
 * - bxt_dmc_ver1_07.bin
 */
> +       if (i915->csr.dmc_payload)
> +               intel_display_power_get(i915, POWER_DOMAIN_MODESET);
> +
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Re: [PATCH] drm/i915: Disable DMC powersaving during GT operations

[Tvrtko Ursulin]

On 12/09/2017 13:45, Tvrtko Ursulin wrote:
> 
> On 12/09/2017 13:37, Chris Wilson wrote:
>> The DMC typifies the worst example of firmware: it overrides system
>> behaviour and is fubar. When no displays are active, the DMC appears to
>> continually toggle its control register trying to change display power
>> states. This in turn has the side effect of slowing down the GT by a few
>> orders of magntidue, making headless operations intolerably slow.
>>
>> This seems to affect all machines with dmc (so a byproduct of the dmc
>> code itself being shared) and severely limits throughput on the CI bxt
>> and triggers the watchdog for incomplete tests.
>>
>> Altenative suggestion is to blacklist all DMC firmware until it is
>> fixed.
> 
> I've sent this as https://patchwork.freedesktop.org/patch/154942/ some 
> time ago. You asked for a long code comment back then. :)
> 
> Anyway, I don't mind we merge one of the two since it is taking an 
> eternity to get this fixes in the firmware. So:
> 
> Reviewed-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>

I take it back, there was a reason in shape of another firmware bug 
which made us put this patch on hold. Imre might know the status of that 
one.

Regards,

Tvrtko
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✓ Fi.CI.BAT: success for drm/i915: Disable DMC powersaving during GT operations

[Patchwork]

== Series Details ==

Series: drm/i915: Disable DMC powersaving during GT operations
URL   : https://patchwork.freedesktop.org/series/30196/
State : success

== Summary ==

Series 30196v1 drm/i915: Disable DMC powersaving during GT operations
https://patchwork.freedesktop.org/api/1.0/series/30196/revisions/1/mbox/

Test chamelium:
        Subgroup dp-crc-fast:
                fail       -> PASS       (fi-kbl-7500u) fdo#102514

fdo#102514 https://bugs.freedesktop.org/show_bug.cgi?id=102514

fi-bdw-5557u     total:289  pass:268  dwarn:0   dfail:0   fail:0   skip:21  time:449s
fi-bdw-gvtdvm    total:289  pass:265  dwarn:0   dfail:0   fail:0   skip:24  time:457s
fi-blb-e6850     total:289  pass:224  dwarn:1   dfail:0   fail:0   skip:64  time:384s
fi-bsw-n3050     total:289  pass:243  dwarn:0   dfail:0   fail:0   skip:46  time:546s
fi-bwr-2160      total:289  pass:184  dwarn:0   dfail:0   fail:0   skip:105 time:268s
fi-bxt-j4205     total:289  pass:260  dwarn:0   dfail:0   fail:0   skip:29  time:512s
fi-byt-j1900     total:289  pass:254  dwarn:1   dfail:0   fail:0   skip:34  time:506s
fi-byt-n2820     total:289  pass:250  dwarn:1   dfail:0   fail:0   skip:38  time:506s
fi-cfl-s         total:289  pass:250  dwarn:4   dfail:0   fail:0   skip:35  time:459s
fi-elk-e7500     total:289  pass:230  dwarn:0   dfail:0   fail:0   skip:59  time:460s
fi-glk-2a        total:289  pass:260  dwarn:0   dfail:0   fail:0   skip:29  time:600s
fi-hsw-4770      total:289  pass:263  dwarn:0   dfail:0   fail:0   skip:26  time:430s
fi-hsw-4770r     total:289  pass:263  dwarn:0   dfail:0   fail:0   skip:26  time:414s
fi-ilk-650       total:289  pass:229  dwarn:0   dfail:0   fail:0   skip:60  time:438s
fi-ivb-3520m     total:289  pass:261  dwarn:0   dfail:0   fail:0   skip:28  time:494s
fi-ivb-3770      total:289  pass:261  dwarn:0   dfail:0   fail:0   skip:28  time:466s
fi-kbl-7500u     total:289  pass:264  dwarn:1   dfail:0   fail:0   skip:24  time:492s
fi-kbl-7560u     total:289  pass:270  dwarn:0   dfail:0   fail:0   skip:19  time:583s
fi-kbl-r         total:289  pass:262  dwarn:0   dfail:0   fail:0   skip:27  time:590s
fi-pnv-d510      total:289  pass:223  dwarn:1   dfail:0   fail:0   skip:65  time:550s
fi-skl-6260u     total:289  pass:269  dwarn:0   dfail:0   fail:0   skip:20  time:464s
fi-skl-6700k     total:289  pass:265  dwarn:0   dfail:0   fail:0   skip:24  time:524s
fi-skl-6770hq    total:289  pass:269  dwarn:0   dfail:0   fail:0   skip:20  time:507s
fi-skl-gvtdvm    total:289  pass:266  dwarn:0   dfail:0   fail:0   skip:23  time:465s
fi-skl-x1585l    total:289  pass:268  dwarn:0   dfail:0   fail:0   skip:21  time:480s
fi-snb-2520m     total:289  pass:251  dwarn:0   dfail:0   fail:0   skip:38  time:575s
fi-snb-2600      total:289  pass:250  dwarn:0   dfail:0   fail:0   skip:39  time:427s

694f07d3df18c02da3f526ae0e1238eb12534e1e drm-tip: 2017y-09m-12d-09h-59m-00s UTC integration manifest
64ca6b9d82b4 drm/i915: Disable DMC powersaving during GT operations

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_5656/
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✗ Fi.CI.IGT: warning for drm/i915: Disable DMC powersaving during GT operations

[Patchwork]

== Series Details ==

Series: drm/i915: Disable DMC powersaving during GT operations
URL   : https://patchwork.freedesktop.org/series/30196/
State : warning

== Summary ==

Test perf:
        Subgroup blocking:
                pass       -> FAIL       (shard-hsw) fdo#102252 +1
Test kms_flip:
        Subgroup wf_vblank-vs-modeset:
                pass       -> DMESG-WARN (shard-hsw)
Test kms_setmode:
        Subgroup basic:
                pass       -> FAIL       (shard-hsw) fdo#99912

fdo#102252 https://bugs.freedesktop.org/show_bug.cgi?id=102252
fdo#99912 https://bugs.freedesktop.org/show_bug.cgi?id=99912

shard-hsw        total:2301 pass:1234 dwarn:1   dfail:0   fail:14  skip:1052 time:9381s

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_5656/shards.html
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Re: [PATCH] drm/i915: Disable DMC powersaving during GT operations

[Imre Deak]

On Tue, Sep 12, 2017 at 01:57:07PM +0100, Tvrtko Ursulin wrote:
> 
> On 12/09/2017 13:45, Tvrtko Ursulin wrote:
> > 
> > On 12/09/2017 13:37, Chris Wilson wrote:
> > > The DMC typifies the worst example of firmware: it overrides system
> > > behaviour and is fubar. When no displays are active, the DMC appears to
> > > continually toggle its control register trying to change display power
> > > states. This in turn has the side effect of slowing down the GT by a few
> > > orders of magntidue, making headless operations intolerably slow.
> > > 
> > > This seems to affect all machines with dmc (so a byproduct of the dmc
> > > code itself being shared) and severely limits throughput on the CI bxt
> > > and triggers the watchdog for incomplete tests.
> > > 
> > > Altenative suggestion is to blacklist all DMC firmware until it is
> > > fixed.
> > 
> > I've sent this as https://patchwork.freedesktop.org/patch/154942/ some
> > time ago. You asked for a long code comment back then. :)
> > 
> > Anyway, I don't mind we merge one of the two since it is taking an
> > eternity to get this fixes in the firmware. So:
> > 
> > Reviewed-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
> 
> I take it back, there was a reason in shape of another firmware bug which
> made us put this patch on hold. Imre might know the status of that one.

Yes, there is a corruption of registes in the context saved/restored during
DC3->DC6 transitions. I have a test case which easily triggers this, but
I was asked to produce an internal trace in addition. To set up that
took me quite a while, but I got the trace now and the firwmare team is
checking it. Let's see if it includes everything they hope to see.

So ideally we'd wait with your W/A - which still is the correct thing -
until the corruption thing is fixed.

--Imre


> 
> Regards,
> 
> Tvrtko
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Re: [PATCH] drm/i915: Disable DMC powersaving during GT operations

[Joonas Lahtinen]

+ Jari & Samu

On Tue, 2017-09-12 at 13:48 +0100, Chris Wilson wrote:
> Quoting Chris Wilson (2017-09-12 13:37:32)
> > diff --git a/drivers/gpu/drm/i915/i915_gem_request.c b/drivers/gpu/drm/i915/i915_gem_request.c
> > index 813a3b546d6e..3c8ebdb5b0b4 100644
> > --- a/drivers/gpu/drm/i915/i915_gem_request.c
> > +++ b/drivers/gpu/drm/i915/i915_gem_request.c
> > @@ -254,6 +254,9 @@ static void mark_busy(struct drm_i915_private *i915)
> >         intel_runtime_pm_get_noresume(i915);
> >         i915->gt.awake = true;
> >  
> 
> /*
>  * The DMC doesn't behave well when it is active (i.e the system is
>  * idle). It continually tries to toggle DC_STATE_EN causing a
>  * severe slow down of the rest of the system (severe enough to trigger
>  * watchdogs and reboot the machine under CI testing).
>  *
>  * Known affected firmware:
>  * - skl_dmc_ver1_26.bin
>  * - bxt_dmc_ver1_07.bin
>  */

Has this patch been tested more widely, does it have negative
performance effects?

Regards, Joonas

> > +       if (i915->csr.dmc_payload)
> > +               intel_display_power_get(i915, POWER_DOMAIN_MODESET);
> > +
-- 
Joonas Lahtinen
Open Source Technology Center
Intel Corporation
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Re: [PATCH] drm/i915: Disable DMC powersaving during GT operations

[Tahvanainen, Jari]

Hello,

+Ricardo related to testing done by GFX QA.

Br, Jari

-----Original Message-----
From: Joonas Lahtinen [mailto:joonas.lahtinen@linux.intel.com] 
Sent: Monday, September 18, 2017 4:41 PM
To: Chris Wilson <chris@chris-wilson.co.uk>; intel-gfx@lists.freedesktop.org
Cc: Ursulin, Tvrtko <tvrtko.ursulin@intel.com>; Deak, Imre <imre.deak@intel.com>; Tahvanainen, Jari <jari.tahvanainen@intel.com>; Kaajas, Samu <samu.kaajas@intel.com>
Subject: Re: [PATCH] drm/i915: Disable DMC powersaving during GT operations

+ Jari & Samu

On Tue, 2017-09-12 at 13:48 +0100, Chris Wilson wrote:
> Quoting Chris Wilson (2017-09-12 13:37:32)
> > diff --git a/drivers/gpu/drm/i915/i915_gem_request.c 
> > b/drivers/gpu/drm/i915/i915_gem_request.c
> > index 813a3b546d6e..3c8ebdb5b0b4 100644
> > --- a/drivers/gpu/drm/i915/i915_gem_request.c
> > +++ b/drivers/gpu/drm/i915/i915_gem_request.c
> > @@ -254,6 +254,9 @@ static void mark_busy(struct drm_i915_private *i915)
> >         intel_runtime_pm_get_noresume(i915);
> >         i915->gt.awake = true;
> >  
> 
> /*
>  * The DMC doesn't behave well when it is active (i.e the system is
>  * idle). It continually tries to toggle DC_STATE_EN causing a
>  * severe slow down of the rest of the system (severe enough to 
> trigger
>  * watchdogs and reboot the machine under CI testing).
>  *
>  * Known affected firmware:
>  * - skl_dmc_ver1_26.bin
>  * - bxt_dmc_ver1_07.bin
>  */

Has this patch been tested more widely, does it have negative performance effects?

Regards, Joonas

> > +       if (i915->csr.dmc_payload)
> > +               intel_display_power_get(i915, POWER_DOMAIN_MODESET);
> > +
--
Joonas Lahtinen
Open Source Technology Center
Intel Corporation
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