* [PATCH 0/2] Add missing BXT/CNL DPLL debugging/checking code
@ 2017-09-22 20:53 Paulo Zanoni
2017-09-22 20:53 ` [PATCH 1/2] drm/i915: add the BXT and CNL DPLL registers to pipe_config_compare Paulo Zanoni
` (4 more replies)
0 siblings, 5 replies; 9+ messages in thread
From: Paulo Zanoni @ 2017-09-22 20:53 UTC (permalink / raw)
To: intel-gfx; +Cc: Paulo Zanoni
These 2 patches just add the missing struct fields to the relevant parts of the
code. Future patches could probably break those structs into per-platform struct
inside an unions or something like that, but let's get this part done first.
Paulo Zanoni (2):
drm/i915: add the BXT and CNL DPLL registers to pipe_config_compare
drm/i915: add missing DPLL fields to i915_shared_dplls_info
drivers/gpu/drm/i915/i915_debugfs.c | 16 ++++++++++++++++
drivers/gpu/drm/i915/intel_display.c | 12 ++++++++++++
2 files changed, 28 insertions(+)
--
2.9.5
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 9+ messages in thread
* [PATCH 1/2] drm/i915: add the BXT and CNL DPLL registers to pipe_config_compare
2017-09-22 20:53 [PATCH 0/2] Add missing BXT/CNL DPLL debugging/checking code Paulo Zanoni
@ 2017-09-22 20:53 ` Paulo Zanoni
2017-09-25 23:16 ` Rodrigo Vivi
2017-09-22 20:53 ` [PATCH 2/2] drm/i915: add missing DPLL fields to i915_shared_dplls_info Paulo Zanoni
` (3 subsequent siblings)
4 siblings, 1 reply; 9+ messages in thread
From: Paulo Zanoni @ 2017-09-22 20:53 UTC (permalink / raw)
To: intel-gfx; +Cc: Paulo Zanoni
Looks like we were missing them.
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
---
drivers/gpu/drm/i915/intel_display.c | 12 ++++++++++++
1 file changed, 12 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 026fa54..64a4105 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -11336,6 +11336,18 @@ intel_pipe_config_compare(struct drm_i915_private *dev_priv,
PIPE_CONF_CHECK_X(dpll_hw_state.ctrl1);
PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr1);
PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr2);
+ PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr0);
+ PIPE_CONF_CHECK_X(dpll_hw_state.ebb0);
+ PIPE_CONF_CHECK_X(dpll_hw_state.ebb4);
+ PIPE_CONF_CHECK_X(dpll_hw_state.pll0);
+ PIPE_CONF_CHECK_X(dpll_hw_state.pll1);
+ PIPE_CONF_CHECK_X(dpll_hw_state.pll2);
+ PIPE_CONF_CHECK_X(dpll_hw_state.pll3);
+ PIPE_CONF_CHECK_X(dpll_hw_state.pll6);
+ PIPE_CONF_CHECK_X(dpll_hw_state.pll8);
+ PIPE_CONF_CHECK_X(dpll_hw_state.pll9);
+ PIPE_CONF_CHECK_X(dpll_hw_state.pll10);
+ PIPE_CONF_CHECK_X(dpll_hw_state.pcsdw12);
PIPE_CONF_CHECK_X(dsi_pll.ctrl);
PIPE_CONF_CHECK_X(dsi_pll.div);
--
2.9.5
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 9+ messages in thread
* [PATCH 2/2] drm/i915: add missing DPLL fields to i915_shared_dplls_info
2017-09-22 20:53 [PATCH 0/2] Add missing BXT/CNL DPLL debugging/checking code Paulo Zanoni
2017-09-22 20:53 ` [PATCH 1/2] drm/i915: add the BXT and CNL DPLL registers to pipe_config_compare Paulo Zanoni
@ 2017-09-22 20:53 ` Paulo Zanoni
2017-09-25 23:21 ` Rodrigo Vivi
2017-09-22 21:23 ` ✗ Fi.CI.BAT: failure for Add missing BXT/CNL DPLL debugging/checking code Patchwork
` (2 subsequent siblings)
4 siblings, 1 reply; 9+ messages in thread
From: Paulo Zanoni @ 2017-09-22 20:53 UTC (permalink / raw)
To: intel-gfx; +Cc: Paulo Zanoni
Looks like we've been forgetting to add these since a long time ago.
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
---
drivers/gpu/drm/i915/i915_debugfs.c | 16 ++++++++++++++++
1 file changed, 16 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
index 13fc259..2b2faa6 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -3481,6 +3481,22 @@ static int i915_shared_dplls_info(struct seq_file *m, void *unused)
seq_printf(m, " fp0: 0x%08x\n", pll->state.hw_state.fp0);
seq_printf(m, " fp1: 0x%08x\n", pll->state.hw_state.fp1);
seq_printf(m, " wrpll: 0x%08x\n", pll->state.hw_state.wrpll);
+ seq_printf(m, " spll: 0x%08x\n", pll->state.hw_state.spll);
+ seq_printf(m, " ctrl1: 0x%08x\n", pll->state.hw_state.ctrl1);
+ seq_printf(m, " cfgcr1: 0x%08x\n", pll->state.hw_state.cfgcr1);
+ seq_printf(m, " cfgcr2: 0x%08x\n", pll->state.hw_state.cfgcr2);
+ seq_printf(m, " cfgcr0: 0x%08x\n", pll->state.hw_state.cfgcr0);
+ seq_printf(m, " ebb0: 0x%08x\n", pll->state.hw_state.ebb0);
+ seq_printf(m, " ebb4: 0x%08x\n", pll->state.hw_state.ebb4);
+ seq_printf(m, " pll0: 0x%08x\n", pll->state.hw_state.pll0);
+ seq_printf(m, " pll1: 0x%08x\n", pll->state.hw_state.pll1);
+ seq_printf(m, " pll2: 0x%08x\n", pll->state.hw_state.pll2);
+ seq_printf(m, " pll3: 0x%08x\n", pll->state.hw_state.pll3);
+ seq_printf(m, " pll6: 0x%08x\n", pll->state.hw_state.pll6);
+ seq_printf(m, " pll8: 0x%08x\n", pll->state.hw_state.pll8);
+ seq_printf(m, " pll9: 0x%08x\n", pll->state.hw_state.pll9);
+ seq_printf(m, " pll10: 0x%08x\n", pll->state.hw_state.pll10);
+ seq_printf(m, " pcsdw12: 0x%08x\n", pll->state.hw_state.pcsdw12);
}
drm_modeset_unlock_all(dev);
--
2.9.5
_______________________________________________
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 9+ messages in thread
* ✗ Fi.CI.BAT: failure for Add missing BXT/CNL DPLL debugging/checking code
2017-09-22 20:53 [PATCH 0/2] Add missing BXT/CNL DPLL debugging/checking code Paulo Zanoni
2017-09-22 20:53 ` [PATCH 1/2] drm/i915: add the BXT and CNL DPLL registers to pipe_config_compare Paulo Zanoni
2017-09-22 20:53 ` [PATCH 2/2] drm/i915: add missing DPLL fields to i915_shared_dplls_info Paulo Zanoni
@ 2017-09-22 21:23 ` Patchwork
2017-09-23 8:05 ` ✓ Fi.CI.BAT: success " Patchwork
2017-09-23 9:19 ` ✓ Fi.CI.IGT: " Patchwork
4 siblings, 0 replies; 9+ messages in thread
From: Patchwork @ 2017-09-22 21:23 UTC (permalink / raw)
To: Paulo Zanoni; +Cc: intel-gfx
== Series Details ==
Series: Add missing BXT/CNL DPLL debugging/checking code
URL : https://patchwork.freedesktop.org/series/30790/
State : failure
== Summary ==
Series 30790v1 Add missing BXT/CNL DPLL debugging/checking code
https://patchwork.freedesktop.org/api/1.0/series/30790/revisions/1/mbox/
Test gem_exec_suspend:
Subgroup basic-s3:
pass -> INCOMPLETE (fi-kbl-7500u) fdo#102850
Test kms_pipe_crc_basic:
Subgroup nonblocking-crc-pipe-b-frame-sequence:
dmesg-warn -> DMESG-FAIL (fi-cfl-s) fdo#102294
Subgroup nonblocking-crc-pipe-c:
skip -> INCOMPLETE (fi-cfl-s)
Test drv_module_reload:
Subgroup basic-no-display:
dmesg-warn -> PASS (fi-glk-1) fdo#102777
fdo#102850 https://bugs.freedesktop.org/show_bug.cgi?id=102850
fdo#102294 https://bugs.freedesktop.org/show_bug.cgi?id=102294
fdo#102777 https://bugs.freedesktop.org/show_bug.cgi?id=102777
fi-bdw-5557u total:289 pass:268 dwarn:0 dfail:0 fail:0 skip:21 time:440s
fi-bdw-gvtdvm total:289 pass:265 dwarn:0 dfail:0 fail:0 skip:24 time:476s
fi-blb-e6850 total:289 pass:224 dwarn:1 dfail:0 fail:0 skip:64 time:416s
fi-bsw-n3050 total:289 pass:243 dwarn:0 dfail:0 fail:0 skip:46 time:522s
fi-bwr-2160 total:289 pass:184 dwarn:0 dfail:0 fail:0 skip:105 time:280s
fi-bxt-j4205 total:289 pass:260 dwarn:0 dfail:0 fail:0 skip:29 time:496s
fi-byt-j1900 total:289 pass:254 dwarn:1 dfail:0 fail:0 skip:34 time:493s
fi-byt-n2820 total:289 pass:250 dwarn:1 dfail:0 fail:0 skip:38 time:492s
fi-cfl-s total:237 pass:188 dwarn:21 dfail:1 fail:0 skip:26
fi-elk-e7500 total:289 pass:230 dwarn:0 dfail:0 fail:0 skip:59 time:421s
fi-glk-1 total:289 pass:260 dwarn:0 dfail:0 fail:0 skip:29 time:565s
fi-hsw-4770 total:289 pass:263 dwarn:0 dfail:0 fail:0 skip:26 time:423s
fi-hsw-4770r total:289 pass:263 dwarn:0 dfail:0 fail:0 skip:26 time:402s
fi-ilk-650 total:289 pass:229 dwarn:0 dfail:0 fail:0 skip:60 time:429s
fi-ivb-3520m total:289 pass:261 dwarn:0 dfail:0 fail:0 skip:28 time:480s
fi-ivb-3770 total:289 pass:261 dwarn:0 dfail:0 fail:0 skip:28 time:460s
fi-kbl-7500u total:118 pass:100 dwarn:1 dfail:0 fail:0 skip:16
fi-kbl-7560u total:289 pass:270 dwarn:0 dfail:0 fail:0 skip:19 time:577s
fi-kbl-r total:289 pass:262 dwarn:0 dfail:0 fail:0 skip:27 time:585s
fi-pnv-d510 total:289 pass:223 dwarn:1 dfail:0 fail:0 skip:65 time:539s
fi-skl-6260u total:289 pass:269 dwarn:0 dfail:0 fail:0 skip:20 time:453s
fi-skl-6700k total:289 pass:265 dwarn:0 dfail:0 fail:0 skip:24 time:752s
fi-skl-6770hq total:289 pass:269 dwarn:0 dfail:0 fail:0 skip:20 time:489s
fi-snb-2520m total:289 pass:251 dwarn:0 dfail:0 fail:0 skip:38 time:573s
fi-snb-2600 total:289 pass:249 dwarn:0 dfail:0 fail:1 skip:39 time:419s
fi-skl-gvtdvm failed to connect after reboot
e0e308721fd283e1c5777657a5941f178f0d49e6 drm-tip: 2017y-09m-22d-13h-31m-38s UTC integration manifest
23ab30003948 drm/i915: add missing DPLL fields to i915_shared_dplls_info
bcc58581aa9e drm/i915: add the BXT and CNL DPLL registers to pipe_config_compare
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_5797/
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 9+ messages in thread
* ✓ Fi.CI.BAT: success for Add missing BXT/CNL DPLL debugging/checking code
2017-09-22 20:53 [PATCH 0/2] Add missing BXT/CNL DPLL debugging/checking code Paulo Zanoni
` (2 preceding siblings ...)
2017-09-22 21:23 ` ✗ Fi.CI.BAT: failure for Add missing BXT/CNL DPLL debugging/checking code Patchwork
@ 2017-09-23 8:05 ` Patchwork
2017-09-23 9:19 ` ✓ Fi.CI.IGT: " Patchwork
4 siblings, 0 replies; 9+ messages in thread
From: Patchwork @ 2017-09-23 8:05 UTC (permalink / raw)
To: Paulo Zanoni; +Cc: intel-gfx
== Series Details ==
Series: Add missing BXT/CNL DPLL debugging/checking code
URL : https://patchwork.freedesktop.org/series/30790/
State : success
== Summary ==
Series 30790v1 Add missing BXT/CNL DPLL debugging/checking code
https://patchwork.freedesktop.org/api/1.0/series/30790/revisions/1/mbox/
Test kms_pipe_crc_basic:
Subgroup suspend-read-crc-pipe-a:
incomplete -> PASS (fi-kbl-7500u) fdo#102850
Test pm_rpm:
Subgroup basic-rte:
dmesg-warn -> PASS (fi-cfl-s) fdo#102294
Test drv_module_reload:
Subgroup basic-reload:
pass -> DMESG-WARN (fi-glk-1) fdo#102777
Subgroup basic-reload-inject:
dmesg-warn -> INCOMPLETE (fi-cfl-s) k.org#196765
fdo#102850 https://bugs.freedesktop.org/show_bug.cgi?id=102850
fdo#102294 https://bugs.freedesktop.org/show_bug.cgi?id=102294
fdo#102777 https://bugs.freedesktop.org/show_bug.cgi?id=102777
k.org#196765 https://bugzilla.kernel.org/show_bug.cgi?id=196765
fi-bdw-5557u total:289 pass:268 dwarn:0 dfail:0 fail:0 skip:21 time:438s
fi-bdw-gvtdvm total:289 pass:265 dwarn:0 dfail:0 fail:0 skip:24 time:477s
fi-blb-e6850 total:289 pass:224 dwarn:1 dfail:0 fail:0 skip:64 time:412s
fi-bsw-n3050 total:289 pass:243 dwarn:0 dfail:0 fail:0 skip:46 time:511s
fi-bwr-2160 total:289 pass:184 dwarn:0 dfail:0 fail:0 skip:105 time:276s
fi-bxt-j4205 total:289 pass:260 dwarn:0 dfail:0 fail:0 skip:29 time:506s
fi-byt-j1900 total:289 pass:254 dwarn:1 dfail:0 fail:0 skip:34 time:490s
fi-byt-n2820 total:289 pass:250 dwarn:1 dfail:0 fail:0 skip:38 time:496s
fi-cfl-s total:288 pass:223 dwarn:33 dfail:0 fail:0 skip:31
fi-elk-e7500 total:289 pass:230 dwarn:0 dfail:0 fail:0 skip:59 time:420s
fi-glk-1 total:289 pass:259 dwarn:1 dfail:0 fail:0 skip:29 time:569s
fi-hsw-4770 total:289 pass:263 dwarn:0 dfail:0 fail:0 skip:26 time:421s
fi-hsw-4770r total:289 pass:263 dwarn:0 dfail:0 fail:0 skip:26 time:402s
fi-ilk-650 total:289 pass:229 dwarn:0 dfail:0 fail:0 skip:60 time:431s
fi-ivb-3520m total:289 pass:261 dwarn:0 dfail:0 fail:0 skip:28 time:487s
fi-ivb-3770 total:289 pass:261 dwarn:0 dfail:0 fail:0 skip:28 time:468s
fi-kbl-7500u total:289 pass:264 dwarn:1 dfail:0 fail:0 skip:24 time:468s
fi-kbl-7560u total:289 pass:270 dwarn:0 dfail:0 fail:0 skip:19 time:564s
fi-kbl-r total:289 pass:262 dwarn:0 dfail:0 fail:0 skip:27 time:592s
fi-pnv-d510 total:289 pass:223 dwarn:1 dfail:0 fail:0 skip:65 time:538s
fi-skl-6260u total:289 pass:269 dwarn:0 dfail:0 fail:0 skip:20 time:454s
fi-skl-6700k total:289 pass:265 dwarn:0 dfail:0 fail:0 skip:24 time:750s
fi-skl-6770hq total:289 pass:269 dwarn:0 dfail:0 fail:0 skip:20 time:491s
fi-skl-gvtdvm total:289 pass:266 dwarn:0 dfail:0 fail:0 skip:23 time:468s
fi-snb-2520m total:289 pass:251 dwarn:0 dfail:0 fail:0 skip:38 time:564s
fi-snb-2600 total:289 pass:250 dwarn:0 dfail:0 fail:0 skip:39 time:418s
6aa0df37d3fc238146f0445f71bb0738490cb6dc drm-tip: 2017y-09m-22d-21h-24m-10s UTC integration manifest
ccee338bbfe4 drm/i915: add missing DPLL fields to i915_shared_dplls_info
e4a979d1fc09 drm/i915: add the BXT and CNL DPLL registers to pipe_config_compare
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_5799/
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 9+ messages in thread
* ✓ Fi.CI.IGT: success for Add missing BXT/CNL DPLL debugging/checking code
2017-09-22 20:53 [PATCH 0/2] Add missing BXT/CNL DPLL debugging/checking code Paulo Zanoni
` (3 preceding siblings ...)
2017-09-23 8:05 ` ✓ Fi.CI.BAT: success " Patchwork
@ 2017-09-23 9:19 ` Patchwork
4 siblings, 0 replies; 9+ messages in thread
From: Patchwork @ 2017-09-23 9:19 UTC (permalink / raw)
To: Paulo Zanoni; +Cc: intel-gfx
== Series Details ==
Series: Add missing BXT/CNL DPLL debugging/checking code
URL : https://patchwork.freedesktop.org/series/30790/
State : success
== Summary ==
Test kms_flip:
Subgroup plain-flip-ts-check:
pass -> FAIL (shard-hsw) fdo#100368
Test kms_setmode:
Subgroup basic:
fail -> PASS (shard-hsw) fdo#99912
Test perf:
Subgroup blocking:
fail -> PASS (shard-hsw) fdo#102252
fdo#100368 https://bugs.freedesktop.org/show_bug.cgi?id=100368
fdo#99912 https://bugs.freedesktop.org/show_bug.cgi?id=99912
fdo#102252 https://bugs.freedesktop.org/show_bug.cgi?id=102252
shard-hsw total:2429 pass:1330 dwarn:5 dfail:0 fail:11 skip:1083 time:9816s
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_5799/shards.html
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [PATCH 1/2] drm/i915: add the BXT and CNL DPLL registers to pipe_config_compare
2017-09-22 20:53 ` [PATCH 1/2] drm/i915: add the BXT and CNL DPLL registers to pipe_config_compare Paulo Zanoni
@ 2017-09-25 23:16 ` Rodrigo Vivi
2017-09-25 23:47 ` Paulo Zanoni
0 siblings, 1 reply; 9+ messages in thread
From: Rodrigo Vivi @ 2017-09-25 23:16 UTC (permalink / raw)
To: Paulo Zanoni; +Cc: intel-gfx
Shouldn't we filter them out per platform?
Anyways it is good for me
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
On Fri, Sep 22, 2017 at 08:53:42PM +0000, Paulo Zanoni wrote:
> Looks like we were missing them.
>
> Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
> ---
> drivers/gpu/drm/i915/intel_display.c | 12 ++++++++++++
> 1 file changed, 12 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index 026fa54..64a4105 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -11336,6 +11336,18 @@ intel_pipe_config_compare(struct drm_i915_private *dev_priv,
> PIPE_CONF_CHECK_X(dpll_hw_state.ctrl1);
> PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr1);
> PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr2);
> + PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr0);
> + PIPE_CONF_CHECK_X(dpll_hw_state.ebb0);
> + PIPE_CONF_CHECK_X(dpll_hw_state.ebb4);
> + PIPE_CONF_CHECK_X(dpll_hw_state.pll0);
> + PIPE_CONF_CHECK_X(dpll_hw_state.pll1);
> + PIPE_CONF_CHECK_X(dpll_hw_state.pll2);
> + PIPE_CONF_CHECK_X(dpll_hw_state.pll3);
> + PIPE_CONF_CHECK_X(dpll_hw_state.pll6);
> + PIPE_CONF_CHECK_X(dpll_hw_state.pll8);
> + PIPE_CONF_CHECK_X(dpll_hw_state.pll9);
> + PIPE_CONF_CHECK_X(dpll_hw_state.pll10);
> + PIPE_CONF_CHECK_X(dpll_hw_state.pcsdw12);
>
> PIPE_CONF_CHECK_X(dsi_pll.ctrl);
> PIPE_CONF_CHECK_X(dsi_pll.div);
> --
> 2.9.5
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [PATCH 2/2] drm/i915: add missing DPLL fields to i915_shared_dplls_info
2017-09-22 20:53 ` [PATCH 2/2] drm/i915: add missing DPLL fields to i915_shared_dplls_info Paulo Zanoni
@ 2017-09-25 23:21 ` Rodrigo Vivi
0 siblings, 0 replies; 9+ messages in thread
From: Rodrigo Vivi @ 2017-09-25 23:21 UTC (permalink / raw)
To: Paulo Zanoni; +Cc: intel-gfx
I wonder why are we adding all of this to debugfs that can be checked
with intel_reg dumps... Assuming it will be already noisy on dmesg if
this and HW missmatch...
But yeap, since we were missing the checks and it is probably making
our life easier, let's move with it and keep everything in sync.
Acked-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
On Fri, Sep 22, 2017 at 08:53:43PM +0000, Paulo Zanoni wrote:
> Looks like we've been forgetting to add these since a long time ago.
>
> Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
> ---
> drivers/gpu/drm/i915/i915_debugfs.c | 16 ++++++++++++++++
> 1 file changed, 16 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
> index 13fc259..2b2faa6 100644
> --- a/drivers/gpu/drm/i915/i915_debugfs.c
> +++ b/drivers/gpu/drm/i915/i915_debugfs.c
> @@ -3481,6 +3481,22 @@ static int i915_shared_dplls_info(struct seq_file *m, void *unused)
> seq_printf(m, " fp0: 0x%08x\n", pll->state.hw_state.fp0);
> seq_printf(m, " fp1: 0x%08x\n", pll->state.hw_state.fp1);
> seq_printf(m, " wrpll: 0x%08x\n", pll->state.hw_state.wrpll);
> + seq_printf(m, " spll: 0x%08x\n", pll->state.hw_state.spll);
> + seq_printf(m, " ctrl1: 0x%08x\n", pll->state.hw_state.ctrl1);
> + seq_printf(m, " cfgcr1: 0x%08x\n", pll->state.hw_state.cfgcr1);
> + seq_printf(m, " cfgcr2: 0x%08x\n", pll->state.hw_state.cfgcr2);
> + seq_printf(m, " cfgcr0: 0x%08x\n", pll->state.hw_state.cfgcr0);
> + seq_printf(m, " ebb0: 0x%08x\n", pll->state.hw_state.ebb0);
> + seq_printf(m, " ebb4: 0x%08x\n", pll->state.hw_state.ebb4);
> + seq_printf(m, " pll0: 0x%08x\n", pll->state.hw_state.pll0);
> + seq_printf(m, " pll1: 0x%08x\n", pll->state.hw_state.pll1);
> + seq_printf(m, " pll2: 0x%08x\n", pll->state.hw_state.pll2);
> + seq_printf(m, " pll3: 0x%08x\n", pll->state.hw_state.pll3);
> + seq_printf(m, " pll6: 0x%08x\n", pll->state.hw_state.pll6);
> + seq_printf(m, " pll8: 0x%08x\n", pll->state.hw_state.pll8);
> + seq_printf(m, " pll9: 0x%08x\n", pll->state.hw_state.pll9);
> + seq_printf(m, " pll10: 0x%08x\n", pll->state.hw_state.pll10);
> + seq_printf(m, " pcsdw12: 0x%08x\n", pll->state.hw_state.pcsdw12);
> }
> drm_modeset_unlock_all(dev);
>
> --
> 2.9.5
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
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^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [PATCH 1/2] drm/i915: add the BXT and CNL DPLL registers to pipe_config_compare
2017-09-25 23:16 ` Rodrigo Vivi
@ 2017-09-25 23:47 ` Paulo Zanoni
0 siblings, 0 replies; 9+ messages in thread
From: Paulo Zanoni @ 2017-09-25 23:47 UTC (permalink / raw)
To: Rodrigo Vivi; +Cc: intel-gfx
Em Seg, 2017-09-25 às 16:16 -0700, Rodrigo Vivi escreveu:
> Shouldn't we filter them out per platform?
Yes, although doing it like this doesn't hurt much. See the cover
letter: we can probably organize our structs in per-platform unions or
something like that.
Thanks for the review.
>
> Anyways it is good for me
>
> Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
>
> On Fri, Sep 22, 2017 at 08:53:42PM +0000, Paulo Zanoni wrote:
> > Looks like we were missing them.
> >
> > Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
> > ---
> > drivers/gpu/drm/i915/intel_display.c | 12 ++++++++++++
> > 1 file changed, 12 insertions(+)
> >
> > diff --git a/drivers/gpu/drm/i915/intel_display.c
> > b/drivers/gpu/drm/i915/intel_display.c
> > index 026fa54..64a4105 100644
> > --- a/drivers/gpu/drm/i915/intel_display.c
> > +++ b/drivers/gpu/drm/i915/intel_display.c
> > @@ -11336,6 +11336,18 @@ intel_pipe_config_compare(struct
> > drm_i915_private *dev_priv,
> > PIPE_CONF_CHECK_X(dpll_hw_state.ctrl1);
> > PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr1);
> > PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr2);
> > + PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr0);
> > + PIPE_CONF_CHECK_X(dpll_hw_state.ebb0);
> > + PIPE_CONF_CHECK_X(dpll_hw_state.ebb4);
> > + PIPE_CONF_CHECK_X(dpll_hw_state.pll0);
> > + PIPE_CONF_CHECK_X(dpll_hw_state.pll1);
> > + PIPE_CONF_CHECK_X(dpll_hw_state.pll2);
> > + PIPE_CONF_CHECK_X(dpll_hw_state.pll3);
> > + PIPE_CONF_CHECK_X(dpll_hw_state.pll6);
> > + PIPE_CONF_CHECK_X(dpll_hw_state.pll8);
> > + PIPE_CONF_CHECK_X(dpll_hw_state.pll9);
> > + PIPE_CONF_CHECK_X(dpll_hw_state.pll10);
> > + PIPE_CONF_CHECK_X(dpll_hw_state.pcsdw12);
> >
> > PIPE_CONF_CHECK_X(dsi_pll.ctrl);
> > PIPE_CONF_CHECK_X(dsi_pll.div);
> > --
> > 2.9.5
> >
> > _______________________________________________
> > Intel-gfx mailing list
> > Intel-gfx@lists.freedesktop.org
> > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 9+ messages in thread
end of thread, other threads:[~2017-09-25 23:47 UTC | newest]
Thread overview: 9+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2017-09-22 20:53 [PATCH 0/2] Add missing BXT/CNL DPLL debugging/checking code Paulo Zanoni
2017-09-22 20:53 ` [PATCH 1/2] drm/i915: add the BXT and CNL DPLL registers to pipe_config_compare Paulo Zanoni
2017-09-25 23:16 ` Rodrigo Vivi
2017-09-25 23:47 ` Paulo Zanoni
2017-09-22 20:53 ` [PATCH 2/2] drm/i915: add missing DPLL fields to i915_shared_dplls_info Paulo Zanoni
2017-09-25 23:21 ` Rodrigo Vivi
2017-09-22 21:23 ` ✗ Fi.CI.BAT: failure for Add missing BXT/CNL DPLL debugging/checking code Patchwork
2017-09-23 8:05 ` ✓ Fi.CI.BAT: success " Patchwork
2017-09-23 9:19 ` ✓ Fi.CI.IGT: " Patchwork
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