From: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
To: Lionel Landwerlin <lionel.g.landwerlin@intel.com>,
intel-gfx@lists.freedesktop.org
Subject: Re: [PATCH i-g-t v2] tests: add slice power programming test
Date: Mon, 02 Oct 2017 12:13:14 +0300 [thread overview]
Message-ID: <1506935594.6755.33.camel@linux.intel.com> (raw)
In-Reply-To: <20170922151133.24917-1-lionel.g.landwerlin@intel.com>
On Fri, 2017-09-22 at 16:11 +0100, Lionel Landwerlin wrote:
> Verifies that the kernel programs slices correctly based by reading
> the value of PWR_CLK_STATE register.
>
> v2: Add subslice tests (Lionel)
> Use MI_SET_PREDICATE for further verification when available (Lionel)
>
> Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
> ---
> tests/Makefile.sources | 1 +
> tests/ctx_rpcs.c | 453 +++++++++++++++++++++++++++++++++++++++++++++++++
This should definitely be 'gem_ctx_rpcs' :)
Unless I missed it, this test only checks that the registers are
written to and get read. It doesn't functionally validate that the
hardware actually performs differently based on what you set?
Maybe under benchmarks/ it would be appropriate to compare the effect
on processing power, and make sure performance improves with additional
slices (except when it doesn't :P)
Regards, Joonas
--
Joonas Lahtinen
Open Source Technology Center
Intel Corporation
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prev parent reply other threads:[~2017-10-02 9:13 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
2017-09-22 15:11 [PATCH i-g-t v2] tests: add slice power programming test Lionel Landwerlin
2017-09-22 15:20 ` Chris Wilson
2017-09-22 16:17 ` ✗ Fi.CI.BAT: failure for tests: add slice power programming test (rev2) Patchwork
2017-09-25 9:32 ` [PATCH i-g-t v2] tests: add slice power programming test Petri Latvala
2017-10-02 9:13 ` Joonas Lahtinen [this message]
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