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From: Vidya Srinivas <vidya.srinivas@intel.com>
To: intel-gfx@lists.freedesktop.org
Subject: [PATCH 01/14] drm/i915/skl+: rename skl_wm_values struct to skl_ddb_values
Date: Tue, 10 Oct 2017 17:47:45 +0530	[thread overview]
Message-ID: <1507637878-17165-2-git-send-email-vidya.srinivas@intel.com> (raw)
In-Reply-To: <1507637878-17165-1-git-send-email-vidya.srinivas@intel.com>

From: Mahesh Kumar <mahesh1.kumar@intel.com>

skl_wm_values struct contains values os pipe/plane DDB only.
so rename it for better readability of code.

s/skl_wm_values/skl_ddb_values

Signed-off-by: Mahesh Kumar <mahesh1.kumar@intel.com>
---
 drivers/gpu/drm/i915/i915_drv.h  |  4 ++--
 drivers/gpu/drm/i915/intel_drv.h |  2 +-
 drivers/gpu/drm/i915/intel_pm.c  | 12 ++++++------
 3 files changed, 9 insertions(+), 9 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 770305b..1b5cf18 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1851,7 +1851,7 @@ struct skl_ddb_allocation {
 	struct skl_ddb_entry y_plane[I915_MAX_PIPES][I915_MAX_PLANES];
 };
 
-struct skl_wm_values {
+struct skl_ddb_values {
 	unsigned dirty_pipes;
 	struct skl_ddb_allocation ddb;
 };
@@ -2511,7 +2511,7 @@ struct drm_i915_private {
 		/* current hardware state */
 		union {
 			struct ilk_wm_values hw;
-			struct skl_wm_values skl_hw;
+			struct skl_ddb_values skl_hw;
 			struct vlv_wm_values vlv;
 			struct g4x_wm_values g4x;
 		};
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 0cab667..160fded 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -396,7 +396,7 @@ struct intel_atomic_state {
 	bool skip_intermediate_wm;
 
 	/* Gen9+ only */
-	struct skl_wm_values wm_results;
+	struct skl_ddb_values wm_results;
 
 	struct i915_sw_fence commit_ready;
 
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 9d0ca26..029487d 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -4981,8 +4981,8 @@ static int skl_update_pipe_wm(struct drm_crtc_state *cstate,
 }
 
 static void
-skl_copy_wm_for_pipe(struct skl_wm_values *dst,
-		     struct skl_wm_values *src,
+skl_copy_wm_for_pipe(struct skl_ddb_values *dst,
+		     struct skl_ddb_values *src,
 		     enum pipe pipe)
 {
 	memcpy(dst->ddb.y_plane[pipe], src->ddb.y_plane[pipe],
@@ -5034,7 +5034,7 @@ static int skl_update_pipe_wm(struct drm_crtc_state *cstate,
 	struct drm_crtc *crtc;
 	struct drm_crtc_state *cstate;
 	struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
-	struct skl_wm_values *results = &intel_state->wm_results;
+	struct skl_ddb_values *results = &intel_state->wm_results;
 	struct drm_device *dev = state->dev;
 	struct skl_pipe_wm *pipe_wm;
 	bool changed = false;
@@ -5136,8 +5136,8 @@ static void skl_initial_wm(struct intel_atomic_state *state,
 	struct intel_crtc *intel_crtc = to_intel_crtc(cstate->base.crtc);
 	struct drm_device *dev = intel_crtc->base.dev;
 	struct drm_i915_private *dev_priv = to_i915(dev);
-	struct skl_wm_values *results = &state->wm_results;
-	struct skl_wm_values *hw_vals = &dev_priv->wm.skl_hw;
+	struct skl_ddb_values *results = &state->wm_results;
+	struct skl_ddb_values *hw_vals = &dev_priv->wm.skl_hw;
 	enum pipe pipe = intel_crtc->pipe;
 
 	if ((results->dirty_pipes & drm_crtc_mask(&intel_crtc->base)) == 0)
@@ -5280,7 +5280,7 @@ void skl_pipe_wm_get_hw_state(struct drm_crtc *crtc,
 void skl_wm_get_hw_state(struct drm_device *dev)
 {
 	struct drm_i915_private *dev_priv = to_i915(dev);
-	struct skl_wm_values *hw = &dev_priv->wm.skl_hw;
+	struct skl_ddb_values *hw = &dev_priv->wm.skl_hw;
 	struct skl_ddb_allocation *ddb = &dev_priv->wm.skl_hw.ddb;
 	struct drm_crtc *crtc;
 	struct intel_crtc *intel_crtc;
-- 
1.9.1

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  reply	other threads:[~2017-10-10 12:09 UTC|newest]

Thread overview: 27+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2017-10-10 12:17 [PATCH 00/14] Adding NV12 support Vidya Srinivas
2017-10-10 12:17 ` Vidya Srinivas [this message]
2017-10-10 12:17 ` [PATCH 02/14] drm/i915/skl+: refactore WM calculation for NV12 Vidya Srinivas
2017-10-10 12:17 ` [PATCH 03/14] drm/i915/skl+: add NV12 in skl_format_to_fourcc Vidya Srinivas
2017-10-10 12:17 ` [PATCH 04/14] drm/i915/skl+: support varification of DDB HW state for NV12 Vidya Srinivas
2017-10-10 12:17 ` [PATCH 05/14] drm/i915/skl+: NV12 related changes for WM Vidya Srinivas
2017-10-10 12:17 ` [PATCH 06/14] drm/i915/skl+: pass skl_wm_level struct to wm compute func Vidya Srinivas
2017-10-10 12:17 ` [PATCH 07/14] drm/i915/skl+: make sure higher latency level has higher wm value Vidya Srinivas
2017-10-10 12:17 ` [PATCH 08/14] drm/i915/skl+: nv12 workaround disable WM level 1-7 Vidya Srinivas
2017-10-10 12:17 ` [PATCH 09/14] drm/i915: Set scaler mode for NV12 Vidya Srinivas
2017-10-10 13:53   ` Mahesh Kumar
2017-10-10 20:24     ` Srinivas, Vidya
2017-10-10 12:17 ` [PATCH 10/14] drm/i915: Update format_is_yuv() to include NV12 Vidya Srinivas
2017-10-10 12:17 ` [PATCH 11/14] drm/i915: Upscale scaler max scale for NV12 Vidya Srinivas
2017-10-10 14:05   ` Mahesh Kumar
2017-10-10 20:26     ` Srinivas, Vidya
2017-10-10 12:17 ` [PATCH 12/14] drm/i915: Add NV12 as supported format for primary plane Vidya Srinivas
2017-10-10 14:09   ` Mahesh Kumar
2017-10-10 14:29     ` Mahesh Kumar
2017-10-10 20:25     ` Srinivas, Vidya
2017-10-16 22:33   ` Kristian Kristensen
2017-10-10 12:17 ` [PATCH 13/14] drm/i915: Add NV12 as supported format for sprite plane Vidya Srinivas
2017-10-16 22:35   ` Kristian Kristensen
2017-10-17  3:58     ` Srinivas, Vidya
2017-10-10 12:17 ` [PATCH 14/14] drm/i915: Add NV12 support to intel_framebuffer_init Vidya Srinivas
2017-10-10 12:47 ` ✓ Fi.CI.BAT: success for Adding NV12 support (rev3) Patchwork
2017-10-10 16:48 ` ✓ Fi.CI.IGT: " Patchwork

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