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From: Vidya Srinivas <vidya.srinivas@intel.com>
To: intel-gfx@lists.freedesktop.org
Subject: [PATCH 07/14] drm/i915/skl+: make sure higher latency level has higher wm value
Date: Tue, 10 Oct 2017 17:47:51 +0530	[thread overview]
Message-ID: <1507637878-17165-8-git-send-email-vidya.srinivas@intel.com> (raw)
In-Reply-To: <1507637878-17165-1-git-send-email-vidya.srinivas@intel.com>

From: Mahesh Kumar <mahesh1.kumar@intel.com>

DDB allocation optimization algorithm require/assumes ddb allocation for
any memory C-state level DDB value to be as high as level below.
Render decompression require level WM to be as high as wm level-0.
This patch fulfils both the requirements.

Signed-off-by: Mahesh Kumar <mahesh1.kumar@intel.com>
---
 drivers/gpu/drm/i915/intel_pm.c | 18 ++++++++++++++++++
 1 file changed, 18 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index e931e4a..c99639b 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -4499,6 +4499,7 @@ static int skl_compute_plane_wm(const struct drm_i915_private *dev_priv,
 				uint16_t ddb_allocation,
 				int level,
 				const struct skl_wm_params *wp,
+				const struct skl_wm_level *result_prev,
 				struct skl_wm_level *result /* out */)
 {
 	const struct drm_plane_state *pstate = &intel_pstate->base;
@@ -4564,6 +4565,15 @@ static int skl_compute_plane_wm(const struct drm_i915_private *dev_priv,
 		} else {
 			res_blocks++;
 		}
+
+		/*
+		 * Make sure result blocks for higher latency levels are atleast
+		 * as high as level below.
+		 * Assumption in DDB algorithm optimization for special cases.
+		 * Also covers Display WA #1125 for RC.
+		 */
+		if (result_prev->plane_res_b > res_blocks)
+			res_blocks = result_prev->plane_res_b;
 	}
 
 	if (res_blocks >= ddb_allocation || res_lines > 31) {
@@ -4622,6 +4632,13 @@ static int skl_compute_plane_wm(const struct drm_i915_private *dev_priv,
 	for (level = 0; level <= max_level; level++) {
 		struct skl_wm_level *result = plane_num ? &wm->uv_wm[level] :
 							  &wm->wm[level];
+		struct skl_wm_level *result_prev;
+
+		if (level)
+			result_prev = plane_num ? &wm->uv_wm[level - 1] :
+						  &wm->wm[level - 1];
+		else
+			result_prev = plane_num ? &wm->uv_wm[0] : &wm->wm[0];
 
 		ret = skl_compute_plane_wm(dev_priv,
 					   cstate,
@@ -4629,6 +4646,7 @@ static int skl_compute_plane_wm(const struct drm_i915_private *dev_priv,
 					   ddb_blocks,
 					   level,
 					   wm_params,
+					   result_prev,
 					   result);
 		if (ret)
 			return ret;
-- 
1.9.1

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  parent reply	other threads:[~2017-10-10 12:09 UTC|newest]

Thread overview: 27+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2017-10-10 12:17 [PATCH 00/14] Adding NV12 support Vidya Srinivas
2017-10-10 12:17 ` [PATCH 01/14] drm/i915/skl+: rename skl_wm_values struct to skl_ddb_values Vidya Srinivas
2017-10-10 12:17 ` [PATCH 02/14] drm/i915/skl+: refactore WM calculation for NV12 Vidya Srinivas
2017-10-10 12:17 ` [PATCH 03/14] drm/i915/skl+: add NV12 in skl_format_to_fourcc Vidya Srinivas
2017-10-10 12:17 ` [PATCH 04/14] drm/i915/skl+: support varification of DDB HW state for NV12 Vidya Srinivas
2017-10-10 12:17 ` [PATCH 05/14] drm/i915/skl+: NV12 related changes for WM Vidya Srinivas
2017-10-10 12:17 ` [PATCH 06/14] drm/i915/skl+: pass skl_wm_level struct to wm compute func Vidya Srinivas
2017-10-10 12:17 ` Vidya Srinivas [this message]
2017-10-10 12:17 ` [PATCH 08/14] drm/i915/skl+: nv12 workaround disable WM level 1-7 Vidya Srinivas
2017-10-10 12:17 ` [PATCH 09/14] drm/i915: Set scaler mode for NV12 Vidya Srinivas
2017-10-10 13:53   ` Mahesh Kumar
2017-10-10 20:24     ` Srinivas, Vidya
2017-10-10 12:17 ` [PATCH 10/14] drm/i915: Update format_is_yuv() to include NV12 Vidya Srinivas
2017-10-10 12:17 ` [PATCH 11/14] drm/i915: Upscale scaler max scale for NV12 Vidya Srinivas
2017-10-10 14:05   ` Mahesh Kumar
2017-10-10 20:26     ` Srinivas, Vidya
2017-10-10 12:17 ` [PATCH 12/14] drm/i915: Add NV12 as supported format for primary plane Vidya Srinivas
2017-10-10 14:09   ` Mahesh Kumar
2017-10-10 14:29     ` Mahesh Kumar
2017-10-10 20:25     ` Srinivas, Vidya
2017-10-16 22:33   ` Kristian Kristensen
2017-10-10 12:17 ` [PATCH 13/14] drm/i915: Add NV12 as supported format for sprite plane Vidya Srinivas
2017-10-16 22:35   ` Kristian Kristensen
2017-10-17  3:58     ` Srinivas, Vidya
2017-10-10 12:17 ` [PATCH 14/14] drm/i915: Add NV12 support to intel_framebuffer_init Vidya Srinivas
2017-10-10 12:47 ` ✓ Fi.CI.BAT: success for Adding NV12 support (rev3) Patchwork
2017-10-10 16:48 ` ✓ Fi.CI.IGT: " Patchwork

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