From: Paulo Zanoni <paulo.r.zanoni@intel.com>
To: Ville Syrjala <ville.syrjala@linux.intel.com>,
intel-gfx@lists.freedesktop.org
Cc: Tomi Sarvela <tomi.p.sarvela@intel.com>
Subject: Re: [PATCH 1/3] drm/i915: Check if the stolen memory "reserved" area is enabled or not
Date: Tue, 14 Nov 2017 18:12:41 -0200 [thread overview]
Message-ID: <1510690361.22559.5.camel@intel.com> (raw)
In-Reply-To: <20171102151737.23336-1-ville.syrjala@linux.intel.com>
Em Qui, 2017-11-02 às 17:17 +0200, Ville Syrjala escreveu:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Apparently there are some machines that put semi-sensible looking
> values
> into the stolen "reserved" base and size, except those values are
> actually
> outside the stolen memory. There is a bit in the register which
> supposedly could tell us whether the reserved area is even enabled or
> not. Let's check for that before we go trusting the base and size.
If this is such a problem since g4x, why didn't we spot it earlier? It
would be nice if you could explain in the commit message (or at least
in this email) what are the consequences you're seeing that made you
realize about this problem. Did something actually explode? I'm
genuinely curious.
Now talking about the patch itself:
If we're going to assume random bits instead of a full-zero in
(possibly) uninitialized stuff, shouldn't we first check bit 1, which
is supposed to tell us if the whole reg is locked or not?
if ((reg_val & 0x3) != 0x3)
ignore stolen reserved stuff;
Anyway, this patch without my suggestions is probably better than the
current situation so:
Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
but please feel investigate the bit 1 thing and CC me on v2 or a
possible follow-up patch with conclusions.
> Cc: Tomi Sarvela <tomi.p.sarvela@intel.com>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
> drivers/gpu/drm/i915/i915_gem_stolen.c | 30
> ++++++++++++++++++++++++++++++
> drivers/gpu/drm/i915/i915_reg.h | 2 ++
> 2 files changed, 32 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/i915_gem_stolen.c
> b/drivers/gpu/drm/i915/i915_gem_stolen.c
> index 03e7abc7e043..44a5dbc8c23b 100644
> --- a/drivers/gpu/drm/i915/i915_gem_stolen.c
> +++ b/drivers/gpu/drm/i915/i915_gem_stolen.c
> @@ -294,6 +294,12 @@ static void g4x_get_stolen_reserved(struct
> drm_i915_private *dev_priv,
> ELK_STOLEN_RESERVED);
> dma_addr_t stolen_top = dev_priv->mm.stolen_base + ggtt-
> >stolen_size;
>
> + if ((reg_val & G4X_STOLEN_RESERVED_ENABLE) == 0) {
> + *base = 0;
> + *size = 0;
> + return;
> + }
> +
> *base = (reg_val & G4X_STOLEN_RESERVED_ADDR2_MASK) << 16;
>
> WARN_ON((reg_val & G4X_STOLEN_RESERVED_ADDR1_MASK) < *base);
> @@ -313,6 +319,12 @@ static void gen6_get_stolen_reserved(struct
> drm_i915_private *dev_priv,
> {
> uint32_t reg_val = I915_READ(GEN6_STOLEN_RESERVED);
>
> + if ((reg_val & GEN6_STOLEN_RESERVED_ENABLE) == 0) {
> + *base = 0;
> + *size = 0;
> + return;
> + }
> +
> *base = reg_val & GEN6_STOLEN_RESERVED_ADDR_MASK;
>
> switch (reg_val & GEN6_STOLEN_RESERVED_SIZE_MASK) {
> @@ -339,6 +351,12 @@ static void gen7_get_stolen_reserved(struct
> drm_i915_private *dev_priv,
> {
> uint32_t reg_val = I915_READ(GEN6_STOLEN_RESERVED);
>
> + if ((reg_val & GEN6_STOLEN_RESERVED_ENABLE) == 0) {
> + *base = 0;
> + *size = 0;
> + return;
> + }
> +
> *base = reg_val & GEN7_STOLEN_RESERVED_ADDR_MASK;
>
> switch (reg_val & GEN7_STOLEN_RESERVED_SIZE_MASK) {
> @@ -359,6 +377,12 @@ static void chv_get_stolen_reserved(struct
> drm_i915_private *dev_priv,
> {
> uint32_t reg_val = I915_READ(GEN6_STOLEN_RESERVED);
>
> + if ((reg_val & GEN6_STOLEN_RESERVED_ENABLE) == 0) {
> + *base = 0;
> + *size = 0;
> + return;
> + }
> +
> *base = reg_val & GEN6_STOLEN_RESERVED_ADDR_MASK;
>
> switch (reg_val & GEN8_STOLEN_RESERVED_SIZE_MASK) {
> @@ -387,6 +411,12 @@ static void bdw_get_stolen_reserved(struct
> drm_i915_private *dev_priv,
> uint32_t reg_val = I915_READ(GEN6_STOLEN_RESERVED);
> dma_addr_t stolen_top;
>
> + if ((reg_val & GEN6_STOLEN_RESERVED_ENABLE) == 0) {
> + *base = 0;
> + *size = 0;
> + return;
> + }
> +
> stolen_top = dev_priv->mm.stolen_base + ggtt->stolen_size;
>
> *base = reg_val & GEN6_STOLEN_RESERVED_ADDR_MASK;
> diff --git a/drivers/gpu/drm/i915/i915_reg.h
> b/drivers/gpu/drm/i915/i915_reg.h
> index f0f8f6059652..dc2cbc428d1b 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -382,6 +382,7 @@ static inline bool i915_mmio_reg_valid(i915_reg_t
> reg)
> #define GEN8_STOLEN_RESERVED_2M (1 << 7)
> #define GEN8_STOLEN_RESERVED_4M (2 << 7)
> #define GEN8_STOLEN_RESERVED_8M (3 << 7)
> +#define GEN6_STOLEN_RESERVED_ENABLE (1 << 0)
>
> /* VGA stuff */
>
> @@ -3398,6 +3399,7 @@ enum i915_power_well_id {
> #define ELK_STOLEN_RESERVED _MMIO(MCHBAR_MIRROR_BASE
> + 0x48)
> #define G4X_STOLEN_RESERVED_ADDR1_MASK (0xFFFF << 16)
> #define G4X_STOLEN_RESERVED_ADDR2_MASK (0xFFF << 4)
> +#define G4X_STOLEN_RESERVED_ENABLE (1 << 0)
>
> /* Memory controller frequency in MCHBAR for Haswell (possible SNB+)
> */
> #define DCLK _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5e04)
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next prev parent reply other threads:[~2017-11-14 20:13 UTC|newest]
Thread overview: 26+ messages / expand[flat|nested] mbox.gz Atom feed top
2017-11-02 15:17 [PATCH 1/3] drm/i915: Check if the stolen memory "reserved" area is enabled or not Ville Syrjala
2017-11-02 15:17 ` [PATCH 2/3] drm/i915: Make the report about a bogus stolen reserved area an error Ville Syrjala
2017-11-14 20:33 ` Paulo Zanoni
2017-11-14 20:41 ` Ville Syrjälä
2017-11-02 15:17 ` [PATCH 3/3] drm/i915: Use ELK stolen memory reserved detection for ILK Ville Syrjala
2017-11-14 20:59 ` Paulo Zanoni
2017-11-14 21:19 ` Ville Syrjälä
2017-11-02 15:38 ` ✓ Fi.CI.BAT: success for series starting with [1/3] drm/i915: Check if the stolen memory "reserved" area is enabled or not Patchwork
2017-11-02 16:34 ` ✗ Fi.CI.IGT: warning " Patchwork
2017-11-02 17:08 ` Ville Syrjälä
2017-11-03 7:19 ` Saarinen, Jani
2017-11-03 8:18 ` Tomi Sarvela
2017-11-03 10:41 ` Ville Syrjälä
2017-11-03 11:14 ` Tomi Sarvela
2017-11-03 10:43 ` Petri Latvala
2017-11-03 11:33 ` Tomi Sarvela
2017-11-03 12:53 ` Tomi Sarvela
2017-11-03 12:52 ` ✓ Fi.CI.IGT: success " Patchwork
2017-11-14 20:12 ` Paulo Zanoni [this message]
2017-11-14 20:19 ` [PATCH 1/3] " Chris Wilson
2017-11-14 20:29 ` Paulo Zanoni
2017-11-14 20:41 ` Chris Wilson
2017-11-14 20:34 ` Ville Syrjälä
2017-11-14 20:44 ` Paulo Zanoni
2017-11-14 21:38 ` Ville Syrjälä
2017-11-15 17:11 ` Ville Syrjälä
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