From: Paulo Zanoni <paulo.r.zanoni@intel.com>
To: Lionel Landwerlin <lionel.g.landwerlin@intel.com>,
intel-gfx@lists.freedesktop.org
Subject: Re: [PATCH v3 4/4] drm/i915/cnl: only divide up base frequency with crystal source
Date: Mon, 04 Dec 2017 16:41:05 -0200 [thread overview]
Message-ID: <1512412865.2753.14.camel@intel.com> (raw)
In-Reply-To: <1512409842.2753.3.camel@intel.com>
Em Seg, 2017-12-04 às 15:50 -0200, Paulo Zanoni escreveu:
> Em Seg, 2017-11-13 às 23:34 +0000, Lionel Landwerlin escreveu:
> > We apply this logic to Gen9 as well. We didn't notice this issue as
> > most part we've encountered so far only use the crystal as source
> > for
> > their timestamp registers.
> >
> > Fixes: dab9178333 ("drm/i915: expose command stream timestamp
> > frequency to userspace")
> > Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
>
> Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
I also merged this since I need it.
Patch 3 still needs a check from the people who were reviewing its
previous versions.
>
> > ---
> > drivers/gpu/drm/i915/intel_device_info.c | 16 ++++++++--------
> > 1 file changed, 8 insertions(+), 8 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/intel_device_info.c
> > b/drivers/gpu/drm/i915/intel_device_info.c
> > index f3e4940fed49..039f8ec7ad27 100644
> > --- a/drivers/gpu/drm/i915/intel_device_info.c
> > +++ b/drivers/gpu/drm/i915/intel_device_info.c
> > @@ -413,15 +413,15 @@ static u32 read_timestamp_frequency(struct
> > drm_i915_private *dev_priv)
> > freq = f24_mhz;
> > break;
> > }
> > - }
> >
> > - /* Now figure out how the command stream's
> > timestamp
> > register
> > - * increments from this frequency (it might
> > increment only
> > - * every few clock cycle).
> > - */
> > - freq >>= 3 - ((rpm_config_reg &
> > - GEN10_RPM_CONFIG0_CTC_SHIFT_PARAMET
> > ER
> > _MASK) >>
> > - GEN10_RPM_CONFIG0_CTC_SHIFT_PARAMETE
> > R_
> > SHIFT);
> > + /* Now figure out how the command stream's
> > timestamp
> > + * register increments from this frequency
> > (it might
> > + * increment only every few clock cycle).
> > + */
> > + freq >>= 3 - ((rpm_config_reg &
> > + GEN10_RPM_CONFIG0_CTC_SHIFT
> > _P
> > ARAMETER_MASK) >>
> > + GEN10_RPM_CONFIG0_CTC_SHIFT_
> > PA
> > RAMETER_SHIFT);
> > + }
> >
> > return freq;
> > }
>
> _______________________________________________
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> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
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next prev parent reply other threads:[~2017-12-04 18:41 UTC|newest]
Thread overview: 12+ messages / expand[flat|nested] mbox.gz Atom feed top
2017-11-13 23:34 [PATCH v3 0/4] drm/i915: some perf cleanups (& fixes!) Lionel Landwerlin
2017-11-13 23:34 ` [PATCH v3 1/4] drm/i915/perf: replace .reg accesses with i915_mmio_reg_offset Lionel Landwerlin
2017-11-14 7:26 ` Ewelina Musial
2017-11-13 23:34 ` [PATCH v3 2/4] drm/i915: fix 64bit divide Lionel Landwerlin
2017-11-14 7:30 ` Ewelina Musial
2017-11-14 14:27 ` Ville Syrjälä
2017-11-13 23:34 ` [PATCH v3 3/4] drm/i915/perf: reuse timestamp frequency from device info Lionel Landwerlin
2017-11-13 23:34 ` [PATCH v3 4/4] drm/i915/cnl: only divide up base frequency with crystal source Lionel Landwerlin
2017-12-04 17:50 ` Paulo Zanoni
2017-12-04 18:41 ` Paulo Zanoni [this message]
2017-11-14 0:10 ` ✓ Fi.CI.BAT: success for drm/i915: some perf cleanups (& fixes!) (rev2) Patchwork
2017-11-14 0:53 ` ✓ Fi.CI.IGT: " Patchwork
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