From: Paulo Zanoni <paulo.r.zanoni@intel.com>
To: Oscar Mateo <oscar.mateo@intel.com>, intel-gfx@lists.freedesktop.org
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Subject: Re: [PATCH 01/27] drm/i915/icl: Add initial Icelake definitions.
Date: Wed, 10 Jan 2018 15:57:22 -0200 [thread overview]
Message-ID: <1515607042.22902.30.camel@intel.com> (raw)
In-Reply-To: <8b3c3c09-3aab-9857-6a4e-512f64aaaf66@intel.com>
Em Ter, 2018-01-09 às 15:59 -0800, Oscar Mateo escreveu:
>
> On 01/09/2018 03:23 PM, Paulo Zanoni wrote:
> > From: Rodrigo Vivi <rodrigo.vivi@intel.com>
> >
> > Icelake is a Intel® Processor containing Intel® HD Graphics.
> >
> > This is just an initial Icelake definition. PCI IDs, Icelake
> > support
> > and new features coming in following patches.
> >
> > v2: Add .ddb_size and .has_guc (Michal Wajdeczko).
> > v3: Add the ICL_FEATURES macro (Kelvin Gardiner).
> >
> > Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
> > Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
> > ---
> > drivers/gpu/drm/i915/i915_drv.h | 2 ++
> > drivers/gpu/drm/i915/i915_pci.c | 13 +++++++++++++
> > drivers/gpu/drm/i915/intel_device_info.c | 1 +
> > drivers/gpu/drm/i915/intel_device_info.h | 2 ++
> > 4 files changed, 18 insertions(+)
> >
> > diff --git a/drivers/gpu/drm/i915/i915_drv.h
> > b/drivers/gpu/drm/i915/i915_drv.h
> > index a689396d0ff6..016920f58ae6 100644
> > --- a/drivers/gpu/drm/i915/i915_drv.h
> > +++ b/drivers/gpu/drm/i915/i915_drv.h
> > @@ -2595,6 +2595,7 @@ intel_info(const struct drm_i915_private
> > *dev_priv)
> > #define IS_GEMINILAKE(dev_priv) IS_PLATFORM(dev_priv,
> > INTEL_GEMINILAKE)
> > #define IS_COFFEELAKE(dev_priv) IS_PLATFORM(dev_priv,
> > INTEL_COFFEELAKE)
> > #define IS_CANNONLAKE(dev_priv) IS_PLATFORM(dev_priv,
> > INTEL_CANNONLAKE)
> > +#define IS_ICELAKE(dev_priv) IS_PLATFORM(dev_priv,
> > INTEL_ICELAKE)
> > #define IS_MOBILE(dev_priv) ((dev_priv)->info.is_mobile)
> > #define IS_HSW_EARLY_SDV(dev_priv) (IS_HASWELL(dev_priv) && \
> > (INTEL_DEVID(dev_priv) &
> > 0xFF00) == 0x0C00)
> > @@ -2706,6 +2707,7 @@ intel_info(const struct drm_i915_private
> > *dev_priv)
> > #define IS_GEN8(dev_priv) (!!((dev_priv)->info.gen_mask &
> > BIT(7)))
> > #define IS_GEN9(dev_priv) (!!((dev_priv)->info.gen_mask &
> > BIT(8)))
> > #define IS_GEN10(dev_priv) (!!((dev_priv)->info.gen_mask &
> > BIT(9)))
> > +#define IS_GEN11(dev_priv) (!!((dev_priv)->info.gen_mask &
> > BIT(10)))
> >
> > #define IS_LP(dev_priv) (INTEL_INFO(dev_priv)->is_lp)
> > #define IS_GEN9_LP(dev_priv) (IS_GEN9(dev_priv) &&
> > IS_LP(dev_priv))
> > diff --git a/drivers/gpu/drm/i915/i915_pci.c
> > b/drivers/gpu/drm/i915/i915_pci.c
> > index 36d48422b475..88cd4a3b12f5 100644
> > --- a/drivers/gpu/drm/i915/i915_pci.c
> > +++ b/drivers/gpu/drm/i915/i915_pci.c
> > @@ -579,6 +579,19 @@ static const struct intel_device_info
> > intel_cannonlake_gt2_info __initconst = {
> > .gt = 2,
> > };
> >
> > +#define GEN11_FEATURES \
> > + GEN10_FEATURES, \
> > + .gen = 11, \
> > + .ddb_size = 2048, \
> > + .has_csr = 0
> > +
> > +static const struct intel_device_info intel_icelake_11_info = {
> > + GEN11_FEATURES,
> > + .platform = INTEL_ICELAKE,
> > + .is_alpha_support = 1,
> > + .has_resource_streamer = 0,
> > +};
> > +
>
> This needs to change to fit the new GEN features inheritance
> organization recently introduced by Rodrigo (with a GEN11_FEATURES
> and I
> guess an ICL_11_PLATFORM). Should I go ahead?
My understanding is that this is already following the new inheritance
model. There's already a GEN11_FEATURES and it doesn't include an
ICL_11_PLATFORM because it doesn't need to (and CNL also doesn't have a
CNL_PLATFORM). What do you think needs to be changed?
The one thing I do see we lack is the __initconst keyword.
>
> > /*
> > * Make sure any device matches here are from most specific to
> > most
> > * general. For example, since the Quanta match is based on the
> > subsystem
> > diff --git a/drivers/gpu/drm/i915/intel_device_info.c
> > b/drivers/gpu/drm/i915/intel_device_info.c
> > index d28592e43512..a2c16140169f 100644
> > --- a/drivers/gpu/drm/i915/intel_device_info.c
> > +++ b/drivers/gpu/drm/i915/intel_device_info.c
> > @@ -56,6 +56,7 @@ static const char * const platform_names[] = {
> > PLATFORM_NAME(GEMINILAKE),
> > PLATFORM_NAME(COFFEELAKE),
> > PLATFORM_NAME(CANNONLAKE),
> > + PLATFORM_NAME(ICELAKE),
> > };
> > #undef PLATFORM_NAME
> >
> > diff --git a/drivers/gpu/drm/i915/intel_device_info.h
> > b/drivers/gpu/drm/i915/intel_device_info.h
> > index 49cb27bd04c1..9542018d11d0 100644
> > --- a/drivers/gpu/drm/i915/intel_device_info.h
> > +++ b/drivers/gpu/drm/i915/intel_device_info.h
> > @@ -69,6 +69,8 @@ enum intel_platform {
> > INTEL_COFFEELAKE,
> > /* gen10 */
> > INTEL_CANNONLAKE,
> > + /* gen11 */
> > + INTEL_ICELAKE,
> > INTEL_MAX_PLATFORMS
> > };
> >
>
>
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
next prev parent reply other threads:[~2018-01-10 17:57 UTC|newest]
Thread overview: 118+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-01-09 23:23 [PATCH 00/27] ICL basic enabling + GEM Paulo Zanoni
2018-01-09 23:23 ` [PATCH 01/27] drm/i915/icl: Add initial Icelake definitions Paulo Zanoni
2018-01-09 23:59 ` Oscar Mateo
2018-01-10 17:57 ` Paulo Zanoni [this message]
2018-01-10 18:08 ` Oscar Mateo
2018-01-10 18:22 ` Rodrigo Vivi
2018-01-10 18:38 ` Paulo Zanoni
2018-01-11 1:25 ` Rodrigo Vivi
2018-01-10 10:15 ` Chris Wilson
2018-01-10 18:19 ` Paulo Zanoni
2018-01-10 19:17 ` Paulo Zanoni
2018-01-19 11:27 ` Joonas Lahtinen
2018-01-09 23:23 ` [PATCH 02/27] drm/i915/icl: Add the ICL PCI IDs Paulo Zanoni
2018-01-10 0:09 ` Oscar Mateo
2018-01-10 1:02 ` De Marchi, Lucas
2018-01-10 1:07 ` Oscar Mateo
2018-01-10 14:08 ` Paulo Zanoni
2018-01-09 23:23 ` [PATCH 03/27] drm/i915/icl: add icelake_init_clock_gating() Paulo Zanoni
2018-01-10 9:39 ` Joonas Lahtinen
2018-01-10 18:42 ` Paulo Zanoni
2018-01-09 23:23 ` [PATCH 04/27] drm/i915/icl: Icelake interrupt register addresses and bits Paulo Zanoni
2018-01-10 19:54 ` Paulo Zanoni
2018-01-09 23:23 ` [PATCH 05/27] drm/i915/icl: Show interrupt registers in debugfs Paulo Zanoni
2018-01-10 9:02 ` Tvrtko Ursulin
2018-01-10 18:49 ` Paulo Zanoni
2018-01-11 8:55 ` Tvrtko Ursulin
2018-01-09 23:23 ` [PATCH 06/27] drm/i915/icl: Prepare for more rings Paulo Zanoni
2018-02-07 22:03 ` Oscar Mateo
2018-01-09 23:23 ` [PATCH 07/27] drm/i915/icl: Interrupt handling Paulo Zanoni
2018-01-10 10:16 ` Joonas Lahtinen
2018-01-10 18:56 ` Paulo Zanoni
2018-01-19 17:30 ` Tvrtko Ursulin
2018-01-19 18:10 ` Paulo Zanoni
2018-01-19 20:33 ` Chris Wilson
2018-01-26 11:22 ` Jani Nikula
2018-02-09 22:34 ` Daniele Ceraolo Spurio
2018-01-09 23:23 ` [PATCH 08/27] drm/i915/icl: Ringbuffer interrupt handling Paulo Zanoni
2018-01-10 10:12 ` Chris Wilson
2018-01-11 19:17 ` Daniele Ceraolo Spurio
2018-01-15 10:38 ` Tvrtko Ursulin
2018-02-01 23:58 ` Belgaumkar, Vinay
2018-02-02 0:36 ` Belgaumkar, Vinay
2018-01-09 23:23 ` [PATCH 09/27] drm/i915/icl: Correctly initialize the Gen11 engines Paulo Zanoni
2018-01-09 23:28 ` [PATCH 10/27] drm/i915/icl: Enhanced execution list support Paulo Zanoni
2018-01-09 23:28 ` [PATCH 11/27] drm/i915/icl: Gen11 render context size Paulo Zanoni
2018-01-11 1:21 ` Rodrigo Vivi
2018-01-11 18:20 ` Oscar Mateo
2018-01-11 18:23 ` [PATCH v3] " Oscar Mateo
2018-01-11 19:40 ` Rodrigo Vivi
2018-01-11 22:53 ` Oscar Mateo
2018-01-11 22:55 ` [PATCH 1/2] drm/i915: Return a default RCS " Oscar Mateo
2018-01-11 22:55 ` [PATCH 2/2 v4] drm/i915/icl: Gen11 render " Oscar Mateo
2018-01-12 0:01 ` Daniele Ceraolo Spurio
2018-01-11 23:08 ` [PATCH 1/2] drm/i915: Return a default RCS " Daniele Ceraolo Spurio
2018-01-09 23:28 ` [PATCH 12/27] drm/i915/icl: Add Indirect Context Offset for Gen11 Paulo Zanoni
2018-01-10 23:44 ` Oscar Mateo
2018-01-25 1:06 ` [PATCH v2 " Michel Thierry
2018-01-09 23:28 ` [PATCH 13/27] drm/i915/icl: Gen11 forcewake support Paulo Zanoni
2018-02-01 0:52 ` [PATCH v10] " Michel Thierry
2018-02-01 10:25 ` Tvrtko Ursulin
2018-02-01 16:02 ` Michel Thierry
2018-02-01 16:08 ` [PATCH v11] " Michel Thierry
2018-02-03 20:26 ` [PATCH v10] " kbuild test robot
2018-02-03 21:43 ` kbuild test robot
2018-01-09 23:28 ` [PATCH 14/27] drm/i915/icl: Set graphics mode register for gen11 Paulo Zanoni
2018-01-10 13:40 ` Arkadiusz Hiler
2018-01-11 19:32 ` Daniele Ceraolo Spurio
2018-01-19 19:30 ` [PATCH v3] " Kelvin Gardiner
2018-01-19 22:46 ` Daniele Ceraolo Spurio
2018-01-09 23:28 ` [PATCH 15/27] drm/i915/icl: new context descriptor support Paulo Zanoni
2018-01-09 23:28 ` [PATCH 16/27] drm/i915/icl: Check for fused-off VDBOX and VEBOX instances Paulo Zanoni
2018-01-10 9:36 ` Chris Wilson
2018-01-10 19:25 ` Oscar Mateo
2018-01-10 19:32 ` Chris Wilson
2018-01-10 19:33 ` Chris Wilson
2018-01-10 23:02 ` Oscar Mateo
2018-01-10 23:03 ` [PATCH v8] " Oscar Mateo
2018-01-09 23:28 ` [PATCH 17/27] drm/i915/icl: Enable the extra video decode and enhancement boxes for Icelake 11 Paulo Zanoni
2018-01-09 23:28 ` [PATCH 18/27] drm/i915/icl: Update subslice define for ICL 11 Paulo Zanoni
2018-01-11 0:06 ` Oscar Mateo
2018-01-11 18:25 ` [PATCH v2] " Oscar Mateo
2018-02-08 16:35 ` Lionel Landwerlin
2018-02-09 17:44 ` Oscar Mateo
2018-02-09 17:48 ` Lionel Landwerlin
2018-02-09 18:00 ` [PATCH v3] " Oscar Mateo
2018-01-09 23:28 ` [PATCH 19/27] drm/i915/icl: Added ICL 11 slice, subslice and EU fuse detection Paulo Zanoni
2018-01-10 12:02 ` Tvrtko Ursulin
2018-01-09 23:28 ` [PATCH 20/27] drm/i915/icl: Make use of the SW counter field in the new context descriptor Paulo Zanoni
2018-01-11 21:10 ` Daniele Ceraolo Spurio
2018-01-11 22:37 ` Oscar Mateo
2018-01-11 23:11 ` Daniele Ceraolo Spurio
2018-01-09 23:28 ` [PATCH 21/27] drm/i915/icl: Add reset control register changes Paulo Zanoni
2018-01-09 23:28 ` [PATCH 22/27] drm/i915/icl: Add configuring MOCS in new Icelake engines Paulo Zanoni
2018-01-09 23:28 ` [PATCH 23/27] drm/i915/icl: Split out the servicing of the Selector and Shared IIR registers Paulo Zanoni
2018-01-09 23:28 ` [PATCH 24/27] drm/i915/icl: Handle RPS interrupts correctly for Gen11 Paulo Zanoni
2018-01-09 23:28 ` [PATCH 25/27] drm/i915/icl: Enable RC6 and RPS in Gen11 Paulo Zanoni
2018-01-09 23:28 ` [PATCH 26/27] drm/i915/icl: allow the reg_read ioctl to read the RCS TIMESTAMP register Paulo Zanoni
2018-01-11 1:19 ` Rodrigo Vivi
2018-01-09 23:28 ` [PATCH 27/27] drm/i915/gen11: add support for reading the timestamp frequency Paulo Zanoni
2018-03-28 11:34 ` Lionel Landwerlin
2018-01-10 9:45 ` [PATCH 10/27] drm/i915/icl: Enhanced execution list support Chris Wilson
2018-01-11 19:55 ` Daniele Ceraolo Spurio
2018-01-11 20:55 ` Daniele Ceraolo Spurio
2018-01-17 21:53 ` [PATCH v5] " Daniele Ceraolo Spurio
2018-01-19 13:05 ` Mika Kuoppala
2018-01-19 16:15 ` Daniele Ceraolo Spurio
2018-01-22 15:08 ` Mika Kuoppala
2018-01-22 15:13 ` Chris Wilson
2018-01-22 16:09 ` Daniele Ceraolo Spurio
2018-01-22 17:32 ` Chris Wilson
2018-01-22 21:38 ` Daniele Ceraolo Spurio
2018-01-11 1:32 ` [PATCH 00/27] ICL basic enabling + GEM Rodrigo Vivi
2018-01-19 11:45 ` Joonas Lahtinen
2018-01-19 11:55 ` Tvrtko Ursulin
2018-01-19 13:14 ` Mika Kuoppala
2018-01-19 12:08 ` Jani Nikula
2018-01-12 10:06 ` ✗ Fi.CI.BAT: failure for ICL basic enabling + GEM (rev24) Patchwork
2018-01-18 10:21 ` ✗ Fi.CI.BAT: failure for ICL basic enabling + GEM (rev25) Patchwork
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=1515607042.22902.30.camel@intel.com \
--to=paulo.r.zanoni@intel.com \
--cc=intel-gfx@lists.freedesktop.org \
--cc=oscar.mateo@intel.com \
--cc=rodrigo.vivi@intel.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox