Re: [PATCH 10/17] drm/i915/icl: initialize MBus during display init

James Ausmus
2018-01-25T22:37:20Z

On Tue, Jan 23, 2018 at 05:05:29PM -0200, Paulo Zanoni wrote:
> From: Mahesh Kumar <mahesh1.kumar@intel.com>
>
> This patch initializes MBus during display initialization.
>
> Changes since V2 (from Paulo):
> - Don't forget to remove the WARN_ON(1) call.
> Changes since V1:
> - Rebase to use function like Macros
>
> Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
> Signed-off-by: Mahesh Kumar <mahesh1.kumar@intel.com>
> Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>

Reviewed-by: James Ausmus <james.ausmus@intel.com>

> ---
> drivers/gpu/drm/i915/intel_runtime_pm.c | 14 +++++++++++++-
> 1 file changed, 13 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c b/drivers/gpu/drm/i915/intel_runtime_pm.c
> index 7801a425398f..a6ed01a528bd 100644
> --- a/drivers/gpu/drm/i915/intel_runtime_pm.c
> +++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
> @@ -2640,6 +2640,18 @@ static void icl_dbuf_disable(struct drm_i915_private *dev_priv)
> DRM_ERROR("DBuf power disable timeout!\n");
> }
>
> +static void icl_mbus_init(struct drm_i915_private *dev_priv)
> +{
> + uint32_t val;
> +
> + val = MBUS_ABOX_BT_CREDIT_POOL1(16) |
> + MBUS_ABOX_BT_CREDIT_POOL2(16) |
> + MBUS_ABOX_B_CREDIT(1) |
> + MBUS_ABOX_BW_CREDIT(1);
> +
> + I915_WRITE(MBUS_ABOX_CTL, val);
> +}
> +
> static void skl_display_core_init(struct drm_i915_private *dev_priv,
> bool resume)
> {
> @@ -2953,7 +2965,7 @@ static void icl_display_core_init(struct drm_i915_private *dev_priv,
> icl_dbuf_enable(dev_priv);
>
> /* 7. Setup MBUS. */
> - /* FIXME: MBUS code not here yet. */
> + icl_mbus_init(dev_priv);
>
> /* 8. CHICKEN_DCPR_1 */
> I915_WRITE(GEN8_CHICKEN_DCPR_1, I915_READ(GEN8_CHICKEN_DCPR_1) |
> --
> 2.14.3
>
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