[PATCH 00/17] ICL display initialization and some plane bits

Paulo Zanoni
2018-01-23T19:05:47Z

Hi

Here's another ICL series. This one includes the very basic steps of display
initialization (although missing quite a few pieces) and some patches related to
planes (dbuf, mbus, bit field changes). Nothing special.

Again, as explained in the other series, the R-B tags in these patches were
given to earlier versions, so they need to be re-confirmed since upstream has
moved quite a bit since then.

Thanks,
Paulo

James Ausmus (1):
drm/i915/icl: Handle expanded PLANE_CTL_FORMAT field

Mahesh Kumar (12):
drm/i915/icl: Enable both DBuf slices during init
drm/i915/icl: Don't allocate fixed bypass path blocks for ICL
drm/i915/icl: Do not fix dbuf block size to 512
drm/i915/icl: Fail flip if ddb allocated are less than min display
buffer needed
drm/i915/icl: NV12 y-plane ddb is not in same plane
drm/i915/icl: Introduce MBus related registers
drm/i915/icl: initialize MBus during display init
drm/i915/icl: program mbus during pipe enable
drm/i915/icl: track dbuf slice-2 status
drm/i915/icl: Enable 2nd DBuf slice only when needed
drm/i915/icl: update ddb entry start/end mask during hw ddb readout
drm/i915/icl: enable SAGV for ICL platform

Paulo Zanoni (4):
drm/i915/icl: add the main CDCLK functions
drm/i915/icl: add ICL support to cnl_set_procmon_ref_values
drm/i915/icl: implement the display init/uninit sequences
drm/i915/gen11: fix the SAGV block time for gen11

drivers/gpu/drm/i915/i915_drv.h | 2 +
drivers/gpu/drm/i915/i915_reg.h | 85 ++++++++++-
drivers/gpu/drm/i915/intel_cdclk.c | 253 +++++++++++++++++++++++++++++++-
drivers/gpu/drm/i915/intel_display.c | 42 +++++-
drivers/gpu/drm/i915/intel_drv.h | 8 +
drivers/gpu/drm/i915/intel_pm.c | 173 ++++++++++++++++++----
drivers/gpu/drm/i915/intel_runtime_pm.c | 188 ++++++++++++++++++++++--
7 files changed, 706 insertions(+), 45 deletions(-)

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2.14.3