* [PATCH 2/4] drm/i915/icl: Show interrupt registers in debugfs
2018-02-20 15:37 [PATCH 1/4] drm/i915/icl: Add the ICL PCI IDs Mika Kuoppala
@ 2018-02-20 15:37 ` Mika Kuoppala
2018-02-22 0:54 ` Daniele Ceraolo Spurio
2018-02-20 15:37 ` [PATCH 3/4] drm/i915/icl: Prepare for more rings Mika Kuoppala
` (4 subsequent siblings)
5 siblings, 1 reply; 13+ messages in thread
From: Mika Kuoppala @ 2018-02-20 15:37 UTC (permalink / raw)
To: intel-gfx; +Cc: Spurio, Ceraolo, Rodrigo Vivi
From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Show GEN11 specific interrupt registers in debugfs
v2: Update for POR changes. (Daniele Ceraolo Spurio)
v3: get runtime pm ref. unify common parts with gen8 (Daniele)
Cc: Ceraolo Spurio, Daniele <daniele.ceraolospurio@intel.com>
Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: Mika Kuoppala <mika.kuoppala@linux.intel.com>
---
drivers/gpu/drm/i915/i915_debugfs.c | 139 ++++++++++++++++++++++++------------
1 file changed, 95 insertions(+), 44 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
index 05b41045b8f9..d4991b335cf5 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -646,6 +646,56 @@ static int i915_gem_batch_pool_info(struct seq_file *m, void *data)
return 0;
}
+static void gen8_display_interrupt_info(struct seq_file *m)
+{
+ struct drm_i915_private *dev_priv = node_to_i915(m->private);
+ int pipe;
+
+ for_each_pipe(dev_priv, pipe) {
+ enum intel_display_power_domain power_domain;
+
+ power_domain = POWER_DOMAIN_PIPE(pipe);
+ if (!intel_display_power_get_if_enabled(dev_priv,
+ power_domain)) {
+ seq_printf(m, "Pipe %c power disabled\n",
+ pipe_name(pipe));
+ continue;
+ }
+ seq_printf(m, "Pipe %c IMR:\t%08x\n",
+ pipe_name(pipe),
+ I915_READ(GEN8_DE_PIPE_IMR(pipe)));
+ seq_printf(m, "Pipe %c IIR:\t%08x\n",
+ pipe_name(pipe),
+ I915_READ(GEN8_DE_PIPE_IIR(pipe)));
+ seq_printf(m, "Pipe %c IER:\t%08x\n",
+ pipe_name(pipe),
+ I915_READ(GEN8_DE_PIPE_IER(pipe)));
+
+ intel_display_power_put(dev_priv, power_domain);
+ }
+
+ seq_printf(m, "Display Engine port interrupt mask:\t%08x\n",
+ I915_READ(GEN8_DE_PORT_IMR));
+ seq_printf(m, "Display Engine port interrupt identity:\t%08x\n",
+ I915_READ(GEN8_DE_PORT_IIR));
+ seq_printf(m, "Display Engine port interrupt enable:\t%08x\n",
+ I915_READ(GEN8_DE_PORT_IER));
+
+ seq_printf(m, "Display Engine misc interrupt mask:\t%08x\n",
+ I915_READ(GEN8_DE_MISC_IMR));
+ seq_printf(m, "Display Engine misc interrupt identity:\t%08x\n",
+ I915_READ(GEN8_DE_MISC_IIR));
+ seq_printf(m, "Display Engine misc interrupt enable:\t%08x\n",
+ I915_READ(GEN8_DE_MISC_IER));
+
+ seq_printf(m, "PCU interrupt mask:\t%08x\n",
+ I915_READ(GEN8_PCU_IMR));
+ seq_printf(m, "PCU interrupt identity:\t%08x\n",
+ I915_READ(GEN8_PCU_IIR));
+ seq_printf(m, "PCU interrupt enable:\t%08x\n",
+ I915_READ(GEN8_PCU_IER));
+}
+
static int i915_interrupt_info(struct seq_file *m, void *data)
{
struct drm_i915_private *dev_priv = node_to_i915(m->private);
@@ -709,6 +759,27 @@ static int i915_interrupt_info(struct seq_file *m, void *data)
I915_READ(GEN8_PCU_IIR));
seq_printf(m, "PCU interrupt enable:\t%08x\n",
I915_READ(GEN8_PCU_IER));
+ } else if (INTEL_GEN(dev_priv) >= 11) {
+ seq_printf(m, "Master Interrupt Control: %08x\n",
+ I915_READ(GEN11_GFX_MSTR_IRQ));
+
+ seq_printf(m, "Render/Copy Intr Enable: %08x\n",
+ I915_READ(GEN11_RENDER_COPY_INTR_ENABLE));
+ seq_printf(m, "VCS/VECS Intr Enable: %08x\n",
+ I915_READ(GEN11_VCS_VECS_INTR_ENABLE));
+ seq_printf(m, "GUC/SG Intr Enable:\t %08x\n",
+ I915_READ(GEN11_GUC_SG_INTR_ENABLE));
+ seq_printf(m, "GPM/WGBOXPERF Intr Enable: %08x\n",
+ I915_READ(GEN11_GPM_WGBOXPERF_INTR_ENABLE));
+ seq_printf(m, "Crypto Intr Enable:\t %08x\n",
+ I915_READ(GEN11_CRYPTO_RSVD_INTR_ENABLE));
+ seq_printf(m, "GUnit/CSME Intr Enable:\t %08x\n",
+ I915_READ(GEN11_GUNIT_CSME_INTR_ENABLE));
+
+ seq_printf(m, "Display Interrupt Control:\t%08x\n",
+ I915_READ(GEN11_DISPLAY_INT_CTL));
+
+ gen8_display_interrupt_info(m);
} else if (INTEL_GEN(dev_priv) >= 8) {
seq_printf(m, "Master Interrupt Control:\t%08x\n",
I915_READ(GEN8_MASTER_IRQ));
@@ -722,49 +793,7 @@ static int i915_interrupt_info(struct seq_file *m, void *data)
i, I915_READ(GEN8_GT_IER(i)));
}
- for_each_pipe(dev_priv, pipe) {
- enum intel_display_power_domain power_domain;
-
- power_domain = POWER_DOMAIN_PIPE(pipe);
- if (!intel_display_power_get_if_enabled(dev_priv,
- power_domain)) {
- seq_printf(m, "Pipe %c power disabled\n",
- pipe_name(pipe));
- continue;
- }
- seq_printf(m, "Pipe %c IMR:\t%08x\n",
- pipe_name(pipe),
- I915_READ(GEN8_DE_PIPE_IMR(pipe)));
- seq_printf(m, "Pipe %c IIR:\t%08x\n",
- pipe_name(pipe),
- I915_READ(GEN8_DE_PIPE_IIR(pipe)));
- seq_printf(m, "Pipe %c IER:\t%08x\n",
- pipe_name(pipe),
- I915_READ(GEN8_DE_PIPE_IER(pipe)));
-
- intel_display_power_put(dev_priv, power_domain);
- }
-
- seq_printf(m, "Display Engine port interrupt mask:\t%08x\n",
- I915_READ(GEN8_DE_PORT_IMR));
- seq_printf(m, "Display Engine port interrupt identity:\t%08x\n",
- I915_READ(GEN8_DE_PORT_IIR));
- seq_printf(m, "Display Engine port interrupt enable:\t%08x\n",
- I915_READ(GEN8_DE_PORT_IER));
-
- seq_printf(m, "Display Engine misc interrupt mask:\t%08x\n",
- I915_READ(GEN8_DE_MISC_IMR));
- seq_printf(m, "Display Engine misc interrupt identity:\t%08x\n",
- I915_READ(GEN8_DE_MISC_IIR));
- seq_printf(m, "Display Engine misc interrupt enable:\t%08x\n",
- I915_READ(GEN8_DE_MISC_IER));
-
- seq_printf(m, "PCU interrupt mask:\t%08x\n",
- I915_READ(GEN8_PCU_IMR));
- seq_printf(m, "PCU interrupt identity:\t%08x\n",
- I915_READ(GEN8_PCU_IIR));
- seq_printf(m, "PCU interrupt enable:\t%08x\n",
- I915_READ(GEN8_PCU_IER));
+ gen8_display_interrupt_info(m);
} else if (IS_VALLEYVIEW(dev_priv)) {
seq_printf(m, "Display IER:\t%08x\n",
I915_READ(VLV_IER));
@@ -846,13 +875,35 @@ static int i915_interrupt_info(struct seq_file *m, void *data)
seq_printf(m, "Graphics Interrupt mask: %08x\n",
I915_READ(GTIMR));
}
- if (INTEL_GEN(dev_priv) >= 6) {
+
+ if (INTEL_GEN(dev_priv) >= 11) {
+ seq_printf(m, "RCS Intr Mask:\t %08x\n",
+ I915_READ(GEN11_RCS0_RSVD_INTR_MASK));
+ seq_printf(m, "BCS Intr Mask:\t %08x\n",
+ I915_READ(GEN11_BCS_RSVD_INTR_MASK));
+ seq_printf(m, "VCS0/VCS1 Intr Mask:\t %08x\n",
+ I915_READ(GEN11_VCS0_VCS1_INTR_MASK));
+ seq_printf(m, "VCS2/VCS3 Intr Mask:\t %08x\n",
+ I915_READ(GEN11_VCS2_VCS3_INTR_MASK));
+ seq_printf(m, "VECS0/VECS1 Intr Mask:\t %08x\n",
+ I915_READ(GEN11_VECS0_VECS1_INTR_MASK));
+ seq_printf(m, "GUC/SG Intr Mask:\t %08x\n",
+ I915_READ(GEN11_GUC_SG_INTR_MASK));
+ seq_printf(m, "GPM/WGBOXPERF Intr Mask: %08x\n",
+ I915_READ(GEN11_GPM_WGBOXPERF_INTR_MASK));
+ seq_printf(m, "Crypto Intr Mask:\t %08x\n",
+ I915_READ(GEN11_CRYPTO_RSVD_INTR_MASK));
+ seq_printf(m, "Gunit/CSME Intr Mask:\t %08x\n",
+ I915_READ(GEN11_GUNIT_CSME_INTR_MASK));
+
+ } else if (INTEL_GEN(dev_priv) >= 6) {
for_each_engine(engine, dev_priv, id) {
seq_printf(m,
"Graphics Interrupt mask (%s): %08x\n",
engine->name, I915_READ_IMR(engine));
}
}
+
intel_runtime_pm_put(dev_priv);
return 0;
--
2.14.1
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 13+ messages in thread* Re: [PATCH 2/4] drm/i915/icl: Show interrupt registers in debugfs
2018-02-20 15:37 ` [PATCH 2/4] drm/i915/icl: Show interrupt registers in debugfs Mika Kuoppala
@ 2018-02-22 0:54 ` Daniele Ceraolo Spurio
2018-02-22 9:35 ` Mika Kuoppala
0 siblings, 1 reply; 13+ messages in thread
From: Daniele Ceraolo Spurio @ 2018-02-22 0:54 UTC (permalink / raw)
To: Mika Kuoppala, intel-gfx; +Cc: Spurio, Rodrigo Vivi, Ceraolo
On 20/02/18 07:37, Mika Kuoppala wrote:
> From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
>
> Show GEN11 specific interrupt registers in debugfs
>
> v2: Update for POR changes. (Daniele Ceraolo Spurio)
> v3: get runtime pm ref. unify common parts with gen8 (Daniele)
>
> Cc: Ceraolo Spurio, Daniele <daniele.ceraolospurio@intel.com>
> Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
> Signed-off-by: Mika Kuoppala <mika.kuoppala@linux.intel.com>
Reviewed-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
> ---
> drivers/gpu/drm/i915/i915_debugfs.c | 139 ++++++++++++++++++++++++------------
> 1 file changed, 95 insertions(+), 44 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
> index 05b41045b8f9..d4991b335cf5 100644
> --- a/drivers/gpu/drm/i915/i915_debugfs.c
> +++ b/drivers/gpu/drm/i915/i915_debugfs.c
> @@ -646,6 +646,56 @@ static int i915_gem_batch_pool_info(struct seq_file *m, void *data)
> return 0;
> }
>
> +static void gen8_display_interrupt_info(struct seq_file *m)
> +{
> + struct drm_i915_private *dev_priv = node_to_i915(m->private);
> + int pipe;
> +
> + for_each_pipe(dev_priv, pipe) {
> + enum intel_display_power_domain power_domain;
> +
> + power_domain = POWER_DOMAIN_PIPE(pipe);
> + if (!intel_display_power_get_if_enabled(dev_priv,
> + power_domain)) {
> + seq_printf(m, "Pipe %c power disabled\n",
> + pipe_name(pipe));
> + continue;
> + }
> + seq_printf(m, "Pipe %c IMR:\t%08x\n",
> + pipe_name(pipe),
> + I915_READ(GEN8_DE_PIPE_IMR(pipe)));
> + seq_printf(m, "Pipe %c IIR:\t%08x\n",
> + pipe_name(pipe),
> + I915_READ(GEN8_DE_PIPE_IIR(pipe)));
> + seq_printf(m, "Pipe %c IER:\t%08x\n",
> + pipe_name(pipe),
> + I915_READ(GEN8_DE_PIPE_IER(pipe)));
> +
> + intel_display_power_put(dev_priv, power_domain);
> + }
> +
> + seq_printf(m, "Display Engine port interrupt mask:\t%08x\n",
> + I915_READ(GEN8_DE_PORT_IMR));
> + seq_printf(m, "Display Engine port interrupt identity:\t%08x\n",
> + I915_READ(GEN8_DE_PORT_IIR));
> + seq_printf(m, "Display Engine port interrupt enable:\t%08x\n",
> + I915_READ(GEN8_DE_PORT_IER));
> +
> + seq_printf(m, "Display Engine misc interrupt mask:\t%08x\n",
> + I915_READ(GEN8_DE_MISC_IMR));
> + seq_printf(m, "Display Engine misc interrupt identity:\t%08x\n",
> + I915_READ(GEN8_DE_MISC_IIR));
> + seq_printf(m, "Display Engine misc interrupt enable:\t%08x\n",
> + I915_READ(GEN8_DE_MISC_IER));
> +
> + seq_printf(m, "PCU interrupt mask:\t%08x\n",
> + I915_READ(GEN8_PCU_IMR));
> + seq_printf(m, "PCU interrupt identity:\t%08x\n",
> + I915_READ(GEN8_PCU_IIR));
> + seq_printf(m, "PCU interrupt enable:\t%08x\n",
> + I915_READ(GEN8_PCU_IER));
> +}
> +
> static int i915_interrupt_info(struct seq_file *m, void *data)
> {
> struct drm_i915_private *dev_priv = node_to_i915(m->private);
> @@ -709,6 +759,27 @@ static int i915_interrupt_info(struct seq_file *m, void *data)
> I915_READ(GEN8_PCU_IIR));
> seq_printf(m, "PCU interrupt enable:\t%08x\n",
> I915_READ(GEN8_PCU_IER));
> + } else if (INTEL_GEN(dev_priv) >= 11) {
> + seq_printf(m, "Master Interrupt Control: %08x\n",
> + I915_READ(GEN11_GFX_MSTR_IRQ));
> +
> + seq_printf(m, "Render/Copy Intr Enable: %08x\n",
> + I915_READ(GEN11_RENDER_COPY_INTR_ENABLE));
> + seq_printf(m, "VCS/VECS Intr Enable: %08x\n",
> + I915_READ(GEN11_VCS_VECS_INTR_ENABLE));
> + seq_printf(m, "GUC/SG Intr Enable:\t %08x\n",
> + I915_READ(GEN11_GUC_SG_INTR_ENABLE));
> + seq_printf(m, "GPM/WGBOXPERF Intr Enable: %08x\n",
> + I915_READ(GEN11_GPM_WGBOXPERF_INTR_ENABLE));
> + seq_printf(m, "Crypto Intr Enable:\t %08x\n",
> + I915_READ(GEN11_CRYPTO_RSVD_INTR_ENABLE));
> + seq_printf(m, "GUnit/CSME Intr Enable:\t %08x\n",
> + I915_READ(GEN11_GUNIT_CSME_INTR_ENABLE));
> +
> + seq_printf(m, "Display Interrupt Control:\t%08x\n",
> + I915_READ(GEN11_DISPLAY_INT_CTL));
> +
> + gen8_display_interrupt_info(m);
> } else if (INTEL_GEN(dev_priv) >= 8) {
> seq_printf(m, "Master Interrupt Control:\t%08x\n",
> I915_READ(GEN8_MASTER_IRQ));
> @@ -722,49 +793,7 @@ static int i915_interrupt_info(struct seq_file *m, void *data)
> i, I915_READ(GEN8_GT_IER(i)));
> }
>
> - for_each_pipe(dev_priv, pipe) {
> - enum intel_display_power_domain power_domain;
> -
> - power_domain = POWER_DOMAIN_PIPE(pipe);
> - if (!intel_display_power_get_if_enabled(dev_priv,
> - power_domain)) {
> - seq_printf(m, "Pipe %c power disabled\n",
> - pipe_name(pipe));
> - continue;
> - }
> - seq_printf(m, "Pipe %c IMR:\t%08x\n",
> - pipe_name(pipe),
> - I915_READ(GEN8_DE_PIPE_IMR(pipe)));
> - seq_printf(m, "Pipe %c IIR:\t%08x\n",
> - pipe_name(pipe),
> - I915_READ(GEN8_DE_PIPE_IIR(pipe)));
> - seq_printf(m, "Pipe %c IER:\t%08x\n",
> - pipe_name(pipe),
> - I915_READ(GEN8_DE_PIPE_IER(pipe)));
> -
> - intel_display_power_put(dev_priv, power_domain);
> - }
> -
> - seq_printf(m, "Display Engine port interrupt mask:\t%08x\n",
> - I915_READ(GEN8_DE_PORT_IMR));
> - seq_printf(m, "Display Engine port interrupt identity:\t%08x\n",
> - I915_READ(GEN8_DE_PORT_IIR));
> - seq_printf(m, "Display Engine port interrupt enable:\t%08x\n",
> - I915_READ(GEN8_DE_PORT_IER));
> -
> - seq_printf(m, "Display Engine misc interrupt mask:\t%08x\n",
> - I915_READ(GEN8_DE_MISC_IMR));
> - seq_printf(m, "Display Engine misc interrupt identity:\t%08x\n",
> - I915_READ(GEN8_DE_MISC_IIR));
> - seq_printf(m, "Display Engine misc interrupt enable:\t%08x\n",
> - I915_READ(GEN8_DE_MISC_IER));
> -
> - seq_printf(m, "PCU interrupt mask:\t%08x\n",
> - I915_READ(GEN8_PCU_IMR));
> - seq_printf(m, "PCU interrupt identity:\t%08x\n",
> - I915_READ(GEN8_PCU_IIR));
> - seq_printf(m, "PCU interrupt enable:\t%08x\n",
> - I915_READ(GEN8_PCU_IER));
> + gen8_display_interrupt_info(m);
> } else if (IS_VALLEYVIEW(dev_priv)) {
> seq_printf(m, "Display IER:\t%08x\n",
> I915_READ(VLV_IER));
> @@ -846,13 +875,35 @@ static int i915_interrupt_info(struct seq_file *m, void *data)
> seq_printf(m, "Graphics Interrupt mask: %08x\n",
> I915_READ(GTIMR));
> }
> - if (INTEL_GEN(dev_priv) >= 6) {
> +
> + if (INTEL_GEN(dev_priv) >= 11) {
> + seq_printf(m, "RCS Intr Mask:\t %08x\n",
> + I915_READ(GEN11_RCS0_RSVD_INTR_MASK));
> + seq_printf(m, "BCS Intr Mask:\t %08x\n",
> + I915_READ(GEN11_BCS_RSVD_INTR_MASK));
> + seq_printf(m, "VCS0/VCS1 Intr Mask:\t %08x\n",
> + I915_READ(GEN11_VCS0_VCS1_INTR_MASK));
> + seq_printf(m, "VCS2/VCS3 Intr Mask:\t %08x\n",
> + I915_READ(GEN11_VCS2_VCS3_INTR_MASK));
> + seq_printf(m, "VECS0/VECS1 Intr Mask:\t %08x\n",
> + I915_READ(GEN11_VECS0_VECS1_INTR_MASK));
> + seq_printf(m, "GUC/SG Intr Mask:\t %08x\n",
> + I915_READ(GEN11_GUC_SG_INTR_MASK));
> + seq_printf(m, "GPM/WGBOXPERF Intr Mask: %08x\n",
> + I915_READ(GEN11_GPM_WGBOXPERF_INTR_MASK));
> + seq_printf(m, "Crypto Intr Mask:\t %08x\n",
> + I915_READ(GEN11_CRYPTO_RSVD_INTR_MASK));
> + seq_printf(m, "Gunit/CSME Intr Mask:\t %08x\n",
> + I915_READ(GEN11_GUNIT_CSME_INTR_MASK));
> +
> + } else if (INTEL_GEN(dev_priv) >= 6) {
> for_each_engine(engine, dev_priv, id) {
> seq_printf(m,
> "Graphics Interrupt mask (%s): %08x\n",
> engine->name, I915_READ_IMR(engine));
> }
> }
> +
> intel_runtime_pm_put(dev_priv);
>
> return 0;
>
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^ permalink raw reply [flat|nested] 13+ messages in thread* Re: [PATCH 2/4] drm/i915/icl: Show interrupt registers in debugfs
2018-02-22 0:54 ` Daniele Ceraolo Spurio
@ 2018-02-22 9:35 ` Mika Kuoppala
0 siblings, 0 replies; 13+ messages in thread
From: Mika Kuoppala @ 2018-02-22 9:35 UTC (permalink / raw)
To: Daniele Ceraolo Spurio, intel-gfx; +Cc: Spurio, Rodrigo Vivi, Ceraolo
Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com> writes:
> On 20/02/18 07:37, Mika Kuoppala wrote:
>> From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
>>
>> Show GEN11 specific interrupt registers in debugfs
>>
>> v2: Update for POR changes. (Daniele Ceraolo Spurio)
>> v3: get runtime pm ref. unify common parts with gen8 (Daniele)
>>
>> Cc: Ceraolo Spurio, Daniele <daniele.ceraolospurio@intel.com>
>> Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
>> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
>> Signed-off-by: Mika Kuoppala <mika.kuoppala@linux.intel.com>
>
> Reviewed-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Pushed 1/4 and this one. Thank you for patches and review.
-Mika
_______________________________________________
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 13+ messages in thread
* [PATCH 3/4] drm/i915/icl: Prepare for more rings
2018-02-20 15:37 [PATCH 1/4] drm/i915/icl: Add the ICL PCI IDs Mika Kuoppala
2018-02-20 15:37 ` [PATCH 2/4] drm/i915/icl: Show interrupt registers in debugfs Mika Kuoppala
@ 2018-02-20 15:37 ` Mika Kuoppala
2018-03-01 12:23 ` Mika Kuoppala
2018-02-20 15:37 ` [PATCH 4/4] drm/i915/icl: Interrupt handling Mika Kuoppala
` (3 subsequent siblings)
5 siblings, 1 reply; 13+ messages in thread
From: Mika Kuoppala @ 2018-02-20 15:37 UTC (permalink / raw)
To: intel-gfx; +Cc: Rodrigo Vivi
From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Gen11 will add more VCS and VECS rings so prepare the
infrastructure to support that.
Bspec: 7021
v2: Rebase.
v3: Rebase.
v4: Rebase.
v5: Rebase.
v6:
- Update for POR changes. (Daniele Ceraolo Spurio)
- Add provisional guc engine ids - to be checked and confirmed.
v7:
- Rebased.
- Added the new ring masks.
- Added the new HW ids.
v8:
- Introduce I915_MAX_VCS/VECS to avoid magic numbers (Michal)
v9: increase MAX_ENGINE_INSTANCE to 3
Cc: Michal Wajdeczko <michal.wajdeczko@intel.com>
Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: Oscar Mateo <oscar.mateo@intel.com>
Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Reviewed-by: Oscar Mateo <oscar.mateo@intel.com>
---
drivers/gpu/drm/i915/i915_drv.h | 3 +++
drivers/gpu/drm/i915/i915_gem.h | 2 +-
drivers/gpu/drm/i915/i915_reg.h | 5 ++++-
drivers/gpu/drm/i915/intel_device_info.c | 3 +++
drivers/gpu/drm/i915/intel_device_info.h | 4 +++-
drivers/gpu/drm/i915/intel_ringbuffer.h | 9 ++++++++-
6 files changed, 22 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 76bfe909168c..2041441f098e 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -2740,6 +2740,9 @@ intel_info(const struct drm_i915_private *dev_priv)
#define BLT_RING ENGINE_MASK(BCS)
#define VEBOX_RING ENGINE_MASK(VECS)
#define BSD2_RING ENGINE_MASK(VCS2)
+#define BSD3_RING ENGINE_MASK(VCS3)
+#define BSD4_RING ENGINE_MASK(VCS4)
+#define VEBOX2_RING ENGINE_MASK(VECS2)
#define ALL_ENGINES (~0)
#define HAS_ENGINE(dev_priv, id) \
diff --git a/drivers/gpu/drm/i915/i915_gem.h b/drivers/gpu/drm/i915/i915_gem.h
index e920dab7f1b8..1b61b7f8c2ec 100644
--- a/drivers/gpu/drm/i915/i915_gem.h
+++ b/drivers/gpu/drm/i915/i915_gem.h
@@ -54,6 +54,6 @@
#define GEM_TRACE(...) do { } while (0)
#endif
-#define I915_NUM_ENGINES 5
+#define I915_NUM_ENGINES 8
#endif /* __I915_GEM_H__ */
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 1412abcb27d4..784d79cbff80 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -178,6 +178,9 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
#define BCS_HW 2
#define VECS_HW 3
#define VCS2_HW 4
+#define VCS3_HW 6
+#define VCS4_HW 7
+#define VECS2_HW 12
/* Engine class */
@@ -188,7 +191,7 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
#define OTHER_CLASS 4
#define MAX_ENGINE_CLASS 4
-#define MAX_ENGINE_INSTANCE 1
+#define MAX_ENGINE_INSTANCE 3
/* PCI config space */
diff --git a/drivers/gpu/drm/i915/intel_device_info.c b/drivers/gpu/drm/i915/intel_device_info.c
index 298f8996cc54..9352f34e75c4 100644
--- a/drivers/gpu/drm/i915/intel_device_info.c
+++ b/drivers/gpu/drm/i915/intel_device_info.c
@@ -489,6 +489,9 @@ void intel_device_info_runtime_init(struct intel_device_info *info)
info->num_scalers[PIPE_C] = 1;
}
+ BUILD_BUG_ON(I915_NUM_ENGINES >
+ sizeof(intel_ring_mask_t) * BITS_PER_BYTE);
+
/*
* Skylake and Broxton currently don't expose the topmost plane as its
* use is exclusive with the legacy cursor and we only want to expose
diff --git a/drivers/gpu/drm/i915/intel_device_info.h b/drivers/gpu/drm/i915/intel_device_info.h
index 71fdfb0451ef..4c6f83b2dd6a 100644
--- a/drivers/gpu/drm/i915/intel_device_info.h
+++ b/drivers/gpu/drm/i915/intel_device_info.h
@@ -125,6 +125,8 @@ struct sseu_dev_info {
u8 has_eu_pg:1;
};
+typedef u8 intel_ring_mask_t;
+
struct intel_device_info {
u16 device_id;
u16 gen_mask;
@@ -132,7 +134,7 @@ struct intel_device_info {
u8 gen;
u8 gt; /* GT number, 0 if undefined */
u8 num_rings;
- u8 ring_mask; /* Rings supported by the HW */
+ intel_ring_mask_t ring_mask; /* Rings supported by the HW */
enum intel_platform platform;
u32 platform_mask;
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.h b/drivers/gpu/drm/i915/intel_ringbuffer.h
index 51523ad049de..f743351c441f 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.h
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.h
@@ -158,6 +158,9 @@ struct i915_ctx_workarounds {
struct drm_i915_gem_request;
+#define I915_MAX_VCS 4
+#define I915_MAX_VECS 2
+
/*
* Engine IDs definitions.
* Keep instances of the same type engine together.
@@ -167,8 +170,12 @@ enum intel_engine_id {
BCS,
VCS,
VCS2,
+ VCS3,
+ VCS4,
#define _VCS(n) (VCS + (n))
- VECS
+ VECS,
+ VECS2
+#define _VECS(n) (VECS + (n))
};
struct i915_priolist {
--
2.14.1
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 13+ messages in thread* Re: [PATCH 3/4] drm/i915/icl: Prepare for more rings
2018-02-20 15:37 ` [PATCH 3/4] drm/i915/icl: Prepare for more rings Mika Kuoppala
@ 2018-03-01 12:23 ` Mika Kuoppala
0 siblings, 0 replies; 13+ messages in thread
From: Mika Kuoppala @ 2018-03-01 12:23 UTC (permalink / raw)
To: intel-gfx; +Cc: Rodrigo Vivi
Mika Kuoppala <mika.kuoppala@linux.intel.com> writes:
> From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
>
> Gen11 will add more VCS and VECS rings so prepare the
> infrastructure to support that.
>
> Bspec: 7021
>
> v2: Rebase.
> v3: Rebase.
> v4: Rebase.
> v5: Rebase.
> v6:
> - Update for POR changes. (Daniele Ceraolo Spurio)
> - Add provisional guc engine ids - to be checked and confirmed.
> v7:
> - Rebased.
> - Added the new ring masks.
> - Added the new HW ids.
> v8:
> - Introduce I915_MAX_VCS/VECS to avoid magic numbers (Michal)
>
> v9: increase MAX_ENGINE_INSTANCE to 3
>
> Cc: Michal Wajdeczko <michal.wajdeczko@intel.com>
> Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
> Signed-off-by: Oscar Mateo <oscar.mateo@intel.com>
> Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
> Reviewed-by: Oscar Mateo <oscar.mateo@intel.com>
Pushed. Thanks for patch and review.
-Mika
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^ permalink raw reply [flat|nested] 13+ messages in thread
* [PATCH 4/4] drm/i915/icl: Interrupt handling
2018-02-20 15:37 [PATCH 1/4] drm/i915/icl: Add the ICL PCI IDs Mika Kuoppala
2018-02-20 15:37 ` [PATCH 2/4] drm/i915/icl: Show interrupt registers in debugfs Mika Kuoppala
2018-02-20 15:37 ` [PATCH 3/4] drm/i915/icl: Prepare for more rings Mika Kuoppala
@ 2018-02-20 15:37 ` Mika Kuoppala
2018-02-27 19:51 ` Daniele Ceraolo Spurio
2018-02-20 16:05 ` ✗ Fi.CI.CHECKPATCH: warning for series starting with [1/4] drm/i915/icl: Add the ICL PCI IDs Patchwork
` (2 subsequent siblings)
5 siblings, 1 reply; 13+ messages in thread
From: Mika Kuoppala @ 2018-02-20 15:37 UTC (permalink / raw)
To: intel-gfx; +Cc: Paulo Zanoni, Rodrigo Vivi
v2: Rebase.
v3:
* Remove DPF, it has been removed from SKL+.
* Fix -internal rebase wrt. execlists interrupt handling.
v4: Rebase.
v5:
* Updated for POR changes. (Daniele Ceraolo Spurio)
* Merged with irq handling fixes by Daniele Ceraolo Spurio:
* Simplify the code by using gen8_cs_irq_handler.
* Fix interrupt handling for the upstream kernel.
v6:
* Remove early bringup debug messages (Tvrtko)
* Add NB about arbitrary spin wait timeout (Tvrtko)
v7 (from Paulo):
* Don't try to write RO bits to registers.
* Don't check for PCH types that don't exist. PCH interrupts are not
here yet.
v9:
* squashed in selector and shared register handling (Daniele)
* skip writing of irq if data is not valid (Daniele)
* use time_after32 (Chris)
* use I915_MAX_VCS and I915_MAX_VECS (Daniele)
* remove fake pm interrupt handling for later patch (Mika)
v10:
* Direct processing of banks. clear banks early (Chris)
* remove poll on valid bit, only clear valid bit (Mika)
* use raw accessors, better naming (Chris)
v11:
* adapt to raw_reg_[read|write]
* bring back polling the valid bit (Daniele)
Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Oscar Mateo <oscar.mateo@intel.com>
Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Signed-off-by: Oscar Mateo <oscar.mateo@intel.com>
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Signed-off-by: Mika Kuoppala <mika.kuoppala@linux.intel.com>
---
drivers/gpu/drm/i915/i915_irq.c | 229 ++++++++++++++++++++++++++++++++++++++++
drivers/gpu/drm/i915/intel_pm.c | 7 +-
2 files changed, 235 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 17de6cef2a30..a79f47ac742a 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -415,6 +415,9 @@ void gen6_enable_rps_interrupts(struct drm_i915_private *dev_priv)
if (READ_ONCE(rps->interrupts_enabled))
return;
+ if (WARN_ON_ONCE(IS_GEN11(dev_priv)))
+ return;
+
spin_lock_irq(&dev_priv->irq_lock);
WARN_ON_ONCE(rps->pm_iir);
WARN_ON_ONCE(I915_READ(gen6_pm_iir(dev_priv)) & dev_priv->pm_rps_events);
@@ -431,6 +434,9 @@ void gen6_disable_rps_interrupts(struct drm_i915_private *dev_priv)
if (!READ_ONCE(rps->interrupts_enabled))
return;
+ if (WARN_ON_ONCE(IS_GEN11(dev_priv)))
+ return;
+
spin_lock_irq(&dev_priv->irq_lock);
rps->interrupts_enabled = false;
@@ -2755,6 +2761,150 @@ static void __fini_wedge(struct wedge_me *w)
(W)->i915; \
__fini_wedge((W)))
+static __always_inline void
+gen11_cs_irq_handler(struct intel_engine_cs * const engine, const u32 iir)
+{
+ gen8_cs_irq_handler(engine, iir, 0);
+}
+
+static void
+gen11_gt_engine_irq_handler(struct drm_i915_private * const i915,
+ const unsigned int bank,
+ const unsigned int engine_n,
+ const u16 iir)
+{
+ struct intel_engine_cs ** const engine = i915->engine;
+
+ switch (bank) {
+ case 0:
+ switch (engine_n) {
+
+ case GEN11_RCS0:
+ return gen11_cs_irq_handler(engine[RCS], iir);
+
+ case GEN11_BCS:
+ return gen11_cs_irq_handler(engine[BCS], iir);
+ }
+ case 1:
+ switch (engine_n) {
+
+ case GEN11_VCS(0):
+ return gen11_cs_irq_handler(engine[_VCS(0)], iir);
+ case GEN11_VCS(1):
+ return gen11_cs_irq_handler(engine[_VCS(1)], iir);
+ case GEN11_VCS(2):
+ return gen11_cs_irq_handler(engine[_VCS(2)], iir);
+ case GEN11_VCS(3):
+ return gen11_cs_irq_handler(engine[_VCS(3)], iir);
+
+ case GEN11_VECS(0):
+ return gen11_cs_irq_handler(engine[_VECS(0)], iir);
+ case GEN11_VECS(1):
+ return gen11_cs_irq_handler(engine[_VECS(1)], iir);
+ }
+ }
+}
+
+static u32
+gen11_gt_engine_intr(struct drm_i915_private * const i915,
+ const unsigned int bank, const unsigned int bit)
+{
+ void __iomem * const regs = i915->regs;
+ u32 timeout_ts;
+ u32 ident;
+
+ raw_reg_write(regs, GEN11_IIR_REG_SELECTOR(bank), BIT(bit));
+
+ /*
+ * NB: Specs do not specify how long to spin wait,
+ * so we do ~100us as an educated guess.
+ */
+ timeout_ts = (local_clock() >> 10) + 100;
+ do {
+ ident = raw_reg_read(regs, GEN11_INTR_IDENTITY_REG(bank));
+ } while (!(ident & GEN11_INTR_DATA_VALID) &&
+ !time_after32(local_clock() >> 10, timeout_ts));
+
+ if (unlikely(!(ident & GEN11_INTR_DATA_VALID))) {
+ DRM_ERROR("INTR_IDENTITY_REG%u:%u 0x%08x not valid!\n",
+ bank, bit, ident);
+ return 0;
+ }
+
+ raw_reg_write(regs, GEN11_INTR_IDENTITY_REG(bank),
+ GEN11_INTR_DATA_VALID);
+
+ return ident & GEN11_INTR_ENGINE_MASK;
+}
+
+static void
+gen11_gt_irq_handler(struct drm_i915_private * const i915,
+ const u32 master_ctl)
+{
+ void __iomem * const regs = i915->regs;
+ unsigned int bank;
+
+ for (bank = 0; bank < 2; bank++) {
+ unsigned long intr_dw;
+ unsigned int bit;
+
+ if (!(master_ctl & GEN11_GT_DW_IRQ(bank)))
+ continue;
+
+ intr_dw = raw_reg_read(regs, GEN11_GT_INTR_DW(bank));
+
+ if (unlikely(!intr_dw))
+ DRM_ERROR("GT_INTR_DW%u blank!\n", bank);
+
+ for_each_set_bit(bit, &intr_dw, 32) {
+ const u16 iir = gen11_gt_engine_intr(i915, bank, bit);
+
+ if (unlikely(!iir))
+ continue;
+
+ gen11_gt_engine_irq_handler(i915, bank, bit, iir);
+ }
+
+ /* Clear must be after shared has been served for engine */
+ raw_reg_write(regs, GEN11_GT_INTR_DW(bank), intr_dw);
+ }
+}
+
+static irqreturn_t gen11_irq_handler(int irq, void *arg)
+{
+ struct drm_i915_private * const i915 = to_i915(arg);
+ void __iomem * const regs = i915->regs;
+ u32 master_ctl;
+
+ if (!intel_irqs_enabled(i915))
+ return IRQ_NONE;
+
+ master_ctl = raw_reg_read(regs, GEN11_GFX_MSTR_IRQ);
+ master_ctl &= ~GEN11_MASTER_IRQ;
+ if (!master_ctl)
+ return IRQ_NONE;
+
+ /* Disable interrupts. */
+ raw_reg_write(regs, GEN11_GFX_MSTR_IRQ, 0);
+
+ /* Find, clear, then process each source of interrupt. */
+ gen11_gt_irq_handler(i915, master_ctl);
+
+ /* IRQs are synced during runtime_suspend, we don't require a wakeref */
+ if (master_ctl & GEN11_DISPLAY_IRQ) {
+ const u32 disp_ctl = raw_reg_read(regs, GEN11_DISPLAY_INT_CTL);
+
+ disable_rpm_wakeref_asserts(i915);
+ gen8_de_irq_handler(i915, disp_ctl);
+ enable_rpm_wakeref_asserts(i915);
+ }
+
+ /* Acknowledge and enable interrupts. */
+ raw_reg_write(regs, GEN11_GFX_MSTR_IRQ, GEN11_MASTER_IRQ | master_ctl);
+
+ return IRQ_HANDLED;
+}
+
/**
* i915_reset_device - do process context error handling work
* @dev_priv: i915 device private
@@ -3180,6 +3330,42 @@ static void gen8_irq_reset(struct drm_device *dev)
ibx_irq_reset(dev_priv);
}
+static void gen11_gt_irq_reset(struct drm_i915_private *dev_priv)
+{
+ /* Disable RCS, BCS, VCS and VECS class engines. */
+ I915_WRITE(GEN11_RENDER_COPY_INTR_ENABLE, 0);
+ I915_WRITE(GEN11_VCS_VECS_INTR_ENABLE, 0);
+
+ /* Restore masks irqs on RCS, BCS, VCS and VECS engines. */
+ I915_WRITE(GEN11_RCS0_RSVD_INTR_MASK, ~0);
+ I915_WRITE(GEN11_BCS_RSVD_INTR_MASK, ~0);
+ I915_WRITE(GEN11_VCS0_VCS1_INTR_MASK, ~0);
+ I915_WRITE(GEN11_VCS2_VCS3_INTR_MASK, ~0);
+ I915_WRITE(GEN11_VECS0_VECS1_INTR_MASK, ~0);
+}
+
+static void gen11_irq_reset(struct drm_device *dev)
+{
+ struct drm_i915_private *dev_priv = dev->dev_private;
+ int pipe;
+
+ I915_WRITE(GEN11_GFX_MSTR_IRQ, 0);
+ POSTING_READ(GEN11_GFX_MSTR_IRQ);
+
+ gen11_gt_irq_reset(dev_priv);
+
+ I915_WRITE(GEN11_DISPLAY_INT_CTL, 0);
+
+ for_each_pipe(dev_priv, pipe)
+ if (intel_display_power_is_enabled(dev_priv,
+ POWER_DOMAIN_PIPE(pipe)))
+ GEN8_IRQ_RESET_NDX(DE_PIPE, pipe);
+
+ GEN3_IRQ_RESET(GEN8_DE_PORT_);
+ GEN3_IRQ_RESET(GEN8_DE_MISC_);
+ GEN3_IRQ_RESET(GEN8_PCU_);
+}
+
void gen8_irq_power_well_post_enable(struct drm_i915_private *dev_priv,
u8 pipe_mask)
{
@@ -3677,6 +3863,41 @@ static int gen8_irq_postinstall(struct drm_device *dev)
return 0;
}
+static void gen11_gt_irq_postinstall(struct drm_i915_private *dev_priv)
+{
+ const u32 irqs = GT_RENDER_USER_INTERRUPT | GT_CONTEXT_SWITCH_INTERRUPT;
+
+ BUILD_BUG_ON(irqs & 0xffff0000);
+
+ /* Enable RCS, BCS, VCS and VECS class interrupts. */
+ I915_WRITE(GEN11_RENDER_COPY_INTR_ENABLE, irqs << 16 | irqs);
+ I915_WRITE(GEN11_VCS_VECS_INTR_ENABLE, irqs << 16 | irqs);
+
+ /* Unmask irqs on RCS, BCS, VCS and VECS engines. */
+ I915_WRITE(GEN11_RCS0_RSVD_INTR_MASK, ~(irqs << 16));
+ I915_WRITE(GEN11_BCS_RSVD_INTR_MASK, ~(irqs << 16));
+ I915_WRITE(GEN11_VCS0_VCS1_INTR_MASK, ~(irqs | irqs << 16));
+ I915_WRITE(GEN11_VCS2_VCS3_INTR_MASK, ~(irqs | irqs << 16));
+ I915_WRITE(GEN11_VECS0_VECS1_INTR_MASK, ~(irqs | irqs << 16));
+
+ dev_priv->pm_imr = 0xffffffff; /* TODO */
+}
+
+static int gen11_irq_postinstall(struct drm_device *dev)
+{
+ struct drm_i915_private *dev_priv = dev->dev_private;
+
+ gen11_gt_irq_postinstall(dev_priv);
+ gen8_de_irq_postinstall(dev_priv);
+
+ I915_WRITE(GEN11_DISPLAY_INT_CTL, GEN11_DISPLAY_IRQ_ENABLE);
+
+ I915_WRITE(GEN11_GFX_MSTR_IRQ, GEN11_MASTER_IRQ);
+ POSTING_READ(GEN11_GFX_MSTR_IRQ);
+
+ return 0;
+}
+
static int cherryview_irq_postinstall(struct drm_device *dev)
{
struct drm_i915_private *dev_priv = to_i915(dev);
@@ -4125,6 +4346,14 @@ void intel_irq_init(struct drm_i915_private *dev_priv)
dev->driver->enable_vblank = i965_enable_vblank;
dev->driver->disable_vblank = i965_disable_vblank;
dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup;
+ } else if (INTEL_GEN(dev_priv) >= 11) {
+ dev->driver->irq_handler = gen11_irq_handler;
+ dev->driver->irq_preinstall = gen11_irq_reset;
+ dev->driver->irq_postinstall = gen11_irq_postinstall;
+ dev->driver->irq_uninstall = gen11_irq_reset;
+ dev->driver->enable_vblank = gen8_enable_vblank;
+ dev->driver->disable_vblank = gen8_disable_vblank;
+ dev_priv->display.hpd_irq_setup = spt_hpd_irq_setup;
} else if (INTEL_GEN(dev_priv) >= 8) {
dev->driver->irq_handler = gen8_irq_handler;
dev->driver->irq_preinstall = gen8_irq_reset;
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index a88f0f213604..7a316f867b42 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -8030,7 +8030,10 @@ void intel_sanitize_gt_powersave(struct drm_i915_private *dev_priv)
dev_priv->gt_pm.rc6.enabled = true; /* force RC6 disabling */
intel_disable_gt_powersave(dev_priv);
- gen6_reset_rps_interrupts(dev_priv);
+ if (INTEL_GEN(dev_priv) < 11)
+ gen6_reset_rps_interrupts(dev_priv);
+ else
+ WARN_ON_ONCE(1);
}
static inline void intel_disable_llc_pstate(struct drm_i915_private *i915)
@@ -8143,6 +8146,8 @@ static void intel_enable_rps(struct drm_i915_private *dev_priv)
cherryview_enable_rps(dev_priv);
} else if (IS_VALLEYVIEW(dev_priv)) {
valleyview_enable_rps(dev_priv);
+ } else if (WARN_ON_ONCE(INTEL_GEN(dev_priv) >= 11)) {
+ /* TODO */
} else if (INTEL_GEN(dev_priv) >= 9) {
gen9_enable_rps(dev_priv);
} else if (IS_BROADWELL(dev_priv)) {
--
2.14.1
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^ permalink raw reply related [flat|nested] 13+ messages in thread* Re: [PATCH 4/4] drm/i915/icl: Interrupt handling
2018-02-20 15:37 ` [PATCH 4/4] drm/i915/icl: Interrupt handling Mika Kuoppala
@ 2018-02-27 19:51 ` Daniele Ceraolo Spurio
2018-02-27 21:18 ` Paulo Zanoni
0 siblings, 1 reply; 13+ messages in thread
From: Daniele Ceraolo Spurio @ 2018-02-27 19:51 UTC (permalink / raw)
To: Mika Kuoppala, intel-gfx; +Cc: Rodrigo Vivi, Paulo Zanoni
On 20/02/18 07:37, Mika Kuoppala wrote:
> v2: Rebase.
>
> v3:
> * Remove DPF, it has been removed from SKL+.
> * Fix -internal rebase wrt. execlists interrupt handling.
>
> v4: Rebase.
>
> v5:
> * Updated for POR changes. (Daniele Ceraolo Spurio)
> * Merged with irq handling fixes by Daniele Ceraolo Spurio:
> * Simplify the code by using gen8_cs_irq_handler.
> * Fix interrupt handling for the upstream kernel.
>
> v6:
> * Remove early bringup debug messages (Tvrtko)
> * Add NB about arbitrary spin wait timeout (Tvrtko)
>
> v7 (from Paulo):
> * Don't try to write RO bits to registers.
> * Don't check for PCH types that don't exist. PCH interrupts are not
> here yet.
>
> v9:
> * squashed in selector and shared register handling (Daniele)
> * skip writing of irq if data is not valid (Daniele)
> * use time_after32 (Chris)
> * use I915_MAX_VCS and I915_MAX_VECS (Daniele)
> * remove fake pm interrupt handling for later patch (Mika)
>
> v10:
> * Direct processing of banks. clear banks early (Chris)
> * remove poll on valid bit, only clear valid bit (Mika)
> * use raw accessors, better naming (Chris)
>
> v11:
> * adapt to raw_reg_[read|write]
> * bring back polling the valid bit (Daniele)
>
> Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
> Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
> Cc: Chris Wilson <chris@chris-wilson.co.uk>
> Cc: Oscar Mateo <oscar.mateo@intel.com>
> Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
> Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
> Signed-off-by: Oscar Mateo <oscar.mateo@intel.com>
> Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
> Signed-off-by: Mika Kuoppala <mika.kuoppala@linux.intel.com>
> ---
> drivers/gpu/drm/i915/i915_irq.c | 229 ++++++++++++++++++++++++++++++++++++++++
> drivers/gpu/drm/i915/intel_pm.c | 7 +-
> 2 files changed, 235 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
> index 17de6cef2a30..a79f47ac742a 100644
> --- a/drivers/gpu/drm/i915/i915_irq.c
> +++ b/drivers/gpu/drm/i915/i915_irq.c
> @@ -415,6 +415,9 @@ void gen6_enable_rps_interrupts(struct drm_i915_private *dev_priv)
> if (READ_ONCE(rps->interrupts_enabled))
> return;
>
> + if (WARN_ON_ONCE(IS_GEN11(dev_priv)))
> + return;
> +
> spin_lock_irq(&dev_priv->irq_lock);
> WARN_ON_ONCE(rps->pm_iir);
> WARN_ON_ONCE(I915_READ(gen6_pm_iir(dev_priv)) & dev_priv->pm_rps_events);
> @@ -431,6 +434,9 @@ void gen6_disable_rps_interrupts(struct drm_i915_private *dev_priv)
> if (!READ_ONCE(rps->interrupts_enabled))
> return;
>
> + if (WARN_ON_ONCE(IS_GEN11(dev_priv)))
> + return;
> +
> spin_lock_irq(&dev_priv->irq_lock);
> rps->interrupts_enabled = false;
>
> @@ -2755,6 +2761,150 @@ static void __fini_wedge(struct wedge_me *w)
> (W)->i915; \
> __fini_wedge((W)))
>
> +static __always_inline void
> +gen11_cs_irq_handler(struct intel_engine_cs * const engine, const u32 iir)
> +{
> + gen8_cs_irq_handler(engine, iir, 0);
> +}
> +
> +static void
> +gen11_gt_engine_irq_handler(struct drm_i915_private * const i915,
> + const unsigned int bank,
> + const unsigned int engine_n,
> + const u16 iir)
> +{
> + struct intel_engine_cs ** const engine = i915->engine;
> +
> + switch (bank) {
> + case 0:
> + switch (engine_n) {
> +
> + case GEN11_RCS0:
> + return gen11_cs_irq_handler(engine[RCS], iir);
> +
> + case GEN11_BCS:
> + return gen11_cs_irq_handler(engine[BCS], iir);
> + }
> + case 1:
> + switch (engine_n) {
> +
> + case GEN11_VCS(0):
> + return gen11_cs_irq_handler(engine[_VCS(0)], iir);
> + case GEN11_VCS(1):
> + return gen11_cs_irq_handler(engine[_VCS(1)], iir);
> + case GEN11_VCS(2):
> + return gen11_cs_irq_handler(engine[_VCS(2)], iir);
> + case GEN11_VCS(3):
> + return gen11_cs_irq_handler(engine[_VCS(3)], iir);
> +
> + case GEN11_VECS(0):
> + return gen11_cs_irq_handler(engine[_VECS(0)], iir);
> + case GEN11_VECS(1):
> + return gen11_cs_irq_handler(engine[_VECS(1)], iir);
> + }
> + }
> +}
> +
> +static u32
> +gen11_gt_engine_intr(struct drm_i915_private * const i915,
> + const unsigned int bank, const unsigned int bit)
> +{
> + void __iomem * const regs = i915->regs;
> + u32 timeout_ts;
> + u32 ident;
> +
> + raw_reg_write(regs, GEN11_IIR_REG_SELECTOR(bank), BIT(bit));
> +
> + /*
> + * NB: Specs do not specify how long to spin wait,
> + * so we do ~100us as an educated guess.
> + */
> + timeout_ts = (local_clock() >> 10) + 100;
> + do {
> + ident = raw_reg_read(regs, GEN11_INTR_IDENTITY_REG(bank));
> + } while (!(ident & GEN11_INTR_DATA_VALID) &&
> + !time_after32(local_clock() >> 10, timeout_ts));
> +
> + if (unlikely(!(ident & GEN11_INTR_DATA_VALID))) {
> + DRM_ERROR("INTR_IDENTITY_REG%u:%u 0x%08x not valid!\n",
> + bank, bit, ident);
> + return 0;
> + }
> +
> + raw_reg_write(regs, GEN11_INTR_IDENTITY_REG(bank),
> + GEN11_INTR_DATA_VALID);
> +
> + return ident & GEN11_INTR_ENGINE_MASK;
> +}
> +
> +static void
> +gen11_gt_irq_handler(struct drm_i915_private * const i915,
> + const u32 master_ctl)
> +{
> + void __iomem * const regs = i915->regs;
> + unsigned int bank;
> +
> + for (bank = 0; bank < 2; bank++) {
> + unsigned long intr_dw;
> + unsigned int bit;
> +
> + if (!(master_ctl & GEN11_GT_DW_IRQ(bank)))
> + continue;
> +
> + intr_dw = raw_reg_read(regs, GEN11_GT_INTR_DW(bank));
> +
> + if (unlikely(!intr_dw))
> + DRM_ERROR("GT_INTR_DW%u blank!\n", bank);
Could continue here, since the other operations in the loop won't be
meaningful if intr_dw=0
> +
> + for_each_set_bit(bit, &intr_dw, 32) {
> + const u16 iir = gen11_gt_engine_intr(i915, bank, bit);
> +
> + if (unlikely(!iir))
> + continue;
> +
> + gen11_gt_engine_irq_handler(i915, bank, bit, iir);
> + }
> +
> + /* Clear must be after shared has been served for engine */
> + raw_reg_write(regs, GEN11_GT_INTR_DW(bank), intr_dw);
> + }
> +}
> +
> +static irqreturn_t gen11_irq_handler(int irq, void *arg)
> +{
> + struct drm_i915_private * const i915 = to_i915(arg);
> + void __iomem * const regs = i915->regs;
> + u32 master_ctl;
> +
> + if (!intel_irqs_enabled(i915))
> + return IRQ_NONE;
> +
> + master_ctl = raw_reg_read(regs, GEN11_GFX_MSTR_IRQ);
> + master_ctl &= ~GEN11_MASTER_IRQ;
> + if (!master_ctl)
> + return IRQ_NONE;
> +
> + /* Disable interrupts. */
> + raw_reg_write(regs, GEN11_GFX_MSTR_IRQ, 0);
> +
> + /* Find, clear, then process each source of interrupt. */
> + gen11_gt_irq_handler(i915, master_ctl);
> +
> + /* IRQs are synced during runtime_suspend, we don't require a wakeref */
> + if (master_ctl & GEN11_DISPLAY_IRQ) {
> + const u32 disp_ctl = raw_reg_read(regs, GEN11_DISPLAY_INT_CTL);
> +
> + disable_rpm_wakeref_asserts(i915);
> + gen8_de_irq_handler(i915, disp_ctl);
gen8_de_irq_handler refers to the provided value as "master_ctl".
GEN11_DISPLAY_INT_CTL has the same format as GEN8_MASTER_IRQ for the
display-related bits (16-30) so it is ok to provide disp_ctl, but we
could use a comment to explain that. Also, gen8_de_irq_handler logs
errors blaming the master when things go wrong, so we could update that
to make things clearer, but that can come as a follow up.
I've checked the bit definitions of the registers used in
gen8_de_irq_handler and some of the bits have moved, but AFAICS among
the ones we use the only one that is impacted is GEN8_DE_MISC_GSE, which
is now gone (bit is now reserved). This shouldn't impact
gen8_de_irq_handler because the interrupt shouldn't trigger at all, but
we could avoid enabling it from gen8_de_irq_postinstall.
Anyway, nothing is functionally wrong so with a comment to explain about
disp_ctl:
reviewed-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Still, an ack from someone more knowledgeable than me with display code
would be nice ;)
Daniele
> + enable_rpm_wakeref_asserts(i915);
> + }
> +
> + /* Acknowledge and enable interrupts. */
> + raw_reg_write(regs, GEN11_GFX_MSTR_IRQ, GEN11_MASTER_IRQ | master_ctl);
> +
> + return IRQ_HANDLED;
> +}
> +
> /**
> * i915_reset_device - do process context error handling work
> * @dev_priv: i915 device private
> @@ -3180,6 +3330,42 @@ static void gen8_irq_reset(struct drm_device *dev)
> ibx_irq_reset(dev_priv);
> }
>
> +static void gen11_gt_irq_reset(struct drm_i915_private *dev_priv)
> +{
> + /* Disable RCS, BCS, VCS and VECS class engines. */
> + I915_WRITE(GEN11_RENDER_COPY_INTR_ENABLE, 0);
> + I915_WRITE(GEN11_VCS_VECS_INTR_ENABLE, 0);
> +
> + /* Restore masks irqs on RCS, BCS, VCS and VECS engines. */
> + I915_WRITE(GEN11_RCS0_RSVD_INTR_MASK, ~0);
> + I915_WRITE(GEN11_BCS_RSVD_INTR_MASK, ~0);
> + I915_WRITE(GEN11_VCS0_VCS1_INTR_MASK, ~0);
> + I915_WRITE(GEN11_VCS2_VCS3_INTR_MASK, ~0);
> + I915_WRITE(GEN11_VECS0_VECS1_INTR_MASK, ~0);
> +}
> +
> +static void gen11_irq_reset(struct drm_device *dev)
> +{
> + struct drm_i915_private *dev_priv = dev->dev_private;
> + int pipe;
> +
> + I915_WRITE(GEN11_GFX_MSTR_IRQ, 0);
> + POSTING_READ(GEN11_GFX_MSTR_IRQ);
> +
> + gen11_gt_irq_reset(dev_priv);
> +
> + I915_WRITE(GEN11_DISPLAY_INT_CTL, 0);
> +
> + for_each_pipe(dev_priv, pipe)
> + if (intel_display_power_is_enabled(dev_priv,
> + POWER_DOMAIN_PIPE(pipe)))
> + GEN8_IRQ_RESET_NDX(DE_PIPE, pipe);
> +
> + GEN3_IRQ_RESET(GEN8_DE_PORT_);
> + GEN3_IRQ_RESET(GEN8_DE_MISC_);
> + GEN3_IRQ_RESET(GEN8_PCU_);
> +}
> +
> void gen8_irq_power_well_post_enable(struct drm_i915_private *dev_priv,
> u8 pipe_mask)
> {
> @@ -3677,6 +3863,41 @@ static int gen8_irq_postinstall(struct drm_device *dev)
> return 0;
> }
>
> +static void gen11_gt_irq_postinstall(struct drm_i915_private *dev_priv)
> +{
> + const u32 irqs = GT_RENDER_USER_INTERRUPT | GT_CONTEXT_SWITCH_INTERRUPT;
> +
> + BUILD_BUG_ON(irqs & 0xffff0000);
> +
> + /* Enable RCS, BCS, VCS and VECS class interrupts. */
> + I915_WRITE(GEN11_RENDER_COPY_INTR_ENABLE, irqs << 16 | irqs);
> + I915_WRITE(GEN11_VCS_VECS_INTR_ENABLE, irqs << 16 | irqs);
> +
> + /* Unmask irqs on RCS, BCS, VCS and VECS engines. */
> + I915_WRITE(GEN11_RCS0_RSVD_INTR_MASK, ~(irqs << 16));
> + I915_WRITE(GEN11_BCS_RSVD_INTR_MASK, ~(irqs << 16));
> + I915_WRITE(GEN11_VCS0_VCS1_INTR_MASK, ~(irqs | irqs << 16));
> + I915_WRITE(GEN11_VCS2_VCS3_INTR_MASK, ~(irqs | irqs << 16));
> + I915_WRITE(GEN11_VECS0_VECS1_INTR_MASK, ~(irqs | irqs << 16));
> +
> + dev_priv->pm_imr = 0xffffffff; /* TODO */
> +}
> +
> +static int gen11_irq_postinstall(struct drm_device *dev)
> +{
> + struct drm_i915_private *dev_priv = dev->dev_private;
> +
> + gen11_gt_irq_postinstall(dev_priv);
> + gen8_de_irq_postinstall(dev_priv);
> +
> + I915_WRITE(GEN11_DISPLAY_INT_CTL, GEN11_DISPLAY_IRQ_ENABLE);
> +
> + I915_WRITE(GEN11_GFX_MSTR_IRQ, GEN11_MASTER_IRQ);
> + POSTING_READ(GEN11_GFX_MSTR_IRQ);
> +
> + return 0;
> +}
> +
> static int cherryview_irq_postinstall(struct drm_device *dev)
> {
> struct drm_i915_private *dev_priv = to_i915(dev);
> @@ -4125,6 +4346,14 @@ void intel_irq_init(struct drm_i915_private *dev_priv)
> dev->driver->enable_vblank = i965_enable_vblank;
> dev->driver->disable_vblank = i965_disable_vblank;
> dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup;
> + } else if (INTEL_GEN(dev_priv) >= 11) {
> + dev->driver->irq_handler = gen11_irq_handler;
> + dev->driver->irq_preinstall = gen11_irq_reset;
> + dev->driver->irq_postinstall = gen11_irq_postinstall;
> + dev->driver->irq_uninstall = gen11_irq_reset;
> + dev->driver->enable_vblank = gen8_enable_vblank;
> + dev->driver->disable_vblank = gen8_disable_vblank;
> + dev_priv->display.hpd_irq_setup = spt_hpd_irq_setup;
> } else if (INTEL_GEN(dev_priv) >= 8) {
> dev->driver->irq_handler = gen8_irq_handler;
> dev->driver->irq_preinstall = gen8_irq_reset;
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index a88f0f213604..7a316f867b42 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -8030,7 +8030,10 @@ void intel_sanitize_gt_powersave(struct drm_i915_private *dev_priv)
> dev_priv->gt_pm.rc6.enabled = true; /* force RC6 disabling */
> intel_disable_gt_powersave(dev_priv);
>
> - gen6_reset_rps_interrupts(dev_priv);
> + if (INTEL_GEN(dev_priv) < 11)
> + gen6_reset_rps_interrupts(dev_priv);
> + else
> + WARN_ON_ONCE(1);
> }
>
> static inline void intel_disable_llc_pstate(struct drm_i915_private *i915)
> @@ -8143,6 +8146,8 @@ static void intel_enable_rps(struct drm_i915_private *dev_priv)
> cherryview_enable_rps(dev_priv);
> } else if (IS_VALLEYVIEW(dev_priv)) {
> valleyview_enable_rps(dev_priv);
> + } else if (WARN_ON_ONCE(INTEL_GEN(dev_priv) >= 11)) {
> + /* TODO */
> } else if (INTEL_GEN(dev_priv) >= 9) {
> gen9_enable_rps(dev_priv);
> } else if (IS_BROADWELL(dev_priv)) {
>
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^ permalink raw reply [flat|nested] 13+ messages in thread* Re: [PATCH 4/4] drm/i915/icl: Interrupt handling
2018-02-27 19:51 ` Daniele Ceraolo Spurio
@ 2018-02-27 21:18 ` Paulo Zanoni
2018-03-01 12:22 ` Mika Kuoppala
0 siblings, 1 reply; 13+ messages in thread
From: Paulo Zanoni @ 2018-02-27 21:18 UTC (permalink / raw)
To: Daniele Ceraolo Spurio, Mika Kuoppala, intel-gfx; +Cc: Rodrigo Vivi
Em Ter, 2018-02-27 às 11:51 -0800, Daniele Ceraolo Spurio escreveu:
>
> On 20/02/18 07:37, Mika Kuoppala wrote:
> > v2: Rebase.
> >
> > v3:
> > * Remove DPF, it has been removed from SKL+.
> > * Fix -internal rebase wrt. execlists interrupt handling.
> >
> > v4: Rebase.
> >
> > v5:
> > * Updated for POR changes. (Daniele Ceraolo Spurio)
> > * Merged with irq handling fixes by Daniele Ceraolo Spurio:
> > * Simplify the code by using gen8_cs_irq_handler.
> > * Fix interrupt handling for the upstream kernel.
> >
> > v6:
> > * Remove early bringup debug messages (Tvrtko)
> > * Add NB about arbitrary spin wait timeout (Tvrtko)
> >
> > v7 (from Paulo):
> > * Don't try to write RO bits to registers.
> > * Don't check for PCH types that don't exist. PCH interrupts are
> > not
> > here yet.
> >
> > v9:
> > * squashed in selector and shared register handling (Daniele)
> > * skip writing of irq if data is not valid (Daniele)
> > * use time_after32 (Chris)
> > * use I915_MAX_VCS and I915_MAX_VECS (Daniele)
> > * remove fake pm interrupt handling for later patch (Mika)
> >
> > v10:
> > * Direct processing of banks. clear banks early (Chris)
> > * remove poll on valid bit, only clear valid bit (Mika)
> > * use raw accessors, better naming (Chris)
> >
> > v11:
> > * adapt to raw_reg_[read|write]
> > * bring back polling the valid bit (Daniele)
> >
> > Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
> > Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
> > Cc: Chris Wilson <chris@chris-wilson.co.uk>
> > Cc: Oscar Mateo <oscar.mateo@intel.com>
> > Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
> > Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
> > Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.
> > com>
> > Signed-off-by: Oscar Mateo <oscar.mateo@intel.com>
> > Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
> > Signed-off-by: Mika Kuoppala <mika.kuoppala@linux.intel.com>
> > ---
> > drivers/gpu/drm/i915/i915_irq.c | 229
> > ++++++++++++++++++++++++++++++++++++++++
> > drivers/gpu/drm/i915/intel_pm.c | 7 +-
> > 2 files changed, 235 insertions(+), 1 deletion(-)
> >
> > diff --git a/drivers/gpu/drm/i915/i915_irq.c
> > b/drivers/gpu/drm/i915/i915_irq.c
> > index 17de6cef2a30..a79f47ac742a 100644
> > --- a/drivers/gpu/drm/i915/i915_irq.c
> > +++ b/drivers/gpu/drm/i915/i915_irq.c
> > @@ -415,6 +415,9 @@ void gen6_enable_rps_interrupts(struct
> > drm_i915_private *dev_priv)
> > if (READ_ONCE(rps->interrupts_enabled))
> > return;
> >
> > + if (WARN_ON_ONCE(IS_GEN11(dev_priv)))
> > + return;
> > +
> > spin_lock_irq(&dev_priv->irq_lock);
> > WARN_ON_ONCE(rps->pm_iir);
> > WARN_ON_ONCE(I915_READ(gen6_pm_iir(dev_priv)) & dev_priv-
> > >pm_rps_events);
> > @@ -431,6 +434,9 @@ void gen6_disable_rps_interrupts(struct
> > drm_i915_private *dev_priv)
> > if (!READ_ONCE(rps->interrupts_enabled))
> > return;
> >
> > + if (WARN_ON_ONCE(IS_GEN11(dev_priv)))
> > + return;
> > +
> > spin_lock_irq(&dev_priv->irq_lock);
> > rps->interrupts_enabled = false;
> >
> > @@ -2755,6 +2761,150 @@ static void __fini_wedge(struct wedge_me
> > *w)
> > (W)->i915;
> > \
> > __fini_wedge((W)))
> >
> > +static __always_inline void
> > +gen11_cs_irq_handler(struct intel_engine_cs * const engine, const
> > u32 iir)
> > +{
> > + gen8_cs_irq_handler(engine, iir, 0);
> > +}
> > +
> > +static void
> > +gen11_gt_engine_irq_handler(struct drm_i915_private * const i915,
> > + const unsigned int bank,
> > + const unsigned int engine_n,
> > + const u16 iir)
> > +{
> > + struct intel_engine_cs ** const engine = i915->engine;
> > +
> > + switch (bank) {
> > + case 0:
> > + switch (engine_n) {
> > +
> > + case GEN11_RCS0:
> > + return gen11_cs_irq_handler(engine[RCS],
> > iir);
> > +
> > + case GEN11_BCS:
> > + return gen11_cs_irq_handler(engine[BCS],
> > iir);
> > + }
> > + case 1:
> > + switch (engine_n) {
> > +
> > + case GEN11_VCS(0):
> > + return
> > gen11_cs_irq_handler(engine[_VCS(0)], iir);
> > + case GEN11_VCS(1):
> > + return
> > gen11_cs_irq_handler(engine[_VCS(1)], iir);
> > + case GEN11_VCS(2):
> > + return
> > gen11_cs_irq_handler(engine[_VCS(2)], iir);
> > + case GEN11_VCS(3):
> > + return
> > gen11_cs_irq_handler(engine[_VCS(3)], iir);
> > +
> > + case GEN11_VECS(0):
> > + return
> > gen11_cs_irq_handler(engine[_VECS(0)], iir);
> > + case GEN11_VECS(1):
> > + return
> > gen11_cs_irq_handler(engine[_VECS(1)], iir);
> > + }
> > + }
> > +}
> > +
> > +static u32
> > +gen11_gt_engine_intr(struct drm_i915_private * const i915,
> > + const unsigned int bank, const unsigned int
> > bit)
> > +{
> > + void __iomem * const regs = i915->regs;
> > + u32 timeout_ts;
> > + u32 ident;
> > +
> > + raw_reg_write(regs, GEN11_IIR_REG_SELECTOR(bank),
> > BIT(bit));
> > +
> > + /*
> > + * NB: Specs do not specify how long to spin wait,
> > + * so we do ~100us as an educated guess.
> > + */
> > + timeout_ts = (local_clock() >> 10) + 100;
> > + do {
> > + ident = raw_reg_read(regs,
> > GEN11_INTR_IDENTITY_REG(bank));
> > + } while (!(ident & GEN11_INTR_DATA_VALID) &&
> > + !time_after32(local_clock() >> 10, timeout_ts));
> > +
> > + if (unlikely(!(ident & GEN11_INTR_DATA_VALID))) {
> > + DRM_ERROR("INTR_IDENTITY_REG%u:%u 0x%08x not
> > valid!\n",
> > + bank, bit, ident);
> > + return 0;
> > + }
> > +
> > + raw_reg_write(regs, GEN11_INTR_IDENTITY_REG(bank),
> > + GEN11_INTR_DATA_VALID);
> > +
> > + return ident & GEN11_INTR_ENGINE_MASK;
> > +}
> > +
> > +static void
> > +gen11_gt_irq_handler(struct drm_i915_private * const i915,
> > + const u32 master_ctl)
> > +{
> > + void __iomem * const regs = i915->regs;
> > + unsigned int bank;
> > +
> > + for (bank = 0; bank < 2; bank++) {
> > + unsigned long intr_dw;
> > + unsigned int bit;
> > +
> > + if (!(master_ctl & GEN11_GT_DW_IRQ(bank)))
> > + continue;
> > +
> > + intr_dw = raw_reg_read(regs,
> > GEN11_GT_INTR_DW(bank));
> > +
> > + if (unlikely(!intr_dw))
> > + DRM_ERROR("GT_INTR_DW%u blank!\n", bank);
>
> Could continue here, since the other operations in the loop won't be
> meaningful if intr_dw=0
>
> > +
> > + for_each_set_bit(bit, &intr_dw, 32) {
> > + const u16 iir = gen11_gt_engine_intr(i915,
> > bank, bit);
> > +
> > + if (unlikely(!iir))
> > + continue;
> > +
> > + gen11_gt_engine_irq_handler(i915, bank,
> > bit, iir);
> > + }
> > +
> > + /* Clear must be after shared has been served for
> > engine */
> > + raw_reg_write(regs, GEN11_GT_INTR_DW(bank),
> > intr_dw);
> > + }
> > +}
> > +
> > +static irqreturn_t gen11_irq_handler(int irq, void *arg)
> > +{
> > + struct drm_i915_private * const i915 = to_i915(arg);
> > + void __iomem * const regs = i915->regs;
> > + u32 master_ctl;
> > +
> > + if (!intel_irqs_enabled(i915))
> > + return IRQ_NONE;
> > +
> > + master_ctl = raw_reg_read(regs, GEN11_GFX_MSTR_IRQ);
> > + master_ctl &= ~GEN11_MASTER_IRQ;
> > + if (!master_ctl)
> > + return IRQ_NONE;
> > +
> > + /* Disable interrupts. */
> > + raw_reg_write(regs, GEN11_GFX_MSTR_IRQ, 0);
> > +
> > + /* Find, clear, then process each source of interrupt. */
> > + gen11_gt_irq_handler(i915, master_ctl);
> > +
> > + /* IRQs are synced during runtime_suspend, we don't
> > require a wakeref */
> > + if (master_ctl & GEN11_DISPLAY_IRQ) {
> > + const u32 disp_ctl = raw_reg_read(regs,
> > GEN11_DISPLAY_INT_CTL);
> > +
> > + disable_rpm_wakeref_asserts(i915);
> > + gen8_de_irq_handler(i915, disp_ctl);
>
> gen8_de_irq_handler refers to the provided value as "master_ctl".
> GEN11_DISPLAY_INT_CTL has the same format as GEN8_MASTER_IRQ for the
> display-related bits (16-30) so it is ok to provide disp_ctl, but we
> could use a comment to explain that. Also, gen8_de_irq_handler logs
> errors blaming the master when things go wrong, so we could update
> that
> to make things clearer, but that can come as a follow up.
>
> I've checked the bit definitions of the registers used in
> gen8_de_irq_handler and some of the bits have moved, but AFAICS
> among
> the ones we use the only one that is impacted is GEN8_DE_MISC_GSE,
> which
> is now gone (bit is now reserved). This shouldn't impact
> gen8_de_irq_handler because the interrupt shouldn't trigger at all,
> but
> we could avoid enabling it from gen8_de_irq_postinstall.
We have a patch for the GSE bit. Also, a few other display-related
interrupts have changed, and we have patches for them too.
All the display-related interrupt patches depend on this patch here, I
didn't send them yet to the list since I realized this patch here would
still get a few new versions, generating more and conflicts on each
version.
Once this one is merged we can send the display interrupt ones.
>
> Anyway, nothing is functionally wrong so with a comment to explain
> about
> disp_ctl:
>
> reviewed-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
>
> Still, an ack from someone more knowledgeable than me with display
> code
> would be nice ;)
>
> Daniele
>
> > + enable_rpm_wakeref_asserts(i915);
> > + }
> > +
> > + /* Acknowledge and enable interrupts. */
> > + raw_reg_write(regs, GEN11_GFX_MSTR_IRQ, GEN11_MASTER_IRQ |
> > master_ctl);
> > +
> > + return IRQ_HANDLED;
> > +}
> > +
> > /**
> > * i915_reset_device - do process context error handling work
> > * @dev_priv: i915 device private
> > @@ -3180,6 +3330,42 @@ static void gen8_irq_reset(struct drm_device
> > *dev)
> > ibx_irq_reset(dev_priv);
> > }
> >
> > +static void gen11_gt_irq_reset(struct drm_i915_private *dev_priv)
> > +{
> > + /* Disable RCS, BCS, VCS and VECS class engines. */
> > + I915_WRITE(GEN11_RENDER_COPY_INTR_ENABLE, 0);
> > + I915_WRITE(GEN11_VCS_VECS_INTR_ENABLE, 0);
> > +
> > + /* Restore masks irqs on RCS, BCS, VCS and VECS engines.
> > */
> > + I915_WRITE(GEN11_RCS0_RSVD_INTR_MASK, ~0);
> > + I915_WRITE(GEN11_BCS_RSVD_INTR_MASK, ~0);
> > + I915_WRITE(GEN11_VCS0_VCS1_INTR_MASK, ~0);
> > + I915_WRITE(GEN11_VCS2_VCS3_INTR_MASK, ~0);
> > + I915_WRITE(GEN11_VECS0_VECS1_INTR_MASK, ~0);
> > +}
> > +
> > +static void gen11_irq_reset(struct drm_device *dev)
> > +{
> > + struct drm_i915_private *dev_priv = dev->dev_private;
> > + int pipe;
> > +
> > + I915_WRITE(GEN11_GFX_MSTR_IRQ, 0);
> > + POSTING_READ(GEN11_GFX_MSTR_IRQ);
> > +
> > + gen11_gt_irq_reset(dev_priv);
> > +
> > + I915_WRITE(GEN11_DISPLAY_INT_CTL, 0);
> > +
> > + for_each_pipe(dev_priv, pipe)
> > + if (intel_display_power_is_enabled(dev_priv,
> > + POWER_DOMAIN_PI
> > PE(pipe)))
> > + GEN8_IRQ_RESET_NDX(DE_PIPE, pipe);
> > +
> > + GEN3_IRQ_RESET(GEN8_DE_PORT_);
> > + GEN3_IRQ_RESET(GEN8_DE_MISC_);
> > + GEN3_IRQ_RESET(GEN8_PCU_);
> > +}
> > +
> > void gen8_irq_power_well_post_enable(struct drm_i915_private
> > *dev_priv,
> > u8 pipe_mask)
> > {
> > @@ -3677,6 +3863,41 @@ static int gen8_irq_postinstall(struct
> > drm_device *dev)
> > return 0;
> > }
> >
> > +static void gen11_gt_irq_postinstall(struct drm_i915_private
> > *dev_priv)
> > +{
> > + const u32 irqs = GT_RENDER_USER_INTERRUPT |
> > GT_CONTEXT_SWITCH_INTERRUPT;
> > +
> > + BUILD_BUG_ON(irqs & 0xffff0000);
> > +
> > + /* Enable RCS, BCS, VCS and VECS class interrupts. */
> > + I915_WRITE(GEN11_RENDER_COPY_INTR_ENABLE, irqs << 16 |
> > irqs);
> > + I915_WRITE(GEN11_VCS_VECS_INTR_ENABLE, irqs << 16
> > | irqs);
> > +
> > + /* Unmask irqs on RCS, BCS, VCS and VECS engines. */
> > + I915_WRITE(GEN11_RCS0_RSVD_INTR_MASK, ~(irqs <<
> > 16));
> > + I915_WRITE(GEN11_BCS_RSVD_INTR_MASK, ~(irqs <<
> > 16));
> > + I915_WRITE(GEN11_VCS0_VCS1_INTR_MASK, ~(irqs | irqs
> > << 16));
> > + I915_WRITE(GEN11_VCS2_VCS3_INTR_MASK, ~(irqs | irqs
> > << 16));
> > + I915_WRITE(GEN11_VECS0_VECS1_INTR_MASK, ~(irqs |
> > irqs << 16));
> > +
> > + dev_priv->pm_imr = 0xffffffff; /* TODO */
> > +}
> > +
> > +static int gen11_irq_postinstall(struct drm_device *dev)
> > +{
> > + struct drm_i915_private *dev_priv = dev->dev_private;
> > +
> > + gen11_gt_irq_postinstall(dev_priv);
> > + gen8_de_irq_postinstall(dev_priv);
> > +
> > + I915_WRITE(GEN11_DISPLAY_INT_CTL,
> > GEN11_DISPLAY_IRQ_ENABLE);
> > +
> > + I915_WRITE(GEN11_GFX_MSTR_IRQ, GEN11_MASTER_IRQ);
> > + POSTING_READ(GEN11_GFX_MSTR_IRQ);
> > +
> > + return 0;
> > +}
> > +
> > static int cherryview_irq_postinstall(struct drm_device *dev)
> > {
> > struct drm_i915_private *dev_priv = to_i915(dev);
> > @@ -4125,6 +4346,14 @@ void intel_irq_init(struct drm_i915_private
> > *dev_priv)
> > dev->driver->enable_vblank = i965_enable_vblank;
> > dev->driver->disable_vblank =
> > i965_disable_vblank;
> > dev_priv->display.hpd_irq_setup =
> > i915_hpd_irq_setup;
> > + } else if (INTEL_GEN(dev_priv) >= 11) {
> > + dev->driver->irq_handler = gen11_irq_handler;
> > + dev->driver->irq_preinstall = gen11_irq_reset;
> > + dev->driver->irq_postinstall =
> > gen11_irq_postinstall;
> > + dev->driver->irq_uninstall = gen11_irq_reset;
> > + dev->driver->enable_vblank = gen8_enable_vblank;
> > + dev->driver->disable_vblank = gen8_disable_vblank;
> > + dev_priv->display.hpd_irq_setup =
> > spt_hpd_irq_setup;
> > } else if (INTEL_GEN(dev_priv) >= 8) {
> > dev->driver->irq_handler = gen8_irq_handler;
> > dev->driver->irq_preinstall = gen8_irq_reset;
> > diff --git a/drivers/gpu/drm/i915/intel_pm.c
> > b/drivers/gpu/drm/i915/intel_pm.c
> > index a88f0f213604..7a316f867b42 100644
> > --- a/drivers/gpu/drm/i915/intel_pm.c
> > +++ b/drivers/gpu/drm/i915/intel_pm.c
> > @@ -8030,7 +8030,10 @@ void intel_sanitize_gt_powersave(struct
> > drm_i915_private *dev_priv)
> > dev_priv->gt_pm.rc6.enabled = true; /* force RC6
> > disabling */
> > intel_disable_gt_powersave(dev_priv);
> >
> > - gen6_reset_rps_interrupts(dev_priv);
> > + if (INTEL_GEN(dev_priv) < 11)
> > + gen6_reset_rps_interrupts(dev_priv);
> > + else
> > + WARN_ON_ONCE(1);
> > }
> >
> > static inline void intel_disable_llc_pstate(struct
> > drm_i915_private *i915)
> > @@ -8143,6 +8146,8 @@ static void intel_enable_rps(struct
> > drm_i915_private *dev_priv)
> > cherryview_enable_rps(dev_priv);
> > } else if (IS_VALLEYVIEW(dev_priv)) {
> > valleyview_enable_rps(dev_priv);
> > + } else if (WARN_ON_ONCE(INTEL_GEN(dev_priv) >= 11)) {
> > + /* TODO */
> > } else if (INTEL_GEN(dev_priv) >= 9) {
> > gen9_enable_rps(dev_priv);
> > } else if (IS_BROADWELL(dev_priv)) {
> >
_______________________________________________
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 13+ messages in thread* Re: [PATCH 4/4] drm/i915/icl: Interrupt handling
2018-02-27 21:18 ` Paulo Zanoni
@ 2018-03-01 12:22 ` Mika Kuoppala
0 siblings, 0 replies; 13+ messages in thread
From: Mika Kuoppala @ 2018-03-01 12:22 UTC (permalink / raw)
To: Paulo Zanoni, Daniele Ceraolo Spurio, intel-gfx; +Cc: Rodrigo Vivi
Paulo Zanoni <paulo.r.zanoni@intel.com> writes:
> Em Ter, 2018-02-27 às 11:51 -0800, Daniele Ceraolo Spurio escreveu:
>>
>> On 20/02/18 07:37, Mika Kuoppala wrote:
>> > v2: Rebase.
>> >
>> > v3:
>> > * Remove DPF, it has been removed from SKL+.
>> > * Fix -internal rebase wrt. execlists interrupt handling.
>> >
>> > v4: Rebase.
>> >
>> > v5:
>> > * Updated for POR changes. (Daniele Ceraolo Spurio)
>> > * Merged with irq handling fixes by Daniele Ceraolo Spurio:
>> > * Simplify the code by using gen8_cs_irq_handler.
>> > * Fix interrupt handling for the upstream kernel.
>> >
>> > v6:
>> > * Remove early bringup debug messages (Tvrtko)
>> > * Add NB about arbitrary spin wait timeout (Tvrtko)
>> >
>> > v7 (from Paulo):
>> > * Don't try to write RO bits to registers.
>> > * Don't check for PCH types that don't exist. PCH interrupts are
>> > not
>> > here yet.
>> >
>> > v9:
>> > * squashed in selector and shared register handling (Daniele)
>> > * skip writing of irq if data is not valid (Daniele)
>> > * use time_after32 (Chris)
>> > * use I915_MAX_VCS and I915_MAX_VECS (Daniele)
>> > * remove fake pm interrupt handling for later patch (Mika)
>> >
>> > v10:
>> > * Direct processing of banks. clear banks early (Chris)
>> > * remove poll on valid bit, only clear valid bit (Mika)
>> > * use raw accessors, better naming (Chris)
>> >
>> > v11:
>> > * adapt to raw_reg_[read|write]
>> > * bring back polling the valid bit (Daniele)
>> >
>> > Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
>> > Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
>> > Cc: Chris Wilson <chris@chris-wilson.co.uk>
>> > Cc: Oscar Mateo <oscar.mateo@intel.com>
>> > Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
>> > Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
>> > Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.
>> > com>
>> > Signed-off-by: Oscar Mateo <oscar.mateo@intel.com>
>> > Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
>> > Signed-off-by: Mika Kuoppala <mika.kuoppala@linux.intel.com>
>> > ---
>> > drivers/gpu/drm/i915/i915_irq.c | 229
>> > ++++++++++++++++++++++++++++++++++++++++
>> > drivers/gpu/drm/i915/intel_pm.c | 7 +-
>> > 2 files changed, 235 insertions(+), 1 deletion(-)
>> >
>> > diff --git a/drivers/gpu/drm/i915/i915_irq.c
>> > b/drivers/gpu/drm/i915/i915_irq.c
>> > index 17de6cef2a30..a79f47ac742a 100644
>> > --- a/drivers/gpu/drm/i915/i915_irq.c
>> > +++ b/drivers/gpu/drm/i915/i915_irq.c
>> > @@ -415,6 +415,9 @@ void gen6_enable_rps_interrupts(struct
>> > drm_i915_private *dev_priv)
>> > if (READ_ONCE(rps->interrupts_enabled))
>> > return;
>> >
>> > + if (WARN_ON_ONCE(IS_GEN11(dev_priv)))
>> > + return;
>> > +
>> > spin_lock_irq(&dev_priv->irq_lock);
>> > WARN_ON_ONCE(rps->pm_iir);
>> > WARN_ON_ONCE(I915_READ(gen6_pm_iir(dev_priv)) & dev_priv-
>> > >pm_rps_events);
>> > @@ -431,6 +434,9 @@ void gen6_disable_rps_interrupts(struct
>> > drm_i915_private *dev_priv)
>> > if (!READ_ONCE(rps->interrupts_enabled))
>> > return;
>> >
>> > + if (WARN_ON_ONCE(IS_GEN11(dev_priv)))
>> > + return;
>> > +
>> > spin_lock_irq(&dev_priv->irq_lock);
>> > rps->interrupts_enabled = false;
>> >
>> > @@ -2755,6 +2761,150 @@ static void __fini_wedge(struct wedge_me
>> > *w)
>> > (W)->i915;
>> > \
>> > __fini_wedge((W)))
>> >
>> > +static __always_inline void
>> > +gen11_cs_irq_handler(struct intel_engine_cs * const engine, const
>> > u32 iir)
>> > +{
>> > + gen8_cs_irq_handler(engine, iir, 0);
>> > +}
>> > +
>> > +static void
>> > +gen11_gt_engine_irq_handler(struct drm_i915_private * const i915,
>> > + const unsigned int bank,
>> > + const unsigned int engine_n,
>> > + const u16 iir)
>> > +{
>> > + struct intel_engine_cs ** const engine = i915->engine;
>> > +
>> > + switch (bank) {
>> > + case 0:
>> > + switch (engine_n) {
>> > +
>> > + case GEN11_RCS0:
>> > + return gen11_cs_irq_handler(engine[RCS],
>> > iir);
>> > +
>> > + case GEN11_BCS:
>> > + return gen11_cs_irq_handler(engine[BCS],
>> > iir);
>> > + }
>> > + case 1:
>> > + switch (engine_n) {
>> > +
>> > + case GEN11_VCS(0):
>> > + return
>> > gen11_cs_irq_handler(engine[_VCS(0)], iir);
>> > + case GEN11_VCS(1):
>> > + return
>> > gen11_cs_irq_handler(engine[_VCS(1)], iir);
>> > + case GEN11_VCS(2):
>> > + return
>> > gen11_cs_irq_handler(engine[_VCS(2)], iir);
>> > + case GEN11_VCS(3):
>> > + return
>> > gen11_cs_irq_handler(engine[_VCS(3)], iir);
>> > +
>> > + case GEN11_VECS(0):
>> > + return
>> > gen11_cs_irq_handler(engine[_VECS(0)], iir);
>> > + case GEN11_VECS(1):
>> > + return
>> > gen11_cs_irq_handler(engine[_VECS(1)], iir);
>> > + }
>> > + }
>> > +}
>> > +
>> > +static u32
>> > +gen11_gt_engine_intr(struct drm_i915_private * const i915,
>> > + const unsigned int bank, const unsigned int
>> > bit)
>> > +{
>> > + void __iomem * const regs = i915->regs;
>> > + u32 timeout_ts;
>> > + u32 ident;
>> > +
>> > + raw_reg_write(regs, GEN11_IIR_REG_SELECTOR(bank),
>> > BIT(bit));
>> > +
>> > + /*
>> > + * NB: Specs do not specify how long to spin wait,
>> > + * so we do ~100us as an educated guess.
>> > + */
>> > + timeout_ts = (local_clock() >> 10) + 100;
>> > + do {
>> > + ident = raw_reg_read(regs,
>> > GEN11_INTR_IDENTITY_REG(bank));
>> > + } while (!(ident & GEN11_INTR_DATA_VALID) &&
>> > + !time_after32(local_clock() >> 10, timeout_ts));
>> > +
>> > + if (unlikely(!(ident & GEN11_INTR_DATA_VALID))) {
>> > + DRM_ERROR("INTR_IDENTITY_REG%u:%u 0x%08x not
>> > valid!\n",
>> > + bank, bit, ident);
>> > + return 0;
>> > + }
>> > +
>> > + raw_reg_write(regs, GEN11_INTR_IDENTITY_REG(bank),
>> > + GEN11_INTR_DATA_VALID);
>> > +
>> > + return ident & GEN11_INTR_ENGINE_MASK;
>> > +}
>> > +
>> > +static void
>> > +gen11_gt_irq_handler(struct drm_i915_private * const i915,
>> > + const u32 master_ctl)
>> > +{
>> > + void __iomem * const regs = i915->regs;
>> > + unsigned int bank;
>> > +
>> > + for (bank = 0; bank < 2; bank++) {
>> > + unsigned long intr_dw;
>> > + unsigned int bit;
>> > +
>> > + if (!(master_ctl & GEN11_GT_DW_IRQ(bank)))
>> > + continue;
>> > +
>> > + intr_dw = raw_reg_read(regs,
>> > GEN11_GT_INTR_DW(bank));
>> > +
>> > + if (unlikely(!intr_dw))
>> > + DRM_ERROR("GT_INTR_DW%u blank!\n", bank);
>>
>> Could continue here, since the other operations in the loop won't be
>> meaningful if intr_dw=0
>>
>> > +
>> > + for_each_set_bit(bit, &intr_dw, 32) {
>> > + const u16 iir = gen11_gt_engine_intr(i915,
>> > bank, bit);
>> > +
>> > + if (unlikely(!iir))
>> > + continue;
>> > +
>> > + gen11_gt_engine_irq_handler(i915, bank,
>> > bit, iir);
>> > + }
>> > +
>> > + /* Clear must be after shared has been served for
>> > engine */
>> > + raw_reg_write(regs, GEN11_GT_INTR_DW(bank),
>> > intr_dw);
>> > + }
>> > +}
>> > +
>> > +static irqreturn_t gen11_irq_handler(int irq, void *arg)
>> > +{
>> > + struct drm_i915_private * const i915 = to_i915(arg);
>> > + void __iomem * const regs = i915->regs;
>> > + u32 master_ctl;
>> > +
>> > + if (!intel_irqs_enabled(i915))
>> > + return IRQ_NONE;
>> > +
>> > + master_ctl = raw_reg_read(regs, GEN11_GFX_MSTR_IRQ);
>> > + master_ctl &= ~GEN11_MASTER_IRQ;
>> > + if (!master_ctl)
>> > + return IRQ_NONE;
>> > +
>> > + /* Disable interrupts. */
>> > + raw_reg_write(regs, GEN11_GFX_MSTR_IRQ, 0);
>> > +
>> > + /* Find, clear, then process each source of interrupt. */
>> > + gen11_gt_irq_handler(i915, master_ctl);
>> > +
>> > + /* IRQs are synced during runtime_suspend, we don't
>> > require a wakeref */
>> > + if (master_ctl & GEN11_DISPLAY_IRQ) {
>> > + const u32 disp_ctl = raw_reg_read(regs,
>> > GEN11_DISPLAY_INT_CTL);
>> > +
>> > + disable_rpm_wakeref_asserts(i915);
>> > + gen8_de_irq_handler(i915, disp_ctl);
>>
>> gen8_de_irq_handler refers to the provided value as "master_ctl".
>> GEN11_DISPLAY_INT_CTL has the same format as GEN8_MASTER_IRQ for the
>> display-related bits (16-30) so it is ok to provide disp_ctl, but we
>> could use a comment to explain that. Also, gen8_de_irq_handler logs
>> errors blaming the master when things go wrong, so we could update
>> that
>> to make things clearer, but that can come as a follow up.
>>
>> I've checked the bit definitions of the registers used in
>> gen8_de_irq_handler and some of the bits have moved, but AFAICS
>> among
>> the ones we use the only one that is impacted is GEN8_DE_MISC_GSE,
>> which
>> is now gone (bit is now reserved). This shouldn't impact
>> gen8_de_irq_handler because the interrupt shouldn't trigger at all,
>> but
>> we could avoid enabling it from gen8_de_irq_postinstall.
>
> We have a patch for the GSE bit. Also, a few other display-related
> interrupts have changed, and we have patches for them too.
>
> All the display-related interrupt patches depend on this patch here, I
> didn't send them yet to the list since I realized this patch here would
> still get a few new versions, generating more and conflicts on each
> version.
>
> Once this one is merged we can send the display interrupt ones.
>
This is now pushed with the suggested changes by Daniele.
Thanks for review.
-Mika
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^ permalink raw reply [flat|nested] 13+ messages in thread
* ✗ Fi.CI.CHECKPATCH: warning for series starting with [1/4] drm/i915/icl: Add the ICL PCI IDs
2018-02-20 15:37 [PATCH 1/4] drm/i915/icl: Add the ICL PCI IDs Mika Kuoppala
` (2 preceding siblings ...)
2018-02-20 15:37 ` [PATCH 4/4] drm/i915/icl: Interrupt handling Mika Kuoppala
@ 2018-02-20 16:05 ` Patchwork
2018-02-20 16:19 ` ✓ Fi.CI.BAT: success " Patchwork
2018-02-20 21:56 ` ✗ Fi.CI.IGT: warning " Patchwork
5 siblings, 0 replies; 13+ messages in thread
From: Patchwork @ 2018-02-20 16:05 UTC (permalink / raw)
To: Mika Kuoppala; +Cc: intel-gfx
== Series Details ==
Series: series starting with [1/4] drm/i915/icl: Add the ICL PCI IDs
URL : https://patchwork.freedesktop.org/series/38604/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
976122bb3624 drm/i915/icl: Add the ICL PCI IDs
-:47: ERROR: Macros with complex values should be enclosed in parentheses
#47: FILE: include/drm/i915_pciids.h:435:
+#define INTEL_ICL_11_IDS(info) \
+ INTEL_VGA_DEVICE(0x8A50, info), \
+ INTEL_VGA_DEVICE(0x8A51, info), \
+ INTEL_VGA_DEVICE(0x8A5C, info), \
+ INTEL_VGA_DEVICE(0x8A5D, info), \
+ INTEL_VGA_DEVICE(0x8A52, info), \
+ INTEL_VGA_DEVICE(0x8A5A, info), \
+ INTEL_VGA_DEVICE(0x8A5B, info), \
+ INTEL_VGA_DEVICE(0x8A71, info), \
+ INTEL_VGA_DEVICE(0x8A70, info)
-:47: CHECK: Macro argument reuse 'info' - possible side-effects?
#47: FILE: include/drm/i915_pciids.h:435:
+#define INTEL_ICL_11_IDS(info) \
+ INTEL_VGA_DEVICE(0x8A50, info), \
+ INTEL_VGA_DEVICE(0x8A51, info), \
+ INTEL_VGA_DEVICE(0x8A5C, info), \
+ INTEL_VGA_DEVICE(0x8A5D, info), \
+ INTEL_VGA_DEVICE(0x8A52, info), \
+ INTEL_VGA_DEVICE(0x8A5A, info), \
+ INTEL_VGA_DEVICE(0x8A5B, info), \
+ INTEL_VGA_DEVICE(0x8A71, info), \
+ INTEL_VGA_DEVICE(0x8A70, info)
total: 1 errors, 0 warnings, 1 checks, 23 lines checked
03836e973026 drm/i915/icl: Show interrupt registers in debugfs
ecc8c181594e drm/i915/icl: Prepare for more rings
64d966e1377d drm/i915/icl: Interrupt handling
-:101: CHECK: Blank lines aren't necessary after an open brace '{'
#101: FILE: drivers/gpu/drm/i915/i915_irq.c:2781:
+ switch (engine_n) {
+
-:110: CHECK: Blank lines aren't necessary after an open brace '{'
#110: FILE: drivers/gpu/drm/i915/i915_irq.c:2790:
+ switch (engine_n) {
+
total: 0 errors, 0 warnings, 2 checks, 284 lines checked
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^ permalink raw reply [flat|nested] 13+ messages in thread* ✓ Fi.CI.BAT: success for series starting with [1/4] drm/i915/icl: Add the ICL PCI IDs
2018-02-20 15:37 [PATCH 1/4] drm/i915/icl: Add the ICL PCI IDs Mika Kuoppala
` (3 preceding siblings ...)
2018-02-20 16:05 ` ✗ Fi.CI.CHECKPATCH: warning for series starting with [1/4] drm/i915/icl: Add the ICL PCI IDs Patchwork
@ 2018-02-20 16:19 ` Patchwork
2018-02-20 21:56 ` ✗ Fi.CI.IGT: warning " Patchwork
5 siblings, 0 replies; 13+ messages in thread
From: Patchwork @ 2018-02-20 16:19 UTC (permalink / raw)
To: Mika Kuoppala; +Cc: intel-gfx
== Series Details ==
Series: series starting with [1/4] drm/i915/icl: Add the ICL PCI IDs
URL : https://patchwork.freedesktop.org/series/38604/
State : success
== Summary ==
Series 38604v1 series starting with [1/4] drm/i915/icl: Add the ICL PCI IDs
https://patchwork.freedesktop.org/api/1.0/series/38604/revisions/1/mbox/
Test debugfs_test:
Subgroup read_all_entries:
pass -> INCOMPLETE (fi-snb-2520m) fdo#103713
fdo#103713 https://bugs.freedesktop.org/show_bug.cgi?id=103713
fi-bdw-5557u total:288 pass:267 dwarn:0 dfail:0 fail:0 skip:21 time:414s
fi-bdw-gvtdvm total:288 pass:264 dwarn:0 dfail:0 fail:0 skip:24 time:425s
fi-blb-e6850 total:288 pass:223 dwarn:1 dfail:0 fail:0 skip:64 time:372s
fi-bsw-n3050 total:288 pass:242 dwarn:0 dfail:0 fail:0 skip:46 time:479s
fi-bwr-2160 total:288 pass:183 dwarn:0 dfail:0 fail:0 skip:105 time:282s
fi-bxt-j4205 total:288 pass:259 dwarn:0 dfail:0 fail:0 skip:29 time:479s
fi-byt-j1900 total:288 pass:253 dwarn:0 dfail:0 fail:0 skip:35 time:462s
fi-byt-n2820 total:288 pass:249 dwarn:0 dfail:0 fail:0 skip:39 time:450s
fi-cfl-s2 total:288 pass:262 dwarn:0 dfail:0 fail:0 skip:26 time:559s
fi-elk-e7500 total:288 pass:229 dwarn:0 dfail:0 fail:0 skip:59 time:412s
fi-gdg-551 total:288 pass:179 dwarn:0 dfail:0 fail:1 skip:108 time:282s
fi-glk-1 total:288 pass:260 dwarn:0 dfail:0 fail:0 skip:28 time:507s
fi-hsw-4770 total:288 pass:261 dwarn:0 dfail:0 fail:0 skip:27 time:385s
fi-ilk-650 total:288 pass:228 dwarn:0 dfail:0 fail:0 skip:60 time:407s
fi-ivb-3520m total:288 pass:259 dwarn:0 dfail:0 fail:0 skip:29 time:454s
fi-ivb-3770 total:288 pass:255 dwarn:0 dfail:0 fail:0 skip:33 time:414s
fi-kbl-7500u total:288 pass:263 dwarn:1 dfail:0 fail:0 skip:24 time:450s
fi-kbl-7560u total:288 pass:269 dwarn:0 dfail:0 fail:0 skip:19 time:495s
fi-kbl-7567u total:288 pass:268 dwarn:0 dfail:0 fail:0 skip:20 time:445s
fi-kbl-r total:288 pass:261 dwarn:0 dfail:0 fail:0 skip:27 time:490s
fi-pnv-d510 total:288 pass:222 dwarn:1 dfail:0 fail:0 skip:65 time:588s
fi-skl-6260u total:288 pass:268 dwarn:0 dfail:0 fail:0 skip:20 time:424s
fi-skl-6600u total:288 pass:261 dwarn:0 dfail:0 fail:0 skip:27 time:500s
fi-skl-6700hq total:288 pass:262 dwarn:0 dfail:0 fail:0 skip:26 time:515s
fi-skl-6700k2 total:288 pass:264 dwarn:0 dfail:0 fail:0 skip:24 time:489s
fi-skl-6770hq total:288 pass:268 dwarn:0 dfail:0 fail:0 skip:20 time:475s
fi-skl-guc total:288 pass:260 dwarn:0 dfail:0 fail:0 skip:28 time:407s
fi-skl-gvtdvm total:288 pass:265 dwarn:0 dfail:0 fail:0 skip:23 time:430s
fi-snb-2520m total:3 pass:2 dwarn:0 dfail:0 fail:0 skip:0
fi-snb-2600 total:288 pass:248 dwarn:0 dfail:0 fail:0 skip:40 time:395s
fi-bxt-dsi failed to collect. IGT log at Patchwork_8082/fi-bxt-dsi/run0.log
3d51421431733258a56a6205924d90f822d6fdae drm-tip: 2018y-02m-20d-15h-34m-58s UTC integration manifest
64d966e1377d drm/i915/icl: Interrupt handling
ecc8c181594e drm/i915/icl: Prepare for more rings
03836e973026 drm/i915/icl: Show interrupt registers in debugfs
976122bb3624 drm/i915/icl: Add the ICL PCI IDs
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_8082/issues.html
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^ permalink raw reply [flat|nested] 13+ messages in thread* ✗ Fi.CI.IGT: warning for series starting with [1/4] drm/i915/icl: Add the ICL PCI IDs
2018-02-20 15:37 [PATCH 1/4] drm/i915/icl: Add the ICL PCI IDs Mika Kuoppala
` (4 preceding siblings ...)
2018-02-20 16:19 ` ✓ Fi.CI.BAT: success " Patchwork
@ 2018-02-20 21:56 ` Patchwork
5 siblings, 0 replies; 13+ messages in thread
From: Patchwork @ 2018-02-20 21:56 UTC (permalink / raw)
To: Mika Kuoppala; +Cc: intel-gfx
== Series Details ==
Series: series starting with [1/4] drm/i915/icl: Add the ICL PCI IDs
URL : https://patchwork.freedesktop.org/series/38604/
State : warning
== Summary ==
Test kms_flip:
Subgroup 2x-plain-flip-fb-recreate-interruptible:
pass -> FAIL (shard-hsw) fdo#100368 +1
Subgroup modeset-vs-vblank-race-interruptible:
pass -> FAIL (shard-hsw) fdo#103060 +2
Test perf:
Subgroup oa-exponents:
pass -> FAIL (shard-apl) fdo#102254
Subgroup enable-disable:
pass -> FAIL (shard-apl) fdo#103715
Test gem_eio:
Subgroup in-flight:
pass -> DMESG-WARN (shard-snb) fdo#104058
Subgroup in-flight-external:
pass -> FAIL (shard-hsw) fdo#104676
Test kms_frontbuffer_tracking:
Subgroup fbc-rgb565-draw-pwrite:
pass -> SKIP (shard-snb) fdo#101623
Test gem_pwrite:
Subgroup big-cpu-backwards:
pass -> SKIP (shard-apl)
Test kms_universal_plane:
Subgroup disable-primary-vs-flip-pipe-b:
pass -> SKIP (shard-snb)
Test kms_cursor_legacy:
Subgroup cursor-vs-flip-toggle:
pass -> SKIP (shard-snb)
Test kms_plane_multiple:
Subgroup legacy-pipe-b-tiling-x:
pass -> SKIP (shard-snb)
Test kms_draw_crc:
Subgroup draw-method-rgb565-blt-untiled:
pass -> SKIP (shard-snb)
fdo#100368 https://bugs.freedesktop.org/show_bug.cgi?id=100368
fdo#103060 https://bugs.freedesktop.org/show_bug.cgi?id=103060
fdo#102254 https://bugs.freedesktop.org/show_bug.cgi?id=102254
fdo#103715 https://bugs.freedesktop.org/show_bug.cgi?id=103715
fdo#104058 https://bugs.freedesktop.org/show_bug.cgi?id=104058
fdo#104676 https://bugs.freedesktop.org/show_bug.cgi?id=104676
fdo#101623 https://bugs.freedesktop.org/show_bug.cgi?id=101623
shard-apl total:3427 pass:1792 dwarn:1 dfail:0 fail:11 skip:1622 time:12049s
shard-hsw total:3429 pass:1755 dwarn:1 dfail:0 fail:7 skip:1665 time:11638s
shard-snb total:3429 pass:1343 dwarn:2 dfail:0 fail:2 skip:2082 time:6493s
Blacklisted hosts:
shard-kbl total:3429 pass:1924 dwarn:2 dfail:0 fail:9 skip:1494 time:9658s
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_8082/shards.html
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^ permalink raw reply [flat|nested] 13+ messages in thread