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From: Paulo Zanoni <paulo.r.zanoni@intel.com>
To: intel-gfx@lists.freedesktop.org
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>,
	Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
Subject: Re: [PATCH 29/24] drm/i915/icl: DP_AUX_E is valid on ICL+
Date: Thu, 24 May 2018 17:12:02 -0700	[thread overview]
Message-ID: <1527207122.2558.11.camel@intel.com> (raw)
In-Reply-To: <20180524234241.3665-5-paulo.r.zanoni@intel.com>

Em Qui, 2018-05-24 às 16:42 -0700, Paulo Zanoni escreveu:
> From: James Ausmus <james.ausmus@intel.com>
> 
> Add support for DP_AUX_E. Here we also introduce the bits for the AUX
> power well E, however ICL power well support is still not enabled
> yet,
> so the power well is not used.
> 
> Cc: Paulo Zanoni <paulo.r.zanoni@intel.com>
> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
> Cc: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
> Signed-off-by: James Ausmus <james.ausmus@intel.com>
> Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
> ---
>  drivers/gpu/drm/i915/i915_drv.h         | 1 +
>  drivers/gpu/drm/i915/i915_irq.c         | 6 ++++++
>  drivers/gpu/drm/i915/i915_reg.h         | 8 ++++++++
>  drivers/gpu/drm/i915/intel_display.h    | 3 ++-
>  drivers/gpu/drm/i915/intel_dp.c         | 7 +++++++
>  drivers/gpu/drm/i915/intel_runtime_pm.c | 2 ++
>  6 files changed, 26 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_drv.h
> b/drivers/gpu/drm/i915/i915_drv.h
> index b86ed6401120..a85329f053dc 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -1005,6 +1005,7 @@ enum modeset_restore {
>  #define DP_AUX_B 0x10
>  #define DP_AUX_C 0x20
>  #define DP_AUX_D 0x30
> +#define DP_AUX_E 0x50
>  #define DP_AUX_F 0x60
>  
>  #define DDC_PIN_B  0x05
> diff --git a/drivers/gpu/drm/i915/i915_irq.c
> b/drivers/gpu/drm/i915/i915_irq.c
> index 9f1b01ca4ed1..672bfaf2052a 100644
> --- a/drivers/gpu/drm/i915/i915_irq.c
> +++ b/drivers/gpu/drm/i915/i915_irq.c
> @@ -2783,6 +2783,9 @@ gen8_de_irq_handler(struct drm_i915_private
> *dev_priv, u32 master_ctl)
>  					    GEN9_AUX_CHANNEL_C |
>  					    GEN9_AUX_CHANNEL_D;
>  
> +			if (INTEL_GEN(dev_priv) >= 11)
> +				tmp_mask |= ICL_AUX_CHANNEL_E;
> +
>  			if (IS_CNL_WITH_PORT_F(dev_priv) ||
>  			    INTEL_GEN(dev_priv) >= 11)
>  				tmp_mask |= CNL_AUX_CHANNEL_F;
> @@ -4168,6 +4171,9 @@ static void gen8_de_irq_postinstall(struct
> drm_i915_private *dev_priv)
>  		de_pipe_masked |= GEN8_DE_PIPE_IRQ_FAULT_ERRORS;
>  	}
>  
> +	if (INTEL_GEN(dev_priv) >= 11)
> +		de_port_masked |= ICL_AUX_CHANNEL_E;
> +
>  	if (IS_CNL_WITH_PORT_F(dev_priv) || INTEL_GEN(dev_priv) >=
> 11)
>  		de_port_masked |= CNL_AUX_CHANNEL_F;
>  
> diff --git a/drivers/gpu/drm/i915/i915_reg.h
> b/drivers/gpu/drm/i915/i915_reg.h
> index ae7070c0806d..ba5285348534 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -5342,6 +5342,13 @@ enum {
>  #define _DPD_AUX_CH_DATA4	(dev_priv->info.display_mmio_offset 
> + 0x64320)
>  #define _DPD_AUX_CH_DATA5	(dev_priv->info.display_mmio_offset 
> + 0x64324)
>  
> +#define _DPE_AUX_CH_CTL		(dev_priv-
> >info.display_mmio_offset + 0x64410)
> +#define _DPE_AUX_CH_DATA1	(dev_priv->info.display_mmio_offset 
> + 0x64414)
> +#define _DPE_AUX_CH_DATA2	(dev_priv->info.display_mmio_offset 
> + 0x64418)
> +#define _DPE_AUX_CH_DATA3	(dev_priv->info.display_mmio_offset 
> + 0x6441c)
> +#define _DPE_AUX_CH_DATA4	(dev_priv->info.display_mmio_offset 
> + 0x64420)
> +#define _DPE_AUX_CH_DATA5	(dev_priv->info.display_mmio_offset 
> + 0x64424)
> +
>  #define _DPF_AUX_CH_CTL		(dev_priv-
> >info.display_mmio_offset + 0x64510)
>  #define _DPF_AUX_CH_DATA1	(dev_priv->info.display_mmio_offset 
> + 0x64514)
>  #define _DPF_AUX_CH_DATA2	(dev_priv->info.display_mmio_offset 
> + 0x64518)
> @@ -7040,6 +7047,7 @@ enum {
>  #define GEN8_DE_PORT_IMR _MMIO(0x44444)
>  #define GEN8_DE_PORT_IIR _MMIO(0x44448)
>  #define GEN8_DE_PORT_IER _MMIO(0x4444c)
> +#define  ICL_AUX_CHANNEL_E		(1 << 29)
>  #define  CNL_AUX_CHANNEL_F		(1 << 28)
>  #define  GEN9_AUX_CHANNEL_D		(1 << 27)
>  #define  GEN9_AUX_CHANNEL_C		(1 << 26)
> diff --git a/drivers/gpu/drm/i915/intel_display.h
> b/drivers/gpu/drm/i915/intel_display.h
> index fcedc600706b..653d85f8a374 100644
> --- a/drivers/gpu/drm/i915/intel_display.h
> +++ b/drivers/gpu/drm/i915/intel_display.h
> @@ -162,7 +162,7 @@ enum aux_ch {
>  	AUX_CH_B,
>  	AUX_CH_C,
>  	AUX_CH_D,
> -	_AUX_CH_E, /* does not exist */
> +	AUX_CH_E, /* ICL+ */
>  	AUX_CH_F,
>  };
>  
> @@ -203,6 +203,7 @@ enum intel_display_power_domain {
>  	POWER_DOMAIN_AUX_B,
>  	POWER_DOMAIN_AUX_C,
>  	POWER_DOMAIN_AUX_D,
> +	POWER_DOMAIN_AUX_E,
>  	POWER_DOMAIN_AUX_F,
>  	POWER_DOMAIN_AUX_IO_A,
>  	POWER_DOMAIN_GMBUS,
> diff --git a/drivers/gpu/drm/i915/intel_dp.c
> b/drivers/gpu/drm/i915/intel_dp.c
> index bcc3f330b301..588a5de3a8ee 100644
> --- a/drivers/gpu/drm/i915/intel_dp.c
> +++ b/drivers/gpu/drm/i915/intel_dp.c
> @@ -1527,6 +1527,9 @@ static enum aux_ch intel_aux_ch(struct intel_dp
> *intel_dp)
>  	case DP_AUX_D:
>  		aux_ch = AUX_CH_D;
>  		break;
> +	case DP_AUX_E:
> +		aux_ch = AUX_CH_E;
> +		break;
>  	case DP_AUX_F:
>  		aux_ch = AUX_CH_F;
>  		break;
> @@ -1554,6 +1557,8 @@ intel_aux_power_domain(struct intel_dp
> *intel_dp)
>  		return POWER_DOMAIN_AUX_C;
>  	case AUX_CH_D:
>  		return POWER_DOMAIN_AUX_D;
> +	case AUX_CH_E:
> +		return POWER_DOMAIN_AUX_E;
>  	case AUX_CH_F:
>  		return POWER_DOMAIN_AUX_F;
>  	default:
> @@ -1640,6 +1645,7 @@ static i915_reg_t skl_aux_ctl_reg(struct
> intel_dp *intel_dp)
>  	case AUX_CH_B:
>  	case AUX_CH_C:
>  	case AUX_CH_D:
> +	case AUX_CH_E:
>  	case AUX_CH_F:
>  		return DP_AUX_CH_CTL(aux_ch);
>  	default:
> @@ -1658,6 +1664,7 @@ static i915_reg_t skl_aux_data_reg(struct
> intel_dp *intel_dp, int index)
>  	case AUX_CH_B:
>  	case AUX_CH_C:
>  	case AUX_CH_D:
> +	case AUX_CH_E:
>  	case AUX_CH_F:
>  		return DP_AUX_CH_DATA(aux_ch, index);
>  	default:
> diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c
> b/drivers/gpu/drm/i915/intel_runtime_pm.c
> index 53a6eaa9671a..0e4a631afc7d 100644
> --- a/drivers/gpu/drm/i915/intel_runtime_pm.c
> +++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
> @@ -128,6 +128,8 @@ intel_display_power_domain_str(enum
> intel_display_power_domain domain)
>  		return "AUX_C";
>  	case POWER_DOMAIN_AUX_D:
>  		return "AUX_D";
> +	case POWER_DOMAIN_AUX_E:
> +		return "AUX E";

This should be "AUX_E" instead of "AUX E" and I'm 100% sure it's an
error I introduced myself to the patch.

>  	case POWER_DOMAIN_AUX_F:
>  		return "AUX_F";
>  	case POWER_DOMAIN_AUX_IO_A:
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  reply	other threads:[~2018-05-25  0:12 UTC|newest]

Thread overview: 127+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2018-05-22  0:25 [PATCH 00/24] More ICL display patches Paulo Zanoni
2018-05-22  0:25 ` [PATCH 01/24] drm/i915/icl: Extend AUX F interrupts to ICL Paulo Zanoni
2018-05-23 19:02   ` Srivatsa, Anusha
2018-05-22  0:25 ` [PATCH 02/24] drm/i915/icl: GSE interrupt moves from DE_MISC to GU_MISC Paulo Zanoni
2018-05-24  9:22   ` Mika Kuoppala
2018-05-24 22:51     ` Dhinakaran Pandiyan
2018-05-25 12:00       ` Mika Kuoppala
2018-05-25 19:43         ` [PATCH v2] " Dhinakaran Pandiyan
2018-05-25 19:56           ` Chris Wilson
2018-06-14  1:51             ` Dhinakaran Pandiyan
2018-06-14 10:32               ` Ville Syrjälä
2018-06-14 20:21                 ` Dhinakaran Pandiyan
2018-06-14 19:54             ` [PATCH v3] " Dhinakaran Pandiyan
2018-06-15 23:18               ` Paulo Zanoni
2018-05-22  0:25 ` [PATCH 03/24] drm/i915/icl: introduce tc_port Paulo Zanoni
2018-05-22  6:13   ` Kumar, Mahesh
2018-05-22  0:25 ` [PATCH 04/24] drm/i915/icl: Support for TC North Display interrupts Paulo Zanoni
2018-06-13 22:20   ` Lucas De Marchi
2018-06-15 23:47     ` Paulo Zanoni
2018-05-22  0:25 ` [PATCH 05/24] drm/i915/icp: Add Interrupt Support Paulo Zanoni
2018-05-24 23:53   ` Lucas De Marchi
2018-05-25  0:45     ` Dhinakaran Pandiyan
2018-05-25  0:43       ` Lucas De Marchi
2018-05-30  0:04         ` Lucas De Marchi
2018-06-13 22:23           ` Lucas De Marchi
2018-06-14  0:04             ` Paulo Zanoni
2018-06-14  2:21             ` Dhinakaran Pandiyan
2018-06-18 19:10               ` Anusha Srivatsa
2018-05-22  0:25 ` [PATCH 06/24] drm/i915/ICL: Add register definition for DFLEXDPMLE Paulo Zanoni
2018-05-25  0:26   ` Paulo Zanoni
2018-05-25 16:14     ` Lucas De Marchi
2018-05-25 16:58       ` Manasi Navare
2018-05-25 18:52   ` [PATCH v2 " Manasi Navare
2018-05-25 19:03   ` [PATCH v3 06/24] drm/i915/icl: " Manasi Navare
2018-05-22  0:25 ` [PATCH 07/24] drm/i915/icl: Add DDI HDMI level selection for ICL Paulo Zanoni
2018-05-25 16:26   ` Lucas De Marchi
2018-06-01 22:32     ` Paulo Zanoni
2018-06-11 23:51       ` Lucas De Marchi
2018-05-22  0:25 ` [PATCH 08/24] drm/i915/icl: Map VBT DDC Pin to BSpec DDC Pin Paulo Zanoni
2018-05-23 19:43   ` James Ausmus
2018-05-22  0:25 ` [PATCH 09/24] drm/i915/icl: Add Icelake PCH detection Paulo Zanoni
2018-05-25  0:29   ` Paulo Zanoni
2018-05-22  0:25 ` [PATCH 10/24] drm/i915/icl: add icelake_get_ddi_pll() Paulo Zanoni
2018-06-13 23:15   ` Lucas De Marchi
2018-06-13 23:51     ` Paulo Zanoni
2018-06-13 23:55       ` Lucas De Marchi
2018-05-22  0:25 ` [PATCH 11/24] drm/i915/icl: Get DDI clock for ICL based on PLLs Paulo Zanoni
2018-05-22 11:44   ` Mika Kahola
2018-05-23  5:48     ` Lucas De Marchi
2018-05-23 21:54     ` Paulo Zanoni
2018-05-23 21:15   ` Paulo Zanoni
2018-05-23 22:44   ` [PATCH v2 " Paulo Zanoni
2018-05-24 13:12     ` Mika Kahola
2018-05-22  0:25 ` [PATCH 12/24] drm/i915/icl: Calculate link clock using the new registers Paulo Zanoni
2018-05-25  0:33   ` Paulo Zanoni
2018-05-22  0:25 ` [PATCH 13/24] drm/i915/icl: unconditionally init DDI for every port Paulo Zanoni
2018-06-13 23:34   ` Lucas De Marchi
2018-06-13 23:47     ` Paulo Zanoni
2018-05-22  0:25 ` [PATCH 14/24] drm/i915/icl: start adding the TBT pll Paulo Zanoni
2018-06-14  0:37   ` Lucas De Marchi
2018-05-22  0:25 ` [PATCH 15/24] drm/i915/icl: compute the TBT PLL registers Paulo Zanoni
2018-06-08 20:19   ` Srivatsa, Anusha
2018-06-13 21:19     ` Paulo Zanoni
2018-06-18 19:57       ` Srivatsa, Anusha
2018-06-13 21:42   ` [PATCH v2 " Paulo Zanoni
2018-05-22  0:25 ` [PATCH 16/24] drm/i915/icl: Handle hotplug interrupts for DP over TBT Paulo Zanoni
2018-06-14  0:51   ` Lucas De Marchi
2018-05-22  0:25 ` [PATCH 17/24] drm/i915/icl: Add 10-bit support for hdmi Paulo Zanoni
2018-06-20 16:55   ` Ville Syrjälä
2018-05-22  0:25 ` [PATCH 18/24] drm/i915/icl: implement icl_digital_port_connected() Paulo Zanoni
2018-06-19 22:28   ` Lucas De Marchi
2018-06-20 21:01     ` Paulo Zanoni
2018-05-22  0:25 ` [PATCH 19/24] drm/i915/icl: store the port type for TC ports Paulo Zanoni
2018-06-14 19:59   ` Rodrigo Vivi
2018-06-21  0:37     ` Paulo Zanoni
2018-05-22  0:25 ` [PATCH 20/24] drm/i915/icl: implement the tc/legacy HPD {dis, }connect flow for DP Paulo Zanoni
2018-06-21 22:04   ` Srivatsa, Anusha
2018-07-11 21:28     ` Paulo Zanoni
2018-05-22  0:25 ` [PATCH 21/24] drm/i915/icl: implement the legacy HPD {dis, }connect flow for HDMI Paulo Zanoni
2018-06-26 11:41   ` Mika Kahola
2018-05-22  0:25 ` [PATCH 22/24] drm/i915/icl: Update FIA supported lane count for hpd Paulo Zanoni
2018-06-21 22:45   ` Srivatsa, Anusha
2018-05-22  0:25 ` [PATCH 23/24] drm/i915/icl: program MG_DP_MODE Paulo Zanoni
2018-06-19 12:59   ` Maarten Lankhorst
2018-06-19 13:00     ` Maarten Lankhorst
2018-05-22  0:25 ` [PATCH 24/24] drm/i915/icl: toggle PHY clock gating around link training Paulo Zanoni
2018-06-19 13:22   ` Maarten Lankhorst
2018-05-22  0:38 ` ✗ Fi.CI.CHECKPATCH: warning for More ICL display patches Patchwork
2018-05-22  0:45 ` ✗ Fi.CI.SPARSE: " Patchwork
2018-05-22  1:00 ` ✓ Fi.CI.BAT: success " Patchwork
2018-05-22  1:52 ` ✓ Fi.CI.IGT: " Patchwork
2018-05-23 22:59 ` ✗ Fi.CI.CHECKPATCH: warning for More ICL display patches (rev2) Patchwork
2018-05-23 23:06 ` ✗ Fi.CI.SPARSE: " Patchwork
2018-05-23 23:19 ` ✓ Fi.CI.BAT: success " Patchwork
2018-05-24  0:54 ` ✗ Fi.CI.IGT: failure " Patchwork
2018-05-24 23:42 ` [PATCH 25/24] drm/i915/icl: fix gmbus gpio pin mapping Paulo Zanoni
2018-05-24 23:42   ` [PATCH 26/24] drm/i915/icl: Add allowed DP rates for Icelake Paulo Zanoni
2018-05-25 18:32     ` James Ausmus
2018-06-01 23:43       ` Paulo Zanoni
2018-06-14 19:24         ` Rodrigo Vivi
2018-06-15  0:45           ` Manasi Navare
2018-06-15  5:20             ` Rodrigo Vivi
2018-06-14 19:23     ` Rodrigo Vivi
2018-06-19 20:39       ` Manasi Navare
2018-05-24 23:42   ` [PATCH 27/24] drm/i915/dp: Add support for HBR3 and TPS4 during link training Paulo Zanoni
2018-05-25 18:41     ` James Ausmus
2018-05-24 23:42   ` [PATCH 28/24] drm/i915/icl: implement DVFS for ICL Paulo Zanoni
2018-06-14 19:47     ` Rodrigo Vivi
2018-05-24 23:42   ` [PATCH 29/24] drm/i915/icl: DP_AUX_E is valid on ICL+ Paulo Zanoni
2018-05-25  0:12     ` Paulo Zanoni [this message]
2018-06-11 23:01       ` Paulo Zanoni
2018-05-24 23:42   ` [PATCH 30/24] drm/i915/icl: update VBT's child_device_config flags2 field Paulo Zanoni
2018-06-14 19:33     ` Rodrigo Vivi
2018-05-25  0:36   ` [PATCH 25/24] drm/i915/icl: fix gmbus gpio pin mapping Lucas De Marchi
2018-05-25 16:24     ` Ville Syrjälä
2018-05-25 16:26       ` Lucas De Marchi
2018-06-14 19:28     ` Rodrigo Vivi
2018-06-14 19:07   ` Rodrigo Vivi
2018-06-14 20:43     ` Paulo Zanoni
2018-05-24 23:59 ` ✗ Fi.CI.CHECKPATCH: warning for More ICL display patches (rev7) Patchwork
2018-05-25  0:06 ` ✗ Fi.CI.SPARSE: " Patchwork
2018-05-25  0:14 ` ✗ Fi.CI.BAT: failure " Patchwork
2018-05-25  0:49 ` ✗ Fi.CI.BAT: failure for More ICL display patches (rev8) Patchwork
2018-05-25 20:11 ` ✗ Fi.CI.BAT: failure for More ICL display patches (rev11) Patchwork
2018-06-01 23:22 ` [PATCH 00/24] More ICL display patches Paulo Zanoni
2018-06-13 21:49 ` ✗ Fi.CI.BAT: failure for More ICL display patches (rev12) Patchwork
2018-06-14 20:20 ` ✗ Fi.CI.BAT: failure for More ICL display patches (rev13) Patchwork

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