[PATCH v5 1/2] drm/i915/gmbus: Increase the Bytes per Rd/Wr Op

[PATCH v5 1/2] drm/i915/gmbus: Increase the Bytes per Rd/Wr Op

[Ramalingam C]

GMBUS HW supports 511Bytes as Max Bytes per single RD/WR op. Instead of
enabling the 511Bytes per RD/WR cycle on legacy platforms for no
absolute ROIs, this change allows the max bytes per op upto 511Bytes
from Gen9 onwards.

v2:
  No Change.
v3:
  Inline function for max_xfer_size and renaming of the macro.[Jani]
v4:
  Extra brackets removed [ville]
  Commit msg is modified.
v5:
  Collecting the Reviewed-By received.

Cc: Jani Nikula <jani.nikula@intel.com>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Ramalingam C <ramalingam.c@intel.com>
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h  |  1 +
 drivers/gpu/drm/i915/intel_i2c.c | 11 +++++++++--
 2 files changed, 10 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index c30cfcd90754..7353ad447936 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -3093,6 +3093,7 @@ enum i915_power_well_id {
 #define   GMBUS_CYCLE_STOP	(4 << 25)
 #define   GMBUS_BYTE_COUNT_SHIFT 16
 #define   GMBUS_BYTE_COUNT_MAX   256U
+#define   GEN9_GMBUS_BYTE_COUNT_MAX 511U
 #define   GMBUS_SLAVE_INDEX_SHIFT 8
 #define   GMBUS_SLAVE_ADDR_SHIFT 1
 #define   GMBUS_SLAVE_READ	(1 << 0)
diff --git a/drivers/gpu/drm/i915/intel_i2c.c b/drivers/gpu/drm/i915/intel_i2c.c
index 97606c1be70d..82bb9c33ab1c 100644
--- a/drivers/gpu/drm/i915/intel_i2c.c
+++ b/drivers/gpu/drm/i915/intel_i2c.c
@@ -361,6 +361,13 @@ gmbus_wait_idle(struct drm_i915_private *dev_priv)
 	return ret;
 }
 
+static inline
+unsigned int gmbus_max_xfer_size(struct drm_i915_private *dev_priv)
+{
+	return INTEL_GEN(dev_priv) >= 9 ? GEN9_GMBUS_BYTE_COUNT_MAX :
+	       GMBUS_BYTE_COUNT_MAX;
+}
+
 static int
 gmbus_xfer_read_chunk(struct drm_i915_private *dev_priv,
 		      unsigned short addr, u8 *buf, unsigned int len,
@@ -400,7 +407,7 @@ gmbus_xfer_read(struct drm_i915_private *dev_priv, struct i2c_msg *msg,
 	int ret;
 
 	do {
-		len = min(rx_size, GMBUS_BYTE_COUNT_MAX);
+		len = min(rx_size, gmbus_max_xfer_size(dev_priv));
 
 		ret = gmbus_xfer_read_chunk(dev_priv, msg->addr,
 					    buf, len, gmbus1_index);
@@ -462,7 +469,7 @@ gmbus_xfer_write(struct drm_i915_private *dev_priv, struct i2c_msg *msg,
 	int ret;
 
 	do {
-		len = min(tx_size, GMBUS_BYTE_COUNT_MAX);
+		len = min(tx_size, gmbus_max_xfer_size(dev_priv));
 
 		ret = gmbus_xfer_write_chunk(dev_priv, msg->addr, buf, len,
 					     gmbus1_index);
-- 
2.7.4

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[PATCH v6 2/2] drm/i915/gmbus: Enable burst read

[Ramalingam C]

Support for Burst read in HW is added for HDCP2.2 compliance
requirement.

This patch enables the burst read for all the gmbus read of more than
511Bytes, on capable platforms.

v2:
  Extra line is removed.
v3:
  Macro is added for detecting the BURST_READ Support [Jani]
  Runtime detection of the need for burst_read [Jani]
  Calculation enhancement.
v4:
  GMBUS0 reg val is passed from caller [ville]
  Removed a extra var [ville]
  Extra brackets are removed [ville]
  Implemented the handling of 512Bytes Burst Read.
v5:
  Burst read max length is fixed at 767Bytes [Ville]
v6:
  Collecting the received reviewed-by.

Signed-off-by: Ramalingam C <ramalingam.c@intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/i915_drv.h  |  3 ++
 drivers/gpu/drm/i915/i915_reg.h  |  1 +
 drivers/gpu/drm/i915/intel_i2c.c | 61 +++++++++++++++++++++++++++++++++-------
 3 files changed, 55 insertions(+), 10 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 2b684f431c60..7636afd78368 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -2574,6 +2574,9 @@ intel_info(const struct drm_i915_private *dev_priv)
 	 IS_SKL_GT3(dev_priv) || IS_SKL_GT4(dev_priv))
 
 #define HAS_GMBUS_IRQ(dev_priv) (INTEL_GEN(dev_priv) >= 4)
+#define HAS_GMBUS_BURST_READ(dev_priv) (INTEL_GEN(dev_priv) >= 10 || \
+					IS_GEMINILAKE(dev_priv) || \
+					IS_KABYLAKE(dev_priv))
 
 /* With the 945 and later, Y tiling got adjusted so that it was 32 128-byte
  * rows, which changed the alignment requirements and fence programming.
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 7353ad447936..7bfc11a676b1 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -3064,6 +3064,7 @@ enum i915_power_well_id {
 #define   GMBUS_RATE_400KHZ	(2 << 8) /* reserved on Pineview */
 #define   GMBUS_RATE_1MHZ	(3 << 8) /* reserved on Pineview */
 #define   GMBUS_HOLD_EXT	(1 << 7) /* 300ns hold time, rsvd on Pineview */
+#define   GMBUS_BYTE_CNT_OVERRIDE (1 << 6)
 #define   GMBUS_PIN_DISABLED	0
 #define   GMBUS_PIN_SSC		1
 #define   GMBUS_PIN_VGADDC	2
diff --git a/drivers/gpu/drm/i915/intel_i2c.c b/drivers/gpu/drm/i915/intel_i2c.c
index 82bb9c33ab1c..bef32b7c248e 100644
--- a/drivers/gpu/drm/i915/intel_i2c.c
+++ b/drivers/gpu/drm/i915/intel_i2c.c
@@ -371,12 +371,29 @@ unsigned int gmbus_max_xfer_size(struct drm_i915_private *dev_priv)
 static int
 gmbus_xfer_read_chunk(struct drm_i915_private *dev_priv,
 		      unsigned short addr, u8 *buf, unsigned int len,
-		      u32 gmbus1_index)
+		      u32 gmbus0_reg, u32 gmbus1_index)
 {
+	unsigned int size = len;
+	bool burst_read = len > gmbus_max_xfer_size(dev_priv);
+	bool extra_byte_added = false;
+
+	if (burst_read) {
+		/*
+		 * As per HW Spec, for 512Bytes need to read extra Byte and
+		 * Ignore the extra byte read.
+		 */
+		if (len == 512) {
+			extra_byte_added = true;
+			len++;
+		}
+		size = len % 256 + 256;
+		I915_WRITE_FW(GMBUS0, gmbus0_reg | GMBUS_BYTE_CNT_OVERRIDE);
+	}
+
 	I915_WRITE_FW(GMBUS1,
 		      gmbus1_index |
 		      GMBUS_CYCLE_WAIT |
-		      (len << GMBUS_BYTE_COUNT_SHIFT) |
+		      (size << GMBUS_BYTE_COUNT_SHIFT) |
 		      (addr << GMBUS_SLAVE_ADDR_SHIFT) |
 		      GMBUS_SLAVE_READ | GMBUS_SW_RDY);
 	while (len) {
@@ -389,17 +406,34 @@ gmbus_xfer_read_chunk(struct drm_i915_private *dev_priv,
 
 		val = I915_READ_FW(GMBUS3);
 		do {
+			if (extra_byte_added && len == 1)
+				break;
+
 			*buf++ = val & 0xff;
 			val >>= 8;
 		} while (--len && ++loop < 4);
+
+		if (burst_read && len == size - 4)
+			/* Reset the override bit */
+			I915_WRITE_FW(GMBUS0, gmbus0_reg);
 	}
 
 	return 0;
 }
 
+/*
+ * HW spec says that 512Bytes in Burst read need special treatment.
+ * But it doesn't talk about other multiple of 256Bytes. And couldn't locate
+ * an I2C slave, which supports such a lengthy burst read too for experiments.
+ *
+ * So until things get clarified on HW support, to avoid the burst read length
+ * in fold of 256Bytes except 512, max burst read length is fixed at 767Bytes.
+ */
+#define INTEL_GMBUS_BURST_READ_MAX_LEN		767U
+
 static int
 gmbus_xfer_read(struct drm_i915_private *dev_priv, struct i2c_msg *msg,
-		u32 gmbus1_index)
+		u32 gmbus0_reg, u32 gmbus1_index)
 {
 	u8 *buf = msg->buf;
 	unsigned int rx_size = msg->len;
@@ -407,10 +441,13 @@ gmbus_xfer_read(struct drm_i915_private *dev_priv, struct i2c_msg *msg,
 	int ret;
 
 	do {
-		len = min(rx_size, gmbus_max_xfer_size(dev_priv));
+		if (HAS_GMBUS_BURST_READ(dev_priv))
+			len = min(rx_size, INTEL_GMBUS_BURST_READ_MAX_LEN);
+		else
+			len = min(rx_size, gmbus_max_xfer_size(dev_priv));
 
-		ret = gmbus_xfer_read_chunk(dev_priv, msg->addr,
-					    buf, len, gmbus1_index);
+		ret = gmbus_xfer_read_chunk(dev_priv, msg->addr, buf, len,
+					    gmbus0_reg, gmbus1_index);
 		if (ret)
 			return ret;
 
@@ -498,7 +535,8 @@ gmbus_is_index_xfer(struct i2c_msg *msgs, int i, int num)
 }
 
 static int
-gmbus_index_xfer(struct drm_i915_private *dev_priv, struct i2c_msg *msgs)
+gmbus_index_xfer(struct drm_i915_private *dev_priv, struct i2c_msg *msgs,
+		 u32 gmbus0_reg)
 {
 	u32 gmbus1_index = 0;
 	u32 gmbus5 = 0;
@@ -516,7 +554,8 @@ gmbus_index_xfer(struct drm_i915_private *dev_priv, struct i2c_msg *msgs)
 		I915_WRITE_FW(GMBUS5, gmbus5);
 
 	if (msgs[1].flags & I2C_M_RD)
-		ret = gmbus_xfer_read(dev_priv, &msgs[1], gmbus1_index);
+		ret = gmbus_xfer_read(dev_priv, &msgs[1], gmbus0_reg,
+				      gmbus1_index);
 	else
 		ret = gmbus_xfer_write(dev_priv, &msgs[1], gmbus1_index);
 
@@ -551,10 +590,12 @@ do_gmbus_xfer(struct i2c_adapter *adapter, struct i2c_msg *msgs, int num,
 	for (; i < num; i += inc) {
 		inc = 1;
 		if (gmbus_is_index_xfer(msgs, i, num)) {
-			ret = gmbus_index_xfer(dev_priv, &msgs[i]);
+			ret = gmbus_index_xfer(dev_priv, &msgs[i],
+					       gmbus0_source | bus->reg0);
 			inc = 2; /* an index transmission is two msgs */
 		} else if (msgs[i].flags & I2C_M_RD) {
-			ret = gmbus_xfer_read(dev_priv, &msgs[i], 0);
+			ret = gmbus_xfer_read(dev_priv, &msgs[i],
+					      gmbus0_source | bus->reg0, 0);
 		} else {
 			ret = gmbus_xfer_write(dev_priv, &msgs[i], 0);
 		}
-- 
2.7.4

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✗ Fi.CI.CHECKPATCH: warning for series starting with [v5,1/2] drm/i915/gmbus: Increase the Bytes per Rd/Wr Op

[Patchwork]

== Series Details ==

Series: series starting with [v5,1/2] drm/i915/gmbus: Increase the Bytes per Rd/Wr Op
URL   : https://patchwork.freedesktop.org/series/45576/
State : warning

== Summary ==

$ dim checkpatch origin/drm-tip
3065ccd37dd8 drm/i915/gmbus: Increase the Bytes per Rd/Wr Op
968b33b77723 drm/i915/gmbus: Enable burst read
-:42: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'dev_priv' - possible side-effects?
#42: FILE: drivers/gpu/drm/i915/i915_drv.h:2577:
+#define HAS_GMBUS_BURST_READ(dev_priv) (INTEL_GEN(dev_priv) >= 10 || \
+					IS_GEMINILAKE(dev_priv) || \
+					IS_KABYLAKE(dev_priv))

total: 0 errors, 0 warnings, 1 checks, 130 lines checked

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✗ Fi.CI.SPARSE: warning for series starting with [v5,1/2] drm/i915/gmbus: Increase the Bytes per Rd/Wr Op

[Patchwork]

== Series Details ==

Series: series starting with [v5,1/2] drm/i915/gmbus: Increase the Bytes per Rd/Wr Op
URL   : https://patchwork.freedesktop.org/series/45576/
State : warning

== Summary ==

$ dim sparse origin/drm-tip
Commit: drm/i915/gmbus: Increase the Bytes per Rd/Wr Op
-O:drivers/gpu/drm/i915/intel_i2c.c:403:23: warning: expression using sizeof(void)
-O:drivers/gpu/drm/i915/intel_i2c.c:465:23: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/intel_i2c.c:410:23: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/intel_i2c.c:410:23: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/intel_i2c.c:472:23: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/intel_i2c.c:472:23: warning: expression using sizeof(void)

Commit: drm/i915/gmbus: Enable burst read
-O:drivers/gpu/drm/i915/intel_i2c.c:410:23: warning: expression using sizeof(void)
-O:drivers/gpu/drm/i915/intel_i2c.c:410:23: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/intel_i2c.c:445:31: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/intel_i2c.c:447:31: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/intel_i2c.c:447:31: warning: expression using sizeof(void)
-drivers/gpu/drm/i915/selftests/../i915_drv.h:3672:16: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/selftests/../i915_drv.h:3675:16: warning: expression using sizeof(void)

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✓ Fi.CI.BAT: success for series starting with [v5,1/2] drm/i915/gmbus: Increase the Bytes per Rd/Wr Op

[Patchwork]

== Series Details ==

Series: series starting with [v5,1/2] drm/i915/gmbus: Increase the Bytes per Rd/Wr Op
URL   : https://patchwork.freedesktop.org/series/45576/
State : success

== Summary ==

= CI Bug Log - changes from CI_DRM_4397 -> Patchwork_9467 =

== Summary - SUCCESS ==

  No regressions found.

  External URL: https://patchwork.freedesktop.org/api/1.0/series/45576/revisions/1/mbox/

== Known issues ==

  Here are the changes found in Patchwork_9467 that come from known issues:

  === IGT changes ===

    ==== Issues hit ====

    igt@kms_frontbuffer_tracking@basic:
      fi-hsw-peppy:       PASS -> DMESG-FAIL (fdo#106103, fdo#102614)

    igt@kms_pipe_crc_basic@nonblocking-crc-pipe-c-frame-sequence:
      fi-whl-u:           PASS -> FAIL (fdo#103481)

    
  fdo#102614 https://bugs.freedesktop.org/show_bug.cgi?id=102614
  fdo#103481 https://bugs.freedesktop.org/show_bug.cgi?id=103481
  fdo#106103 https://bugs.freedesktop.org/show_bug.cgi?id=106103


== Participating hosts (44 -> 39) ==

  Missing    (5): fi-ctg-p8600 fi-ilk-m540 fi-byt-squawks fi-bsw-cyan fi-hsw-4200u 


== Build changes ==

    * Linux: CI_DRM_4397 -> Patchwork_9467

  CI_DRM_4397: 7306233935b0e426454e8adcf09a8022faa03cbc @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_4530: 0e98bf69f146eb72fe3a7c3b19a049b5786f0ca3 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_9467: 968b33b77723ba1e10028b97c56c13477cfa732b @ git://anongit.freedesktop.org/gfx-ci/linux


== Linux commits ==

968b33b77723 drm/i915/gmbus: Enable burst read
3065ccd37dd8 drm/i915/gmbus: Increase the Bytes per Rd/Wr Op

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_9467/issues.html
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Re: [PATCH v5 1/2] drm/i915/gmbus: Increase the Bytes per Rd/Wr Op

[Ramalingam C]

Please ignore this series as I have pushed it again to it's original 
series itself. Sorry for the inconvenience.

https://patchwork.freedesktop.org/series/41632/

Thanks and Regards,
Ram


On Thursday 28 June 2018 06:18 PM, Ramalingam C wrote:
> GMBUS HW supports 511Bytes as Max Bytes per single RD/WR op. Instead of
> enabling the 511Bytes per RD/WR cycle on legacy platforms for no
> absolute ROIs, this change allows the max bytes per op upto 511Bytes
> from Gen9 onwards.
>
> v2:
>    No Change.
> v3:
>    Inline function for max_xfer_size and renaming of the macro.[Jani]
> v4:
>    Extra brackets removed [ville]
>    Commit msg is modified.
> v5:
>    Collecting the Reviewed-By received.
>
> Cc: Jani Nikula <jani.nikula@intel.com>
> Cc: Chris Wilson <chris@chris-wilson.co.uk>
> Signed-off-by: Ramalingam C <ramalingam.c@intel.com>
> Reviewed-by: Jani Nikula <jani.nikula@intel.com>
> ---
>   drivers/gpu/drm/i915/i915_reg.h  |  1 +
>   drivers/gpu/drm/i915/intel_i2c.c | 11 +++++++++--
>   2 files changed, 10 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index c30cfcd90754..7353ad447936 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -3093,6 +3093,7 @@ enum i915_power_well_id {
>   #define   GMBUS_CYCLE_STOP	(4 << 25)
>   #define   GMBUS_BYTE_COUNT_SHIFT 16
>   #define   GMBUS_BYTE_COUNT_MAX   256U
> +#define   GEN9_GMBUS_BYTE_COUNT_MAX 511U
>   #define   GMBUS_SLAVE_INDEX_SHIFT 8
>   #define   GMBUS_SLAVE_ADDR_SHIFT 1
>   #define   GMBUS_SLAVE_READ	(1 << 0)
> diff --git a/drivers/gpu/drm/i915/intel_i2c.c b/drivers/gpu/drm/i915/intel_i2c.c
> index 97606c1be70d..82bb9c33ab1c 100644
> --- a/drivers/gpu/drm/i915/intel_i2c.c
> +++ b/drivers/gpu/drm/i915/intel_i2c.c
> @@ -361,6 +361,13 @@ gmbus_wait_idle(struct drm_i915_private *dev_priv)
>   	return ret;
>   }
>   
> +static inline
> +unsigned int gmbus_max_xfer_size(struct drm_i915_private *dev_priv)
> +{
> +	return INTEL_GEN(dev_priv) >= 9 ? GEN9_GMBUS_BYTE_COUNT_MAX :
> +	       GMBUS_BYTE_COUNT_MAX;
> +}
> +
>   static int
>   gmbus_xfer_read_chunk(struct drm_i915_private *dev_priv,
>   		      unsigned short addr, u8 *buf, unsigned int len,
> @@ -400,7 +407,7 @@ gmbus_xfer_read(struct drm_i915_private *dev_priv, struct i2c_msg *msg,
>   	int ret;
>   
>   	do {
> -		len = min(rx_size, GMBUS_BYTE_COUNT_MAX);
> +		len = min(rx_size, gmbus_max_xfer_size(dev_priv));
>   
>   		ret = gmbus_xfer_read_chunk(dev_priv, msg->addr,
>   					    buf, len, gmbus1_index);
> @@ -462,7 +469,7 @@ gmbus_xfer_write(struct drm_i915_private *dev_priv, struct i2c_msg *msg,
>   	int ret;
>   
>   	do {
> -		len = min(tx_size, GMBUS_BYTE_COUNT_MAX);
> +		len = min(tx_size, gmbus_max_xfer_size(dev_priv));
>   
>   		ret = gmbus_xfer_write_chunk(dev_priv, msg->addr, buf, len,
>   					     gmbus1_index);

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✓ Fi.CI.IGT: success for series starting with [v5,1/2] drm/i915/gmbus: Increase the Bytes per Rd/Wr Op

[Patchwork]

== Series Details ==

Series: series starting with [v5,1/2] drm/i915/gmbus: Increase the Bytes per Rd/Wr Op
URL   : https://patchwork.freedesktop.org/series/45576/
State : success

== Summary ==

= CI Bug Log - changes from CI_DRM_4397_full -> Patchwork_9467_full =

== Summary - WARNING ==

  Minor unknown changes coming with Patchwork_9467_full need to be verified
  manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_9467_full, please notify your bug team to allow them
  to document this new failure mode, which will reduce false positives in CI.

  

== Possible new issues ==

  Here are the unknown changes that may have been introduced in Patchwork_9467_full:

  === IGT changes ===

    ==== Possible regressions ====

    igt@drv_selftest@live_gtt:
      {shard-glk9}:       NOTRUN -> INCOMPLETE

    igt@drv_selftest@mock_scatterlist:
      {shard-glk9}:       NOTRUN -> DMESG-WARN

    
    ==== Warnings ====

    igt@gem_exec_schedule@deep-blt:
      shard-kbl:          PASS -> SKIP

    
== Known issues ==

  Here are the changes found in Patchwork_9467_full that come from known issues:

  === IGT changes ===

    ==== Issues hit ====

    igt@drv_selftest@live_hangcheck:
      shard-apl:          PASS -> DMESG-FAIL (fdo#106947, fdo#106560)

    igt@gem_mmap_gtt@coherency:
      shard-glk:          NOTRUN -> FAIL (fdo#100587)

    igt@kms_cursor_legacy@2x-long-nonblocking-modeset-vs-cursor-atomic:
      shard-glk:          NOTRUN -> FAIL (fdo#106509)

    igt@kms_flip@2x-plain-flip-fb-recreate-interruptible:
      shard-glk:          NOTRUN -> FAIL (fdo#100368)

    igt@kms_flip@flip-vs-expired-vblank:
      shard-hsw:          PASS -> FAIL (fdo#105363, fdo#102887)

    igt@kms_flip@plain-flip-fb-recreate:
      shard-glk:          PASS -> FAIL (fdo#100368)

    igt@kms_flip_tiling@flip-x-tiled:
      shard-glk:          PASS -> FAIL (fdo#104724, fdo#103822)

    igt@kms_setmode@basic:
      shard-apl:          PASS -> FAIL (fdo#99912)
      shard-kbl:          PASS -> FAIL (fdo#99912)

    igt@perf_pmu@busy-accuracy-98-vcs1:
      shard-snb:          NOTRUN -> INCOMPLETE (fdo#105411)

    
    ==== Possible fixes ====

    igt@gem_exec_schedule@preemptive-hang-render:
      shard-snb:          INCOMPLETE (fdo#105411) -> SKIP

    igt@kms_flip@2x-flip-vs-expired-vblank:
      shard-glk:          FAIL (fdo#105363) -> PASS

    igt@kms_flip@flip-vs-expired-vblank:
      shard-glk:          FAIL (fdo#105189) -> PASS

    
  {name}: This element is suppressed. This means it is ignored when computing
          the status of the difference (SUCCESS, WARNING, or FAILURE).

  fdo#100368 https://bugs.freedesktop.org/show_bug.cgi?id=100368
  fdo#100587 https://bugs.freedesktop.org/show_bug.cgi?id=100587
  fdo#102887 https://bugs.freedesktop.org/show_bug.cgi?id=102887
  fdo#103822 https://bugs.freedesktop.org/show_bug.cgi?id=103822
  fdo#104724 https://bugs.freedesktop.org/show_bug.cgi?id=104724
  fdo#105189 https://bugs.freedesktop.org/show_bug.cgi?id=105189
  fdo#105363 https://bugs.freedesktop.org/show_bug.cgi?id=105363
  fdo#105411 https://bugs.freedesktop.org/show_bug.cgi?id=105411
  fdo#106509 https://bugs.freedesktop.org/show_bug.cgi?id=106509
  fdo#106560 https://bugs.freedesktop.org/show_bug.cgi?id=106560
  fdo#106947 https://bugs.freedesktop.org/show_bug.cgi?id=106947
  fdo#99912 https://bugs.freedesktop.org/show_bug.cgi?id=99912


== Participating hosts (6 -> 6) ==

  No changes in participating hosts


== Build changes ==

    * Linux: CI_DRM_4397 -> Patchwork_9467

  CI_DRM_4397: 7306233935b0e426454e8adcf09a8022faa03cbc @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_4530: 0e98bf69f146eb72fe3a7c3b19a049b5786f0ca3 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_9467: 968b33b77723ba1e10028b97c56c13477cfa732b @ git://anongit.freedesktop.org/gfx-ci/linux
  piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_9467/shards.html
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[PATCH v6 0/2] GMBUS changes

[Ramalingam C]

I am not aware if there is a reason for restricting the Bytes per GMBUS
WR/RD to 256 at present. But HW has 9Bits for Total Byte count for a
single read or Write cycle. Means we can extend a cycle of RD/WR to
511Bytes.

At present nothing much as ROI, as most of the usecases are for less
than 256Bytes. On GLK tested for 300Bytes on single normal read, found
to be working fine.

First patch does it. But I have restricted the extension to Gen9 onwards,
as I am not sure about the legacy platforms.

And second patch is enabling the burst read for all GMBUS read of more
than 511Bytes, on supported platforms. Basically this Burst read is
enabled in HW for HDCP2.2 compliance requirement. Instead of enabling
the burst read only for HDCP on special API this patch enables it for
all GMBUS read of >511Bytes, on capable platforms.

At present there is no clarity on special handling required for N*256
Bytes (Where N is >2). So as per discussions, at present we are fixing
the max length for BURST read to 767 Bytes.

Changes in V5 and V6:
  - Max length of Burst read is fixed at 767. [ville]
  - Collected Reviewed-by tags received.

Ramalingam C (2):
  drm/i915/gmbus: Increase the Bytes per Rd/Wr Op
  drm/i915/gmbus: Enable burst read

 drivers/gpu/drm/i915/i915_drv.h  |  3 ++
 drivers/gpu/drm/i915/i915_reg.h  |  2 ++
 drivers/gpu/drm/i915/intel_i2c.c | 61 ++++++++++++++++++++++++++++++++--------
 3 files changed, 55 insertions(+), 11 deletions(-)

-- 
2.7.4

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[PATCH v5 1/2] drm/i915/gmbus: Increase the Bytes per Rd/Wr Op

[Ramalingam C]

GMBUS HW supports 511Bytes as Max Bytes per single RD/WR op. Instead of
enabling the 511Bytes per RD/WR cycle on legacy platforms for no
absolute ROIs, this change allows the max bytes per op upto 511Bytes
from Gen9 onwards.

v2:
  No Change.
v3:
  Inline function for max_xfer_size and renaming of the macro.[Jani]
v4:
  Extra brackets removed [ville]
  Commit msg is modified.
v5:
  Collecting the Reviewed-By received.

Cc: Jani Nikula <jani.nikula@intel.com>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Ramalingam C <ramalingam.c@intel.com>
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h  |  1 +
 drivers/gpu/drm/i915/intel_i2c.c | 11 +++++++++--
 2 files changed, 10 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index c30cfcd90754..7353ad447936 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -3093,6 +3093,7 @@ enum i915_power_well_id {
 #define   GMBUS_CYCLE_STOP	(4 << 25)
 #define   GMBUS_BYTE_COUNT_SHIFT 16
 #define   GMBUS_BYTE_COUNT_MAX   256U
+#define   GEN9_GMBUS_BYTE_COUNT_MAX 511U
 #define   GMBUS_SLAVE_INDEX_SHIFT 8
 #define   GMBUS_SLAVE_ADDR_SHIFT 1
 #define   GMBUS_SLAVE_READ	(1 << 0)
diff --git a/drivers/gpu/drm/i915/intel_i2c.c b/drivers/gpu/drm/i915/intel_i2c.c
index 97606c1be70d..82bb9c33ab1c 100644
--- a/drivers/gpu/drm/i915/intel_i2c.c
+++ b/drivers/gpu/drm/i915/intel_i2c.c
@@ -361,6 +361,13 @@ gmbus_wait_idle(struct drm_i915_private *dev_priv)
 	return ret;
 }
 
+static inline
+unsigned int gmbus_max_xfer_size(struct drm_i915_private *dev_priv)
+{
+	return INTEL_GEN(dev_priv) >= 9 ? GEN9_GMBUS_BYTE_COUNT_MAX :
+	       GMBUS_BYTE_COUNT_MAX;
+}
+
 static int
 gmbus_xfer_read_chunk(struct drm_i915_private *dev_priv,
 		      unsigned short addr, u8 *buf, unsigned int len,
@@ -400,7 +407,7 @@ gmbus_xfer_read(struct drm_i915_private *dev_priv, struct i2c_msg *msg,
 	int ret;
 
 	do {
-		len = min(rx_size, GMBUS_BYTE_COUNT_MAX);
+		len = min(rx_size, gmbus_max_xfer_size(dev_priv));
 
 		ret = gmbus_xfer_read_chunk(dev_priv, msg->addr,
 					    buf, len, gmbus1_index);
@@ -462,7 +469,7 @@ gmbus_xfer_write(struct drm_i915_private *dev_priv, struct i2c_msg *msg,
 	int ret;
 
 	do {
-		len = min(tx_size, GMBUS_BYTE_COUNT_MAX);
+		len = min(tx_size, gmbus_max_xfer_size(dev_priv));
 
 		ret = gmbus_xfer_write_chunk(dev_priv, msg->addr, buf, len,
 					     gmbus1_index);
-- 
2.7.4

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