[PATCH v5] drm/i915: Use crtc_state->has_psr instead of CAN_PSR for pipe update

[PATCH v5] drm/i915: Use crtc_state->has_psr instead of CAN_PSR for pipe update

[Tarun Vyas]

In commit "drm/i915: Wait for PSR exit before checking for vblank
evasion", the idea was to limit the PSR IDLE checks when PSR is
actually supported. While CAN_PSR does do that check, it doesn't
applies on a per-crtc basis. crtc_state->has_psr is a more granular
check that only applies to pipe(s) that have PSR enabled.

Without the has_psr check, we end up waiting on the eDP transcoder's
PSR_STATUS register irrespective of whether the pipe being updated is
driving it or not.

Fixes: a608987970b9 ("drm/i915: Wait for PSR exit before checking for
vblank evasion")

v2: Remove unnecessary parantheses, make checkpatch happy.

v3: Move the has_psr check to intel_psr_wait_for_idle and commit
    message changes (DK).

v4: Derive dev_priv from intel_crtc_state (DK)

v5: Commit message changes to reflect the HW behavior (DK)

Reviewed-by: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
Signed-off-by: Tarun Vyas <tarun.vyas@intel.com>
---
 drivers/gpu/drm/i915/intel_drv.h    | 2 +-
 drivers/gpu/drm/i915/intel_psr.c    | 7 ++++++-
 drivers/gpu/drm/i915/intel_sprite.c | 2 +-
 3 files changed, 8 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 61e715ddd0d5..699073fbecb1 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -1923,7 +1923,7 @@ void intel_psr_compute_config(struct intel_dp *intel_dp,
 void intel_psr_irq_control(struct drm_i915_private *dev_priv, bool debug);
 void intel_psr_irq_handler(struct drm_i915_private *dev_priv, u32 psr_iir);
 void intel_psr_short_pulse(struct intel_dp *intel_dp);
-int intel_psr_wait_for_idle(struct drm_i915_private *dev_priv);
+int intel_psr_wait_for_idle(const struct intel_crtc_state *new_crtc_state);
 
 /* intel_runtime_pm.c */
 int intel_power_domains_init(struct drm_i915_private *);
diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c
index 23acc9ac8d4d..e97db5dd75b1 100644
--- a/drivers/gpu/drm/i915/intel_psr.c
+++ b/drivers/gpu/drm/i915/intel_psr.c
@@ -717,11 +717,16 @@ void intel_psr_disable(struct intel_dp *intel_dp,
 	cancel_work_sync(&dev_priv->psr.work);
 }
 
-int intel_psr_wait_for_idle(struct drm_i915_private *dev_priv)
+int intel_psr_wait_for_idle(const struct intel_crtc_state *new_crtc_state)
 {
+	struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->base.crtc);
+	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 	i915_reg_t reg;
 	u32 mask;
 
+	if (!new_crtc_state->has_psr)
+		return 0;
+
 	/*
 	 * The sole user right now is intel_pipe_update_start(),
 	 * which won't race with psr_enable/disable, which is
diff --git a/drivers/gpu/drm/i915/intel_sprite.c b/drivers/gpu/drm/i915/intel_sprite.c
index 4990d6e84ddf..9d6d1ac149da 100644
--- a/drivers/gpu/drm/i915/intel_sprite.c
+++ b/drivers/gpu/drm/i915/intel_sprite.c
@@ -118,7 +118,7 @@ void intel_pipe_update_start(const struct intel_crtc_state *new_crtc_state)
 	 * VBL interrupts will start the PSR exit and prevent a PSR
 	 * re-entry as well.
 	 */
-	if (CAN_PSR(dev_priv) && intel_psr_wait_for_idle(dev_priv))
+	if (intel_psr_wait_for_idle(new_crtc_state))
 		DRM_ERROR("PSR idle timed out, atomic update may fail\n");
 
 	local_irq_disable();
-- 
2.13.5

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✓ Fi.CI.BAT: success for drm/i915: Use crtc_state->has_psr instead of CAN_PSR for pipe update (rev5)

[Patchwork]

== Series Details ==

Series: drm/i915: Use crtc_state->has_psr instead of CAN_PSR for pipe update (rev5)
URL   : https://patchwork.freedesktop.org/series/46104/
State : success

== Summary ==

= CI Bug Log - changes from CI_DRM_4473 -> Patchwork_9621 =

== Summary - SUCCESS ==

  No regressions found.

  External URL: https://patchwork.freedesktop.org/api/1.0/series/46104/revisions/5/mbox/

== Known issues ==

  Here are the changes found in Patchwork_9621 that come from known issues:

  === IGT changes ===

    ==== Issues hit ====

    igt@kms_chamelium@dp-edid-read:
      fi-kbl-7500u:       PASS -> FAIL (fdo#103841)

    
    ==== Possible fixes ====

    igt@kms_pipe_crc_basic@suspend-read-crc-pipe-c:
      fi-skl-6700k2:      FAIL (fdo#103191) -> PASS

    
  fdo#103191 https://bugs.freedesktop.org/show_bug.cgi?id=103191
  fdo#103841 https://bugs.freedesktop.org/show_bug.cgi?id=103841


== Participating hosts (46 -> 41) ==

  Additional (1): fi-skl-guc 
  Missing    (6): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-ctg-p8600 fi-elk-e7500 


== Build changes ==

    * Linux: CI_DRM_4473 -> Patchwork_9621

  CI_DRM_4473: 17c95b123220c6896ac9cf99c78be4709da704d4 @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_4549: e19fd5549e9cf603251704117fc64f4068be5016 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_9621: fc1a85e5bd3fc7157ce77f91f4b5143cc21828c4 @ git://anongit.freedesktop.org/gfx-ci/linux


== Linux commits ==

fc1a85e5bd3f drm/i915: Use crtc_state->has_psr instead of CAN_PSR for pipe update

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_9621/issues.html
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Re: [PATCH v5] drm/i915: Use crtc_state->has_psr instead of CAN_PSR for pipe update

[Dhinakaran Pandiyan]

On Wed, 2018-07-11 at 22:33 -0700, Tarun Vyas wrote:
> In commit "drm/i915: Wait for PSR exit before checking for vblank
> evasion", the idea was to limit the PSR IDLE checks when PSR is
> actually supported. While CAN_PSR does do that check, it doesn't
> applies on a per-crtc basis. crtc_state->has_psr is a more granular
> check that only applies to pipe(s) that have PSR enabled.
> 
> Without the has_psr check, we end up waiting on the eDP transcoder's
> PSR_STATUS register irrespective of whether the pipe being updated is
> driving it or not.
> 
> Fixes: a608987970b9 ("drm/i915: Wait for PSR exit before checking for
> vblank evasion")
> 
Pushed this to -queued after checking v4's shards results (only commit
message changed between v5 and v4)

-DK
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