* [PATCH 2/4] i915/dp/dsc: Add DSC PPS register definitions
2018-07-17 21:10 [PATCH 1/4] drm/i915/icl: Add VIDEO_DIP regsiters Anusha Srivatsa
@ 2018-07-17 21:10 ` Anusha Srivatsa
2018-07-18 18:55 ` Manasi Navare
2018-07-20 1:30 ` Manasi Navare
2018-07-17 21:11 ` [PATCH 3/4] i915/dp/dsc: Add Rate Control Buffer Threshold Registers Anusha Srivatsa
` (5 subsequent siblings)
6 siblings, 2 replies; 15+ messages in thread
From: Anusha Srivatsa @ 2018-07-17 21:10 UTC (permalink / raw)
To: intel-gfx; +Cc: Lucas De Marchi
From: "Srivatsa, Anusha" <anusha.srivatsa@intel.com>
Display Stream Compression(DSC) has a set of Picture
Parameter Set(PPS) components that the encoder must
communicate to the decoder.
This patch adds register definitions to
the PPS parameters for eDP/MIPI case and Display Port.
v2:
- Use _MMIO_PIPE instead of _MMIO(_PICK()). (Manasi)
- Use DSC constants as arguments. (Manasi)
Cc: Lucas De Marchi <lucas.demarchi@intel.com>
Cc: Ville Syrjala <ville.syrjala@linux.intel.com>
Cc: Manasi Navare <manasi.d.navare@intel.com>
Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
---
drivers/gpu/drm/i915/i915_reg.h | 255 ++++++++++++++++++++++++++++++++++++++++
1 file changed, 255 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 23e70a4..e8687b0 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -10244,4 +10244,259 @@ enum skl_power_gate {
_ICL_PHY_MISC_B)
#define ICL_PHY_MISC_DE_IO_COMP_PWR_DOWN (1 << 23)
+/* Icelake Display Stream Compression Registers */
+#define DSCA_PICTURE_PARAMETER_SET_0 0x6B200
+#define DSCC_PICTURE_PARAMETER_SET_0 0x6BA00
+#define _ICL_DSC0_PICTURE_PARAMETER_SET_0_PB 0x78270
+#define _ICL_DSC1_PICTURE_PARAMETER_SET_0_PB 0x78370
+#define _ICL_DSC0_PICTURE_PARAMETER_SET_0_PC 0x78470
+#define _ICL_DSC1_PICTURE_PARAMETER_SET_0_PC 0x78570
+#define ICL_DSC0_PICTURE_PARAMETER_SET_0(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
+ _ICL_DSC0_PICTURE_PARAMETER_SET_0_PB, \
+ _ICL_DSC0_PICTURE_PARAMETER_SET_0_PC)
+#define ICL_DSC1_PICTURE_PARAMETER_SET_0(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
+ _ICL_DSC1_PICTURE_PARAMETER_SET_0_PB, \
+ _ICL_DSC1_PICTURE_PARAMETER_SET_0_PC)
+#define DSC_VBR_ENABLE (1 << 19)
+#define DSC_422_ENABLE (1 << 18)
+#define DSC_COLOR_SPACE_CONVERSION (1 << 17)
+#define DSC_BLOCK_PREDICTION (1 << 16)
+#define DSC_LINE_BUF_DEPTH_SHIFT 12
+#define DSC_BPC_SHIFT 8
+#define DSC_VER_MIN_SHIFT 4
+#define DSC_VER_MAJ (0x1 << 0)
+
+#define DSCA_PICTURE_PARAMETER_SET_1 0x6B204
+#define DSCC_PICTURE_PARAMETER_SET_1 0x6BA04
+#define _ICL_DSC0_PICTURE_PARAMETER_SET_1_PB 0x78274
+#define _ICL_DSC1_PICTURE_PARAMETER_SET_1_PB 0x78374
+#define _ICL_DSC0_PICTURE_PARAMETER_SET_1_PC 0x78474
+#define _ICL_DSC1_PICTURE_PARAMETER_SET_1_PC 0x78574
+#define ICL_DSC0_PICTURE_PARAMETER_SET_1(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
+ _ICL_DSC0_PICTURE_PARAMETER_SET_1_PB, \
+ _ICL_DSC0_PICTURE_PARAMETER_SET_1_PC)
+#define ICL_DSC1_PICTURE_PARAMETER_SET_1(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
+ _ICL_DSC1_PICTURE_PARAMETER_SET_1_PB, \
+ _ICL_DSC1_PICTURE_PARAMETER_SET_1_PC)
+#define DSC_BPP(bpp) ((bpp) << 0)
+
+#define DSCA_PICTURE_PARAMETER_SET_2 0x6B208
+#define DSCC_PICTURE_PARAMETER_SET_2 0x6BA08
+#define _ICL_DSC0_PICTURE_PARAMETER_SET_2_PB 0x78278
+#define _ICL_DSC1_PICTURE_PARAMETER_SET_2_PB 0x78378
+#define _ICL_DSC0_PICTURE_PARAMETER_SET_2_PC 0x78478
+#define _ICL_DSC1_PICTURE_PARAMETER_SET_2_PC 0x78578
+#define ICL_DSC0_PICTURE_PARAMETER_SET_2(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
+ _ICL_DSC0_PICTURE_PARAMETER_SET_2_PB, \
+ _ICL_DSC0_PICTURE_PARAMETER_SET_2_PC)
+#define ICL_DSC1_PICTURE_PARAMETER_SET_2(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
+ _ICL_DSC1_PICTURE_PARAMETER_SET_2_PB, \
+ _ICL_DSC1_PICTURE_PARAMETER_SET_2_PC)
+#define DSC_PIC_WIDTH(pic_width) ((pic_width) << 16)
+#define DSC_PIC_HEIGHT(pic_height) ((pic_height) << 0)
+
+#define DSCA_PICTURE_PARAMETER_SET_3 0x6B20C
+#define DSCC_PICTURE_PARAMETER_SET_3 0x6BA0C
+#define _ICL_DSC0_PICTURE_PARAMETER_SET_3_PB 0x7827C
+#define _ICL_DSC1_PICTURE_PARAMETER_SET_3_PB 0x7837C
+#define _ICL_DSC0_PICTURE_PARAMETER_SET_3_PC 0x7847C
+#define _ICL_DSC1_PICTURE_PARAMETER_SET_3_PC 0x7857C
+#define ICL_DSC0_PICTURE_PARAMETER_SET_3(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
+ _ICL_DSC0_PICTURE_PARAMETER_SET_3_PB, \
+ _ICL_DSC0_PICTURE_PARAMETER_SET_3_PC)
+#define ICL_DSC1_PICTURE_PARAMETER_SET_3(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
+ _ICL_DSC1_PICTURE_PARAMETER_SET_3_PB, \
+ _ICL_DSC1_PICTURE_PARAMETER_SET_3_PC)
+#define DSC_SLICE_WIDTH(slice_width) ((slice_width) << 16)
+#define DSC_SLICE_HEIGHT(slice_height) ((slice_height) << 0)
+
+#define DSCA_PICTURE_PARAMETER_SET_4 0x6B210
+#define DSCC_PICTURE_PARAMETER_SET_4 0x6BA10
+#define _ICL_DSC0_PICTURE_PARAMETER_SET_4_PB 0x78280
+#define _ICL_DSC1_PICTURE_PARAMETER_SET_4_PB 0x78380
+#define _ICL_DSC0_PICTURE_PARAMETER_SET_4_PC 0x78480
+#define _ICL_DSC1_PICTURE_PARAMETER_SET_4_PC 0x78580
+#define ICL_DSC0_PICTURE_PARAMETER_SET_4(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
+ _ICL_DSC0_PICTURE_PARAMETER_SET_4_PB, \
+ _ICL_DSC0_PICTURE_PARAMETER_SET_4_PC)
+#define ICL_DSC1_PICTURE_PARAMETER_SET_4(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
+ _ICL_DSC0_PICTURE_PARAMETER_SET_4_PB, \
+ _ICL_DSC1_PICTURE_PARAMETER_SET_4_PC)
+#define DSC_INITIAL_DEC_DELAY(dec_delay) ((dec_delay) << 16)
+#define DSC_INITIAL_XMIT_DELAY(xmit_delay) ((xmit_delay) << 0)
+
+#define DSCA_PICTURE_PARAMETER_SET_5 0x6B214
+#define DSCC_PICTURE_PARAMETER_SET_5 0x6BA14
+#define _ICL_DSC0_PICTURE_PARAMETER_SET_5_PB 0x78284
+#define _ICL_DSC1_PICTURE_PARAMETER_SET_5_PB 0x78384
+#define _ICL_DSC0_PICTURE_PARAMETER_SET_5_PC 0x78484
+#define _ICL_DSC1_PICTURE_PARAMETER_SET_5_PC 0x78584
+#define ICL_DSC0_PICTURE_PARAMETER_SET_5(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
+ _ICL_DSC0_PICTURE_PARAMETER_SET_5_PB, \
+ _ICL_DSC0_PICTURE_PARAMETER_SET_5_PC)
+#define ICL_DSC1_PICTURE_PARAMETER_SET_5(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
+ _ICL_DSC1_PICTURE_PARAMETER_SET_5_PC, \
+ _ICL_DSC1_PICTURE_PARAMETER_SET_5_PC)
+#define DSC_SCALE_DEC_INTINT(scale_dec) ((scale_dec) << 16)
+#define DSC_SCALE_INC_INT(scale_inc) ((scale_inc) << 0)
+
+#define DSCA_PICTURE_PARAMETER_SET_6 0x6B218
+#define DSCC_PICTURE_PARAMETER_SET_6 0x6BA18
+#define _ICL_DSC0_PICTURE_PARAMETER_SET_6_PB 0x78288
+#define _ICL_DSC1_PICTURE_PARAMETER_SET_6_PB 0x78388
+#define _ICL_DSC0_PICTURE_PARAMETER_SET_6_PC 0x78488
+#define _ICL_DSC1_PICTURE_PARAMETER_SET_6_PC 0x78588
+#define ICL_DSC0_PICTURE_PARAMETER_SET_6(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
+ _ICL_DSC0_PICTURE_PARAMETER_SET_6_PB, \
+ _ICL_DSC0_PICTURE_PARAMETER_SET_6_PC)
+#define ICL_DSC1_PICTURE_PARAMETER_SET_6(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
+ _ICL_DSC1_PICTURE_PARAMETER_SET_6_PB, \
+ _ICL_DSC1_PICTURE_PARAMETER_SET_6_PC)
+#define DSC_FLATNESS_MAX_QP(max_qp) (qp << 24)
+#define DSC_FLATNESS_MIN_QP(min_qp) (qp << 16)
+#define DSC_FIRST_LINE_BPG_OFFSET(offset) ((offset) << 8)
+#define DSC_INITIAL_SCALE_VALUE(value) ((value) << 0)
+
+#define DSCA_PICTURE_PARAMETER_SET_7 0x6B21C
+#define DSCC_PICTURE_PARAMETER_SET_7 0x6BA1C
+#define _ICL_DSC0_PICTURE_PARAMETER_SET_7_PB 0x7828C
+#define _ICL_DSC1_PICTURE_PARAMETER_SET_7_PB 0x7838C
+#define _ICL_DSC0_PICTURE_PARAMETER_SET_7_PC 0x7848C
+#define _ICL_DSC1_PICTURE_PARAMETER_SET_7_PC 0x7858C
+#define ICL_DSC0_PICTURE_PARAMETER_SET_7(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
+ _ICL_DSC0_PICTURE_PARAMETER_SET_7_PB, \
+ _ICL_DSC0_PICTURE_PARAMETER_SET_7_PC)
+#define ICL_DSC1_PICTURE_PARAMETER_SET_7(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
+ _ICL_DSC1_PICTURE_PARAMETER_SET_7_PB, \
+ _ICL_DSC1_PICTURE_PARAMETER_SET_7_PC)
+#define DSC_NFL_BPG_OFFSET(bpg_offset) ((bpg_offset) << 16)
+#define DSC_SLICE_BPG_OFFSET(bpg_offset) ((bpg_offset) << 0)
+
+#define DSCA_PICTURE_PARAMETER_SET_8 0x6B220
+#define DSCC_PICTURE_PARAMETER_SET_8 0x6BA20
+#define _ICL_DSC0_PICTURE_PARAMETER_SET_8_PB 0x78290
+#define _ICL_DSC1_PICTURE_PARAMETER_SET_8_PB 0x78390
+#define _ICL_DSC0_PICTURE_PARAMETER_SET_8_PC 0x78490
+#define _ICL_DSC1_PICTURE_PARAMETER_SET_8_PC 0x78590
+#define ICL_DSC0_PICTURE_PARAMETER_SET_8(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
+ _ICL_DSC0_PICTURE_PARAMETER_SET_8_PB, \
+ _ICL_DSC0_PICTURE_PARAMETER_SET_8_PC)
+#define ICL_DSC1_PICTURE_PARAMETER_SET_8(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
+ _ICL_DSC1_PICTURE_PARAMETER_SET_8_PB, \
+ _ICL_DSC1_PICTURE_PARAMETER_SET_8_PC)
+#define DSC_INITIAL_OFFSET(initial_offset) ((initial_offset) << 16)
+#define DSC_FINAL_OFFSET(final_offset) ((final_offset) << 0)
+
+#define DSCA_PICTURE_PARAMETER_SET_9 0x6B224
+#define DSCC_PICTURE_PARAMETER_SET_9 0x6BA24
+#define _ICL_DSC0_PICTURE_PARAMETER_SET_9_PB 0x78294
+#define _ICL_DSC1_PICTURE_PARAMETER_SET_9_PB 0x78394
+#define _ICL_DSC0_PICTURE_PARAMETER_SET_9_PC 0x78494
+#define _ICL_DSC1_PICTURE_PARAMETER_SET_9_PC 0x78594
+#define ICL_DSC0_PICTURE_PARAMETER_SET_9(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
+ _ICL_DSC0_PICTURE_PARAMETER_SET_9_PB, \
+ _ICL_DSC0_PICTURE_PARAMETER_SET_9_PC)
+#define ICL_DSC1_PICTURE_PARAMETER_SET_9(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
+ _ICL_DSC1_PICTURE_PARAMETER_SET_9_PB, \
+ _ICL_DSC1_PICTURE_PARAMETER_SET_9_PC)
+#define DSC_RC_EDGE_FACTOR(rc_edge_fact) ((rc_edge_fact) << 16)
+#define DSC_RC_MODEL_SIZE(rc_model_size) ((rc_model_size) << 0)
+
+#define DSCA_PICTURE_PARAMETER_SET_10 0x6B228
+#define DSCC_PICTURE_PARAMETER_SET_10 0x6BA28
+#define _ICL_DSC0_PICTURE_PARAMETER_SET_10_PB 0x78298
+#define _ICL_DSC1_PICTURE_PARAMETER_SET_10_PB 0x78398
+#define _ICL_DSC0_PICTURE_PARAMETER_SET_10_PC 0x78498
+#define _ICL_DSC1_PICTURE_PARAMETER_SET_10_PC 0x78598
+#define ICL_DSC0_PICTURE_PARAMETER_SET_10(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
+ _ICL_DSC0_PICTURE_PARAMETER_SET_10_PB, \
+ _ICL_DSC0_PICTURE_PARAMETER_SET_10_PC)
+#define ICL_DSC1_PICTURE_PARAMETER_SET_10(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
+ _ICL_DSC1_PICTURE_PARAMETER_SET_10_PB, \
+ _ICL_DSC1_PICTURE_PARAMETER_SET_10_PC)
+#define DSC_RC_TARGET_OFF_LOW(rc_tgt_off_low) ((rc_tgt_off_low) << 20)
+#define DSC_RC_TARGET_OFF_HIGH(rc_tgt_off_high) ((rc_tgt_off_high) << 16)
+#define DSC_RC_QUANT_INC_LIMIT1(lim) ((lim) << 8)
+#define DSC_RC_QUANT_INC_LIMIT0(lim) ((lim) << 0)
+
+#define DSCA_PICTURE_PARAMETER_SET_11 0x6B22C
+#define DSCC_PICTURE_PARAMETER_SET_11 0x6BA2C
+#define _ICL_DSC0_PICTURE_PARAMETER_SET_11_PB 0x7829C
+#define _ICL_DSC1_PICTURE_PARAMETER_SET_11_PB 0x7839C
+#define _ICL_DSC0_PICTURE_PARAMETER_SET_11_PC 0x7849C
+#define _ICL_DSC1_PICTURE_PARAMETER_SET_11_PC 0x7859C
+#define ICL_DSC0_PICTURE_PARAMETER_SET_11(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
+ _ICL_DSC0_PICTURE_PARAMETER_SET_11_PB, \
+ _ICL_DSC0_PICTURE_PARAMETER_SET_11_PC)
+#define ICL_DSC1_PICTURE_PARAMETER_SET_11(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
+ _ICL_DSC1_PICTURE_PARAMETER_SET_11_PB, \
+ _ICL_DSC1_PICTURE_PARAMETER_SET_11_PC)
+
+#define DSCA_PICTURE_PARAMETER_SET_12 0x6B260
+#define DSCC_PICTURE_PARAMETER_SET_12 0x6BA60
+#define _ICL_DSC0_PICTURE_PARAMETER_SET_12_PB 0x782A0
+#define _ICL_DSC1_PICTURE_PARAMETER_SET_12_PB 0x783A0
+#define _ICL_DSC0_PICTURE_PARAMETER_SET_12_PC 0x784A0
+#define _ICL_DSC1_PICTURE_PARAMETER_SET_12_PC 0x785A0
+#define ICL_DSC0_PICTURE_PARAMETER_SET_12(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
+ _ICL_DSC0_PICTURE_PARAMETER_SET_12_PB, \
+ _ICL_DSC0_PICTURE_PARAMETER_SET_12_PC)
+#define ICL_DSC1_PICTURE_PARAMETER_SET_12(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
+ _ICL_DSC1_PICTURE_PARAMETER_SET_12_PB, \
+ _ICL_DSC1_PICTURE_PARAMETER_SET_12_PC)
+
+#define DSCA_PICTURE_PARAMETER_SET_13 0x6B264
+#define DSCC_PICTURE_PARAMETER_SET_13 0x6BA64
+#define _ICL_DSC0_PICTURE_PARAMETER_SET_13_PB 0x782A4
+#define _ICL_DSC1_PICTURE_PARAMETER_SET_13_PB 0x783A4
+#define _ICL_DSC0_PICTURE_PARAMETER_SET_13_PC 0x784A4
+#define _ICL_DSC1_PICTURE_PARAMETER_SET_13_PC 0x785A4
+#define ICL_DSC0_PICTURE_PARAMETER_SET_13(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
+ _ICL_DSC0_PICTURE_PARAMETER_SET_13_PB, \
+ _ICL_DSC0_PICTURE_PARAMETER_SET_13_PC)
+#define ICL_DSC1_PICTURE_PARAMETER_SET_13(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
+ _ICL_DSC1_PICTURE_PARAMETER_SET_13_PB, \
+ _ICL_DSC1_PICTURE_PARAMETER_SET_13_PC)
+
+#define DSCA_PICTURE_PARAMETER_SET_14 0x6B268
+#define DSCC_PICTURE_PARAMETER_SET_14 0x6BA68
+#define _ICL_DSC0_PICTURE_PARAMETER_SET_14_PB 0x782A8
+#define _ICL_DSC1_PICTURE_PARAMETER_SET_14_PB 0x783A8
+#define _ICL_DSC0_PICTURE_PARAMETER_SET_14_PC 0x784A8
+#define _ICL_DSC1_PICTURE_PARAMETER_SET_14_PC 0x785A8
+#define ICL_DSC0_PICTURE_PARAMETER_SET_14(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
+ _ICL_DSC0_PICTURE_PARAMETER_SET_14_PB, \
+ _ICL_DSC0_PICTURE_PARAMETER_SET_14_PC)
+#define ICL_DSC1_PICTURE_PARAMETER_SET_14(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
+ _ICL_DSC1_PICTURE_PARAMETER_SET_14_PB, \
+ _ICL_DSC1_PICTURE_PARAMETER_SET_14_PC)
+
+#define DSCA_PICTURE_PARAMETER_SET_15 0x6B26C
+#define DSCC_PICTURE_PARAMETER_SET_15 0x6BA6C
+#define _ICL_DSC0_PICTURE_PARAMETER_SET_15_PB 0x782AC
+#define _ICL_DSC1_PICTURE_PARAMETER_SET_15_PB 0x783AC
+#define _ICL_DSC0_PICTURE_PARAMETER_SET_15_PC 0x784AC
+#define _ICL_DSC1_PICTURE_PARAMETER_SET_15_PC 0x785AC
+#define ICL_DSC0_PICTURE_PARAMETER_SET_15(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
+ _ICL_DSC0_PICTURE_PARAMETER_SET_15_PB, \
+ _ICL_DSC0_PICTURE_PARAMETER_SET_15_PC)
+#define ICL_DSC1_PICTURE_PARAMETER_SET_15(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
+ _ICL_DSC1_PICTURE_PARAMETER_SET_15_PB, \
+ _ICL_DSC1_PICTURE_PARAMETER_SET_15_PC)
+
+#define DSCA_PICTURE_PARAMETER_SET_16 0x6B270
+#define DSCC_PICTURE_PARAMETER_SET_16 0x6BA70
+#define _ICL_DSC0_PICTURE_PARAMETER_SET_16_PB 0x782B0
+#define _ICL_DSC1_PICTURE_PARAMETER_SET_16_PB 0x783B0
+#define _ICL_DSC0_PICTURE_PARAMETER_SET_16_PC 0x784B0
+#define _ICL_DSC1_PICTURE_PARAMETER_SET_16_PC 0x785B0
+#define ICL_DSC0_PICTURE_PARAMETER_SET_16(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
+ _ICL_DSC0_PICTURE_PARAMETER_SET_16_PB, \
+ _ICL_DSC0_PICTURE_PARAMETER_SET_16_PC)
+#define ICL_DSC1_PICTURE_PARAMETER_SET_16(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
+ _ICL_DSC1_PICTURE_PARAMETER_SET_16_PB, \
+ _ICL_DSC1_PICTURE_PARAMETER_SET_16_PC)
+#define DSC_SLICE_PER_LINE(slice_per_line) ((slice_per_line) << 16)
+#define DSC_SLICE_CHUNK_SIZE(slice_chunk_aize) (slice_chunk_size << 0)
+
#endif /* _I915_REG_H_ */
--
2.7.4
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^ permalink raw reply related [flat|nested] 15+ messages in thread* Re: [PATCH 2/4] i915/dp/dsc: Add DSC PPS register definitions
2018-07-17 21:10 ` [PATCH 2/4] i915/dp/dsc: Add DSC PPS register definitions Anusha Srivatsa
@ 2018-07-18 18:55 ` Manasi Navare
2018-07-20 1:30 ` Manasi Navare
1 sibling, 0 replies; 15+ messages in thread
From: Manasi Navare @ 2018-07-18 18:55 UTC (permalink / raw)
To: Anusha Srivatsa; +Cc: intel-gfx, Lucas De Marchi
On Tue, Jul 17, 2018 at 02:10:59PM -0700, Anusha Srivatsa wrote:
> From: "Srivatsa, Anusha" <anusha.srivatsa@intel.com>
>
> Display Stream Compression(DSC) has a set of Picture
> Parameter Set(PPS) components that the encoder must
> communicate to the decoder.
>
> This patch adds register definitions to
> the PPS parameters for eDP/MIPI case and Display Port.
>
> v2:
> - Use _MMIO_PIPE instead of _MMIO(_PICK()). (Manasi)
> - Use DSC constants as arguments. (Manasi)
>
> Cc: Lucas De Marchi <lucas.demarchi@intel.com>
> Cc: Ville Syrjala <ville.syrjala@linux.intel.com>
> Cc: Manasi Navare <manasi.d.navare@intel.com>
> Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
Looks good to me, checked against the spec.
Reviewed-by: Manasi Navare <manasi.d.navare@intel.com>
> ---
> drivers/gpu/drm/i915/i915_reg.h | 255 ++++++++++++++++++++++++++++++++++++++++
> 1 file changed, 255 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 23e70a4..e8687b0 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -10244,4 +10244,259 @@ enum skl_power_gate {
> _ICL_PHY_MISC_B)
> #define ICL_PHY_MISC_DE_IO_COMP_PWR_DOWN (1 << 23)
>
> +/* Icelake Display Stream Compression Registers */
> +#define DSCA_PICTURE_PARAMETER_SET_0 0x6B200
> +#define DSCC_PICTURE_PARAMETER_SET_0 0x6BA00
> +#define _ICL_DSC0_PICTURE_PARAMETER_SET_0_PB 0x78270
> +#define _ICL_DSC1_PICTURE_PARAMETER_SET_0_PB 0x78370
> +#define _ICL_DSC0_PICTURE_PARAMETER_SET_0_PC 0x78470
> +#define _ICL_DSC1_PICTURE_PARAMETER_SET_0_PC 0x78570
> +#define ICL_DSC0_PICTURE_PARAMETER_SET_0(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
> + _ICL_DSC0_PICTURE_PARAMETER_SET_0_PB, \
> + _ICL_DSC0_PICTURE_PARAMETER_SET_0_PC)
> +#define ICL_DSC1_PICTURE_PARAMETER_SET_0(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
> + _ICL_DSC1_PICTURE_PARAMETER_SET_0_PB, \
> + _ICL_DSC1_PICTURE_PARAMETER_SET_0_PC)
> +#define DSC_VBR_ENABLE (1 << 19)
> +#define DSC_422_ENABLE (1 << 18)
> +#define DSC_COLOR_SPACE_CONVERSION (1 << 17)
> +#define DSC_BLOCK_PREDICTION (1 << 16)
> +#define DSC_LINE_BUF_DEPTH_SHIFT 12
> +#define DSC_BPC_SHIFT 8
> +#define DSC_VER_MIN_SHIFT 4
> +#define DSC_VER_MAJ (0x1 << 0)
> +
> +#define DSCA_PICTURE_PARAMETER_SET_1 0x6B204
> +#define DSCC_PICTURE_PARAMETER_SET_1 0x6BA04
> +#define _ICL_DSC0_PICTURE_PARAMETER_SET_1_PB 0x78274
> +#define _ICL_DSC1_PICTURE_PARAMETER_SET_1_PB 0x78374
> +#define _ICL_DSC0_PICTURE_PARAMETER_SET_1_PC 0x78474
> +#define _ICL_DSC1_PICTURE_PARAMETER_SET_1_PC 0x78574
> +#define ICL_DSC0_PICTURE_PARAMETER_SET_1(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
> + _ICL_DSC0_PICTURE_PARAMETER_SET_1_PB, \
> + _ICL_DSC0_PICTURE_PARAMETER_SET_1_PC)
> +#define ICL_DSC1_PICTURE_PARAMETER_SET_1(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
> + _ICL_DSC1_PICTURE_PARAMETER_SET_1_PB, \
> + _ICL_DSC1_PICTURE_PARAMETER_SET_1_PC)
> +#define DSC_BPP(bpp) ((bpp) << 0)
> +
> +#define DSCA_PICTURE_PARAMETER_SET_2 0x6B208
> +#define DSCC_PICTURE_PARAMETER_SET_2 0x6BA08
> +#define _ICL_DSC0_PICTURE_PARAMETER_SET_2_PB 0x78278
> +#define _ICL_DSC1_PICTURE_PARAMETER_SET_2_PB 0x78378
> +#define _ICL_DSC0_PICTURE_PARAMETER_SET_2_PC 0x78478
> +#define _ICL_DSC1_PICTURE_PARAMETER_SET_2_PC 0x78578
> +#define ICL_DSC0_PICTURE_PARAMETER_SET_2(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
> + _ICL_DSC0_PICTURE_PARAMETER_SET_2_PB, \
> + _ICL_DSC0_PICTURE_PARAMETER_SET_2_PC)
> +#define ICL_DSC1_PICTURE_PARAMETER_SET_2(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
> + _ICL_DSC1_PICTURE_PARAMETER_SET_2_PB, \
> + _ICL_DSC1_PICTURE_PARAMETER_SET_2_PC)
> +#define DSC_PIC_WIDTH(pic_width) ((pic_width) << 16)
> +#define DSC_PIC_HEIGHT(pic_height) ((pic_height) << 0)
> +
> +#define DSCA_PICTURE_PARAMETER_SET_3 0x6B20C
> +#define DSCC_PICTURE_PARAMETER_SET_3 0x6BA0C
> +#define _ICL_DSC0_PICTURE_PARAMETER_SET_3_PB 0x7827C
> +#define _ICL_DSC1_PICTURE_PARAMETER_SET_3_PB 0x7837C
> +#define _ICL_DSC0_PICTURE_PARAMETER_SET_3_PC 0x7847C
> +#define _ICL_DSC1_PICTURE_PARAMETER_SET_3_PC 0x7857C
> +#define ICL_DSC0_PICTURE_PARAMETER_SET_3(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
> + _ICL_DSC0_PICTURE_PARAMETER_SET_3_PB, \
> + _ICL_DSC0_PICTURE_PARAMETER_SET_3_PC)
> +#define ICL_DSC1_PICTURE_PARAMETER_SET_3(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
> + _ICL_DSC1_PICTURE_PARAMETER_SET_3_PB, \
> + _ICL_DSC1_PICTURE_PARAMETER_SET_3_PC)
> +#define DSC_SLICE_WIDTH(slice_width) ((slice_width) << 16)
> +#define DSC_SLICE_HEIGHT(slice_height) ((slice_height) << 0)
> +
> +#define DSCA_PICTURE_PARAMETER_SET_4 0x6B210
> +#define DSCC_PICTURE_PARAMETER_SET_4 0x6BA10
> +#define _ICL_DSC0_PICTURE_PARAMETER_SET_4_PB 0x78280
> +#define _ICL_DSC1_PICTURE_PARAMETER_SET_4_PB 0x78380
> +#define _ICL_DSC0_PICTURE_PARAMETER_SET_4_PC 0x78480
> +#define _ICL_DSC1_PICTURE_PARAMETER_SET_4_PC 0x78580
> +#define ICL_DSC0_PICTURE_PARAMETER_SET_4(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
> + _ICL_DSC0_PICTURE_PARAMETER_SET_4_PB, \
> + _ICL_DSC0_PICTURE_PARAMETER_SET_4_PC)
> +#define ICL_DSC1_PICTURE_PARAMETER_SET_4(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
> + _ICL_DSC0_PICTURE_PARAMETER_SET_4_PB, \
> + _ICL_DSC1_PICTURE_PARAMETER_SET_4_PC)
> +#define DSC_INITIAL_DEC_DELAY(dec_delay) ((dec_delay) << 16)
> +#define DSC_INITIAL_XMIT_DELAY(xmit_delay) ((xmit_delay) << 0)
> +
> +#define DSCA_PICTURE_PARAMETER_SET_5 0x6B214
> +#define DSCC_PICTURE_PARAMETER_SET_5 0x6BA14
> +#define _ICL_DSC0_PICTURE_PARAMETER_SET_5_PB 0x78284
> +#define _ICL_DSC1_PICTURE_PARAMETER_SET_5_PB 0x78384
> +#define _ICL_DSC0_PICTURE_PARAMETER_SET_5_PC 0x78484
> +#define _ICL_DSC1_PICTURE_PARAMETER_SET_5_PC 0x78584
> +#define ICL_DSC0_PICTURE_PARAMETER_SET_5(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
> + _ICL_DSC0_PICTURE_PARAMETER_SET_5_PB, \
> + _ICL_DSC0_PICTURE_PARAMETER_SET_5_PC)
> +#define ICL_DSC1_PICTURE_PARAMETER_SET_5(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
> + _ICL_DSC1_PICTURE_PARAMETER_SET_5_PC, \
> + _ICL_DSC1_PICTURE_PARAMETER_SET_5_PC)
> +#define DSC_SCALE_DEC_INTINT(scale_dec) ((scale_dec) << 16)
> +#define DSC_SCALE_INC_INT(scale_inc) ((scale_inc) << 0)
> +
> +#define DSCA_PICTURE_PARAMETER_SET_6 0x6B218
> +#define DSCC_PICTURE_PARAMETER_SET_6 0x6BA18
> +#define _ICL_DSC0_PICTURE_PARAMETER_SET_6_PB 0x78288
> +#define _ICL_DSC1_PICTURE_PARAMETER_SET_6_PB 0x78388
> +#define _ICL_DSC0_PICTURE_PARAMETER_SET_6_PC 0x78488
> +#define _ICL_DSC1_PICTURE_PARAMETER_SET_6_PC 0x78588
> +#define ICL_DSC0_PICTURE_PARAMETER_SET_6(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
> + _ICL_DSC0_PICTURE_PARAMETER_SET_6_PB, \
> + _ICL_DSC0_PICTURE_PARAMETER_SET_6_PC)
> +#define ICL_DSC1_PICTURE_PARAMETER_SET_6(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
> + _ICL_DSC1_PICTURE_PARAMETER_SET_6_PB, \
> + _ICL_DSC1_PICTURE_PARAMETER_SET_6_PC)
> +#define DSC_FLATNESS_MAX_QP(max_qp) (qp << 24)
> +#define DSC_FLATNESS_MIN_QP(min_qp) (qp << 16)
> +#define DSC_FIRST_LINE_BPG_OFFSET(offset) ((offset) << 8)
> +#define DSC_INITIAL_SCALE_VALUE(value) ((value) << 0)
> +
> +#define DSCA_PICTURE_PARAMETER_SET_7 0x6B21C
> +#define DSCC_PICTURE_PARAMETER_SET_7 0x6BA1C
> +#define _ICL_DSC0_PICTURE_PARAMETER_SET_7_PB 0x7828C
> +#define _ICL_DSC1_PICTURE_PARAMETER_SET_7_PB 0x7838C
> +#define _ICL_DSC0_PICTURE_PARAMETER_SET_7_PC 0x7848C
> +#define _ICL_DSC1_PICTURE_PARAMETER_SET_7_PC 0x7858C
> +#define ICL_DSC0_PICTURE_PARAMETER_SET_7(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
> + _ICL_DSC0_PICTURE_PARAMETER_SET_7_PB, \
> + _ICL_DSC0_PICTURE_PARAMETER_SET_7_PC)
> +#define ICL_DSC1_PICTURE_PARAMETER_SET_7(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
> + _ICL_DSC1_PICTURE_PARAMETER_SET_7_PB, \
> + _ICL_DSC1_PICTURE_PARAMETER_SET_7_PC)
> +#define DSC_NFL_BPG_OFFSET(bpg_offset) ((bpg_offset) << 16)
> +#define DSC_SLICE_BPG_OFFSET(bpg_offset) ((bpg_offset) << 0)
> +
> +#define DSCA_PICTURE_PARAMETER_SET_8 0x6B220
> +#define DSCC_PICTURE_PARAMETER_SET_8 0x6BA20
> +#define _ICL_DSC0_PICTURE_PARAMETER_SET_8_PB 0x78290
> +#define _ICL_DSC1_PICTURE_PARAMETER_SET_8_PB 0x78390
> +#define _ICL_DSC0_PICTURE_PARAMETER_SET_8_PC 0x78490
> +#define _ICL_DSC1_PICTURE_PARAMETER_SET_8_PC 0x78590
> +#define ICL_DSC0_PICTURE_PARAMETER_SET_8(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
> + _ICL_DSC0_PICTURE_PARAMETER_SET_8_PB, \
> + _ICL_DSC0_PICTURE_PARAMETER_SET_8_PC)
> +#define ICL_DSC1_PICTURE_PARAMETER_SET_8(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
> + _ICL_DSC1_PICTURE_PARAMETER_SET_8_PB, \
> + _ICL_DSC1_PICTURE_PARAMETER_SET_8_PC)
> +#define DSC_INITIAL_OFFSET(initial_offset) ((initial_offset) << 16)
> +#define DSC_FINAL_OFFSET(final_offset) ((final_offset) << 0)
> +
> +#define DSCA_PICTURE_PARAMETER_SET_9 0x6B224
> +#define DSCC_PICTURE_PARAMETER_SET_9 0x6BA24
> +#define _ICL_DSC0_PICTURE_PARAMETER_SET_9_PB 0x78294
> +#define _ICL_DSC1_PICTURE_PARAMETER_SET_9_PB 0x78394
> +#define _ICL_DSC0_PICTURE_PARAMETER_SET_9_PC 0x78494
> +#define _ICL_DSC1_PICTURE_PARAMETER_SET_9_PC 0x78594
> +#define ICL_DSC0_PICTURE_PARAMETER_SET_9(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
> + _ICL_DSC0_PICTURE_PARAMETER_SET_9_PB, \
> + _ICL_DSC0_PICTURE_PARAMETER_SET_9_PC)
> +#define ICL_DSC1_PICTURE_PARAMETER_SET_9(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
> + _ICL_DSC1_PICTURE_PARAMETER_SET_9_PB, \
> + _ICL_DSC1_PICTURE_PARAMETER_SET_9_PC)
> +#define DSC_RC_EDGE_FACTOR(rc_edge_fact) ((rc_edge_fact) << 16)
> +#define DSC_RC_MODEL_SIZE(rc_model_size) ((rc_model_size) << 0)
> +
> +#define DSCA_PICTURE_PARAMETER_SET_10 0x6B228
> +#define DSCC_PICTURE_PARAMETER_SET_10 0x6BA28
> +#define _ICL_DSC0_PICTURE_PARAMETER_SET_10_PB 0x78298
> +#define _ICL_DSC1_PICTURE_PARAMETER_SET_10_PB 0x78398
> +#define _ICL_DSC0_PICTURE_PARAMETER_SET_10_PC 0x78498
> +#define _ICL_DSC1_PICTURE_PARAMETER_SET_10_PC 0x78598
> +#define ICL_DSC0_PICTURE_PARAMETER_SET_10(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
> + _ICL_DSC0_PICTURE_PARAMETER_SET_10_PB, \
> + _ICL_DSC0_PICTURE_PARAMETER_SET_10_PC)
> +#define ICL_DSC1_PICTURE_PARAMETER_SET_10(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
> + _ICL_DSC1_PICTURE_PARAMETER_SET_10_PB, \
> + _ICL_DSC1_PICTURE_PARAMETER_SET_10_PC)
> +#define DSC_RC_TARGET_OFF_LOW(rc_tgt_off_low) ((rc_tgt_off_low) << 20)
> +#define DSC_RC_TARGET_OFF_HIGH(rc_tgt_off_high) ((rc_tgt_off_high) << 16)
> +#define DSC_RC_QUANT_INC_LIMIT1(lim) ((lim) << 8)
> +#define DSC_RC_QUANT_INC_LIMIT0(lim) ((lim) << 0)
> +
> +#define DSCA_PICTURE_PARAMETER_SET_11 0x6B22C
> +#define DSCC_PICTURE_PARAMETER_SET_11 0x6BA2C
> +#define _ICL_DSC0_PICTURE_PARAMETER_SET_11_PB 0x7829C
> +#define _ICL_DSC1_PICTURE_PARAMETER_SET_11_PB 0x7839C
> +#define _ICL_DSC0_PICTURE_PARAMETER_SET_11_PC 0x7849C
> +#define _ICL_DSC1_PICTURE_PARAMETER_SET_11_PC 0x7859C
> +#define ICL_DSC0_PICTURE_PARAMETER_SET_11(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
> + _ICL_DSC0_PICTURE_PARAMETER_SET_11_PB, \
> + _ICL_DSC0_PICTURE_PARAMETER_SET_11_PC)
> +#define ICL_DSC1_PICTURE_PARAMETER_SET_11(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
> + _ICL_DSC1_PICTURE_PARAMETER_SET_11_PB, \
> + _ICL_DSC1_PICTURE_PARAMETER_SET_11_PC)
> +
> +#define DSCA_PICTURE_PARAMETER_SET_12 0x6B260
> +#define DSCC_PICTURE_PARAMETER_SET_12 0x6BA60
> +#define _ICL_DSC0_PICTURE_PARAMETER_SET_12_PB 0x782A0
> +#define _ICL_DSC1_PICTURE_PARAMETER_SET_12_PB 0x783A0
> +#define _ICL_DSC0_PICTURE_PARAMETER_SET_12_PC 0x784A0
> +#define _ICL_DSC1_PICTURE_PARAMETER_SET_12_PC 0x785A0
> +#define ICL_DSC0_PICTURE_PARAMETER_SET_12(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
> + _ICL_DSC0_PICTURE_PARAMETER_SET_12_PB, \
> + _ICL_DSC0_PICTURE_PARAMETER_SET_12_PC)
> +#define ICL_DSC1_PICTURE_PARAMETER_SET_12(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
> + _ICL_DSC1_PICTURE_PARAMETER_SET_12_PB, \
> + _ICL_DSC1_PICTURE_PARAMETER_SET_12_PC)
> +
> +#define DSCA_PICTURE_PARAMETER_SET_13 0x6B264
> +#define DSCC_PICTURE_PARAMETER_SET_13 0x6BA64
> +#define _ICL_DSC0_PICTURE_PARAMETER_SET_13_PB 0x782A4
> +#define _ICL_DSC1_PICTURE_PARAMETER_SET_13_PB 0x783A4
> +#define _ICL_DSC0_PICTURE_PARAMETER_SET_13_PC 0x784A4
> +#define _ICL_DSC1_PICTURE_PARAMETER_SET_13_PC 0x785A4
> +#define ICL_DSC0_PICTURE_PARAMETER_SET_13(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
> + _ICL_DSC0_PICTURE_PARAMETER_SET_13_PB, \
> + _ICL_DSC0_PICTURE_PARAMETER_SET_13_PC)
> +#define ICL_DSC1_PICTURE_PARAMETER_SET_13(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
> + _ICL_DSC1_PICTURE_PARAMETER_SET_13_PB, \
> + _ICL_DSC1_PICTURE_PARAMETER_SET_13_PC)
> +
> +#define DSCA_PICTURE_PARAMETER_SET_14 0x6B268
> +#define DSCC_PICTURE_PARAMETER_SET_14 0x6BA68
> +#define _ICL_DSC0_PICTURE_PARAMETER_SET_14_PB 0x782A8
> +#define _ICL_DSC1_PICTURE_PARAMETER_SET_14_PB 0x783A8
> +#define _ICL_DSC0_PICTURE_PARAMETER_SET_14_PC 0x784A8
> +#define _ICL_DSC1_PICTURE_PARAMETER_SET_14_PC 0x785A8
> +#define ICL_DSC0_PICTURE_PARAMETER_SET_14(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
> + _ICL_DSC0_PICTURE_PARAMETER_SET_14_PB, \
> + _ICL_DSC0_PICTURE_PARAMETER_SET_14_PC)
> +#define ICL_DSC1_PICTURE_PARAMETER_SET_14(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
> + _ICL_DSC1_PICTURE_PARAMETER_SET_14_PB, \
> + _ICL_DSC1_PICTURE_PARAMETER_SET_14_PC)
> +
> +#define DSCA_PICTURE_PARAMETER_SET_15 0x6B26C
> +#define DSCC_PICTURE_PARAMETER_SET_15 0x6BA6C
> +#define _ICL_DSC0_PICTURE_PARAMETER_SET_15_PB 0x782AC
> +#define _ICL_DSC1_PICTURE_PARAMETER_SET_15_PB 0x783AC
> +#define _ICL_DSC0_PICTURE_PARAMETER_SET_15_PC 0x784AC
> +#define _ICL_DSC1_PICTURE_PARAMETER_SET_15_PC 0x785AC
> +#define ICL_DSC0_PICTURE_PARAMETER_SET_15(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
> + _ICL_DSC0_PICTURE_PARAMETER_SET_15_PB, \
> + _ICL_DSC0_PICTURE_PARAMETER_SET_15_PC)
> +#define ICL_DSC1_PICTURE_PARAMETER_SET_15(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
> + _ICL_DSC1_PICTURE_PARAMETER_SET_15_PB, \
> + _ICL_DSC1_PICTURE_PARAMETER_SET_15_PC)
> +
> +#define DSCA_PICTURE_PARAMETER_SET_16 0x6B270
> +#define DSCC_PICTURE_PARAMETER_SET_16 0x6BA70
> +#define _ICL_DSC0_PICTURE_PARAMETER_SET_16_PB 0x782B0
> +#define _ICL_DSC1_PICTURE_PARAMETER_SET_16_PB 0x783B0
> +#define _ICL_DSC0_PICTURE_PARAMETER_SET_16_PC 0x784B0
> +#define _ICL_DSC1_PICTURE_PARAMETER_SET_16_PC 0x785B0
> +#define ICL_DSC0_PICTURE_PARAMETER_SET_16(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
> + _ICL_DSC0_PICTURE_PARAMETER_SET_16_PB, \
> + _ICL_DSC0_PICTURE_PARAMETER_SET_16_PC)
> +#define ICL_DSC1_PICTURE_PARAMETER_SET_16(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
> + _ICL_DSC1_PICTURE_PARAMETER_SET_16_PB, \
> + _ICL_DSC1_PICTURE_PARAMETER_SET_16_PC)
> +#define DSC_SLICE_PER_LINE(slice_per_line) ((slice_per_line) << 16)
> +#define DSC_SLICE_CHUNK_SIZE(slice_chunk_aize) (slice_chunk_size << 0)
> +
> #endif /* _I915_REG_H_ */
> --
> 2.7.4
>
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^ permalink raw reply [flat|nested] 15+ messages in thread* Re: [PATCH 2/4] i915/dp/dsc: Add DSC PPS register definitions
2018-07-17 21:10 ` [PATCH 2/4] i915/dp/dsc: Add DSC PPS register definitions Anusha Srivatsa
2018-07-18 18:55 ` Manasi Navare
@ 2018-07-20 1:30 ` Manasi Navare
1 sibling, 0 replies; 15+ messages in thread
From: Manasi Navare @ 2018-07-20 1:30 UTC (permalink / raw)
To: Anusha Srivatsa; +Cc: intel-gfx, Lucas De Marchi
Anusha,
This is not the correct latest patch. This still doesnt have _MMIO for DSCA_
and DSCC registers.
On Tue, Jul 17, 2018 at 02:10:59PM -0700, Anusha Srivatsa wrote:
> From: "Srivatsa, Anusha" <anusha.srivatsa@intel.com>
>
> Display Stream Compression(DSC) has a set of Picture
> Parameter Set(PPS) components that the encoder must
> communicate to the decoder.
>
> This patch adds register definitions to
> the PPS parameters for eDP/MIPI case and Display Port.
>
> v2:
> - Use _MMIO_PIPE instead of _MMIO(_PICK()). (Manasi)
> - Use DSC constants as arguments. (Manasi)
>
> Cc: Lucas De Marchi <lucas.demarchi@intel.com>
> Cc: Ville Syrjala <ville.syrjala@linux.intel.com>
> Cc: Manasi Navare <manasi.d.navare@intel.com>
> Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
> ---
> drivers/gpu/drm/i915/i915_reg.h | 255 ++++++++++++++++++++++++++++++++++++++++
> 1 file changed, 255 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 23e70a4..e8687b0 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -10244,4 +10244,259 @@ enum skl_power_gate {
> _ICL_PHY_MISC_B)
> #define ICL_PHY_MISC_DE_IO_COMP_PWR_DOWN (1 << 23)
>
> +/* Icelake Display Stream Compression Registers */
> +#define DSCA_PICTURE_PARAMETER_SET_0 0x6B200
This should be _MMIO() for the reg value
and same for below
Manasi
> +#define DSCC_PICTURE_PARAMETER_SET_0 0x6BA00
> +#define _ICL_DSC0_PICTURE_PARAMETER_SET_0_PB 0x78270
> +#define _ICL_DSC1_PICTURE_PARAMETER_SET_0_PB 0x78370
> +#define _ICL_DSC0_PICTURE_PARAMETER_SET_0_PC 0x78470
> +#define _ICL_DSC1_PICTURE_PARAMETER_SET_0_PC 0x78570
> +#define ICL_DSC0_PICTURE_PARAMETER_SET_0(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
> + _ICL_DSC0_PICTURE_PARAMETER_SET_0_PB, \
> + _ICL_DSC0_PICTURE_PARAMETER_SET_0_PC)
> +#define ICL_DSC1_PICTURE_PARAMETER_SET_0(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
> + _ICL_DSC1_PICTURE_PARAMETER_SET_0_PB, \
> + _ICL_DSC1_PICTURE_PARAMETER_SET_0_PC)
> +#define DSC_VBR_ENABLE (1 << 19)
> +#define DSC_422_ENABLE (1 << 18)
> +#define DSC_COLOR_SPACE_CONVERSION (1 << 17)
> +#define DSC_BLOCK_PREDICTION (1 << 16)
> +#define DSC_LINE_BUF_DEPTH_SHIFT 12
> +#define DSC_BPC_SHIFT 8
> +#define DSC_VER_MIN_SHIFT 4
> +#define DSC_VER_MAJ (0x1 << 0)
> +
> +#define DSCA_PICTURE_PARAMETER_SET_1 0x6B204
> +#define DSCC_PICTURE_PARAMETER_SET_1 0x6BA04
> +#define _ICL_DSC0_PICTURE_PARAMETER_SET_1_PB 0x78274
> +#define _ICL_DSC1_PICTURE_PARAMETER_SET_1_PB 0x78374
> +#define _ICL_DSC0_PICTURE_PARAMETER_SET_1_PC 0x78474
> +#define _ICL_DSC1_PICTURE_PARAMETER_SET_1_PC 0x78574
> +#define ICL_DSC0_PICTURE_PARAMETER_SET_1(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
> + _ICL_DSC0_PICTURE_PARAMETER_SET_1_PB, \
> + _ICL_DSC0_PICTURE_PARAMETER_SET_1_PC)
> +#define ICL_DSC1_PICTURE_PARAMETER_SET_1(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
> + _ICL_DSC1_PICTURE_PARAMETER_SET_1_PB, \
> + _ICL_DSC1_PICTURE_PARAMETER_SET_1_PC)
> +#define DSC_BPP(bpp) ((bpp) << 0)
> +
> +#define DSCA_PICTURE_PARAMETER_SET_2 0x6B208
> +#define DSCC_PICTURE_PARAMETER_SET_2 0x6BA08
> +#define _ICL_DSC0_PICTURE_PARAMETER_SET_2_PB 0x78278
> +#define _ICL_DSC1_PICTURE_PARAMETER_SET_2_PB 0x78378
> +#define _ICL_DSC0_PICTURE_PARAMETER_SET_2_PC 0x78478
> +#define _ICL_DSC1_PICTURE_PARAMETER_SET_2_PC 0x78578
> +#define ICL_DSC0_PICTURE_PARAMETER_SET_2(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
> + _ICL_DSC0_PICTURE_PARAMETER_SET_2_PB, \
> + _ICL_DSC0_PICTURE_PARAMETER_SET_2_PC)
> +#define ICL_DSC1_PICTURE_PARAMETER_SET_2(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
> + _ICL_DSC1_PICTURE_PARAMETER_SET_2_PB, \
> + _ICL_DSC1_PICTURE_PARAMETER_SET_2_PC)
> +#define DSC_PIC_WIDTH(pic_width) ((pic_width) << 16)
> +#define DSC_PIC_HEIGHT(pic_height) ((pic_height) << 0)
> +
> +#define DSCA_PICTURE_PARAMETER_SET_3 0x6B20C
> +#define DSCC_PICTURE_PARAMETER_SET_3 0x6BA0C
> +#define _ICL_DSC0_PICTURE_PARAMETER_SET_3_PB 0x7827C
> +#define _ICL_DSC1_PICTURE_PARAMETER_SET_3_PB 0x7837C
> +#define _ICL_DSC0_PICTURE_PARAMETER_SET_3_PC 0x7847C
> +#define _ICL_DSC1_PICTURE_PARAMETER_SET_3_PC 0x7857C
> +#define ICL_DSC0_PICTURE_PARAMETER_SET_3(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
> + _ICL_DSC0_PICTURE_PARAMETER_SET_3_PB, \
> + _ICL_DSC0_PICTURE_PARAMETER_SET_3_PC)
> +#define ICL_DSC1_PICTURE_PARAMETER_SET_3(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
> + _ICL_DSC1_PICTURE_PARAMETER_SET_3_PB, \
> + _ICL_DSC1_PICTURE_PARAMETER_SET_3_PC)
> +#define DSC_SLICE_WIDTH(slice_width) ((slice_width) << 16)
> +#define DSC_SLICE_HEIGHT(slice_height) ((slice_height) << 0)
> +
> +#define DSCA_PICTURE_PARAMETER_SET_4 0x6B210
> +#define DSCC_PICTURE_PARAMETER_SET_4 0x6BA10
> +#define _ICL_DSC0_PICTURE_PARAMETER_SET_4_PB 0x78280
> +#define _ICL_DSC1_PICTURE_PARAMETER_SET_4_PB 0x78380
> +#define _ICL_DSC0_PICTURE_PARAMETER_SET_4_PC 0x78480
> +#define _ICL_DSC1_PICTURE_PARAMETER_SET_4_PC 0x78580
> +#define ICL_DSC0_PICTURE_PARAMETER_SET_4(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
> + _ICL_DSC0_PICTURE_PARAMETER_SET_4_PB, \
> + _ICL_DSC0_PICTURE_PARAMETER_SET_4_PC)
> +#define ICL_DSC1_PICTURE_PARAMETER_SET_4(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
> + _ICL_DSC0_PICTURE_PARAMETER_SET_4_PB, \
> + _ICL_DSC1_PICTURE_PARAMETER_SET_4_PC)
> +#define DSC_INITIAL_DEC_DELAY(dec_delay) ((dec_delay) << 16)
> +#define DSC_INITIAL_XMIT_DELAY(xmit_delay) ((xmit_delay) << 0)
> +
> +#define DSCA_PICTURE_PARAMETER_SET_5 0x6B214
> +#define DSCC_PICTURE_PARAMETER_SET_5 0x6BA14
> +#define _ICL_DSC0_PICTURE_PARAMETER_SET_5_PB 0x78284
> +#define _ICL_DSC1_PICTURE_PARAMETER_SET_5_PB 0x78384
> +#define _ICL_DSC0_PICTURE_PARAMETER_SET_5_PC 0x78484
> +#define _ICL_DSC1_PICTURE_PARAMETER_SET_5_PC 0x78584
> +#define ICL_DSC0_PICTURE_PARAMETER_SET_5(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
> + _ICL_DSC0_PICTURE_PARAMETER_SET_5_PB, \
> + _ICL_DSC0_PICTURE_PARAMETER_SET_5_PC)
> +#define ICL_DSC1_PICTURE_PARAMETER_SET_5(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
> + _ICL_DSC1_PICTURE_PARAMETER_SET_5_PC, \
> + _ICL_DSC1_PICTURE_PARAMETER_SET_5_PC)
> +#define DSC_SCALE_DEC_INTINT(scale_dec) ((scale_dec) << 16)
> +#define DSC_SCALE_INC_INT(scale_inc) ((scale_inc) << 0)
> +
> +#define DSCA_PICTURE_PARAMETER_SET_6 0x6B218
> +#define DSCC_PICTURE_PARAMETER_SET_6 0x6BA18
> +#define _ICL_DSC0_PICTURE_PARAMETER_SET_6_PB 0x78288
> +#define _ICL_DSC1_PICTURE_PARAMETER_SET_6_PB 0x78388
> +#define _ICL_DSC0_PICTURE_PARAMETER_SET_6_PC 0x78488
> +#define _ICL_DSC1_PICTURE_PARAMETER_SET_6_PC 0x78588
> +#define ICL_DSC0_PICTURE_PARAMETER_SET_6(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
> + _ICL_DSC0_PICTURE_PARAMETER_SET_6_PB, \
> + _ICL_DSC0_PICTURE_PARAMETER_SET_6_PC)
> +#define ICL_DSC1_PICTURE_PARAMETER_SET_6(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
> + _ICL_DSC1_PICTURE_PARAMETER_SET_6_PB, \
> + _ICL_DSC1_PICTURE_PARAMETER_SET_6_PC)
> +#define DSC_FLATNESS_MAX_QP(max_qp) (qp << 24)
> +#define DSC_FLATNESS_MIN_QP(min_qp) (qp << 16)
> +#define DSC_FIRST_LINE_BPG_OFFSET(offset) ((offset) << 8)
> +#define DSC_INITIAL_SCALE_VALUE(value) ((value) << 0)
> +
> +#define DSCA_PICTURE_PARAMETER_SET_7 0x6B21C
> +#define DSCC_PICTURE_PARAMETER_SET_7 0x6BA1C
> +#define _ICL_DSC0_PICTURE_PARAMETER_SET_7_PB 0x7828C
> +#define _ICL_DSC1_PICTURE_PARAMETER_SET_7_PB 0x7838C
> +#define _ICL_DSC0_PICTURE_PARAMETER_SET_7_PC 0x7848C
> +#define _ICL_DSC1_PICTURE_PARAMETER_SET_7_PC 0x7858C
> +#define ICL_DSC0_PICTURE_PARAMETER_SET_7(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
> + _ICL_DSC0_PICTURE_PARAMETER_SET_7_PB, \
> + _ICL_DSC0_PICTURE_PARAMETER_SET_7_PC)
> +#define ICL_DSC1_PICTURE_PARAMETER_SET_7(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
> + _ICL_DSC1_PICTURE_PARAMETER_SET_7_PB, \
> + _ICL_DSC1_PICTURE_PARAMETER_SET_7_PC)
> +#define DSC_NFL_BPG_OFFSET(bpg_offset) ((bpg_offset) << 16)
> +#define DSC_SLICE_BPG_OFFSET(bpg_offset) ((bpg_offset) << 0)
> +
> +#define DSCA_PICTURE_PARAMETER_SET_8 0x6B220
> +#define DSCC_PICTURE_PARAMETER_SET_8 0x6BA20
> +#define _ICL_DSC0_PICTURE_PARAMETER_SET_8_PB 0x78290
> +#define _ICL_DSC1_PICTURE_PARAMETER_SET_8_PB 0x78390
> +#define _ICL_DSC0_PICTURE_PARAMETER_SET_8_PC 0x78490
> +#define _ICL_DSC1_PICTURE_PARAMETER_SET_8_PC 0x78590
> +#define ICL_DSC0_PICTURE_PARAMETER_SET_8(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
> + _ICL_DSC0_PICTURE_PARAMETER_SET_8_PB, \
> + _ICL_DSC0_PICTURE_PARAMETER_SET_8_PC)
> +#define ICL_DSC1_PICTURE_PARAMETER_SET_8(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
> + _ICL_DSC1_PICTURE_PARAMETER_SET_8_PB, \
> + _ICL_DSC1_PICTURE_PARAMETER_SET_8_PC)
> +#define DSC_INITIAL_OFFSET(initial_offset) ((initial_offset) << 16)
> +#define DSC_FINAL_OFFSET(final_offset) ((final_offset) << 0)
> +
> +#define DSCA_PICTURE_PARAMETER_SET_9 0x6B224
> +#define DSCC_PICTURE_PARAMETER_SET_9 0x6BA24
> +#define _ICL_DSC0_PICTURE_PARAMETER_SET_9_PB 0x78294
> +#define _ICL_DSC1_PICTURE_PARAMETER_SET_9_PB 0x78394
> +#define _ICL_DSC0_PICTURE_PARAMETER_SET_9_PC 0x78494
> +#define _ICL_DSC1_PICTURE_PARAMETER_SET_9_PC 0x78594
> +#define ICL_DSC0_PICTURE_PARAMETER_SET_9(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
> + _ICL_DSC0_PICTURE_PARAMETER_SET_9_PB, \
> + _ICL_DSC0_PICTURE_PARAMETER_SET_9_PC)
> +#define ICL_DSC1_PICTURE_PARAMETER_SET_9(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
> + _ICL_DSC1_PICTURE_PARAMETER_SET_9_PB, \
> + _ICL_DSC1_PICTURE_PARAMETER_SET_9_PC)
> +#define DSC_RC_EDGE_FACTOR(rc_edge_fact) ((rc_edge_fact) << 16)
> +#define DSC_RC_MODEL_SIZE(rc_model_size) ((rc_model_size) << 0)
> +
> +#define DSCA_PICTURE_PARAMETER_SET_10 0x6B228
> +#define DSCC_PICTURE_PARAMETER_SET_10 0x6BA28
> +#define _ICL_DSC0_PICTURE_PARAMETER_SET_10_PB 0x78298
> +#define _ICL_DSC1_PICTURE_PARAMETER_SET_10_PB 0x78398
> +#define _ICL_DSC0_PICTURE_PARAMETER_SET_10_PC 0x78498
> +#define _ICL_DSC1_PICTURE_PARAMETER_SET_10_PC 0x78598
> +#define ICL_DSC0_PICTURE_PARAMETER_SET_10(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
> + _ICL_DSC0_PICTURE_PARAMETER_SET_10_PB, \
> + _ICL_DSC0_PICTURE_PARAMETER_SET_10_PC)
> +#define ICL_DSC1_PICTURE_PARAMETER_SET_10(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
> + _ICL_DSC1_PICTURE_PARAMETER_SET_10_PB, \
> + _ICL_DSC1_PICTURE_PARAMETER_SET_10_PC)
> +#define DSC_RC_TARGET_OFF_LOW(rc_tgt_off_low) ((rc_tgt_off_low) << 20)
> +#define DSC_RC_TARGET_OFF_HIGH(rc_tgt_off_high) ((rc_tgt_off_high) << 16)
> +#define DSC_RC_QUANT_INC_LIMIT1(lim) ((lim) << 8)
> +#define DSC_RC_QUANT_INC_LIMIT0(lim) ((lim) << 0)
> +
> +#define DSCA_PICTURE_PARAMETER_SET_11 0x6B22C
> +#define DSCC_PICTURE_PARAMETER_SET_11 0x6BA2C
> +#define _ICL_DSC0_PICTURE_PARAMETER_SET_11_PB 0x7829C
> +#define _ICL_DSC1_PICTURE_PARAMETER_SET_11_PB 0x7839C
> +#define _ICL_DSC0_PICTURE_PARAMETER_SET_11_PC 0x7849C
> +#define _ICL_DSC1_PICTURE_PARAMETER_SET_11_PC 0x7859C
> +#define ICL_DSC0_PICTURE_PARAMETER_SET_11(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
> + _ICL_DSC0_PICTURE_PARAMETER_SET_11_PB, \
> + _ICL_DSC0_PICTURE_PARAMETER_SET_11_PC)
> +#define ICL_DSC1_PICTURE_PARAMETER_SET_11(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
> + _ICL_DSC1_PICTURE_PARAMETER_SET_11_PB, \
> + _ICL_DSC1_PICTURE_PARAMETER_SET_11_PC)
> +
> +#define DSCA_PICTURE_PARAMETER_SET_12 0x6B260
> +#define DSCC_PICTURE_PARAMETER_SET_12 0x6BA60
> +#define _ICL_DSC0_PICTURE_PARAMETER_SET_12_PB 0x782A0
> +#define _ICL_DSC1_PICTURE_PARAMETER_SET_12_PB 0x783A0
> +#define _ICL_DSC0_PICTURE_PARAMETER_SET_12_PC 0x784A0
> +#define _ICL_DSC1_PICTURE_PARAMETER_SET_12_PC 0x785A0
> +#define ICL_DSC0_PICTURE_PARAMETER_SET_12(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
> + _ICL_DSC0_PICTURE_PARAMETER_SET_12_PB, \
> + _ICL_DSC0_PICTURE_PARAMETER_SET_12_PC)
> +#define ICL_DSC1_PICTURE_PARAMETER_SET_12(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
> + _ICL_DSC1_PICTURE_PARAMETER_SET_12_PB, \
> + _ICL_DSC1_PICTURE_PARAMETER_SET_12_PC)
> +
> +#define DSCA_PICTURE_PARAMETER_SET_13 0x6B264
> +#define DSCC_PICTURE_PARAMETER_SET_13 0x6BA64
> +#define _ICL_DSC0_PICTURE_PARAMETER_SET_13_PB 0x782A4
> +#define _ICL_DSC1_PICTURE_PARAMETER_SET_13_PB 0x783A4
> +#define _ICL_DSC0_PICTURE_PARAMETER_SET_13_PC 0x784A4
> +#define _ICL_DSC1_PICTURE_PARAMETER_SET_13_PC 0x785A4
> +#define ICL_DSC0_PICTURE_PARAMETER_SET_13(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
> + _ICL_DSC0_PICTURE_PARAMETER_SET_13_PB, \
> + _ICL_DSC0_PICTURE_PARAMETER_SET_13_PC)
> +#define ICL_DSC1_PICTURE_PARAMETER_SET_13(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
> + _ICL_DSC1_PICTURE_PARAMETER_SET_13_PB, \
> + _ICL_DSC1_PICTURE_PARAMETER_SET_13_PC)
> +
> +#define DSCA_PICTURE_PARAMETER_SET_14 0x6B268
> +#define DSCC_PICTURE_PARAMETER_SET_14 0x6BA68
> +#define _ICL_DSC0_PICTURE_PARAMETER_SET_14_PB 0x782A8
> +#define _ICL_DSC1_PICTURE_PARAMETER_SET_14_PB 0x783A8
> +#define _ICL_DSC0_PICTURE_PARAMETER_SET_14_PC 0x784A8
> +#define _ICL_DSC1_PICTURE_PARAMETER_SET_14_PC 0x785A8
> +#define ICL_DSC0_PICTURE_PARAMETER_SET_14(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
> + _ICL_DSC0_PICTURE_PARAMETER_SET_14_PB, \
> + _ICL_DSC0_PICTURE_PARAMETER_SET_14_PC)
> +#define ICL_DSC1_PICTURE_PARAMETER_SET_14(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
> + _ICL_DSC1_PICTURE_PARAMETER_SET_14_PB, \
> + _ICL_DSC1_PICTURE_PARAMETER_SET_14_PC)
> +
> +#define DSCA_PICTURE_PARAMETER_SET_15 0x6B26C
> +#define DSCC_PICTURE_PARAMETER_SET_15 0x6BA6C
> +#define _ICL_DSC0_PICTURE_PARAMETER_SET_15_PB 0x782AC
> +#define _ICL_DSC1_PICTURE_PARAMETER_SET_15_PB 0x783AC
> +#define _ICL_DSC0_PICTURE_PARAMETER_SET_15_PC 0x784AC
> +#define _ICL_DSC1_PICTURE_PARAMETER_SET_15_PC 0x785AC
> +#define ICL_DSC0_PICTURE_PARAMETER_SET_15(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
> + _ICL_DSC0_PICTURE_PARAMETER_SET_15_PB, \
> + _ICL_DSC0_PICTURE_PARAMETER_SET_15_PC)
> +#define ICL_DSC1_PICTURE_PARAMETER_SET_15(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
> + _ICL_DSC1_PICTURE_PARAMETER_SET_15_PB, \
> + _ICL_DSC1_PICTURE_PARAMETER_SET_15_PC)
> +
> +#define DSCA_PICTURE_PARAMETER_SET_16 0x6B270
> +#define DSCC_PICTURE_PARAMETER_SET_16 0x6BA70
> +#define _ICL_DSC0_PICTURE_PARAMETER_SET_16_PB 0x782B0
> +#define _ICL_DSC1_PICTURE_PARAMETER_SET_16_PB 0x783B0
> +#define _ICL_DSC0_PICTURE_PARAMETER_SET_16_PC 0x784B0
> +#define _ICL_DSC1_PICTURE_PARAMETER_SET_16_PC 0x785B0
> +#define ICL_DSC0_PICTURE_PARAMETER_SET_16(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
> + _ICL_DSC0_PICTURE_PARAMETER_SET_16_PB, \
> + _ICL_DSC0_PICTURE_PARAMETER_SET_16_PC)
> +#define ICL_DSC1_PICTURE_PARAMETER_SET_16(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
> + _ICL_DSC1_PICTURE_PARAMETER_SET_16_PB, \
> + _ICL_DSC1_PICTURE_PARAMETER_SET_16_PC)
> +#define DSC_SLICE_PER_LINE(slice_per_line) ((slice_per_line) << 16)
> +#define DSC_SLICE_CHUNK_SIZE(slice_chunk_aize) (slice_chunk_size << 0)
> +
> #endif /* _I915_REG_H_ */
> --
> 2.7.4
>
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^ permalink raw reply [flat|nested] 15+ messages in thread
* [PATCH 3/4] i915/dp/dsc: Add Rate Control Buffer Threshold Registers
2018-07-17 21:10 [PATCH 1/4] drm/i915/icl: Add VIDEO_DIP regsiters Anusha Srivatsa
2018-07-17 21:10 ` [PATCH 2/4] i915/dp/dsc: Add DSC PPS register definitions Anusha Srivatsa
@ 2018-07-17 21:11 ` Anusha Srivatsa
2018-07-17 21:11 ` [PATCH 4/4] i915/dp/dsc: Add Rate Control Range Parameter Registers Anusha Srivatsa
` (4 subsequent siblings)
6 siblings, 0 replies; 15+ messages in thread
From: Anusha Srivatsa @ 2018-07-17 21:11 UTC (permalink / raw)
To: intel-gfx; +Cc: Jani Nikula
From: "Srivatsa, Anusha" <anusha.srivatsa@intel.com>
Add register defines and shifts that control the RC buffer threshold
between encoder and decoder for eDP/MIPI and DP cases.
The actual values are calculated usung a helper function.
This patch adds the shifts to registers where the value will
be written during atomic commit.
v2:
- Use _MMIO_PIPE() instead of _MMIO_(_PICK()) (Manasi)
- Combine shifts (Manasi)
Cc: Jani Nikula <jani.nikula@intel.com>
Cc: Ville Syrjala <ville.syrjala@linux.intel.com>
Cc: Manasi Navare <manasi.d.navare@intel.com>
Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
Reviewed-by: Manasi Navare <manasi.d.navare@intel.com>
---
drivers/gpu/drm/i915/i915_reg.h | 52 +++++++++++++++++++++++++++++++++++++++++
1 file changed, 52 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index e8687b0..6fe2691 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -10499,4 +10499,56 @@ enum skl_power_gate {
#define DSC_SLICE_PER_LINE(slice_per_line) ((slice_per_line) << 16)
#define DSC_SLICE_CHUNK_SIZE(slice_chunk_aize) (slice_chunk_size << 0)
+/* Icelake Rate Control Buffer Threshold Registers */
+#define DSCA_RC_BUF_THRESH_0 _MMIO(0x6B230)
+#define DSCA_RC_BUF_THRESH_0_UDW _MMIO(0x6B230 + 4)
+#define DSCC_RC_BUF_THRESH_0 _MMIO(0x6BA30)
+#define DSCC_RC_BUF_THRESH_0_UDW _MMIO(0x6BA30 + 4)
+#define _ICL_DSC0_RC_BUF_THRESH_0_PB (0x78254)
+#define _ICL_DSC0_RC_BUF_THRESH_0_UDW_PB (0x78254 + 4)
+#define _ICL_DSC1_RC_BUF_THRESH_0_PB (0x78354)
+#define _ICL_DSC1_RC_BUF_THRESH_0_UDW_PB (0x78354 + 4)
+#define _ICL_DSC0_RC_BUF_THRESH_0_PC (0x78454)
+#define _ICL_DSC0_RC_BUF_THRESH_0_UDW_PC (0x78454 + 4)
+#define _ICL_DSC1_RC_BUF_THRESH_0_PC (0x78554)
+#define _ICL_DSC1_RC_BUF_THRESH_0_UDW_PC (0x78554 + 4)
+#define ICL_DSC0_RC_BUF_THRESH_0(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
+ _ICL_DSC0_RC_BUF_THRESH_0_PB, \
+ _ICL_DSC0_RC_BUF_THRESH_0_PC)
+#define ICL_DSC0_RC_BUF_THRESH_0_UDW(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
+ _ICL_DSC0_RC_BUF_THRESH_0_UDW_PB, \
+ _ICL_DSC0_RC_BUF_THRESH_0_UDW_PC)
+#define ICL_DSC1_RC_BUF_THRESH_0(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
+ _ICL_DSC1_RC_BUF_THRESH_0_PB, \
+ _ICL_DSC1_RC_BUF_THRESH_0_PC)
+#define ICL_DSC1_RC_BUF_THRESH_0_UDW(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
+ _ICL_DSC1_RC_BUF_THRESH_0_UDW_PB, \
+ _ICL_DSC1_RC_BUF_THRESH_0_UDW_PC)
+
+#define DSCA_RC_BUF_THRESH_1 _MMIO(0x6B238)
+#define DSCA_RC_BUF_THRESH_1_UDW _MMIO(0x6B238 + 4)
+#define DSCC_RC_BUF_THRESH_1 _MMIO(0x6BA38)
+#define DSCC_RC_BUF_THRESH_1_UDW _MMIO(0x6BA38 + 4)
+#define _ICL_DSC0_RC_BUF_THRESH_1_PB (0x7825C)
+#define _ICL_DSC0_RC_BUF_THRESH_1_UDW_PB (0x7825C + 4)
+#define _ICL_DSC1_RC_BUF_THRESH_1_PB (0x7835C)
+#define _ICL_DSC1_RC_BUF_THRESH_1_UDW_PB (0x7835C + 4)
+#define _ICL_DSC0_RC_BUF_THRESH_1_PC (0x7845C)
+#define _ICL_DSC0_RC_BUF_THRESH_1_UDW_PC (0x7845C + 4)
+#define _ICL_DSC1_RC_BUF_THRESH_1_PC (0x7855C)
+#define _ICL_DSC1_RC_BUF_THRESH_1_UDW_PC (0x7855C + 4)
+#define ICL_DSC0_RC_BUF_THRESH_1(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
+ _ICL_DSC0_RC_BUF_THRESH_1_PB, \
+ _ICL_DSC0_RC_BUF_THRESH_1_PC)
+#define ICL_DSC0_RC_BUF_THRESH_1_UDW(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
+ _ICL_DSC0_RC_BUF_THRESH_1_UDW_PB, \
+ _ICL_DSC0_RC_BUF_THRESH_1_UDW_PC)
+#define ICL_DSC1_RC_BUF_THRESH_1(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
+ _ICL_DSC1_RC_BUF_THRESH_1_PB, \
+ _ICL_DSC1_RC_BUF_THRESH_1_PC)
+#define ICL_DSC1_RC_BUF_THRESH_1_UDW(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
+ _ICL_DSC1_RC_BUF_THRESH_1_UDW_PB, \
+ _ICL_DSC1_RC_BUF_THRESH_1_UDW_PC)
+
+
#endif /* _I915_REG_H_ */
--
2.7.4
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^ permalink raw reply related [flat|nested] 15+ messages in thread* [PATCH 4/4] i915/dp/dsc: Add Rate Control Range Parameter Registers
2018-07-17 21:10 [PATCH 1/4] drm/i915/icl: Add VIDEO_DIP regsiters Anusha Srivatsa
2018-07-17 21:10 ` [PATCH 2/4] i915/dp/dsc: Add DSC PPS register definitions Anusha Srivatsa
2018-07-17 21:11 ` [PATCH 3/4] i915/dp/dsc: Add Rate Control Buffer Threshold Registers Anusha Srivatsa
@ 2018-07-17 21:11 ` Anusha Srivatsa
2018-07-18 18:57 ` Manasi Navare
2018-07-17 21:33 ` ✗ Fi.CI.CHECKPATCH: warning for series starting with [1/4] drm/i915/icl: Add VIDEO_DIP regsiters Patchwork
` (3 subsequent siblings)
6 siblings, 1 reply; 15+ messages in thread
From: Anusha Srivatsa @ 2018-07-17 21:11 UTC (permalink / raw)
To: intel-gfx; +Cc: Jani Nikula
From: "Srivatsa, Anusha" <anusha.srivatsa@intel.com>
RC model has these parameters that correspond with each of
15 ranges of RC buffer threshold value in the RC model.
The three elements are range_min_qp, range_max_qp and
range_bpg_offset.
Add the Rate Control range values for eDP/MIPI and DP case.
The actual values are calculated usung a helper function.
This patch adds the shifts to registers where the value will
be written during atomic commit.
v2:
- Use _MMIO_PIPE() instead of _MMIO(_PICK()) (Manasi)
- Combine shifts (Manasi)
Cc: Jose Souza <jose.souza@intel.com>
Cc: Jani Nikula <jani.nikula@intel.com>
Cc: Ville Syrjala <ville.syrjala@linux.intel.com>
Cc: Manasi Navare <manasi.d.navare@intel.com>
Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
---
drivers/gpu/drm/i915/i915_reg.h | 104 ++++++++++++++++++++++++++++++++++++++++
1 file changed, 104 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 6fe2691..d763b6d 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -7678,6 +7678,110 @@ enum {
#define SHOTPLUG_CTL_TC _MMIO(0xc4034)
#define ICP_TC_HPD_ENABLE(tc_port) (8 << (tc_port) * 4)
+/* Icelake DSC Rate Control Range Parameter Registers */
+#define DSCA_RC_RANGE_PARAMETERS_0 _MMIO(0x6B240)
+#define DSCA_RC_RANGE_PARAMETERS_0_UDW _MMIO(0x6B240 + 4)
+#define DSCC_RC_RANGE_PARAMETERS_0 _MMIO(0x6BA40)
+#define DSCC_RC_RANGE_PARAMETERS_0_UDW _MMIO(0x6BA40 + 4)
+#define _ICL_DSC0_RC_RANGE_PARAMETERS_0_PB (0x78208)
+#define _ICL_DSC0_RC_RANGE_PARAMETERS_0_UDW_PB (0x78208 + 4)
+#define _ICL_DSC1_RC_RANGE_PARAMETERS_0_PB (0x78308)
+#define _ICL_DSC1_RC_RANGE_PARAMETERS_0_UDW_PB (0x78308 + 4)
+#define _ICL_DSC0_RC_RANGE_PARAMETERS_0_PC (0x78408)
+#define _ICL_DSC0_RC_RANGE_PARAMETERS_0_UDW_PC (0x78408 + 4)
+#define _ICL_DSC1_RC_RANGE_PARAMETERS_0_PC (0x78508)
+#define _ICL_DSC1_RC_RANGE_PARAMETERS_0_UDW_PC (0x78508 + 4)
+#define ICL_DSC0_RC_RANGE_PARAMETERS_0(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
+ _ICL_DSC0_RC_RANGE_PARAMETERS_0_PB, \
+ _ICL_DSC0_RC_RANGE_PARAMETERS_0_PC)
+#define ICL_DSC0_RC_RANGE_PARAMETERS_0_UDW(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
+ _ICL_DSC0_RC_RANGE_PARAMETERS_0_UDW_PB, \
+ _ICL_DSC0_RC_RANGE_PARAMETERS_0_UDW_PC)
+#define ICL_DSC1_RC_RANGE_PARAMETERS_0(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
+ _ICL_DSC1_RC_RANGE_PARAMETERS_0_PB, \
+ _ICL_DSC1_RC_RANGE_PARAMETERS_0_PC)
+#define ICL_DSC1_RC_RANGE_PARAMETERS_0_UDW(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
+ _ICL_DSC1_RC_RANGE_PARAMETERS_0_UDW_PB, \
+ _ICL_DSC1_RC_RANGE_PARAMETERS_0_UDW_PC)
+#define RC_BPG_OFFSET_SHIFT 10
+#define RC_MAX_QP_SHIFT 5
+#define RC_MIN_QP_SHIFT 0
+
+#define DSCA_RC_RANGE_PARAMETERS_1 _MMIO(0x6B248)
+#define DSCA_RC_RANGE_PARAMETERS_1_UDW _MMIO(0x6B248 + 4)
+#define DSCC_RC_RANGE_PARAMETERS_1 _MMIO(0x6BA48)
+#define DSCC_RC_RANGE_PARAMETERS_1_UDW _MMIO(0x6BA48 + 4)
+#define _ICL_DSC0_RC_RANGE_PARAMETERS_1_PB (0x78210)
+#define _ICL_DSC0_RC_RANGE_PARAMETERS_1_UDW_PB (0x78210 + 4)
+#define _ICL_DSC1_RC_RANGE_PARAMETERS_1_PB (0x78310)
+#define _ICL_DSC1_RC_RANGE_PARAMETERS_1_UDW_PB (0x78310 + 4)
+#define _ICL_DSC0_RC_RANGE_PARAMETERS_1_PC (0x78410)
+#define _ICL_DSC0_RC_RANGE_PARAMETERS_1_UDW_PC (0x78410 + 4)
+#define _ICL_DSC1_RC_RANGE_PARAMETERS_1_PC (0x78510)
+#define _ICL_DSC1_RC_RANGE_PARAMETERS_1_UDW_PC (0x78510 + 4)
+#define ICL_DSC0_RC_RANGE_PARAMETERS_1(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
+ _ICL_DSC0_RC_RANGE_PARAMETERS_1_PB, \
+ _ICL_DSC0_RC_RANGE_PARAMETERS_1_PC)
+#define ICL_DSC0_RC_RANGE_PARAMETERS_1_UDW(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
+ _ICL_DSC0_RC_RANGE_PARAMETERS_1_UDW_PB, \
+ _ICL_DSC0_RC_RANGE_PARAMETERS_1_UDW_PC)
+#define ICL_DSC1_RC_RANGE_PARAMETERS_1(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
+ _ICL_DSC1_RC_RANGE_PARAMETERS_1_PB, \
+ _ICL_DSC1_RC_RANGE_PARAMETERS_1_PC)
+#define ICL_DSC1_RC_RANGE_PARAMETERS_1_UDW(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
+ _ICL_DSC1_RC_RANGE_PARAMETERS_1_UDW_PB, \
+ _ICL_DSC1_RC_RANGE_PARAMETERS_1_UDW_PC)
+
+#define DSCA_RC_RANGE_PARAMETERS_2 _MMIO(0x6B250)
+#define DSCA_RC_RANGE_PARAMETERS_2_UDW _MMIO(0x6B250 + 4)
+#define DSCC_RC_RANGE_PARAMETERS_2 _MMIO(0x6BA50)
+#define DSCC_RC_RANGE_PARAMETERS_2_UDW _MMIO(0x6BA50 + 4)
+#define _ICL_DSC0_RC_RANGE_PARAMETERS_2_PB (0x78218)
+#define _ICL_DSC0_RC_RANGE_PARAMETERS_2_UDW_PB (0x78218 + 4)
+#define _ICL_DSC1_RC_RANGE_PARAMETERS_2_PB (0x78318)
+#define _ICL_DSC1_RC_RANGE_PARAMETERS_2_UDW_PB (0x78318 + 4)
+#define _ICL_DSC0_RC_RANGE_PARAMETERS_2_PC (0x78418)
+#define _ICL_DSC0_RC_RANGE_PARAMETERS_2_UDW_PC (0x78418 + 4)
+#define _ICL_DSC1_RC_RANGE_PARAMETERS_2_PC (0x78518)
+#define _ICL_DSC1_RC_RANGE_PARAMETERS_2_UDW_PC (0x78518 + 4)
+#define ICL_DSC0_RC_RANGE_PARAMETERS_2(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
+ _ICL_DSC0_RC_RANGE_PARAMETERS_2_PB, \
+ _ICL_DSC0_RC_RANGE_PARAMETERS_2_PC)
+#define ICL_DSC0_RC_RANGE_PARAMETERS_2_UDW(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
+ _ICL_DSC0_RC_RANGE_PARAMETERS_2_UDW_PB, \
+ _ICL_DSC0_RC_RANGE_PARAMETERS_2_UDW_PC)
+#define ICL_DSC1_RC_RANGE_PARAMETERS_2(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
+ _ICL_DSC1_RC_RANGE_PARAMETERS_2_PB, \
+ _ICL_DSC1_RC_RANGE_PARAMETERS_2_PC)
+#define ICL_DSC1_RC_RANGE_PARAMETERS_2_UDW(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
+ _ICL_DSC1_RC_RANGE_PARAMETERS_2_UDW_PB, \
+ _ICL_DSC1_RC_RANGE_PARAMETERS_2_UDW_PC)
+
+#define DSCA_RC_RANGE_PARAMETERS_3 _MMIO(0x6B258)
+#define DSCA_RC_RANGE_PARAMETERS_3_UDW _MMIO(0x6B258 + 4)
+#define DSCC_RC_RANGE_PARAMETERS_3 _MMIO(0x6BA58)
+#define DSCC_RC_RANGE_PARAMETERS_3_UDW _MMIO(0x6BA58 + 4)
+#define _ICL_DSC0_RC_RANGE_PARAMETERS_3_PB (0x78220)
+#define _ICL_DSC0_RC_RANGE_PARAMETERS_3_UDW_PB (0x78220 + 4)
+#define _ICL_DSC1_RC_RANGE_PARAMETERS_3_PB (0x78320)
+#define _ICL_DSC1_RC_RANGE_PARAMETERS_3_UDW_PB (0x78320 + 4)
+#define _ICL_DSC0_RC_RANGE_PARAMETERS_3_PC (0x78420)
+#define _ICL_DSC0_RC_RANGE_PARAMETERS_3_UDW_PC (0x78420 + 4)
+#define _ICL_DSC1_RC_RANGE_PARAMETERS_3_PC (0x78520)
+#define _ICL_DSC1_RC_RANGE_PARAMETERS_3_UDW_PC (0x78520 + 4)
+#define ICL_DSC0_RC_RANGE_PARAMETERS_3(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
+ _ICL_DSC0_RC_RANGE_PARAMETERS_3_PB, \
+ _ICL_DSC0_RC_RANGE_PARAMETERS_3_PC)
+#define ICL_DSC0_RC_RANGE_PARAMETERS_3_UDW(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
+ _ICL_DSC0_RC_RANGE_PARAMETERS_3_UDW_PB, \
+ _ICL_DSC0_RC_RANGE_PARAMETERS_3_UDW_PC)
+#define ICL_DSC1_RC_RANGE_PARAMETERS_3(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
+ _ICL_DSC1_RC_RANGE_PARAMETERS_3_PB, \
+ _ICL_DSC1_RC_RANGE_PARAMETERS_3_PC)
+#define ICL_DSC1_RC_RANGE_PARAMETERS_3_UDW(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
+ _ICL_DSC1_RC_RANGE_PARAMETERS_3_UDW_PB, \
+ _ICL_DSC1_RC_RANGE_PARAMETERS_3_UDW_PC)
+
#define ICP_TC_HPD_LONG_DETECT(tc_port) (2 << (tc_port) * 4)
#define ICP_TC_HPD_SHORT_DETECT(tc_port) (1 << (tc_port) * 4)
--
2.7.4
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^ permalink raw reply related [flat|nested] 15+ messages in thread* Re: [PATCH 4/4] i915/dp/dsc: Add Rate Control Range Parameter Registers
2018-07-17 21:11 ` [PATCH 4/4] i915/dp/dsc: Add Rate Control Range Parameter Registers Anusha Srivatsa
@ 2018-07-18 18:57 ` Manasi Navare
0 siblings, 0 replies; 15+ messages in thread
From: Manasi Navare @ 2018-07-18 18:57 UTC (permalink / raw)
To: Anusha Srivatsa; +Cc: Jani Nikula, intel-gfx
On Tue, Jul 17, 2018 at 02:11:01PM -0700, Anusha Srivatsa wrote:
> From: "Srivatsa, Anusha" <anusha.srivatsa@intel.com>
>
> RC model has these parameters that correspond with each of
> 15 ranges of RC buffer threshold value in the RC model.
> The three elements are range_min_qp, range_max_qp and
> range_bpg_offset.
>
> Add the Rate Control range values for eDP/MIPI and DP case.
> The actual values are calculated usung a helper function.
> This patch adds the shifts to registers where the value will
> be written during atomic commit.
>
> v2:
> - Use _MMIO_PIPE() instead of _MMIO(_PICK()) (Manasi)
> - Combine shifts (Manasi)
>
> Cc: Jose Souza <jose.souza@intel.com>
> Cc: Jani Nikula <jani.nikula@intel.com>
> Cc: Ville Syrjala <ville.syrjala@linux.intel.com>
> Cc: Manasi Navare <manasi.d.navare@intel.com>
> Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
Matches the spec, looks good to me.
Reviewed-by: Manasi Navare <manasi.d.navare@intel.com>
> ---
> drivers/gpu/drm/i915/i915_reg.h | 104 ++++++++++++++++++++++++++++++++++++++++
> 1 file changed, 104 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 6fe2691..d763b6d 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -7678,6 +7678,110 @@ enum {
>
> #define SHOTPLUG_CTL_TC _MMIO(0xc4034)
> #define ICP_TC_HPD_ENABLE(tc_port) (8 << (tc_port) * 4)
> +/* Icelake DSC Rate Control Range Parameter Registers */
> +#define DSCA_RC_RANGE_PARAMETERS_0 _MMIO(0x6B240)
> +#define DSCA_RC_RANGE_PARAMETERS_0_UDW _MMIO(0x6B240 + 4)
> +#define DSCC_RC_RANGE_PARAMETERS_0 _MMIO(0x6BA40)
> +#define DSCC_RC_RANGE_PARAMETERS_0_UDW _MMIO(0x6BA40 + 4)
> +#define _ICL_DSC0_RC_RANGE_PARAMETERS_0_PB (0x78208)
> +#define _ICL_DSC0_RC_RANGE_PARAMETERS_0_UDW_PB (0x78208 + 4)
> +#define _ICL_DSC1_RC_RANGE_PARAMETERS_0_PB (0x78308)
> +#define _ICL_DSC1_RC_RANGE_PARAMETERS_0_UDW_PB (0x78308 + 4)
> +#define _ICL_DSC0_RC_RANGE_PARAMETERS_0_PC (0x78408)
> +#define _ICL_DSC0_RC_RANGE_PARAMETERS_0_UDW_PC (0x78408 + 4)
> +#define _ICL_DSC1_RC_RANGE_PARAMETERS_0_PC (0x78508)
> +#define _ICL_DSC1_RC_RANGE_PARAMETERS_0_UDW_PC (0x78508 + 4)
> +#define ICL_DSC0_RC_RANGE_PARAMETERS_0(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
> + _ICL_DSC0_RC_RANGE_PARAMETERS_0_PB, \
> + _ICL_DSC0_RC_RANGE_PARAMETERS_0_PC)
> +#define ICL_DSC0_RC_RANGE_PARAMETERS_0_UDW(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
> + _ICL_DSC0_RC_RANGE_PARAMETERS_0_UDW_PB, \
> + _ICL_DSC0_RC_RANGE_PARAMETERS_0_UDW_PC)
> +#define ICL_DSC1_RC_RANGE_PARAMETERS_0(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
> + _ICL_DSC1_RC_RANGE_PARAMETERS_0_PB, \
> + _ICL_DSC1_RC_RANGE_PARAMETERS_0_PC)
> +#define ICL_DSC1_RC_RANGE_PARAMETERS_0_UDW(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
> + _ICL_DSC1_RC_RANGE_PARAMETERS_0_UDW_PB, \
> + _ICL_DSC1_RC_RANGE_PARAMETERS_0_UDW_PC)
> +#define RC_BPG_OFFSET_SHIFT 10
> +#define RC_MAX_QP_SHIFT 5
> +#define RC_MIN_QP_SHIFT 0
> +
> +#define DSCA_RC_RANGE_PARAMETERS_1 _MMIO(0x6B248)
> +#define DSCA_RC_RANGE_PARAMETERS_1_UDW _MMIO(0x6B248 + 4)
> +#define DSCC_RC_RANGE_PARAMETERS_1 _MMIO(0x6BA48)
> +#define DSCC_RC_RANGE_PARAMETERS_1_UDW _MMIO(0x6BA48 + 4)
> +#define _ICL_DSC0_RC_RANGE_PARAMETERS_1_PB (0x78210)
> +#define _ICL_DSC0_RC_RANGE_PARAMETERS_1_UDW_PB (0x78210 + 4)
> +#define _ICL_DSC1_RC_RANGE_PARAMETERS_1_PB (0x78310)
> +#define _ICL_DSC1_RC_RANGE_PARAMETERS_1_UDW_PB (0x78310 + 4)
> +#define _ICL_DSC0_RC_RANGE_PARAMETERS_1_PC (0x78410)
> +#define _ICL_DSC0_RC_RANGE_PARAMETERS_1_UDW_PC (0x78410 + 4)
> +#define _ICL_DSC1_RC_RANGE_PARAMETERS_1_PC (0x78510)
> +#define _ICL_DSC1_RC_RANGE_PARAMETERS_1_UDW_PC (0x78510 + 4)
> +#define ICL_DSC0_RC_RANGE_PARAMETERS_1(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
> + _ICL_DSC0_RC_RANGE_PARAMETERS_1_PB, \
> + _ICL_DSC0_RC_RANGE_PARAMETERS_1_PC)
> +#define ICL_DSC0_RC_RANGE_PARAMETERS_1_UDW(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
> + _ICL_DSC0_RC_RANGE_PARAMETERS_1_UDW_PB, \
> + _ICL_DSC0_RC_RANGE_PARAMETERS_1_UDW_PC)
> +#define ICL_DSC1_RC_RANGE_PARAMETERS_1(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
> + _ICL_DSC1_RC_RANGE_PARAMETERS_1_PB, \
> + _ICL_DSC1_RC_RANGE_PARAMETERS_1_PC)
> +#define ICL_DSC1_RC_RANGE_PARAMETERS_1_UDW(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
> + _ICL_DSC1_RC_RANGE_PARAMETERS_1_UDW_PB, \
> + _ICL_DSC1_RC_RANGE_PARAMETERS_1_UDW_PC)
> +
> +#define DSCA_RC_RANGE_PARAMETERS_2 _MMIO(0x6B250)
> +#define DSCA_RC_RANGE_PARAMETERS_2_UDW _MMIO(0x6B250 + 4)
> +#define DSCC_RC_RANGE_PARAMETERS_2 _MMIO(0x6BA50)
> +#define DSCC_RC_RANGE_PARAMETERS_2_UDW _MMIO(0x6BA50 + 4)
> +#define _ICL_DSC0_RC_RANGE_PARAMETERS_2_PB (0x78218)
> +#define _ICL_DSC0_RC_RANGE_PARAMETERS_2_UDW_PB (0x78218 + 4)
> +#define _ICL_DSC1_RC_RANGE_PARAMETERS_2_PB (0x78318)
> +#define _ICL_DSC1_RC_RANGE_PARAMETERS_2_UDW_PB (0x78318 + 4)
> +#define _ICL_DSC0_RC_RANGE_PARAMETERS_2_PC (0x78418)
> +#define _ICL_DSC0_RC_RANGE_PARAMETERS_2_UDW_PC (0x78418 + 4)
> +#define _ICL_DSC1_RC_RANGE_PARAMETERS_2_PC (0x78518)
> +#define _ICL_DSC1_RC_RANGE_PARAMETERS_2_UDW_PC (0x78518 + 4)
> +#define ICL_DSC0_RC_RANGE_PARAMETERS_2(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
> + _ICL_DSC0_RC_RANGE_PARAMETERS_2_PB, \
> + _ICL_DSC0_RC_RANGE_PARAMETERS_2_PC)
> +#define ICL_DSC0_RC_RANGE_PARAMETERS_2_UDW(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
> + _ICL_DSC0_RC_RANGE_PARAMETERS_2_UDW_PB, \
> + _ICL_DSC0_RC_RANGE_PARAMETERS_2_UDW_PC)
> +#define ICL_DSC1_RC_RANGE_PARAMETERS_2(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
> + _ICL_DSC1_RC_RANGE_PARAMETERS_2_PB, \
> + _ICL_DSC1_RC_RANGE_PARAMETERS_2_PC)
> +#define ICL_DSC1_RC_RANGE_PARAMETERS_2_UDW(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
> + _ICL_DSC1_RC_RANGE_PARAMETERS_2_UDW_PB, \
> + _ICL_DSC1_RC_RANGE_PARAMETERS_2_UDW_PC)
> +
> +#define DSCA_RC_RANGE_PARAMETERS_3 _MMIO(0x6B258)
> +#define DSCA_RC_RANGE_PARAMETERS_3_UDW _MMIO(0x6B258 + 4)
> +#define DSCC_RC_RANGE_PARAMETERS_3 _MMIO(0x6BA58)
> +#define DSCC_RC_RANGE_PARAMETERS_3_UDW _MMIO(0x6BA58 + 4)
> +#define _ICL_DSC0_RC_RANGE_PARAMETERS_3_PB (0x78220)
> +#define _ICL_DSC0_RC_RANGE_PARAMETERS_3_UDW_PB (0x78220 + 4)
> +#define _ICL_DSC1_RC_RANGE_PARAMETERS_3_PB (0x78320)
> +#define _ICL_DSC1_RC_RANGE_PARAMETERS_3_UDW_PB (0x78320 + 4)
> +#define _ICL_DSC0_RC_RANGE_PARAMETERS_3_PC (0x78420)
> +#define _ICL_DSC0_RC_RANGE_PARAMETERS_3_UDW_PC (0x78420 + 4)
> +#define _ICL_DSC1_RC_RANGE_PARAMETERS_3_PC (0x78520)
> +#define _ICL_DSC1_RC_RANGE_PARAMETERS_3_UDW_PC (0x78520 + 4)
> +#define ICL_DSC0_RC_RANGE_PARAMETERS_3(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
> + _ICL_DSC0_RC_RANGE_PARAMETERS_3_PB, \
> + _ICL_DSC0_RC_RANGE_PARAMETERS_3_PC)
> +#define ICL_DSC0_RC_RANGE_PARAMETERS_3_UDW(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
> + _ICL_DSC0_RC_RANGE_PARAMETERS_3_UDW_PB, \
> + _ICL_DSC0_RC_RANGE_PARAMETERS_3_UDW_PC)
> +#define ICL_DSC1_RC_RANGE_PARAMETERS_3(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
> + _ICL_DSC1_RC_RANGE_PARAMETERS_3_PB, \
> + _ICL_DSC1_RC_RANGE_PARAMETERS_3_PC)
> +#define ICL_DSC1_RC_RANGE_PARAMETERS_3_UDW(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
> + _ICL_DSC1_RC_RANGE_PARAMETERS_3_UDW_PB, \
> + _ICL_DSC1_RC_RANGE_PARAMETERS_3_UDW_PC)
> +
> #define ICP_TC_HPD_LONG_DETECT(tc_port) (2 << (tc_port) * 4)
> #define ICP_TC_HPD_SHORT_DETECT(tc_port) (1 << (tc_port) * 4)
>
> --
> 2.7.4
>
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 15+ messages in thread
* ✗ Fi.CI.CHECKPATCH: warning for series starting with [1/4] drm/i915/icl: Add VIDEO_DIP regsiters
2018-07-17 21:10 [PATCH 1/4] drm/i915/icl: Add VIDEO_DIP regsiters Anusha Srivatsa
` (2 preceding siblings ...)
2018-07-17 21:11 ` [PATCH 4/4] i915/dp/dsc: Add Rate Control Range Parameter Registers Anusha Srivatsa
@ 2018-07-17 21:33 ` Patchwork
2018-07-17 21:59 ` ✓ Fi.CI.BAT: success " Patchwork
` (2 subsequent siblings)
6 siblings, 0 replies; 15+ messages in thread
From: Patchwork @ 2018-07-17 21:33 UTC (permalink / raw)
To: Anusha Srivatsa; +Cc: intel-gfx
== Series Details ==
Series: series starting with [1/4] drm/i915/icl: Add VIDEO_DIP regsiters
URL : https://patchwork.freedesktop.org/series/46742/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
0ccb8db4366a drm/i915/icl: Add VIDEO_DIP regsiters
-:66: WARNING:LONG_LINE: line over 100 characters
#66: FILE: drivers/gpu/drm/i915/i915_reg.h:7873:
+#define ICL_VIDEO_DIP_PPS_DATA(trans, i) _MMIO_TRANS2(trans, _ICL_VIDEO_DIP_PPS_DATA_A + (i) * 4)
-:67: WARNING:LONG_LINE: line over 100 characters
#67: FILE: drivers/gpu/drm/i915/i915_reg.h:7874:
+#define ICL_VIDEO_DIP_PPS_ECC(trans, i) _MMIO_TRANS2(trans, _ICL_VIDEO_DIP_PPS_ECC_A + (i) * 4)
total: 0 errors, 2 warnings, 0 checks, 41 lines checked
f7a62fccc3eb i915/dp/dsc: Add DSC PPS register definitions
f6a9fee4d495 i915/dp/dsc: Add Rate Control Buffer Threshold Registers
-:82: CHECK:LINE_SPACING: Please don't use multiple blank lines
#82: FILE: drivers/gpu/drm/i915/i915_reg.h:10553:
+
+
total: 0 errors, 0 warnings, 1 checks, 56 lines checked
7ba6acbd53cb i915/dp/dsc: Add Rate Control Range Parameter Registers
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 15+ messages in thread* ✓ Fi.CI.BAT: success for series starting with [1/4] drm/i915/icl: Add VIDEO_DIP regsiters
2018-07-17 21:10 [PATCH 1/4] drm/i915/icl: Add VIDEO_DIP regsiters Anusha Srivatsa
` (3 preceding siblings ...)
2018-07-17 21:33 ` ✗ Fi.CI.CHECKPATCH: warning for series starting with [1/4] drm/i915/icl: Add VIDEO_DIP regsiters Patchwork
@ 2018-07-17 21:59 ` Patchwork
2018-07-18 5:14 ` ✓ Fi.CI.IGT: " Patchwork
2018-07-18 18:53 ` [PATCH 1/4] " Manasi Navare
6 siblings, 0 replies; 15+ messages in thread
From: Patchwork @ 2018-07-17 21:59 UTC (permalink / raw)
To: Anusha Srivatsa; +Cc: intel-gfx
== Series Details ==
Series: series starting with [1/4] drm/i915/icl: Add VIDEO_DIP regsiters
URL : https://patchwork.freedesktop.org/series/46742/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_4503 -> Patchwork_9699 =
== Summary - WARNING ==
Minor unknown changes coming with Patchwork_9699 need to be verified
manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_9699, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
External URL: https://patchwork.freedesktop.org/api/1.0/series/46742/revisions/1/mbox/
== Possible new issues ==
Here are the unknown changes that may have been introduced in Patchwork_9699:
=== IGT changes ===
==== Warnings ====
igt@gem_exec_gttfill@basic:
fi-pnv-d510: PASS -> SKIP
== Known issues ==
Here are the changes found in Patchwork_9699 that come from known issues:
=== IGT changes ===
==== Issues hit ====
igt@debugfs_test@read_all_entries:
fi-snb-2520m: PASS -> INCOMPLETE (fdo#103713)
==== Possible fixes ====
igt@drv_selftest@live_hangcheck:
fi-skl-guc: DMESG-FAIL (fdo#107174) -> PASS
{fi-cfl-8109u}: DMESG-FAIL (fdo#106560) -> PASS
igt@kms_chamelium@dp-crc-fast:
fi-kbl-7500u: FAIL (fdo#103841) -> PASS +1
igt@kms_flip@basic-flip-vs-dpms:
fi-skl-6700hq: DMESG-WARN (fdo#105998) -> PASS
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
fdo#103713 https://bugs.freedesktop.org/show_bug.cgi?id=103713
fdo#103841 https://bugs.freedesktop.org/show_bug.cgi?id=103841
fdo#105998 https://bugs.freedesktop.org/show_bug.cgi?id=105998
fdo#106560 https://bugs.freedesktop.org/show_bug.cgi?id=106560
fdo#107174 https://bugs.freedesktop.org/show_bug.cgi?id=107174
== Participating hosts (46 -> 41) ==
Missing (5): fi-ctg-p8600 fi-ilk-m540 fi-byt-squawks fi-bsw-cyan fi-hsw-4200u
== Build changes ==
* Linux: CI_DRM_4503 -> Patchwork_9699
CI_DRM_4503: 4aa6797dfafaf527949bf55d3c8513c6902dfec2 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_4562: 8781fd89a63eabed9359d02b50583cca67ff3673 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_9699: 7ba6acbd53cb88b3af7163a2d339209f6b3b7fec @ git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
7ba6acbd53cb i915/dp/dsc: Add Rate Control Range Parameter Registers
f6a9fee4d495 i915/dp/dsc: Add Rate Control Buffer Threshold Registers
f7a62fccc3eb i915/dp/dsc: Add DSC PPS register definitions
0ccb8db4366a drm/i915/icl: Add VIDEO_DIP regsiters
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_9699/issues.html
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 15+ messages in thread* ✓ Fi.CI.IGT: success for series starting with [1/4] drm/i915/icl: Add VIDEO_DIP regsiters
2018-07-17 21:10 [PATCH 1/4] drm/i915/icl: Add VIDEO_DIP regsiters Anusha Srivatsa
` (4 preceding siblings ...)
2018-07-17 21:59 ` ✓ Fi.CI.BAT: success " Patchwork
@ 2018-07-18 5:14 ` Patchwork
2018-07-18 18:53 ` [PATCH 1/4] " Manasi Navare
6 siblings, 0 replies; 15+ messages in thread
From: Patchwork @ 2018-07-18 5:14 UTC (permalink / raw)
To: Anusha Srivatsa; +Cc: intel-gfx
== Series Details ==
Series: series starting with [1/4] drm/i915/icl: Add VIDEO_DIP regsiters
URL : https://patchwork.freedesktop.org/series/46742/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_4503_full -> Patchwork_9699_full =
== Summary - WARNING ==
Minor unknown changes coming with Patchwork_9699_full need to be verified
manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_9699_full, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
== Possible new issues ==
Here are the unknown changes that may have been introduced in Patchwork_9699_full:
=== IGT changes ===
==== Warnings ====
igt@gem_exec_schedule@deep-bsd2:
shard-kbl: SKIP -> PASS +2
igt@gem_mocs_settings@mocs-rc6-ctx-render:
shard-kbl: PASS -> SKIP
igt@kms_cursor_crc@cursor-64x64-offscreen:
shard-snb: SKIP -> PASS
igt@kms_frontbuffer_tracking@fbc-2p-primscrn-spr-indfb-draw-render:
shard-hsw: PASS -> SKIP
== Known issues ==
Here are the changes found in Patchwork_9699_full that come from known issues:
=== IGT changes ===
==== Issues hit ====
igt@kms_cursor_legacy@2x-long-cursor-vs-flip-legacy:
shard-hsw: PASS -> FAIL (fdo#105767)
igt@kms_frontbuffer_tracking@fbc-suspend:
shard-kbl: PASS -> INCOMPLETE (fdo#105959, fdo#103665)
igt@kms_setmode@basic:
shard-apl: PASS -> FAIL (fdo#99912)
==== Possible fixes ====
igt@gem_exec_big:
shard-hsw: INCOMPLETE (fdo#103540) -> PASS
shard-snb: INCOMPLETE (fdo#105411) -> PASS
igt@gem_exec_suspend@basic-s3:
shard-apl: FAIL (fdo#103375) -> PASS
igt@kms_flip@flip-vs-expired-vblank-interruptible:
shard-apl: FAIL (fdo#105363, fdo#102887) -> PASS
igt@kms_flip@modeset-vs-vblank-race-interruptible:
shard-hsw: FAIL (fdo#103060) -> PASS
igt@kms_flip@plain-flip-ts-check-interruptible:
shard-glk: FAIL (fdo#100368) -> PASS
fdo#100368 https://bugs.freedesktop.org/show_bug.cgi?id=100368
fdo#102887 https://bugs.freedesktop.org/show_bug.cgi?id=102887
fdo#103060 https://bugs.freedesktop.org/show_bug.cgi?id=103060
fdo#103375 https://bugs.freedesktop.org/show_bug.cgi?id=103375
fdo#103540 https://bugs.freedesktop.org/show_bug.cgi?id=103540
fdo#103665 https://bugs.freedesktop.org/show_bug.cgi?id=103665
fdo#105363 https://bugs.freedesktop.org/show_bug.cgi?id=105363
fdo#105411 https://bugs.freedesktop.org/show_bug.cgi?id=105411
fdo#105767 https://bugs.freedesktop.org/show_bug.cgi?id=105767
fdo#105959 https://bugs.freedesktop.org/show_bug.cgi?id=105959
fdo#99912 https://bugs.freedesktop.org/show_bug.cgi?id=99912
== Participating hosts (5 -> 5) ==
No changes in participating hosts
== Build changes ==
* Linux: CI_DRM_4503 -> Patchwork_9699
CI_DRM_4503: 4aa6797dfafaf527949bf55d3c8513c6902dfec2 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_4562: 8781fd89a63eabed9359d02b50583cca67ff3673 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_9699: 7ba6acbd53cb88b3af7163a2d339209f6b3b7fec @ git://anongit.freedesktop.org/gfx-ci/linux
piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_9699/shards.html
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 15+ messages in thread* Re: [PATCH 1/4] drm/i915/icl: Add VIDEO_DIP regsiters
2018-07-17 21:10 [PATCH 1/4] drm/i915/icl: Add VIDEO_DIP regsiters Anusha Srivatsa
` (5 preceding siblings ...)
2018-07-18 5:14 ` ✓ Fi.CI.IGT: " Patchwork
@ 2018-07-18 18:53 ` Manasi Navare
2018-07-18 20:54 ` Rodrigo Vivi
6 siblings, 1 reply; 15+ messages in thread
From: Manasi Navare @ 2018-07-18 18:53 UTC (permalink / raw)
To: Anusha Srivatsa; +Cc: Jani Nikula, intel-gfx
On Tue, Jul 17, 2018 at 02:10:58PM -0700, Anusha Srivatsa wrote:
> From: "Srivatsa, Anusha" <anusha.srivatsa@intel.com>
>
> The Picture Parameter Set metadata for DSC has to be sent
> to the panel through secondary data packets. Add the error
> correction registers, data registers and control registers
> for the same.
>
> The control registers for transcoders A and B are already
> defined and will be reused for Icelake purpose. This patch adds
> Control register for EDP and transcoder C apart from adding the
> PPS data and error registers.
>
> v2: reuse MMIO_TRANS2 for _PPS_DATA and _PPS_ECC.
> The _MMIO_TRANS2(pipe, reg) macro definition takes care of the eDp case
>
> Cc: Jani Nikula <jani.nikula@intel.com>
> Cc: Ville Syrjala <ville.syrjala@linux.intel.com>
> Cc: Manasi Navare <manasi.d.navare@intel.com>
> Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
Checked against the spec and tested it.
Reviewed-by: Manasi Navare <manasi.d.navare@intel.com>
> ---
> drivers/gpu/drm/i915/i915_reg.h | 23 +++++++++++++++++++++++
> 1 file changed, 23 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 1f222af..23e70a4 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -4605,6 +4605,16 @@ enum {
> #define VIDEO_DIP_ENABLE_GMP_HSW (1 << 4)
> #define VIDEO_DIP_ENABLE_SPD_HSW (1 << 0)
>
> +#define DRM_DIP_ENABLE (1 << 28)
> +#define PSR_VSC_BIT_7_SET (1 << 27)
> +#define VSC_SELECT_MASK (0x3 << 26)
> +#define VSC_SELECT_SHIFT 26
> +#define VSC_DIP_HW_HEA_DATA (0 << 26)
> +#define VSC_DIP_HW_HEA_SW_DATA (1 << 26)
> +#define VSC_DIP_HW_DATA_SW_HEA (2 << 26)
> +#define VSC_DIP_SW_HEA_DATA (3 << 26)
> +#define VDIP_ENABLE_PPS (1 << 24)
> +
> /* Panel power sequencing */
> #define PPS_BASE 0x61200
> #define VLV_PPS_BASE (VLV_DISPLAY_BASE + PPS_BASE)
> @@ -7843,12 +7853,25 @@ enum {
> #define _HSW_VIDEO_DIP_VSC_ECC_B 0x61344
> #define _HSW_VIDEO_DIP_GCP_B 0x61210
>
> +/* Icelake PPS_DATA and _ECC DIP Registers.
> + * These are available for transcoders B,C and eDP.
> + * Adding the _A so as to reuse the _MMIO_TRANS2
> + * definition, with which it offsets to the right location.
> + */
> +
> +#define _ICL_VIDEO_DIP_PPS_DATA_A 0x60350
> +#define _ICL_VIDEO_DIP_PPS_DATA_B 0x61350
> +#define _ICL_VIDEO_DIP_PPS_ECC_A 0x603D4
> +#define _ICL_VIDEO_DIP_PPS_ECC_B 0x613D4
> +
> #define HSW_TVIDEO_DIP_CTL(trans) _MMIO_TRANS2(trans, _HSW_VIDEO_DIP_CTL_A)
> #define HSW_TVIDEO_DIP_AVI_DATA(trans, i) _MMIO_TRANS2(trans, _HSW_VIDEO_DIP_AVI_DATA_A + (i) * 4)
> #define HSW_TVIDEO_DIP_VS_DATA(trans, i) _MMIO_TRANS2(trans, _HSW_VIDEO_DIP_VS_DATA_A + (i) * 4)
> #define HSW_TVIDEO_DIP_SPD_DATA(trans, i) _MMIO_TRANS2(trans, _HSW_VIDEO_DIP_SPD_DATA_A + (i) * 4)
> #define HSW_TVIDEO_DIP_GCP(trans) _MMIO_TRANS2(trans, _HSW_VIDEO_DIP_GCP_A)
> #define HSW_TVIDEO_DIP_VSC_DATA(trans, i) _MMIO_TRANS2(trans, _HSW_VIDEO_DIP_VSC_DATA_A + (i) * 4)
> +#define ICL_VIDEO_DIP_PPS_DATA(trans, i) _MMIO_TRANS2(trans, _ICL_VIDEO_DIP_PPS_DATA_A + (i) * 4)
> +#define ICL_VIDEO_DIP_PPS_ECC(trans, i) _MMIO_TRANS2(trans, _ICL_VIDEO_DIP_PPS_ECC_A + (i) * 4)
>
> #define _HSW_STEREO_3D_CTL_A 0x70020
> #define S3D_ENABLE (1 << 31)
> --
> 2.7.4
>
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 15+ messages in thread* Re: [PATCH 1/4] drm/i915/icl: Add VIDEO_DIP regsiters
2018-07-18 18:53 ` [PATCH 1/4] " Manasi Navare
@ 2018-07-18 20:54 ` Rodrigo Vivi
2018-07-18 22:06 ` Srivatsa, Anusha
0 siblings, 1 reply; 15+ messages in thread
From: Rodrigo Vivi @ 2018-07-18 20:54 UTC (permalink / raw)
To: Manasi Navare; +Cc: Jani Nikula, intel-gfx
On Wed, Jul 18, 2018 at 11:53:54AM -0700, Manasi Navare wrote:
> On Tue, Jul 17, 2018 at 02:10:58PM -0700, Anusha Srivatsa wrote:
> > From: "Srivatsa, Anusha" <anusha.srivatsa@intel.com>
> >
> > The Picture Parameter Set metadata for DSC has to be sent
> > to the panel through secondary data packets. Add the error
> > correction registers, data registers and control registers
> > for the same.
> >
> > The control registers for transcoders A and B are already
> > defined and will be reused for Icelake purpose. This patch adds
> > Control register for EDP and transcoder C apart from adding the
> > PPS data and error registers.
> >
> > v2: reuse MMIO_TRANS2 for _PPS_DATA and _PPS_ECC.
> > The _MMIO_TRANS2(pipe, reg) macro definition takes care of the eDp case
> >
> > Cc: Jani Nikula <jani.nikula@intel.com>
> > Cc: Ville Syrjala <ville.syrjala@linux.intel.com>
> > Cc: Manasi Navare <manasi.d.navare@intel.com>
> > Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
>
> Checked against the spec and tested it.
>
> Reviewed-by: Manasi Navare <manasi.d.navare@intel.com>
>
> > ---
> > drivers/gpu/drm/i915/i915_reg.h | 23 +++++++++++++++++++++++
> > 1 file changed, 23 insertions(+)
> >
> > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> > index 1f222af..23e70a4 100644
> > --- a/drivers/gpu/drm/i915/i915_reg.h
> > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > @@ -4605,6 +4605,16 @@ enum {
> > #define VIDEO_DIP_ENABLE_GMP_HSW (1 << 4)
> > #define VIDEO_DIP_ENABLE_SPD_HSW (1 << 0)
> >
> > +#define DRM_DIP_ENABLE (1 << 28)
> > +#define PSR_VSC_BIT_7_SET (1 << 27)
> > +#define VSC_SELECT_MASK (0x3 << 26)
> > +#define VSC_SELECT_SHIFT 26
> > +#define VSC_DIP_HW_HEA_DATA (0 << 26)
> > +#define VSC_DIP_HW_HEA_SW_DATA (1 << 26)
> > +#define VSC_DIP_HW_DATA_SW_HEA (2 << 26)
> > +#define VSC_DIP_SW_HEA_DATA (3 << 26)
> > +#define VDIP_ENABLE_PPS (1 << 24)
> > +
> > /* Panel power sequencing */
> > #define PPS_BASE 0x61200
> > #define VLV_PPS_BASE (VLV_DISPLAY_BASE + PPS_BASE)
> > @@ -7843,12 +7853,25 @@ enum {
> > #define _HSW_VIDEO_DIP_VSC_ECC_B 0x61344
> > #define _HSW_VIDEO_DIP_GCP_B 0x61210
> >
> > +/* Icelake PPS_DATA and _ECC DIP Registers.
> > + * These are available for transcoders B,C and eDP.
> > + * Adding the _A so as to reuse the _MMIO_TRANS2
> > + * definition, with which it offsets to the right location.
> > + */
> > +
> > +#define _ICL_VIDEO_DIP_PPS_DATA_A 0x60350
> > +#define _ICL_VIDEO_DIP_PPS_DATA_B 0x61350
> > +#define _ICL_VIDEO_DIP_PPS_ECC_A 0x603D4
> > +#define _ICL_VIDEO_DIP_PPS_ECC_B 0x613D4
> > +
> > #define HSW_TVIDEO_DIP_CTL(trans) _MMIO_TRANS2(trans, _HSW_VIDEO_DIP_CTL_A)
> > #define HSW_TVIDEO_DIP_AVI_DATA(trans, i) _MMIO_TRANS2(trans, _HSW_VIDEO_DIP_AVI_DATA_A + (i) * 4)
> > #define HSW_TVIDEO_DIP_VS_DATA(trans, i) _MMIO_TRANS2(trans, _HSW_VIDEO_DIP_VS_DATA_A + (i) * 4)
> > #define HSW_TVIDEO_DIP_SPD_DATA(trans, i) _MMIO_TRANS2(trans, _HSW_VIDEO_DIP_SPD_DATA_A + (i) * 4)
> > #define HSW_TVIDEO_DIP_GCP(trans) _MMIO_TRANS2(trans, _HSW_VIDEO_DIP_GCP_A)
> > #define HSW_TVIDEO_DIP_VSC_DATA(trans, i) _MMIO_TRANS2(trans, _HSW_VIDEO_DIP_VSC_DATA_A + (i) * 4)
> > +#define ICL_VIDEO_DIP_PPS_DATA(trans, i) _MMIO_TRANS2(trans, _ICL_VIDEO_DIP_PPS_DATA_A + (i) * 4)
> > +#define ICL_VIDEO_DIP_PPS_ECC(trans, i) _MMIO_TRANS2(trans, _ICL_VIDEO_DIP_PPS_ECC_A + (i) * 4)
need to make checkpatch happy here ^
> >
> > #define _HSW_STEREO_3D_CTL_A 0x70020
> > #define S3D_ENABLE (1 << 31)
> > --
> > 2.7.4
> >
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 15+ messages in thread* Re: [PATCH 1/4] drm/i915/icl: Add VIDEO_DIP regsiters
2018-07-18 20:54 ` Rodrigo Vivi
@ 2018-07-18 22:06 ` Srivatsa, Anusha
2018-07-18 22:34 ` Rodrigo Vivi
0 siblings, 1 reply; 15+ messages in thread
From: Srivatsa, Anusha @ 2018-07-18 22:06 UTC (permalink / raw)
To: Vivi, Rodrigo, Navare, Manasi D
Cc: Nikula, Jani, intel-gfx@lists.freedesktop.org
>-----Original Message-----
>From: Vivi, Rodrigo
>Sent: Wednesday, July 18, 2018 1:54 PM
>To: Navare, Manasi D <manasi.d.navare@intel.com>
>Cc: Srivatsa, Anusha <anusha.srivatsa@intel.com>; Nikula, Jani
><jani.nikula@intel.com>; intel-gfx@lists.freedesktop.org
>Subject: Re: [Intel-gfx] [PATCH 1/4] drm/i915/icl: Add VIDEO_DIP regsiters
>
>On Wed, Jul 18, 2018 at 11:53:54AM -0700, Manasi Navare wrote:
>> On Tue, Jul 17, 2018 at 02:10:58PM -0700, Anusha Srivatsa wrote:
>> > From: "Srivatsa, Anusha" <anusha.srivatsa@intel.com>
>> >
>> > The Picture Parameter Set metadata for DSC has to be sent to the
>> > panel through secondary data packets. Add the error correction
>> > registers, data registers and control registers for the same.
>> >
>> > The control registers for transcoders A and B are already defined
>> > and will be reused for Icelake purpose. This patch adds Control
>> > register for EDP and transcoder C apart from adding the PPS data and
>> > error registers.
>> >
>> > v2: reuse MMIO_TRANS2 for _PPS_DATA and _PPS_ECC.
>> > The _MMIO_TRANS2(pipe, reg) macro definition takes care of the eDp
>> > case
>> >
>> > Cc: Jani Nikula <jani.nikula@intel.com>
>> > Cc: Ville Syrjala <ville.syrjala@linux.intel.com>
>> > Cc: Manasi Navare <manasi.d.navare@intel.com>
>> > Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
>>
>> Checked against the spec and tested it.
>>
>> Reviewed-by: Manasi Navare <manasi.d.navare@intel.com>
>>
>> > ---
>> > drivers/gpu/drm/i915/i915_reg.h | 23 +++++++++++++++++++++++
>> > 1 file changed, 23 insertions(+)
>> >
>> > diff --git a/drivers/gpu/drm/i915/i915_reg.h
>> > b/drivers/gpu/drm/i915/i915_reg.h index 1f222af..23e70a4 100644
>> > --- a/drivers/gpu/drm/i915/i915_reg.h
>> > +++ b/drivers/gpu/drm/i915/i915_reg.h
>> > @@ -4605,6 +4605,16 @@ enum {
>> > #define VIDEO_DIP_ENABLE_GMP_HSW (1 << 4)
>> > #define VIDEO_DIP_ENABLE_SPD_HSW (1 << 0)
>> >
>> > +#define DRM_DIP_ENABLE (1 << 28)
>> > +#define PSR_VSC_BIT_7_SET (1 << 27)
>> > +#define VSC_SELECT_MASK (0x3 << 26)
>> > +#define VSC_SELECT_SHIFT 26
>> > +#define VSC_DIP_HW_HEA_DATA (0 << 26)
>> > +#define VSC_DIP_HW_HEA_SW_DATA (1 << 26)
>> > +#define VSC_DIP_HW_DATA_SW_HEA (2 << 26)
>> > +#define VSC_DIP_SW_HEA_DATA (3 << 26)
>> > +#define VDIP_ENABLE_PPS (1 << 24)
>> > +
>> > /* Panel power sequencing */
>> > #define PPS_BASE 0x61200
>> > #define VLV_PPS_BASE (VLV_DISPLAY_BASE +
>PPS_BASE)
>> > @@ -7843,12 +7853,25 @@ enum {
>> > #define _HSW_VIDEO_DIP_VSC_ECC_B 0x61344
>> > #define _HSW_VIDEO_DIP_GCP_B 0x61210
>> >
>> > +/* Icelake PPS_DATA and _ECC DIP Registers.
>> > + * These are available for transcoders B,C and eDP.
>> > + * Adding the _A so as to reuse the _MMIO_TRANS2
>> > + * definition, with which it offsets to the right location.
>> > + */
>> > +
>> > +#define _ICL_VIDEO_DIP_PPS_DATA_A 0x60350
>> > +#define _ICL_VIDEO_DIP_PPS_DATA_B 0x61350
>> > +#define _ICL_VIDEO_DIP_PPS_ECC_A 0x603D4
>> > +#define _ICL_VIDEO_DIP_PPS_ECC_B 0x613D4
>> > +
>> > #define HSW_TVIDEO_DIP_CTL(trans) _MMIO_TRANS2(trans,
>_HSW_VIDEO_DIP_CTL_A)
>> > #define HSW_TVIDEO_DIP_AVI_DATA(trans, i) _MMIO_TRANS2(trans,
>_HSW_VIDEO_DIP_AVI_DATA_A + (i) * 4)
>> > #define HSW_TVIDEO_DIP_VS_DATA(trans, i) _MMIO_TRANS2(trans,
>_HSW_VIDEO_DIP_VS_DATA_A + (i) * 4)
>> > #define HSW_TVIDEO_DIP_SPD_DATA(trans, i) _MMIO_TRANS2(trans,
>_HSW_VIDEO_DIP_SPD_DATA_A + (i) * 4)
>> > #define HSW_TVIDEO_DIP_GCP(trans) _MMIO_TRANS2(trans,
>_HSW_VIDEO_DIP_GCP_A)
>> > #define HSW_TVIDEO_DIP_VSC_DATA(trans, i) _MMIO_TRANS2(trans,
>_HSW_VIDEO_DIP_VSC_DATA_A + (i) * 4)
>> > +#define ICL_VIDEO_DIP_PPS_DATA(trans, i) _MMIO_TRANS2(trans,
>_ICL_VIDEO_DIP_PPS_DATA_A + (i) * 4)
>> > +#define ICL_VIDEO_DIP_PPS_ECC(trans, i) _MMIO_TRANS2(trans,
>_ICL_VIDEO_DIP_PPS_ECC_A + (i) * 4)
>
>need to make checkpatch happy here ^
Rodrigo,
There are actually some lines right above this that are over 80 characters....
I thought splitting the line might not look good here. :(
Anusha
>> >
>> > #define _HSW_STEREO_3D_CTL_A 0x70020
>> > #define S3D_ENABLE (1 << 31)
>> > --
>> > 2.7.4
>> >
>> _______________________________________________
>> Intel-gfx mailing list
>> Intel-gfx@lists.freedesktop.org
>> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 15+ messages in thread* Re: [PATCH 1/4] drm/i915/icl: Add VIDEO_DIP regsiters
2018-07-18 22:06 ` Srivatsa, Anusha
@ 2018-07-18 22:34 ` Rodrigo Vivi
2018-07-19 0:51 ` Rodrigo Vivi
0 siblings, 1 reply; 15+ messages in thread
From: Rodrigo Vivi @ 2018-07-18 22:34 UTC (permalink / raw)
To: Srivatsa, Anusha; +Cc: Nikula, Jani, intel-gfx@lists.freedesktop.org
On Wed, Jul 18, 2018 at 03:06:45PM -0700, Srivatsa, Anusha wrote:
>
>
> >-----Original Message-----
> >From: Vivi, Rodrigo
> >Sent: Wednesday, July 18, 2018 1:54 PM
> >To: Navare, Manasi D <manasi.d.navare@intel.com>
> >Cc: Srivatsa, Anusha <anusha.srivatsa@intel.com>; Nikula, Jani
> ><jani.nikula@intel.com>; intel-gfx@lists.freedesktop.org
> >Subject: Re: [Intel-gfx] [PATCH 1/4] drm/i915/icl: Add VIDEO_DIP regsiters
> >
> >On Wed, Jul 18, 2018 at 11:53:54AM -0700, Manasi Navare wrote:
> >> On Tue, Jul 17, 2018 at 02:10:58PM -0700, Anusha Srivatsa wrote:
> >> > From: "Srivatsa, Anusha" <anusha.srivatsa@intel.com>
> >> >
> >> > The Picture Parameter Set metadata for DSC has to be sent to the
> >> > panel through secondary data packets. Add the error correction
> >> > registers, data registers and control registers for the same.
> >> >
> >> > The control registers for transcoders A and B are already defined
> >> > and will be reused for Icelake purpose. This patch adds Control
> >> > register for EDP and transcoder C apart from adding the PPS data and
> >> > error registers.
> >> >
> >> > v2: reuse MMIO_TRANS2 for _PPS_DATA and _PPS_ECC.
> >> > The _MMIO_TRANS2(pipe, reg) macro definition takes care of the eDp
> >> > case
> >> >
> >> > Cc: Jani Nikula <jani.nikula@intel.com>
> >> > Cc: Ville Syrjala <ville.syrjala@linux.intel.com>
> >> > Cc: Manasi Navare <manasi.d.navare@intel.com>
> >> > Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
> >>
> >> Checked against the spec and tested it.
> >>
> >> Reviewed-by: Manasi Navare <manasi.d.navare@intel.com>
> >>
> >> > ---
> >> > drivers/gpu/drm/i915/i915_reg.h | 23 +++++++++++++++++++++++
> >> > 1 file changed, 23 insertions(+)
> >> >
> >> > diff --git a/drivers/gpu/drm/i915/i915_reg.h
> >> > b/drivers/gpu/drm/i915/i915_reg.h index 1f222af..23e70a4 100644
> >> > --- a/drivers/gpu/drm/i915/i915_reg.h
> >> > +++ b/drivers/gpu/drm/i915/i915_reg.h
> >> > @@ -4605,6 +4605,16 @@ enum {
> >> > #define VIDEO_DIP_ENABLE_GMP_HSW (1 << 4)
> >> > #define VIDEO_DIP_ENABLE_SPD_HSW (1 << 0)
> >> >
> >> > +#define DRM_DIP_ENABLE (1 << 28)
> >> > +#define PSR_VSC_BIT_7_SET (1 << 27)
> >> > +#define VSC_SELECT_MASK (0x3 << 26)
> >> > +#define VSC_SELECT_SHIFT 26
> >> > +#define VSC_DIP_HW_HEA_DATA (0 << 26)
> >> > +#define VSC_DIP_HW_HEA_SW_DATA (1 << 26)
> >> > +#define VSC_DIP_HW_DATA_SW_HEA (2 << 26)
> >> > +#define VSC_DIP_SW_HEA_DATA (3 << 26)
> >> > +#define VDIP_ENABLE_PPS (1 << 24)
> >> > +
> >> > /* Panel power sequencing */
> >> > #define PPS_BASE 0x61200
> >> > #define VLV_PPS_BASE (VLV_DISPLAY_BASE +
> >PPS_BASE)
> >> > @@ -7843,12 +7853,25 @@ enum {
> >> > #define _HSW_VIDEO_DIP_VSC_ECC_B 0x61344
> >> > #define _HSW_VIDEO_DIP_GCP_B 0x61210
> >> >
> >> > +/* Icelake PPS_DATA and _ECC DIP Registers.
> >> > + * These are available for transcoders B,C and eDP.
> >> > + * Adding the _A so as to reuse the _MMIO_TRANS2
> >> > + * definition, with which it offsets to the right location.
> >> > + */
> >> > +
> >> > +#define _ICL_VIDEO_DIP_PPS_DATA_A 0x60350
> >> > +#define _ICL_VIDEO_DIP_PPS_DATA_B 0x61350
> >> > +#define _ICL_VIDEO_DIP_PPS_ECC_A 0x603D4
> >> > +#define _ICL_VIDEO_DIP_PPS_ECC_B 0x613D4
> >> > +
> >> > #define HSW_TVIDEO_DIP_CTL(trans) _MMIO_TRANS2(trans,
> >_HSW_VIDEO_DIP_CTL_A)
> >> > #define HSW_TVIDEO_DIP_AVI_DATA(trans, i) _MMIO_TRANS2(trans,
> >_HSW_VIDEO_DIP_AVI_DATA_A + (i) * 4)
> >> > #define HSW_TVIDEO_DIP_VS_DATA(trans, i) _MMIO_TRANS2(trans,
> >_HSW_VIDEO_DIP_VS_DATA_A + (i) * 4)
> >> > #define HSW_TVIDEO_DIP_SPD_DATA(trans, i) _MMIO_TRANS2(trans,
> >_HSW_VIDEO_DIP_SPD_DATA_A + (i) * 4)
> >> > #define HSW_TVIDEO_DIP_GCP(trans) _MMIO_TRANS2(trans,
> >_HSW_VIDEO_DIP_GCP_A)
> >> > #define HSW_TVIDEO_DIP_VSC_DATA(trans, i) _MMIO_TRANS2(trans,
> >_HSW_VIDEO_DIP_VSC_DATA_A + (i) * 4)
> >> > +#define ICL_VIDEO_DIP_PPS_DATA(trans, i) _MMIO_TRANS2(trans,
> >_ICL_VIDEO_DIP_PPS_DATA_A + (i) * 4)
> >> > +#define ICL_VIDEO_DIP_PPS_ECC(trans, i) _MMIO_TRANS2(trans,
> >_ICL_VIDEO_DIP_PPS_ECC_A + (i) * 4)
> >
> >need to make checkpatch happy here ^
>
> Rodrigo,
> There are actually some lines right above this that are over 80 characters....
> I thought splitting the line might not look good here. :(
This is not what checkpatch complained about
check your tabs vs spaces..
>
>
> Anusha
> >> >
> >> > #define _HSW_STEREO_3D_CTL_A 0x70020
> >> > #define S3D_ENABLE (1 << 31)
> >> > --
> >> > 2.7.4
> >> >
> >> _______________________________________________
> >> Intel-gfx mailing list
> >> Intel-gfx@lists.freedesktop.org
> >> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 15+ messages in thread* Re: [PATCH 1/4] drm/i915/icl: Add VIDEO_DIP regsiters
2018-07-18 22:34 ` Rodrigo Vivi
@ 2018-07-19 0:51 ` Rodrigo Vivi
0 siblings, 0 replies; 15+ messages in thread
From: Rodrigo Vivi @ 2018-07-19 0:51 UTC (permalink / raw)
To: Srivatsa, Anusha; +Cc: Nikula, Jani, intel-gfx@lists.freedesktop.org
On Wed, Jul 18, 2018 at 03:34:05PM -0700, Rodrigo Vivi wrote:
> On Wed, Jul 18, 2018 at 03:06:45PM -0700, Srivatsa, Anusha wrote:
> >
> >
> > >-----Original Message-----
> > >From: Vivi, Rodrigo
> > >Sent: Wednesday, July 18, 2018 1:54 PM
> > >To: Navare, Manasi D <manasi.d.navare@intel.com>
> > >Cc: Srivatsa, Anusha <anusha.srivatsa@intel.com>; Nikula, Jani
> > ><jani.nikula@intel.com>; intel-gfx@lists.freedesktop.org
> > >Subject: Re: [Intel-gfx] [PATCH 1/4] drm/i915/icl: Add VIDEO_DIP regsiters
> > >
> > >On Wed, Jul 18, 2018 at 11:53:54AM -0700, Manasi Navare wrote:
> > >> On Tue, Jul 17, 2018 at 02:10:58PM -0700, Anusha Srivatsa wrote:
> > >> > From: "Srivatsa, Anusha" <anusha.srivatsa@intel.com>
> > >> >
> > >> > The Picture Parameter Set metadata for DSC has to be sent to the
> > >> > panel through secondary data packets. Add the error correction
> > >> > registers, data registers and control registers for the same.
> > >> >
> > >> > The control registers for transcoders A and B are already defined
> > >> > and will be reused for Icelake purpose. This patch adds Control
> > >> > register for EDP and transcoder C apart from adding the PPS data and
> > >> > error registers.
> > >> >
> > >> > v2: reuse MMIO_TRANS2 for _PPS_DATA and _PPS_ECC.
> > >> > The _MMIO_TRANS2(pipe, reg) macro definition takes care of the eDp
> > >> > case
> > >> >
> > >> > Cc: Jani Nikula <jani.nikula@intel.com>
> > >> > Cc: Ville Syrjala <ville.syrjala@linux.intel.com>
> > >> > Cc: Manasi Navare <manasi.d.navare@intel.com>
> > >> > Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
> > >>
> > >> Checked against the spec and tested it.
> > >>
> > >> Reviewed-by: Manasi Navare <manasi.d.navare@intel.com>
> > >>
> > >> > ---
> > >> > drivers/gpu/drm/i915/i915_reg.h | 23 +++++++++++++++++++++++
> > >> > 1 file changed, 23 insertions(+)
> > >> >
> > >> > diff --git a/drivers/gpu/drm/i915/i915_reg.h
> > >> > b/drivers/gpu/drm/i915/i915_reg.h index 1f222af..23e70a4 100644
> > >> > --- a/drivers/gpu/drm/i915/i915_reg.h
> > >> > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > >> > @@ -4605,6 +4605,16 @@ enum {
> > >> > #define VIDEO_DIP_ENABLE_GMP_HSW (1 << 4)
> > >> > #define VIDEO_DIP_ENABLE_SPD_HSW (1 << 0)
> > >> >
> > >> > +#define DRM_DIP_ENABLE (1 << 28)
> > >> > +#define PSR_VSC_BIT_7_SET (1 << 27)
> > >> > +#define VSC_SELECT_MASK (0x3 << 26)
> > >> > +#define VSC_SELECT_SHIFT 26
> > >> > +#define VSC_DIP_HW_HEA_DATA (0 << 26)
> > >> > +#define VSC_DIP_HW_HEA_SW_DATA (1 << 26)
> > >> > +#define VSC_DIP_HW_DATA_SW_HEA (2 << 26)
> > >> > +#define VSC_DIP_SW_HEA_DATA (3 << 26)
> > >> > +#define VDIP_ENABLE_PPS (1 << 24)
> > >> > +
> > >> > /* Panel power sequencing */
> > >> > #define PPS_BASE 0x61200
> > >> > #define VLV_PPS_BASE (VLV_DISPLAY_BASE +
> > >PPS_BASE)
> > >> > @@ -7843,12 +7853,25 @@ enum {
> > >> > #define _HSW_VIDEO_DIP_VSC_ECC_B 0x61344
> > >> > #define _HSW_VIDEO_DIP_GCP_B 0x61210
> > >> >
> > >> > +/* Icelake PPS_DATA and _ECC DIP Registers.
> > >> > + * These are available for transcoders B,C and eDP.
> > >> > + * Adding the _A so as to reuse the _MMIO_TRANS2
> > >> > + * definition, with which it offsets to the right location.
> > >> > + */
> > >> > +
> > >> > +#define _ICL_VIDEO_DIP_PPS_DATA_A 0x60350
> > >> > +#define _ICL_VIDEO_DIP_PPS_DATA_B 0x61350
> > >> > +#define _ICL_VIDEO_DIP_PPS_ECC_A 0x603D4
> > >> > +#define _ICL_VIDEO_DIP_PPS_ECC_B 0x613D4
> > >> > +
> > >> > #define HSW_TVIDEO_DIP_CTL(trans) _MMIO_TRANS2(trans,
> > >_HSW_VIDEO_DIP_CTL_A)
> > >> > #define HSW_TVIDEO_DIP_AVI_DATA(trans, i) _MMIO_TRANS2(trans,
> > >_HSW_VIDEO_DIP_AVI_DATA_A + (i) * 4)
> > >> > #define HSW_TVIDEO_DIP_VS_DATA(trans, i) _MMIO_TRANS2(trans,
> > >_HSW_VIDEO_DIP_VS_DATA_A + (i) * 4)
> > >> > #define HSW_TVIDEO_DIP_SPD_DATA(trans, i) _MMIO_TRANS2(trans,
> > >_HSW_VIDEO_DIP_SPD_DATA_A + (i) * 4)
> > >> > #define HSW_TVIDEO_DIP_GCP(trans) _MMIO_TRANS2(trans,
> > >_HSW_VIDEO_DIP_GCP_A)
> > >> > #define HSW_TVIDEO_DIP_VSC_DATA(trans, i) _MMIO_TRANS2(trans,
> > >_HSW_VIDEO_DIP_VSC_DATA_A + (i) * 4)
> > >> > +#define ICL_VIDEO_DIP_PPS_DATA(trans, i) _MMIO_TRANS2(trans,
> > >_ICL_VIDEO_DIP_PPS_DATA_A + (i) * 4)
> > >> > +#define ICL_VIDEO_DIP_PPS_ECC(trans, i) _MMIO_TRANS2(trans,
> > >_ICL_VIDEO_DIP_PPS_ECC_A + (i) * 4)
> > >
> > >need to make checkpatch happy here ^
> >
> > Rodrigo,
> > There are actually some lines right above this that are over 80 characters....
> > I thought splitting the line might not look good here. :(
>
> This is not what checkpatch complained about
> check your tabs vs spaces..
please accept my apologies. I got confused by my mutt here
and misread the checkpatch report.
pushed to dinq. Thanks for patches and reviews.
>
> >
> >
> > Anusha
> > >> >
> > >> > #define _HSW_STEREO_3D_CTL_A 0x70020
> > >> > #define S3D_ENABLE (1 << 31)
> > >> > --
> > >> > 2.7.4
> > >> >
> > >> _______________________________________________
> > >> Intel-gfx mailing list
> > >> Intel-gfx@lists.freedesktop.org
> > >> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
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