From: Azhar Shaikh <azhar.shaikh@intel.com>
To: intel-gfx@lists.freedesktop.org
Cc: dhinakaran.pandiyan@intel.com
Subject: [PATCH v4] drm/i915/psr: Add PSR mode/revision to debugfs
Date: Wed, 22 Aug 2018 10:23:48 -0700 [thread overview]
Message-ID: <1534958628-193724-1-git-send-email-azhar.shaikh@intel.com> (raw)
Log the PSR mode/revision (PSR1 or PSR2) in the debugfs file
i915_edp_psr_status.
Suggested-by: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
Signed-off-by: Azhar Shaikh <azhar.shaikh@intel.com>
---
Changes in v4:
- Fix the rebase error in v3 of adding typecast to bool
- in i915_edp_psr_status(), which is not needed
Changes in v3:
- rebased
Changes in v2:
- Fix checkpatch warning.
- Add Reviewed-by: from v1
drivers/gpu/drm/i915/i915_debugfs.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
index 26b7e5276b15..544ec5cdfe9f 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -2708,6 +2708,8 @@ static int i915_edp_psr_status(struct seq_file *m, void *data)
intel_runtime_pm_get(dev_priv);
mutex_lock(&dev_priv->psr.lock);
+ seq_printf(m, "PSR mode: %s\n",
+ dev_priv->psr.psr2_enabled ? "PSR2" : "PSR1");
seq_printf(m, "Enabled: %s\n", yesno(dev_priv->psr.enabled));
seq_printf(m, "Busy frontbuffer bits: 0x%03x\n",
dev_priv->psr.busy_frontbuffer_bits);
--
1.9.1
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next reply other threads:[~2018-08-22 17:23 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-08-22 17:23 Azhar Shaikh [this message]
2018-08-22 18:32 ` [PATCH v4] drm/i915/psr: Add PSR mode/revision to debugfs Dhinakaran Pandiyan
2018-08-22 23:50 ` Dhinakaran Pandiyan
2018-08-22 22:23 ` ✓ Fi.CI.BAT: success for drm/i915/psr: Add PSR mode/revision to debugfs (rev4) Patchwork
2018-08-22 23:11 ` ✓ Fi.CI.IGT: " Patchwork
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