From: raviraj.p.sitaram@intel.com
To: intel-gfx@lists.freedesktop.org
Subject: [PATCH] drm/i915/chv: Update csc coefficient matrix during modeset
Date: Mon, 10 Sep 2018 18:31:22 +0530 [thread overview]
Message-ID: <1536584482-12894-1-git-send-email-raviraj.p.sitaram@intel.com> (raw)
From: P Raviraj Sitaram <raviraj.p.sitaram@intel.com>
During modeset, previously configured csc coefficient matrix,if any, will
not persist. This can result in blank screen as csc mode will be programmed
while loading LUT but csc coefficient matrix remains unprogrammed.
Signed-off-by: P Raviraj Sitaram <raviraj.p.sitaram@intel.com>
---
drivers/gpu/drm/i915/intel_display.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index b2bab57cd113..5029c0daa994 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -6014,6 +6014,9 @@ static void valleyview_crtc_enable(struct intel_crtc_state *pipe_config,
i9xx_set_pipeconf(intel_crtc);
+ if (IS_CHERRYVIEW(dev_priv))
+ intel_color_set_csc(&pipe_config->base);
+
intel_crtc->active = true;
intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
--
2.7.4
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next reply other threads:[~2018-09-10 13:08 UTC|newest]
Thread overview: 3+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-09-10 13:01 raviraj.p.sitaram [this message]
2018-09-10 13:42 ` [PATCH] drm/i915/chv: Update csc coefficient matrix during modeset Ville Syrjälä
2018-09-10 13:52 ` [PATCH v10 0/8] YCBCR 4:2:0/4:4:4 output support for LSPCON Vania Toperich
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