* [PATCH] drm/i915/chv: Update csc coefficient matrix during modeset
@ 2018-09-10 13:01 raviraj.p.sitaram
2018-09-10 13:42 ` Ville Syrjälä
0 siblings, 1 reply; 3+ messages in thread
From: raviraj.p.sitaram @ 2018-09-10 13:01 UTC (permalink / raw)
To: intel-gfx
From: P Raviraj Sitaram <raviraj.p.sitaram@intel.com>
During modeset, previously configured csc coefficient matrix,if any, will
not persist. This can result in blank screen as csc mode will be programmed
while loading LUT but csc coefficient matrix remains unprogrammed.
Signed-off-by: P Raviraj Sitaram <raviraj.p.sitaram@intel.com>
---
drivers/gpu/drm/i915/intel_display.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index b2bab57cd113..5029c0daa994 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -6014,6 +6014,9 @@ static void valleyview_crtc_enable(struct intel_crtc_state *pipe_config,
i9xx_set_pipeconf(intel_crtc);
+ if (IS_CHERRYVIEW(dev_priv))
+ intel_color_set_csc(&pipe_config->base);
+
intel_crtc->active = true;
intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
--
2.7.4
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^ permalink raw reply related [flat|nested] 3+ messages in thread
* Re: [PATCH] drm/i915/chv: Update csc coefficient matrix during modeset
2018-09-10 13:01 [PATCH] drm/i915/chv: Update csc coefficient matrix during modeset raviraj.p.sitaram
@ 2018-09-10 13:42 ` Ville Syrjälä
2018-09-10 13:52 ` [PATCH v10 0/8] YCBCR 4:2:0/4:4:4 output support for LSPCON Vania Toperich
0 siblings, 1 reply; 3+ messages in thread
From: Ville Syrjälä @ 2018-09-10 13:42 UTC (permalink / raw)
To: raviraj.p.sitaram; +Cc: intel-gfx
On Mon, Sep 10, 2018 at 06:31:22PM +0530, raviraj.p.sitaram@intel.com wrote:
> From: P Raviraj Sitaram <raviraj.p.sitaram@intel.com>
>
> During modeset, previously configured csc coefficient matrix,if any, will
> not persist. This can result in blank screen as csc mode will be programmed
> while loading LUT but csc coefficient matrix remains unprogrammed.
>
> Signed-off-by: P Raviraj Sitaram <raviraj.p.sitaram@intel.com>
> ---
> drivers/gpu/drm/i915/intel_display.c | 3 +++
> 1 file changed, 3 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index b2bab57cd113..5029c0daa994 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -6014,6 +6014,9 @@ static void valleyview_crtc_enable(struct intel_crtc_state *pipe_config,
>
> i9xx_set_pipeconf(intel_crtc);
>
> + if (IS_CHERRYVIEW(dev_priv))
> + intel_color_set_csc(&pipe_config->base);
> +
No need for the platform check.
> intel_crtc->active = true;
>
> intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
> --
> 2.7.4
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Ville Syrjälä
Intel
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^ permalink raw reply [flat|nested] 3+ messages in thread
* Re: [PATCH v10 0/8] YCBCR 4:2:0/4:4:4 output support for LSPCON
2018-09-10 13:42 ` Ville Syrjälä
@ 2018-09-10 13:52 ` Vania Toperich
0 siblings, 0 replies; 3+ messages in thread
From: Vania Toperich @ 2018-09-10 13:52 UTC (permalink / raw)
To: Ville Syrjälä; +Cc: intel-gfx@lists.freedesktop.org
[-- Attachment #1.1.1: Type: text/plain, Size: 2799 bytes --]
tested-by: Vania Toperich <Vania@bergehenegouwen.com<mailto:Vania@bergehenegouwen.com>>
This patch series does the following:
- Adds concept of CRTC output format, which indicates if a CRTC is
driving RGB/YCBCR4:4:4/YCBCR4:2:0 or other outputs.
- Sets RGB as default output for all displays.
- Enables YCBCR4:4:4/4:2:0 outputs for LSPCON displays
- Drives these outputs on LSPCON using this CRTC output framework.
Sharma, Shashank (2):
drm/i915: Check LSPCON vendor OUI
drm/i915: Write AVI infoframes for MCA LSPCON
Shashank Sharma (6):
drm/i915: Introduce CRTC output format
drm/i915: Add CRTC output format YCBCR 4:2:0
drm/i915: Add CRTC output format YCBCR 4:4:4
drm/i915: Add AVI infoframe support for LSPCON
drm/i915: Write AVI infoframes for Parade LSPCON
drm/i915: Add YCBCR 4:2:0/4:4:4 support for LSPCON
drivers/gpu/drm/i915/i915_reg.h | 2 +
drivers/gpu/drm/i915/intel_color.c | 3 +-
drivers/gpu/drm/i915/intel_crt.c | 3 +
drivers/gpu/drm/i915/intel_ddi.c | 28 ++-
drivers/gpu/drm/i915/intel_display.c | 104 ++++++++---
drivers/gpu/drm/i915/intel_dp.c | 5 +
drivers/gpu/drm/i915/intel_dp_mst.c | 1 +
drivers/gpu/drm/i915/intel_drv.h | 39 +++-
drivers/gpu/drm/i915/intel_dvo.c | 1 +
drivers/gpu/drm/i915/intel_hdmi.c | 24 ++-
drivers/gpu/drm/i915/intel_lspcon.c | 348 +++++++++++++++++++++++++++++++++--
drivers/gpu/drm/i915/intel_lvds.c | 2 +
drivers/gpu/drm/i915/intel_panel.c | 2 +-
drivers/gpu/drm/i915/intel_sdvo.c | 1 +
drivers/gpu/drm/i915/intel_tv.c | 1 +
drivers/gpu/drm/i915/vlv_dsi.c | 1 +
16 files changed, 507 insertions(+), 58 deletions(-)
--
2.7.4
Vania Toperich
IT Specialist
[cid:imaged8560e.PNG@55e6a927.4c8f743d] <http://vbhi.com>
T: <tel:> , M: +31 6 15097042<tel:+31%206%2015097042>
<mailto:>Vania@bergehenegouwen.com<mailto:Vania@bergehenegouwen.com>
vbhi.com<http://vbhi.com>
Pieter Braaijweg 1, 1114 AJ Amsterdam-Duivendrecht
T: +31 20 7993700<tel:+31207993700>, F: +31 20 8907777<tel:+31208907777>, COC: Leiden 28065487, Privacy statement<https://vbhi.com/privacy/>
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_______________________________________________
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
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2018-09-10 13:01 [PATCH] drm/i915/chv: Update csc coefficient matrix during modeset raviraj.p.sitaram
2018-09-10 13:42 ` Ville Syrjälä
2018-09-10 13:52 ` [PATCH v10 0/8] YCBCR 4:2:0/4:4:4 output support for LSPCON Vania Toperich
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