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mx.microsoft.com 1; spf=pass smtp.mailfrom=intel.com; dmarc=pass action=none header.from=intel.com; dkim=pass header.d=intel.com; arc=none Authentication-Results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=intel.com; Received: from PH8PR11MB8287.namprd11.prod.outlook.com (2603:10b6:510:1c7::14) by IA1PR11MB6290.namprd11.prod.outlook.com (2603:10b6:208:3e6::13) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.8356.13; Wed, 15 Jan 2025 19:41:11 +0000 Received: from PH8PR11MB8287.namprd11.prod.outlook.com ([fe80::7e8b:2e5:8ce4:2350]) by PH8PR11MB8287.namprd11.prod.outlook.com ([fe80::7e8b:2e5:8ce4:2350%4]) with mapi id 15.20.8335.017; Wed, 15 Jan 2025 19:41:11 +0000 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable In-Reply-To: <173695792830.3159.388878827702803545@intel.com> References: <20250113204815.114019-1-gustavo.sousa@intel.com> <87msfth14h.fsf@intel.com> <173687228001.2823.13065824358956469360@intel.com> <173694505428.3159.15238384116175670777@intel.com> <173695792830.3159.388878827702803545@intel.com> Subject: Re: [PATCH v5] drm/i915/cmtg: Disable the CMTG From: Gustavo Sousa CC: Jani Nikula , , To: Ville =?utf-8?b?U3lyasOkbMOk?= Date: Wed, 15 Jan 2025 16:41:05 -0300 Message-ID: <173697006552.3159.7695562530356807466@intel.com> User-Agent: alot/0.12.dev27+gd21c920b07eb X-ClientProxiedBy: MW4PR04CA0280.namprd04.prod.outlook.com (2603:10b6:303:89::15) To PH8PR11MB8287.namprd11.prod.outlook.com (2603:10b6:510:1c7::14) MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: PH8PR11MB8287:EE_|IA1PR11MB6290:EE_ X-MS-Office365-Filtering-Correlation-Id: 5fdd02a3-8ea2-4dbd-85ad-08dd359c907f X-LD-Processed: 46c98d88-e344-4ed4-8496-4ed7712e255d,ExtAddr X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|376014|1800799024|366016; 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Because our dr= iver >>> >> >> doesn't currently implement any CMTG sequences, the CMTG ends up = still >>> >> >> enabled after our driver takes over. >>> >> >> >>> >> >> We need to make sure that the CMTG is not enabled if we are not g= oing to >>> >> >> use it. For that, let's add a partial implementation in our drive= r that >>> >> >> only cares about disabling the CMTG if it was found enabled durin= g >>> >> >> initial hardware readout. In the future, we can also implement se= quences >>> >> >> for enabling CMTG if that becomes a needed feature. >>> >> > >>> >> >Doesn't this patch disable the CRTC, not the CMTG? >>> >>=20 >>> >> It disables the CMTG and that's it for LNL and PTL. >>> >>=20 >>> >> For platforms prior to LNL, disabling the CMTG requires a modeset; >>> >> specifically for those, the CRTC is also disabled during the >>> >> sanitization process (not sure if there is a clean way of forcing a >>> >> modeset from the sanitization routine). >>> > >>> >I'm not sure why this whole global state stuff is needed here. >>> >It seems to me that this should be handled more or less the same >>> >as port sync. Ie: >>> > >>> >- track the cmtg state in intel_crtc_state >>>=20 >>> The main reasons I implemented CMTG state as a global state were that >>> CMTG is not a exactly per-pipe thing and it could affect multiple pipes >>> (A and B), at least not on pre-LNL platforms. >> >>I suppose. But it doesn't seem to be fully really independent >>thing either especially given the dependency to the port PLL >>and such, and that's all handled per-pipe. > >To make matters worse, it is possible for CMTG A being driven by PHY B >and vice-versa. So... I'm trying to come up with a way to handle CMTG state as part of the intel_crtc_state. I have some questions that I was hoping you could help me with... 1) For those pre-LNL platforms that have a single CMTG, what would be your suggestion? I was thinking about keeping the state on pipe A's intel_crtc_state, bu= t then how to handle when pipe B's eDP TG is sync'ing with the CMTG? Should we just pull in pipe A's into the atomic state and deal with it? If it is just transcoder B's eDP that is hooked up wit the CMTG, pullin= g pipe A into the atomic state only to handle the CMTG seems rather unnecessary to me. Just accept it and live on? 2) As of LNL, eDP A would sync only with CMTG A and eDP B, with CMTG B. So, I guess having each state in the respective intel_crtc_state seems okay here. If we were to encounter a CMTG dual sync mode (is it fair to consider that a possibility from the GOP?), since only care about disabling of CMTGs for now, I guess we do not need to worry about turning sure the secondary CMTG (which will also be disabled) into primary, right? 3) There is also the case that we could have a CMTG (the single one in pre-LNL; A or B for as of LNL) being clocked by a PHY that is not being used to drive any transcoder. Not sure we could expect that from GOP, but it is nevertheless a valid configuration. We probably wouldn't be able to disable the CMTG during the initial modeset commit in this case, because we need the PHY up before accessing CMTG registers, and such PHY would be already off because of our sanitization routine after hardware state readout. Since our driver doesn't even model the PHY being active and not driving a transcoder (to the best of my knowledge), should we keep this case to be dealt with in the future? -- Gustavo Sousa