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mx.microsoft.com 1; spf=pass smtp.mailfrom=intel.com; dmarc=pass action=none header.from=intel.com; dkim=pass header.d=intel.com; arc=none Authentication-Results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=intel.com; Received: from PH8PR11MB8287.namprd11.prod.outlook.com (2603:10b6:510:1c7::14) by IA0PR11MB7306.namprd11.prod.outlook.com (2603:10b6:208:438::18) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.8398.26; Mon, 3 Feb 2025 13:39:57 +0000 Received: from PH8PR11MB8287.namprd11.prod.outlook.com ([fe80::7e8b:2e5:8ce4:2350]) by PH8PR11MB8287.namprd11.prod.outlook.com ([fe80::7e8b:2e5:8ce4:2350%5]) with mapi id 15.20.8398.021; Mon, 3 Feb 2025 13:39:57 +0000 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable In-Reply-To: References: <20250203085613.236340-1-mohammed.thasleem@intel.com> Subject: Re: [PATCH] drm/i915/dmc: Add debugfs for dc6 counter From: Gustavo Sousa CC: To: Imre Deak , Mohammed Thasleem Date: Mon, 3 Feb 2025 10:39:54 -0300 Message-ID: <173858999403.77773.2784787564938835855@intel.com> User-Agent: alot/0.12.dev27+gd21c920b07eb X-ClientProxiedBy: MW4PR04CA0155.namprd04.prod.outlook.com (2603:10b6:303:85::10) To PH8PR11MB8287.namprd11.prod.outlook.com (2603:10b6:510:1c7::14) MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: PH8PR11MB8287:EE_|IA0PR11MB7306:EE_ X-MS-Office365-Filtering-Correlation-Id: 0b48ac02-e1c7-4672-a696-08dd44583fab X-LD-Processed: 46c98d88-e344-4ed4-8496-4ed7712e255d,ExtAddr X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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>> intel_wakeref_t wakeref; >> + u32 dc6_entry_counter; >> } dmc; >> =20 >> struct { >> diff --git a/drivers/gpu/drm/i915/display/intel_display_power_well.c b/d= rivers/gpu/drm/i915/display/intel_display_power_well.c >> index f45a4f9ba23c..0eb178aa618d 100644 >> --- a/drivers/gpu/drm/i915/display/intel_display_power_well.c >> +++ b/drivers/gpu/drm/i915/display/intel_display_power_well.c >> @@ -869,6 +869,8 @@ void skl_enable_dc6(struct intel_display *display) >> intel_dmc_wl_enable(display, DC_STATE_EN_UPTO_DC6); >> =20 >> gen9_set_dc_state(display, DC_STATE_EN_UPTO_DC6); >> + >> + display->dmc.dc6_entry_counter++; > >AFAIU the goal is to validate that the display HW can reach the DC6 >power state. There is no HW DC6 residency counter (and there wasn't such >a counter earlier either), so an alternative way is required. According >to the HW team the display driver has programmed everything correctly in >order to allow the DC6 power state if the DC5 power state is reached >(indicated by the HW DC5 residency counter incrementing) and DC6 is >enabled by the driver. Yep. That's what I learned as well when looking into this stuff a while ago. > >Based on the above, we'd need a DC6 residency counter maintained by the >driver which is incremented if the DC5 residency counter increments >while DC6 is enabled. The dc6_entry_counter in this patch is not enough >for this, since it doesn't take into account the DC5 residency. While >user space could check both dc6_entry_counter and the DC5 residency, >that check would be racy wrt. the driver enabling/disabling the DC6 >state asynchronously. I'm not sure doing a driver-maintained dc6 entry counter would be something worth implementing. Even if we have successfully entered DC5 and, in theory, DC6 would follow if enabled, this would be a synthetic counter and it could be masking some hardware bug that could be preventing DC6. On the IGT side, we could just skip if we are on a platform that does not support DC6 counters, at least while we do not have a reliable alternative way of checking for DC6. It would be good if we could detect that PG0 was in fact disabled, which I believe is a stronger indication of DC6. -- Gustavo Sousa > >I suppose the driver could take a snapshot of the DC5 residency counter >right after it enables DC6 (dc5_residency_start) and increment the SW >DC6 residency counter right before it disables DC6 or when user space >reads the DC6 counter. So the driver would update the counter at these >two points in the following way: >dc6_residency +=3D dc5_residency_current - dc5_residency_start > >The commit log would need a justification, something along the above >lines. > >> } >> =20 >> void bxt_enable_dc9(struct intel_display *display) >> diff --git a/drivers/gpu/drm/i915/display/intel_dmc.c b/drivers/gpu/drm/= i915/display/intel_dmc.c >> index 221d3abda791..f51bd8e6011d 100644 >> --- a/drivers/gpu/drm/i915/display/intel_dmc.c >> +++ b/drivers/gpu/drm/i915/display/intel_dmc.c >> @@ -1293,6 +1293,7 @@ static int intel_dmc_debugfs_status_show(struct se= q_file *m, void *unused) >> if (i915_mmio_reg_valid(dc6_reg)) >> seq_printf(m, "DC5 -> DC6 count: %d\n", >> intel_de_read(display, dc6_reg)); >> + seq_printf(m, "DC6 entry count: %d\n", display->dmc.dc6_entry_c= ounter); >> =20 >> seq_printf(m, "program base: 0x%08x\n", >> intel_de_read(display, DMC_PROGRAM(dmc->dmc_info[DMC= _FW_MAIN].start_mmioaddr, 0))); >> --=20 >> 2.43.0 >>