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mx.microsoft.com 1; spf=pass smtp.mailfrom=intel.com; dmarc=pass action=none header.from=intel.com; dkim=pass header.d=intel.com; arc=none Authentication-Results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=intel.com; Received: from PH8PR11MB8287.namprd11.prod.outlook.com (2603:10b6:510:1c7::14) by PH7PR11MB7124.namprd11.prod.outlook.com (2603:10b6:510:20f::6) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.8398.24; Mon, 3 Feb 2025 20:40:57 +0000 Received: from PH8PR11MB8287.namprd11.prod.outlook.com ([fe80::7e8b:2e5:8ce4:2350]) by PH8PR11MB8287.namprd11.prod.outlook.com ([fe80::7e8b:2e5:8ce4:2350%5]) with mapi id 15.20.8398.021; Mon, 3 Feb 2025 20:40:57 +0000 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable In-Reply-To: <8102bd56478db361607ddd2848fabf3c4768f3c9.camel@intel.com> References: <173861394843.77773.14213626182925674257@intel.com> <8102bd56478db361607ddd2848fabf3c4768f3c9.camel@intel.com> Subject: Re: [PATCH] drm/i915/dmc: Add debugfs for dc6 counter From: Gustavo Sousa CC: "Thasleem, Mohammed" , "intel-gfx@lists.freedesktop.org" To: "Deak, Imre" , "Vivi, Rodrigo" Date: Mon, 3 Feb 2025 17:40:54 -0300 Message-ID: <173861525455.77773.11090522110857446904@intel.com> User-Agent: alot/0.12.dev27+gd21c920b07eb X-ClientProxiedBy: MW4PR04CA0101.namprd04.prod.outlook.com (2603:10b6:303:83::16) To PH8PR11MB8287.namprd11.prod.outlook.com (2603:10b6:510:1c7::14) MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: PH8PR11MB8287:EE_|PH7PR11MB7124:EE_ X-MS-Office365-Filtering-Correlation-Id: 8c7bc747-b62c-45ea-b6c8-08dd44930fbe X-LD-Processed: 46c98d88-e344-4ed4-8496-4ed7712e255d,ExtAddr X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|366016|376014; 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Some display clock gating etc. >> > > > > > configuration by >> > > > > > the driver could be blocking it. According to the HW team, >> > > > > > DC5 being >> > > > > > entered while DC6 is enabled is a guarantee that DC6 is >> > > > > > allowed from the >> > > > > > display side - i.e. the driver has configured everything >> > > > > > correctly for >> > > > > > that. >> > > > >=20 >> > > > > Fair enough. So IGT test case would check directly if DC5 >> > > > > counter is >> > > > > increasing and DC6 is allowed. >> > > > >=20 >> > > > > Something as simple as this in the kernel code would tell >> > > > > that >> > > > > DC6 is enabled: >> > > > >=20 >> > > > > --- a/drivers/gpu/drm/i915/display/intel_dmc.c >> > > > > +++ b/drivers/gpu/drm/i915/display/intel_dmc.c >> > > > > @@ -1294,6 +1294,10 @@ static int >> > > > > intel_dmc_debugfs_status_show(struct seq_file *m, void >> > > > > *unused) >> > > > > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2= =A0=C2=A0=C2=A0=C2=A0=C2=A0 seq_printf(m, "DC5 -> DC6 count: %d\n", >> > > > > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2= =A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0= =C2=A0=C2=A0=C2=A0 intel_de_read(display, dc6_reg)); >> > > > > =C2=A0 >> > > > > +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 seq_printf(m, "DC6 allowed= : %s\n", >> > > > > str_yes_no((intel_de_read(display, >> > > > > +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2= =A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0= =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2= =A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0= =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 >> > > > > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 DC_STATE_EN) >> > > > > +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2= =A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0= =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2= =A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0= =C2=A0=C2=A0=C2=A0=C2=A0 & 0x3) >> > > > > =3D=3D 2)); >> > > > > + >> > > > >=20 >> > > > > and >> > > > >=20 >> > > > > $ cat i915_dmc_info >> > > > > [snip] >> > > > > DC3 -> DC5 count: 286 >> > > > > DC5 -> DC6 count: 0 >> > > > > DC6 allowed: yes >> > > > > [snip] >> > > > >=20 >> > > > > $ cat i915_dmc_info >> > > > > [snip] >> > > > > DC3 -> DC5 count: 292 >> > > > > DC5 -> DC6 count: 0 >> > > > > DC6 allowed: yes >> > > > > [snip] >> > > > >=20 >> > > > > Thoughts? >> > > >=20 >> > > > The DC5 increment could've happened while DC6 was disabled by >> > > > the driver. >> > >=20 >> > > Yes, it could... in general the dc6 bit would be zero, but right, >> > > there's >> > > a possible race. >> > >=20 >> > > But should we complicate things when we know that on the test >> > > case itself >> > > we are in full control of the modeset?! From the test perspective >> > > I believe >> > > this would be more than enough without complicating things. >> >=20 >> > Imo having a counter which works based on the condition that >> > guarantees the >> > display to allow DC6, would help later in debugging. > >yeap, it makes sense > >> >=20 >> > > But well, if you really believe that we need to go further in the >> > > driver >> > > to cover that it is fine by me. >> > >=20 >> > > But just to ensure that we are in the same page, could you please >> > > open >> > > up a bit more of your idea on when to increase the dc5 sw >> > > counters >> > > in a way that we would ensure that we don't have race and that we >> > > get the dc6 allowed counter correctly? >> >=20 >> > Something like the following: >> >=20 >> > 1. Right after the driver sets DC6_EN, it stores the DC5 HW >> > counter's >> > =C2=A0 current value: >> > =C2=A0 dc5_start =3D dc5_current >> > 2. Right before the driver clears DC6_EN, it updates the DC6 >> > allowed >> > =C2=A0 counter: >> > =C2=A0 dc6_allowed +=3D dc5_current - dc5_start >> > =C2=A0 dc5_start =3D dc5_current >> > 3. When userspace reads the counters via debugfs the driver first >> > =C2=A0 updates dc6_allowed the same way as 2. did if DC6_EN is set. >>=20 >> This sounds good to me. > >I like that as well. > >>=20 >> I'd like to add that we should ensure that DC6 is really being >> allowed, >> so that might need to be handled inside gen9_set_dc_state(), where >> allowed_dc_mask is applied. > >well, for that we can also have the=20 > >--- a/drivers/gpu/drm/i915/display/intel_dmc.c >+++ b/drivers/gpu/drm/i915/display/intel_dmc.c >@@ -1294,6 +1294,10 @@ static int intel_dmc_debugfs_status_show(struct >seq_file *m, void *unused) > seq_printf(m, "DC5 -> DC6 count: %d\n", > intel_de_read(display, dc6_reg)); > >+ seq_printf(m, "DC6 allowed: %s\n", >str_yes_no((intel_de_read(display, >+ =20 >DC_STATE_EN) >+ & 0x3) =3D=3D 2)); > >on top of what Imre suggested right? >so the dc6 count is updated and also we have the live view of the >register set Hm... Not sure if that would be required to validate that the display engine was ready for DC6. I guess the dc6_allowed counter would be enough. > >no? > >not sure why we need to go to the dc9 func... Hm... dc9? Did you mean gen9_set_dc_state()? Function sanitizes the target value for DC_STATE_EN so that we do not use a value that is not allowed (e.g. when the driver was loaded with enable_dc=3D0). -- Gustavo Sousa > >>=20 >> -- >> Gustavo Sousa >>=20 >> >=20 >> > > Btw, while doing this experiment I noticed that the debugfs and >> > > test >> > > also doesn't call that residency anyway and it is just count. So >> > > perhaps with your idea we don't need to change the debugfs >> > > interface. >