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mx.microsoft.com 1; spf=pass smtp.mailfrom=intel.com; dmarc=pass action=none header.from=intel.com; dkim=pass header.d=intel.com; arc=none Authentication-Results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=intel.com; Received: from PH8PR11MB8287.namprd11.prod.outlook.com (2603:10b6:510:1c7::14) by PH7PR11MB7052.namprd11.prod.outlook.com (2603:10b6:510:20f::10) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.8880.17; Wed, 2 Jul 2025 13:11:53 +0000 Received: from PH8PR11MB8287.namprd11.prod.outlook.com ([fe80::7e8b:2e5:8ce4:2350]) by PH8PR11MB8287.namprd11.prod.outlook.com ([fe80::7e8b:2e5:8ce4:2350%4]) with mapi id 15.20.8835.026; Wed, 2 Jul 2025 13:11:53 +0000 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable In-Reply-To: <20250702084620.3837426-3-ankit.k.nautiyal@intel.com> References: <20250702084620.3837426-1-ankit.k.nautiyal@intel.com> <20250702084620.3837426-3-ankit.k.nautiyal@intel.com> Subject: Re: [PATCH 2/2] drm/i915/gmbus: Add Wa_16025573575 for PTL for bit-bashing From: Gustavo Sousa CC: , , "Ankit Nautiyal" To: Ankit Nautiyal , Date: Wed, 2 Jul 2025 10:11:47 -0300 Message-ID: <175146190758.3748.7583185864302070157@intel.com> User-Agent: alot/0.12.dev27+gd21c920b07eb X-ClientProxiedBy: MW4P222CA0018.NAMP222.PROD.OUTLOOK.COM (2603:10b6:303:114::23) To PH8PR11MB8287.namprd11.prod.outlook.com (2603:10b6:510:1c7::14) MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: PH8PR11MB8287:EE_|PH7PR11MB7052:EE_ X-MS-Office365-Filtering-Correlation-Id: a4179780-276d-4f37-0b29-08ddb96a03ad X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|366016|376014|1800799024; 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(Jani) >-Use a separate if-block for the workaround. (Gustavo) > >Signed-off-by: Ankit Nautiyal >--- > .../gpu/drm/i915/display/intel_display_wa.c | 7 ++++ > .../gpu/drm/i915/display/intel_display_wa.h | 1 + > drivers/gpu/drm/i915/display/intel_gmbus.c | 34 +++++++++++++++++-- > 3 files changed, 40 insertions(+), 2 deletions(-) > >diff --git a/drivers/gpu/drm/i915/display/intel_display_wa.c b/drivers/gpu= /drm/i915/display/intel_display_wa.c >index f5e8d58d9a68..12d1df5981f7 100644 >--- a/drivers/gpu/drm/i915/display/intel_display_wa.c >+++ b/drivers/gpu/drm/i915/display/intel_display_wa.c >@@ -42,11 +42,18 @@ void intel_display_wa_apply(struct intel_display *disp= lay) > gen11_display_wa_apply(display); > } >=20 >+static bool intel_display_needs_wa_16025573575(struct intel_display *disp= lay) >+{ >+ return DISPLAY_VER(display) =3D=3D 30; We should also check for 30.02. >+} >+ > bool __intel_display_wa(struct intel_display *display, enum intel_display= _wa wa) > { > switch (wa) { > case INTEL_DISPLAY_WA_16023588340: > return intel_display_needs_wa_16023588340(display); >+ case INTEL_DISPLAY_WA_16025573575: >+ return intel_display_needs_wa_16025573575(display); While it makes sense to have function intel_display_needs_wa_16023588340() (at least for now), I wonder if the same could be said about intel_display_needs_wa_16025573575()... Maybe it would be simpler to just inline the conditions with a single line here instead of adding 5 extra lines to the file. -- Gustavo Sousa > default: > drm_WARN(display->drm, 1, "Missing Wa number: %d\n", wa); > break; >diff --git a/drivers/gpu/drm/i915/display/intel_display_wa.h b/drivers/gpu= /drm/i915/display/intel_display_wa.h >index 146ee70d66f7..d3d241992e55 100644 >--- a/drivers/gpu/drm/i915/display/intel_display_wa.h >+++ b/drivers/gpu/drm/i915/display/intel_display_wa.h >@@ -23,6 +23,7 @@ bool intel_display_needs_wa_16023588340(struct intel_dis= play *display); >=20 > enum intel_display_wa { > INTEL_DISPLAY_WA_16023588340, >+ INTEL_DISPLAY_WA_16025573575, > }; >=20 > bool __intel_display_wa(struct intel_display *display, enum intel_display= _wa wa); >diff --git a/drivers/gpu/drm/i915/display/intel_gmbus.c b/drivers/gpu/drm/= i915/display/intel_gmbus.c >index 0d73f32fe7f1..95cab11c9cde 100644 >--- a/drivers/gpu/drm/i915/display/intel_gmbus.c >+++ b/drivers/gpu/drm/i915/display/intel_gmbus.c >@@ -39,6 +39,7 @@ > #include "intel_de.h" > #include "intel_display_regs.h" > #include "intel_display_types.h" >+#include "intel_display_wa.h" > #include "intel_gmbus.h" > #include "intel_gmbus_regs.h" >=20 >@@ -241,11 +242,18 @@ static u32 get_reserved(struct intel_gmbus *bus) > { > struct intel_display *display =3D bus->display; > u32 reserved =3D 0; >+ u32 preserve_bits =3D 0; >=20 > /* On most chips, these bits must be preserved in software. */ > if (!display->platform.i830 && !display->platform.i845g) >- reserved =3D intel_de_read_notrace(display, bus->gpio_reg= ) & >- (GPIO_DATA_PULLUP_DISABLE | GPIO_CLOCK_PULLUP_DIS= ABLE); >+ preserve_bits |=3D GPIO_DATA_PULLUP_DISABLE | GPIO_CLOCK_= PULLUP_DISABLE; >+ >+ /* PTL: Wa_16025573575: the masks bits need to be preserved throu= gh out */ >+ if (intel_display_wa(display, 16025573575)) >+ preserve_bits |=3D GPIO_CLOCK_DIR_MASK | GPIO_CLOCK_VAL_M= ASK | >+ GPIO_DATA_DIR_MASK | GPIO_DATA_VAL_MASK; >+ >+ reserved =3D intel_de_read_notrace(display, bus->gpio_reg) & pres= erve_bits; >=20 > return reserved; > } >@@ -308,6 +316,22 @@ static void set_data(void *data, int state_high) > intel_de_posting_read(display, bus->gpio_reg); > } >=20 >+static void >+ptl_handle_mask_bits(struct intel_gmbus *bus, bool set) >+{ >+ struct intel_display *display =3D bus->display; >+ u32 reg_val =3D intel_de_read_notrace(display, bus->gpio_reg); >+ u32 mask_bits =3D GPIO_CLOCK_DIR_MASK | GPIO_CLOCK_VAL_MASK | >+ GPIO_DATA_DIR_MASK | GPIO_DATA_VAL_MASK; >+ if (set) >+ reg_val |=3D mask_bits; >+ else >+ reg_val &=3D ~mask_bits; >+ >+ intel_de_write_notrace(display, bus->gpio_reg, reg_val); >+ intel_de_posting_read(display, bus->gpio_reg); >+} >+ > static int > intel_gpio_pre_xfer(struct i2c_adapter *adapter) > { >@@ -319,6 +343,9 @@ intel_gpio_pre_xfer(struct i2c_adapter *adapter) > if (display->platform.pineview) > pnv_gmbus_clock_gating(display, false); >=20 >+ if (intel_display_wa(display, 16025573575)) >+ ptl_handle_mask_bits(bus, true); >+ > set_data(bus, 1); > set_clock(bus, 1); > udelay(I2C_RISEFALL_TIME); >@@ -336,6 +363,9 @@ intel_gpio_post_xfer(struct i2c_adapter *adapter) >=20 > if (display->platform.pineview) > pnv_gmbus_clock_gating(display, true); >+ >+ if (intel_display_wa(display, 16025573575)) >+ ptl_handle_mask_bits(bus, false); > } >=20 > static void >--=20 >2.45.2 >