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mx.microsoft.com 1; spf=pass smtp.mailfrom=intel.com; dmarc=pass action=none header.from=intel.com; dkim=pass header.d=intel.com; arc=none Authentication-Results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=intel.com; Received: from PH8PR11MB8287.namprd11.prod.outlook.com (2603:10b6:510:1c7::14) by MW4PR11MB6764.namprd11.prod.outlook.com (2603:10b6:303:209::15) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.9160.18; Fri, 3 Oct 2025 14:09:50 +0000 Received: from PH8PR11MB8287.namprd11.prod.outlook.com ([fe80::7e8b:2e5:8ce4:2350]) by PH8PR11MB8287.namprd11.prod.outlook.com ([fe80::7e8b:2e5:8ce4:2350%7]) with mapi id 15.20.9160.015; Fri, 3 Oct 2025 14:09:49 +0000 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable In-Reply-To: References: <20251001-pica-power-before-aux-v2-0-6308df4de5a8@intel.com> <20251001-pica-power-before-aux-v2-2-6308df4de5a8@intel.com> Subject: Re: [PATCH v2 2/2] drm/i915/display: Enable PICA power before AUX From: Gustavo Sousa CC: , To: Imre Deak Date: Fri, 3 Oct 2025 11:09:44 -0300 Message-ID: <175950058472.812591.6490111675338161159@intel.com> User-Agent: alot/0.12.dev22+g972188619 X-ClientProxiedBy: BYAPR02CA0008.namprd02.prod.outlook.com (2603:10b6:a02:ee::21) To PH8PR11MB8287.namprd11.prod.outlook.com (2603:10b6:510:1c7::14) MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: PH8PR11MB8287:EE_|MW4PR11MB6764:EE_ X-MS-Office365-Filtering-Correlation-Id: 7a545388-2656-458d-f121-08de0286837f X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|376014|366016|1800799024; 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Starting with Xe2_LPD, >> such power well is the "PICA" power well, which is managed by the driver >> on demand. >>=20 >> While we did add the mapping of AUX power domains to the PICA power >> well, we ended up placing its power well descriptor after the >> descriptor for AUX power. As a result, when enabling power wells for one >> of the aux power domains, the driver will enable AUX power before PICA >> power, going against the order specified in Bspec. >>=20 >> It appears that issue did not become apparent to us mainly because, >> luckily, AUX power is brought up after we assert PICA power, even if >> done in the wrong order; and in enough time for the first AUX >> transaction to succeed. >>=20 >> Furthermore, I have also realized that, in some cases, like driver >> initialization, PICA power is already up when we need to acquire AUX >> power. >>=20 >> One case where we can observe the incorrect ordering is when the driver >> is resuming from runtime PM suspend. Here is an excerpt of a dmesg with >> some extra debug logs extracted from a LNL machine to illustrate the >> issue: >>=20 >> [ +0.000156] xe 0000:00:02.0: [drm:intel_power_well_enable [xe]] en= abling AUX_TC1 >> [ +0.001312] xe 0000:00:02.0: [drm:xelpdp_aux_power_well_enable [xe= ]] DBG: AUX_CH_USBC1 power status: 0 >> [ +0.000127] xe 0000:00:02.0: [drm:intel_power_well_enable [xe]] en= abling PICA_TC >> [ +0.001072] xe 0000:00:02.0: [drm:xe2lpd_pica_power_well_enable [x= e]] DBG: AUX_CH_USBC1 power status: 1 >> [ +0.000102] xe 0000:00:02.0: [drm:xe2lpd_pica_power_well_enable [x= e]] DBG: AUX_CH_USBC2 power status: 0 >> [ +0.000090] xe 0000:00:02.0: [drm:xe2lpd_pica_power_well_enable [x= e]] DBG: AUX_CH_USBC3 power status: 0 >> [ +0.000092] xe 0000:00:02.0: [drm:xe2lpd_pica_power_well_enable [x= e]] DBG: AUX_CH_USBC4 power status: 0 >>=20 >> The first "DBG: ..." line shows that AUX power for TC1 is off after we >> assert and wait. The remaining lines show that AUX power for TC1 was on >> after we enabled PICA power and waited for AUX power. >>=20 >> It is important that we stay compliant with the spec, so let's fix this >> by listing the power wells in an order that matches the requirements >> from Bspec. (As a side note, it would be nice if we could define those >> dependencies explicitly.) >>=20 >> After this change, we have: >>=20 >> [ +0.000146] xe 0000:00:02.0: [drm:intel_power_well_enable [xe]] en= abling PICA_TC >> [ +0.001417] xe 0000:00:02.0: [drm:xe2lpd_pica_power_well_enable [x= e]] DBG: AUX_CH_USBC1 power status: 0 >> [ +0.000116] xe 0000:00:02.0: [drm:xe2lpd_pica_power_well_enable [x= e]] DBG: AUX_CH_USBC2 power status: 0 >> [ +0.000096] xe 0000:00:02.0: [drm:xe2lpd_pica_power_well_enable [x= e]] DBG: AUX_CH_USBC3 power status: 0 >> [ +0.000094] xe 0000:00:02.0: [drm:xe2lpd_pica_power_well_enable [x= e]] DBG: AUX_CH_USBC4 power status: 0 >> [ +0.000095] xe 0000:00:02.0: [drm:intel_power_well_enable [xe]] en= abling AUX_TC1 >> [ +0.000915] xe 0000:00:02.0: [drm:xelpdp_aux_power_well_enable [xe= ]] DBG: AUX_CH_USBC1 power status: 1 >>=20 >> Bspec: 68967, 68886, 72519 >> Signed-off-by: Gustavo Sousa > >Upgrading my R-b from v1, where I didn't consider that the order of >enabling/disabling the PICA PW would change wrt. PW_2/pipe PWs. That >shouldn't be an issue in theory - spec doesn't forbid it -, but Windows >is also using the PW_2 -> pipe PW -> PICA_PW order, so better to keep >that order. > >Thanks again for debugging and fixing this issue: >Reviewed-by: Imre Deak Pushed to drm-intel-next. Thanks the review! -- Gustavo Sousa > >> --- >> drivers/gpu/drm/i915/display/intel_display_power_map.c | 6 +++--- >> 1 file changed, 3 insertions(+), 3 deletions(-) >>=20 >> diff --git a/drivers/gpu/drm/i915/display/intel_display_power_map.c b/dr= ivers/gpu/drm/i915/display/intel_display_power_map.c >> index e89f18b7037f..9b49952994ce 100644 >> --- a/drivers/gpu/drm/i915/display/intel_display_power_map.c >> +++ b/drivers/gpu/drm/i915/display/intel_display_power_map.c >> @@ -1588,8 +1588,8 @@ static const struct i915_power_well_desc_list xe2l= pd_power_wells[] =3D { >> I915_PW_DESCRIPTORS(icl_power_wells_pw_1), >> I915_PW_DESCRIPTORS(xe2lpd_power_wells_dcoff), >> I915_PW_DESCRIPTORS(xelpdp_power_wells_main), >> - I915_PW_DESCRIPTORS(xelpdp_power_wells_aux), >> I915_PW_DESCRIPTORS(xe2lpd_power_wells_pica), >> + I915_PW_DESCRIPTORS(xelpdp_power_wells_aux), >> }; >> =20 >> /* >> @@ -1710,8 +1710,8 @@ static const struct i915_power_well_desc_list xe3l= pd_power_wells[] =3D { >> I915_PW_DESCRIPTORS(icl_power_wells_pw_1), >> I915_PW_DESCRIPTORS(xe3lpd_power_wells_dcoff), >> I915_PW_DESCRIPTORS(xe3lpd_power_wells_main), >> - I915_PW_DESCRIPTORS(xelpdp_power_wells_aux), >> I915_PW_DESCRIPTORS(xe2lpd_power_wells_pica), >> + I915_PW_DESCRIPTORS(xelpdp_power_wells_aux), >> }; >> =20 >> static const struct i915_power_well_desc wcl_power_wells_main[] =3D { >> @@ -1768,8 +1768,8 @@ static const struct i915_power_well_desc_list wcl_= power_wells[] =3D { >> I915_PW_DESCRIPTORS(icl_power_wells_pw_1), >> I915_PW_DESCRIPTORS(xe3lpd_power_wells_dcoff), >> I915_PW_DESCRIPTORS(wcl_power_wells_main), >> - I915_PW_DESCRIPTORS(wcl_power_wells_aux), >> I915_PW_DESCRIPTORS(xe2lpd_power_wells_pica), >> + I915_PW_DESCRIPTORS(wcl_power_wells_aux), >> }; >> =20 >> static void init_power_well_domains(const struct i915_power_well_instan= ce *inst, >>=20 >> --=20 >> 2.51.0 >>