From mboxrd@z Thu Jan 1 00:00:00 1970 From: "Souza, Jose" Subject: Re: [PATCH v2 03/11] drm/i915/psr: Set PSR CRC verification bit in sink inside PSR1 block Date: Mon, 3 Dec 2018 20:24:35 +0000 Message-ID: <18541c55b5e85d3dd026ac175af79ad8c7bec596.camel@intel.com> References: <20181130022525.25676-1-jose.souza@intel.com> <20181130022525.25676-3-jose.souza@intel.com> <8b4076fcf4542928052f8b7354801407ca2c128a.camel@intel.com> Mime-Version: 1.0 Content-Type: multipart/mixed; boundary="===============1651243555==" Return-path: In-Reply-To: <8b4076fcf4542928052f8b7354801407ca2c128a.camel@intel.com> Content-Language: en-US List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" To: "intel-gfx@lists.freedesktop.org" , "Pandiyan, Dhinakaran" Cc: "dri-devel@lists.freedesktop.org" , "Vivi, Rodrigo" List-Id: intel-gfx@lists.freedesktop.org --===============1651243555== Content-Language: en-US Content-Type: multipart/signed; micalg=pgp-sha256; protocol="application/pgp-signature"; boundary="=-K3SIsqD8xg0CUX9Lnv0+" --=-K3SIsqD8xg0CUX9Lnv0+ Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable On Fri, 2018-11-30 at 15:54 -0800, Dhinakaran Pandiyan wrote: > On Thu, 2018-11-29 at 18:25 -0800, Jos=C3=A9 Roberto de Souza wrote: > > As we have a else block for the 'if (dev_priv->psr.psr2_enabled) {' > > and this bit is only set for PSR1 move it to that block to make it > > more easy to read. > >=20 > > Cc: Dhinakaran Pandiyan > > Cc: Rodrigo Vivi > > Signed-off-by: Jos=C3=A9 Roberto de Souza > > --- > > drivers/gpu/drm/i915/intel_psr.c | 5 +++-- > > 1 file changed, 3 insertions(+), 2 deletions(-) > >=20 > > diff --git a/drivers/gpu/drm/i915/intel_psr.c > > b/drivers/gpu/drm/i915/intel_psr.c > > index 8515f4a6f4f1..b04472e637c8 100644 > > --- a/drivers/gpu/drm/i915/intel_psr.c > > +++ b/drivers/gpu/drm/i915/intel_psr.c > > @@ -398,10 +398,11 @@ static void intel_psr_enable_sink(struct > > intel_dp *intel_dp) > > } else { > > if (dev_priv->psr.link_standby) > > dpcd_val |=3D DP_PSR_MAIN_LINK_ACTIVE; > > + > > + if (INTEL_GEN(dev_priv) >=3D 8) > > + dpcd_val |=3D DP_PSR_CRC_VERIFICATION; > > } > > =20 > > - if (!dev_priv->psr.psr2_enabled && INTEL_GEN(dev_priv) >=3D 8) > > - dpcd_val |=3D DP_PSR_CRC_VERIFICATION; > > drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_EN_CFG, dpcd_val); > > =20 > > drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER, > > DP_SET_POWER_D0); >=20 > Do we need this DPCD write? The panel should already be awake by this > point, I think it's worth removing it if there's no regression. >=20 > Your change in this patch looks good, so > Reviewed-by: Dhinakaran Pandiyan >=20 Added to the list to things to TODO. Thanks for the review. >=20 >=20 >=20 --=-K3SIsqD8xg0CUX9Lnv0+ Content-Type: application/pgp-signature; name="signature.asc" Content-Description: This is a digitally signed message part Content-Transfer-Encoding: 7bit -----BEGIN PGP SIGNATURE----- iQEzBAABCAAdFiEEVNG051EijGa0MiaQVenbO/mOWkkFAlwFkQEACgkQVenbO/mO Wklf9gf/XpPgFydYpJNAcUUxCeXwbzY86iZC1b25P/q8V8Uped0l8QCFHB2WzSjA XJjCOl6karZ2/z1w6sgTqTnQdXG29YxJJstE1PPT0dYbZLr2Q07y95uwZXaCFAK6 j8KfevT5UQpbqBc7Iwr61PHeYXmW9cLGj+LeEOI370Opj3XzexYROkUZJ8bcJdT3 LcdZpKK9LK6y5BsNQMzO8uT75oA7f/7nH89N8OfUPuORo2UcXVlB4cDX7SQhGT73 io6E7g03EjVzaTFicqBncpKrjN4Ycs8vG5p6yctf7voQvMbMl9X0KacCAhJRAlzo gq0U3/5JsQKJr/JHMAl1aABC6B+q4w== =UzDg -----END PGP SIGNATURE----- --=-K3SIsqD8xg0CUX9Lnv0+-- --===============1651243555== Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: base64 Content-Disposition: inline X19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX18KSW50ZWwtZ2Z4 IG1haWxpbmcgbGlzdApJbnRlbC1nZnhAbGlzdHMuZnJlZWRlc2t0b3Aub3JnCmh0dHBzOi8vbGlz dHMuZnJlZWRlc2t0b3Aub3JnL21haWxtYW4vbGlzdGluZm8vaW50ZWwtZ2Z4Cg== --===============1651243555==--