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From: Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com>
To: Chris Wilson <chris@chris-wilson.co.uk>, intel-gfx@lists.freedesktop.org
Subject: Re: [PATCH 2/2] drm/i915/scheduler: emulate a scheduler for guc
Date: Wed, 15 Feb 2017 12:33:38 +0000	[thread overview]
Message-ID: <18d050fd-ab70-89c6-16ab-83404a947cb0@linux.intel.com> (raw)
In-Reply-To: <20170215122037.GY18048@nuc-i3427.alporthouse.com>


On 15/02/2017 12:20, Chris Wilson wrote:
> On Wed, Feb 15, 2017 at 11:56:28AM +0000, Tvrtko Ursulin wrote:
>>
>> On 14/02/2017 11:44, Chris Wilson wrote:
>>> diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
>>> index cdc7da60d37a..aa886b5fb2cd 100644
>>> --- a/drivers/gpu/drm/i915/i915_irq.c
>>> +++ b/drivers/gpu/drm/i915/i915_irq.c
>>> @@ -1350,13 +1350,20 @@ static void snb_gt_irq_handler(struct drm_i915_private *dev_priv,
>>> static __always_inline void
>>> gen8_cs_irq_handler(struct intel_engine_cs *engine, u32 iir, int test_shift)
>>> {
>>> -	if (iir & (GT_RENDER_USER_INTERRUPT << test_shift))
>>> -		notify_ring(engine);
>>> +	bool tasklet = false;
>>>
>>> 	if (iir & (GT_CONTEXT_SWITCH_INTERRUPT << test_shift)) {
>>> 		set_bit(ENGINE_IRQ_EXECLIST, &engine->irq_posted);
>>> -		tasklet_hi_schedule(&engine->irq_tasklet);
>>> +		tasklet = true;
>>> 	}
>>> +
>>> +	if (iir & (GT_RENDER_USER_INTERRUPT << test_shift)) {
>>> +		notify_ring(engine);
>>> +		tasklet |= i915.enable_guc_submission;
>>
>> Hm.. noticed that BXT was quite unhappy in CI?
>>
>> I wonder if we need to set ENGINE_IRQ_EXECLISTS here (and clear it
>> in the irq tasklet as well) to be fully identical between the two
>> backends.
>>
>> Not saying that was the reason for the CI unhappiness, just an
>> observation at this stage.
>
> I don't think we want to. Note that the bit will always be unset, so
> that shouldn't be causing the intel_execlists_idle() timeout. I was

Yeah agreed, but when you added the bit test in intel_execlists_idle, 
the commit message said it is a sanity check before suspend. So 
presumably it would make sense to have the same for the GuC tasklet.

> fearing a missed interrupt as we only idle once the request list is
> empty, but that means we didn't process the interrupt. Or something
> scary like that. (I do recall seeing missed interrupts on my skl with
> guc btw, don't know if that is still a feature.)

No idea and no BXT to test on. But it is something new compared to the 
previous CI run. So something changed in the tree in the meantime to 
cause it.

Regards,

Tvrtko
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  reply	other threads:[~2017-02-15 12:33 UTC|newest]

Thread overview: 8+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2017-02-14 11:44 [PATCH 1/2] HAX enable guc submission for CI Chris Wilson
2017-02-14 11:44 ` [PATCH 2/2] drm/i915/scheduler: emulate a scheduler for guc Chris Wilson
2017-02-14 14:03   ` Joonas Lahtinen
2017-02-15 11:56   ` Tvrtko Ursulin
2017-02-15 12:20     ` Chris Wilson
2017-02-15 12:33       ` Tvrtko Ursulin [this message]
2017-03-13  2:28         ` Dong, Chuanxiao
2017-02-14 14:52 ` ✗ Fi.CI.BAT: failure for series starting with [1/2] HAX enable guc submission for CI Patchwork

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