From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-7.2 required=3.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, HK_RANDOM_FROM,INCLUDES_PATCH,MAILING_LIST_MULTI,SIGNED_OFF_BY,SPF_HELO_NONE, SPF_PASS,URIBL_BLOCKED,USER_AGENT_SANE_1 autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 1B78EC32771 for ; Mon, 20 Jan 2020 19:47:14 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id F2C2A22527 for ; Mon, 20 Jan 2020 19:47:13 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org F2C2A22527 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=linux.intel.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=intel-gfx-bounces@lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 8C1606EA89; Mon, 20 Jan 2020 19:47:13 +0000 (UTC) Received: from mga12.intel.com (mga12.intel.com [192.55.52.136]) by gabe.freedesktop.org (Postfix) with ESMTPS id E61036EA89 for ; Mon, 20 Jan 2020 19:47:11 +0000 (UTC) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga006.jf.intel.com ([10.7.209.51]) by fmsmga106.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 20 Jan 2020 11:47:11 -0800 X-IronPort-AV: E=Sophos;i="5.70,343,1574150400"; d="scan'208";a="228507866" Received: from wmszyfel-mobl2.ger.corp.intel.com (HELO [10.252.10.247]) ([10.252.10.247]) by orsmga006-auth.jf.intel.com with ESMTP/TLS/AES256-SHA; 20 Jan 2020 11:47:10 -0800 To: Chris Wilson , intel-gfx@lists.freedesktop.org References: <20200120175704.36340-1-chris@chris-wilson.co.uk> From: Tvrtko Ursulin Organization: Intel Corporation UK Plc Message-ID: <1a812a72-7b17-f5b5-da41-dbeadae5b014@linux.intel.com> Date: Mon, 20 Jan 2020 19:47:08 +0000 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:60.0) Gecko/20100101 Thunderbird/60.9.0 MIME-Version: 1.0 In-Reply-To: <20200120175704.36340-1-chris@chris-wilson.co.uk> Content-Language: en-US Subject: Re: [Intel-gfx] [PATCH] drm/i915: Mark the removal of the i915_request from the sched.link X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Transfer-Encoding: 7bit Content-Type: text/plain; charset="us-ascii"; Format="flowed" Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" On 20/01/2020 17:57, Chris Wilson wrote: > Keep the rq->fence.flags consistent with the status of the > rq->sched.link, and clear the associated bits when decoupling the link > on retirement (as we may wish to inspect those flags independent of > other state). > > Fixes: 32ff621fd744 ("drm/i915/gt: Allow temporary suspension of inflight requests") > References: https://gitlab.freedesktop.org/drm/intel/issues/997 > Signed-off-by: Chris Wilson > Cc: Tvrtko Ursulin > --- > drivers/gpu/drm/i915/i915_request.c | 2 ++ > 1 file changed, 2 insertions(+) > > diff --git a/drivers/gpu/drm/i915/i915_request.c b/drivers/gpu/drm/i915/i915_request.c > index 9ed0d3bc7249..78a5f5d3c070 100644 > --- a/drivers/gpu/drm/i915/i915_request.c > +++ b/drivers/gpu/drm/i915/i915_request.c > @@ -221,6 +221,8 @@ static void remove_from_engine(struct i915_request *rq) > locked = engine; > } > list_del_init(&rq->sched.link); > + clear_bit(I915_FENCE_FLAG_PQUEUE, &rq->fence.flags); This one I think can not be set in retirement. Or there is a path? [comes back after writing the comment below] Race between completion to hold puts the request on hold, then request completes just as it is un-held? It needs retire to happen at the right time, driven by ...? Is this it? > + clear_bit(I915_FENCE_FLAG_HOLD, &rq->fence.flags); This one I think indeed can race with completion. Regards, Tvrtko > spin_unlock_irq(&locked->active.lock); > } > > _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx