From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 7A56AEB64DD for ; Fri, 21 Jul 2023 10:11:02 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 310D210E648; Fri, 21 Jul 2023 10:10:57 +0000 (UTC) Received: from mga18.intel.com (mga18.intel.com [134.134.136.126]) by gabe.freedesktop.org (Postfix) with ESMTPS id B6C7810E647; Fri, 21 Jul 2023 10:10:54 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1689934254; x=1721470254; h=message-id:date:mime-version:subject:to:cc:references: from:in-reply-to:content-transfer-encoding; bh=DlNLP5+kQ2gtILG4UU0QlUbPl4G2stOHE1ua4oEL7vg=; b=kbLL3DTd6ngdn+95Vlg4jEJyCcuehvkkyXi0+561yqiI3XK9gh7+NMOU PB1k0UQ+p/E8pMQc8mx2FHVfMEg5i1NgC5UemFrGU/KeJbEmQQ/5saq/C 6X3AaVbFogBPBjMZkz79VM0ofnTcK68ogAhSRCvvPX2ucrHPKDHUiKe/S eKp7Qs/1Gi4wELJQv3oSca0OqbXfDXvhXBSpiUoGj/rUNQEARZwBg8eSy OGXvoiIO/EncusKVp5vdZhW1zmh7Ote06CzlhLJSsHaJwkPlYHRo2xUu5 M0qGDw5BZIV8gkvej52S2VLhtc/SpOs3nkPyhWowEBQx6r+j5A1XkKeWZ Q==; X-IronPort-AV: E=McAfee;i="6600,9927,10777"; a="351869777" X-IronPort-AV: E=Sophos;i="6.01,220,1684825200"; d="scan'208";a="351869777" Received: from fmsmga007.fm.intel.com ([10.253.24.52]) by orsmga106.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 21 Jul 2023 03:10:54 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10777"; a="728055351" X-IronPort-AV: E=Sophos;i="6.01,220,1684825200"; d="scan'208";a="728055351" Received: from ahajda-mobl.ger.corp.intel.com (HELO [10.213.21.56]) ([10.213.21.56]) by fmsmga007-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 21 Jul 2023 03:10:50 -0700 Message-ID: <1cb56f45-cb68-82f2-dc43-b4706b2e12c1@intel.com> Date: Fri, 21 Jul 2023 12:10:48 +0200 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (Windows NT 10.0; Win64; x64; rv:102.0) Gecko/20100101 Firefox/102.0 Thunderbird/102.13.0 Content-Language: en-US To: Andi Shyti , Jonathan Cavitt , Matt Roper , Chris Wilson , Mika Kuoppala , Nirmoy Das References: <20230720210737.761400-1-andi.shyti@linux.intel.com> <20230720210737.761400-7-andi.shyti@linux.intel.com> From: Andrzej Hajda Organization: Intel Technology Poland sp. z o.o. - ul. Slowackiego 173, 80-298 Gdansk - KRS 101882 - NIP 957-07-52-316 In-Reply-To: <20230720210737.761400-7-andi.shyti@linux.intel.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit Subject: Re: [Intel-gfx] [PATCH v7 6/9] drm/i915/gt: Refactor intel_emit_pipe_control_cs() in a single function X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: intel-gfx , dri-evel , linux-stable Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" On 20.07.2023 23:07, Andi Shyti wrote: > Just a trivial refactoring for reducing the number of code > duplicate. This will come at handy in the next commits. > > Signed-off-by: Andi Shyti > Cc: # v5.8+ > --- > drivers/gpu/drm/i915/gt/gen8_engine_cs.c | 44 +++++++++++++----------- > 1 file changed, 23 insertions(+), 21 deletions(-) > > diff --git a/drivers/gpu/drm/i915/gt/gen8_engine_cs.c b/drivers/gpu/drm/i915/gt/gen8_engine_cs.c > index 9d050b9a19194..202d6ff8b5264 100644 > --- a/drivers/gpu/drm/i915/gt/gen8_engine_cs.c > +++ b/drivers/gpu/drm/i915/gt/gen8_engine_cs.c > @@ -177,23 +177,31 @@ u32 *gen12_emit_aux_table_inv(struct intel_gt *gt, u32 *cs, const i915_reg_t inv > return cs; > } > > +static u32 *intel_emit_pipe_control_cs(struct i915_request *rq, u32 bit_group_0, > + u32 bit_group_1, u32 offset) s/intel/gen12/ but this and few other issues were raised already by Matt in v6. Regards Andrzej > +{ > + u32 *cs; > + > + cs = intel_ring_begin(rq, 6); > + if (IS_ERR(cs)) > + return cs; > + > + cs = gen12_emit_pipe_control(cs, bit_group_0, bit_group_1, > + LRC_PPHWSP_SCRATCH_ADDR); > + intel_ring_advance(rq, cs); > + > + return cs; > +} > + > static int mtl_dummy_pipe_control(struct i915_request *rq) > { > /* Wa_14016712196 */ > if (IS_MTL_GRAPHICS_STEP(rq->engine->i915, M, STEP_A0, STEP_B0) || > - IS_MTL_GRAPHICS_STEP(rq->engine->i915, P, STEP_A0, STEP_B0)) { > - u32 *cs; > - > - /* dummy PIPE_CONTROL + depth flush */ > - cs = intel_ring_begin(rq, 6); > - if (IS_ERR(cs)) > - return PTR_ERR(cs); > - cs = gen12_emit_pipe_control(cs, > - 0, > - PIPE_CONTROL_DEPTH_CACHE_FLUSH, > - LRC_PPHWSP_SCRATCH_ADDR); > - intel_ring_advance(rq, cs); > - } > + IS_MTL_GRAPHICS_STEP(rq->engine->i915, P, STEP_A0, STEP_B0)) > + intel_emit_pipe_control_cs(rq, > + 0, > + PIPE_CONTROL_DEPTH_CACHE_FLUSH, > + LRC_PPHWSP_SCRATCH_ADDR); > > return 0; > } > @@ -210,7 +218,6 @@ int gen12_emit_flush_rcs(struct i915_request *rq, u32 mode) > u32 bit_group_0 = 0; > u32 bit_group_1 = 0; > int err; > - u32 *cs; > > err = mtl_dummy_pipe_control(rq); > if (err) > @@ -244,13 +251,8 @@ int gen12_emit_flush_rcs(struct i915_request *rq, u32 mode) > else if (engine->class == COMPUTE_CLASS) > bit_group_1 &= ~PIPE_CONTROL_3D_ENGINE_FLAGS; > > - cs = intel_ring_begin(rq, 6); > - if (IS_ERR(cs)) > - return PTR_ERR(cs); > - > - cs = gen12_emit_pipe_control(cs, bit_group_0, bit_group_1, > - LRC_PPHWSP_SCRATCH_ADDR); > - intel_ring_advance(rq, cs); > + intel_emit_pipe_control_cs(rq, bit_group_0, bit_group_1, > + LRC_PPHWSP_SCRATCH_ADDR); > } > > if (mode & EMIT_INVALIDATE) {